Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations

Mitsuya FUKAZAWA; Masanori KURIMOTO; Rei AKIYAMA; Hidehiro TAKATA; Makoto NAGATA

doi:10.1587/transele.E92.C.475

Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era

Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations

Mitsuya FUKAZAWA, Masanori KURIMOTO, Rei AKIYAMA, Hidehiro TAKATA, Makoto NAGATA

Author information

Keywords: power supply voltage noise built-in probing circuit, failure susceptibility, dynamic frequency scaling

JOURNAL RESTRICTED ACCESS

2009 Volume E92.C Issue 4 Pages 475-482

DOI https://doi.org/10.1587/transele.E92.C.475

Details

Abstract

Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.

Corresponding author

Register with J-STAGE for free!