A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-V_T PMOS amplifier and a low-V_T NMOS amplifier which is composed of high-V_T NMOSs and a low-V_T cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-V_T CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6ns and a writing time of 0.6ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13ns. The gate level control of the high-V_T NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.