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The Synthesis of Stochastic Circuits for Nanoscale Computation

The Synthesis of Stochastic Circuits for Nanoscale Computation

Weikang Qian, John Backes, Marc D. Riedel
Copyright: © 2009 |Volume: 1 |Issue: 4 |Pages: 19
ISSN: 1941-6318|EISSN: 1941-6326|ISSN: 1941-6318|EISBN13: 9781616921118|EISSN: 1941-6326|DOI: 10.4018/jnmc.2009120903
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MLA

Qian, Weikang, et al. "The Synthesis of Stochastic Circuits for Nanoscale Computation." IJNMC vol.1, no.4 2009: pp.39-57. http://doi.org/10.4018/jnmc.2009120903

APA

Qian, W., Backes, J., & Riedel, M. D. (2009). The Synthesis of Stochastic Circuits for Nanoscale Computation. International Journal of Nanotechnology and Molecular Computation (IJNMC), 1(4), 39-57. http://doi.org/10.4018/jnmc.2009120903

Chicago

Qian, Weikang, John Backes, and Marc D. Riedel. "The Synthesis of Stochastic Circuits for Nanoscale Computation," International Journal of Nanotechnology and Molecular Computation (IJNMC) 1, no.4: 39-57. http://doi.org/10.4018/jnmc.2009120903

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Abstract

Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components—and operations and multiplexing—that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively.

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