System Level Power Management policies are typically based on moving the systemto various power management states, in order to achieve minimum wastage of power. The major challenge in devising such strategies is that the input task arrival rates to a system is usually unpredictable, and hence the power management strategies have to be designed as on-line algorithms. These algorithms are aimed at optimizing wasted power in the face of nondeterministic task arrivals. Previous works on evaluating power management strategies for optimality, have used trace driven simulations, and competitive analysis. In this work, we build upon the competitive analysis based paradigm. Our work views a power management strategy as a winning strategy in a two player game, between the power management algorithm, and a non-deterministic adversary. With the power of non-determinism, we can generate the worst possible scenarios in terms of possible traces of tasks. Such scenarios not only disprove conjectured bounds on the optimality of a power management strategy, but also guides the designer towards a better policy. One could also prove such bounds automatically. To achieve these, we exploit model checkers used in formal verification. However, specific tools which are focused mainly on this kind of power management strategies are under development, which would alleviate some of the state explosion problems inherent in model checking techniques.

We present strategies for "online" dynamic power management (DPM) based on the notion of the competitive ratio that allows us to compare the effectiveness of algorithms against an optimal strategy. This paper makes two contributions: it provides a theoretical basis for the analysis of DPM strategies for systems with multiple power down states: and provides a competitive algorithm based on probabilistically generated inputs that improves the competitive ratio over deterministic strategies. Experimental results show that our probability-based DPM strategy improves the efficiency of power management over the deterministic DPM strategy by 25%, bringing the strategy to within 23% of the optimal offline DPM.

Efficient modeling of concurrency and reactivity along with their efficient implementation in the simulation kernel are crucial to the overall utility of system level models using the C++ based modeling frameworks. However, the concurrency alignment in most modeling frameworks are naturally along hardware units which is supported by the various language constructs and the system designers express concurrency in their system models by providing threads for some modules/units of the model. Our experimental analysis show that this concurrency model leads to inefficient simulation performance and a concurrency alignment along dataflow gives much better simulation performance but changes the conceptual model of hardware structures. As a result, we propose an algorithmic transformation of designs written in these C++ based environments with concurrency alignment along units/modules. This transformation, provided as a compiler front-end, will re-assign the concurrency along the dataflow, as opposed to threading along concurrent hardware/software modules, keeping the functionality of the model unchanged. Such a front-end transformation strategy will relieve hardware system designers from concerns about software engineering issues such as, threading architecture, and simulation performance, while allowing them to design in the most natural manner, whereas, the simulation performance can be enhanced upto almost two times as shown in our experiments.

IP component based system-on-chip design demands an integration, architectural trade-off exploration, and verification environment. Such an environment can only be effective, if system integrators can integrate components from libraries easily, with fast turn-around time and can efficiently simulate for functional and performance validation.

The advent of C++ based design libraries such as SystemC, Cynlib, and other similar design environments, such as SpecC, allows IP designers to create C++ component libraries, which are either pre-packaged generic elements, or specialized IP blocks. However, mere availability of such components does not necessarily imply ease of integration, or fast architectural exploration. The designers/system integrators need an environment that allows them to think about composable design elements, as hardware elements, and lets them use such elements without having to go through C++ software engineering cycles, such as intergation coding in C++, recompilation, and the corresponding softvvare problems.

Dynamic Power Management (DPM) is an important technique to reduce power consumption in embedded and portable systems. Power hungry devices such as disk drives, network interfaces, and other peripheral devices are often designed with multiple power saving states, and control knobs are provided for changing their power states under the operating system control. DPM strategies are "online" strategies since they must make decisions about the timing of transitioning to lower power consumption states during idle periods without knowing when the next request for service will arrive. In this paper, we present a novel approach to designing adaptive online DPM strategies. This approach dynamically learns the probability distribution of idle period lengths from recent request patterns. A probability-based scheme then uses this information to optimize power saving actions. We present experimental results comparing our strategy with various strategies in the literature, including our previous work. Our study includes measuring power usage as well as the additional latency introduced from the delay in powering back up when a new request for service arrives. Our strategy exhibits the lowest power consumption among all the online algorithms. The other algorithms which come close to matching its performance in power all suffer at least an additional 40% latency on average. Meanwhile, the algo-rithms which have comparable latency to our method all use at least 25% more power on average. Thus, our probability-based DPM strategy is the most successful algorithm in balancing power usage as well as latency incurred.

Increased complexity of micro-electronic systems demands a need for efficient system level models. System level models can provide detailed architectural simulation results to make architectural tradeoffs in the early stages of the design process. For effective system-level design, there is a need for an efficient co-simulation model for precise and speedy system level simulation and design exploration. Recently. several object-oriented language based co-design frameworks have been proposed for hardware modeling at the system-level. In this paper, we focus on modeling concurrency in these frameworks and how it can be used to improve the efficiency of system-level simulation. Specifically, we examine the use of threads to implement process concurrency and compare against non-threaded implementations using function calls. This distinction is important because it determines the choice of the class (e.g., synchronous/asynchronous processes, blocks etc) to use for specification of a given system block or behavior. Although, it is a commonly held belief that usage of threads might slow down the simulation perfomance due to context switch overheads, our analysis and experiments show, that by judicious choice of the threading model, and by striking a balance between the usage of threads and function calls in a system model, one can improve the simulation speed. Hardware designs being inherently concurrent. it is very important to be able to express concurrency in co-simulation models without compromising simulation efficiency. Hence our methodology is based on analysing the concurrency in the model before expressing them in a high level language. To demonstrate the simulation effectiveness, we present an architectural model of a system with adaptive memory hierarchy and demonstrate the effect of modeling choices on the overall simulation efficiency.

This paper presents a static transformation algorithm, for C++-based hardware models such as SystemC models. This algorithmic transformation changes the threading structure of the models and generates efficient C++ code with pre-emptive threading for efficient simulation on multi-processor systems. Efficient modeling for simulation and modeling for synthesis seems to be competing goals in the context of C++ based modeling paradigms, because for synthesis, the design should be partitioned according to the targeted hardware units and their interconnections, and concurrency is aligned along unit boundaries. However, for simulation performance, such a model may contain many concurrent modules, implemented by many user-level threads, which is an artifact of the C++-based concurrency modeling mechanism. It has been shown in previous work, however, that multi-threading is not necessarily a simulation performance hindrance. In fact, a proper choice of multithreading, especially in huge simulation models with I/O bound computations, is necessary for simulation efficiency. However, since the existing C++-based modeling frameworks employ user level thread packages, even this necessary threading cannot take advantage of the multi-processors availability, because user-level threads are transparent to operating system kernel. We solve this problem by accepting synthesis targeted SystemC models, and compiling them into multi-threaded simulation models, with kernel-level threads, resulting in faster simulation on multi-processors, as well as on single processors. Concurrency alignment in our resulting code is usually along the dataflow through the model. In our past work we have shown that simulation is faster after such concurrency re-assignment and here we give a foundation for implementing such an algorithm. This work has similarity with Quasi-Static Scheduling work in the literature, however, the aim and context are different, and so is the basis for the algorithm design.

The increasing heterogeneity and complexity of VLSI systems has made the use of C++ popular for building simulation and synthesis models at higher levels of abstraction. Currently, there are several different embodiments of C++ based environments, mostly in the form of hardware modeling libraries built on top of C++. However, the semantic gap between hardware modeling concepts, and the software programming language constructs, poses several issues which require critical examination. In this paper, we address the issue of interoperability between models built using different C++ based modeling libraries, or even modeling "styles" including home-grown C++ models. Model interoperability is the ability to use C++ based descriptions across different C++ based modeling environments. Two important aspects of interoperability are model composability, and model reusability. In this paper we focus on model reusability, analyzing various dimensions of the re usability of C++ based models, in an integration environment for building SOC models. We show how an inheritance based composition may be used to make two distinct C++ based class libraries interoperate. We also outline the implementation of a dynamic composition environment, which allows automatic run-time delegation based composition, to achieve interoperability. These strategies allow system integrators to focus on design composition, rather than software programming details inherent in the current inheritance based solutions.