Micron Technology, Inc. announced a comprehensive enablement program which will provide early access to technical resources, products, and ecosystem partners. The Technology Enablement Program will aid in the design, development, and qualification of next-generation computing platforms that use DDR5, the most technologically advanced DRAM available.
Today’s news, alongside the ratification of the JEDEC DDR5 standard, builds on Micron’s January announcement of DDR5 RDIMM samples and brings the industry one step closer to unlocking the value in next-generation, data-centric applications. Companies joining Micron in the DDR5 Technology Enablement Program include Cadence, Montage, Rambus, Renesas, and Synopsys.
DDR5 delivers improvements to performance, density, and reliability at a time when modern data centers need to feed rapidly growing processor core counts with memory bandwidth, and meet increasing customer demands for reliability, availability, and serviceability. DDR5 will offer greater than twice the effective bandwidth when compared to its predecessor DDR4, helping relieve this bandwidth-per-core crunch and enabling high performance and improved power management in a wide variety of applications.
Channel partners also play a very important role in any new technology’s development and adoption. As part of the DDR5 Technology Enablement Program (TEP), Micron will work alongside channel partners like distributors, value-added resellers, and OEMs/ODMs as they bring new and innovative products that use DDR5 to the market.
Qualified partners that enroll in the program can leverage Micron’s world-class collaboration, quality, and support and enjoy certain other benefits including access to the following:
- Certain DDR5 components and modules
- New DDR5 products as they become available
- Technical resources including data sheets, electrical and thermal models to aid in product development and evaluation as well as consultation on signal integrity and other technical support
- Other ecosystem partners who can aid in chip- and system-level design
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