DELL Inspiron 1420 ELSA LANAI UMA Laptop Schematics

A
ASUS CONFIDENTIAL
1
MODEL NAME : Elsa

PCB NO : ???
ASUS P/N : ???
Lanai UMA Schematics Document

uFCPGA Mobile Merom
Intel Crestline-GM + ICH8M
3
2007-03-19
REV :1.2(DELL: X02)
MB PCB
Part Number
DA800004H0L
Description
PCB 00B LA-3071P REV0 M/B
PROJECT:
A
BOM NO. ???

PCB P/N: ???
REVISION
DATE:
1.2
SHEET
Monday, March 19, 2007
1
B
OF
68
SCHEMATIC FILE NAME :
DESCRIPTION:
Cover Page
C
DESIGN ENGINEER :
RELEASE DATE :
D
LANAI: UMA
POWER
PG 21
Merom
POWER
PG 57
CHARGER
POWER CONTROL PG 49
SWITCH
POWER
CON.
CLOCK
CK410M+LP
POWER SEQUENCE PG 51
LOGIC
PG 59
XDP
POWER
POWER VCORE
(478 Micro-FCPGA)
PG 52
PG 55
POWER I/O
+1.5V_RUN/+1.05V_VCCP
PG 7,8
POWER SYSTEM
5V_ALW & 3.3V_ALW
DISCHARGE PATH PG 49
(Symbol Rev.09)
REGULATOR
PG 58
+VCC_GFX_CORE/+1.25V_RUN
+3.3V_SUS/+5V_SUS/+3.3V_RUN
+5V/+3.3V/+1.8V/+1.25_RUN
Panel Connector
LVDS
PG 54
PG 56
REGULATOR
+1.8V_SUS/+0.9V_DDR_VTT
533/667 MHZ DDR II
PG 28
PG 53
DDR2-SODIMM1
Crestline
PG 19
1299 uFCBGA
PG 9,10,11,12,13,14
C
IO Board
CRT CONN.
TV CONN.
VGA
VGA
TVOUT
TVOUT
DDR2-SODIMM2
PG 19
MINI-CARD
WLAN
PCIEx1 (Lane2)
MINI-CARD
WWAN
USB2.0(P9)
USB2.0(P0,P1)
DMI INTERFACE
USB CONN.
PG 39
USB Board
USB2.0(P2,3)
USB CONN.x2
D.B
CON
PCIE (Lane6)
USB2.0(P2,3)
PCIEx1 (Lane2)
USB2.0(P9)
PG 50
PCI
ICH8-M
PCIE (Lane4)
USB2.0(P6)
USB2.0(P7)
676 BGA
PG 15,16,17,18
(Symbol Rev.09)
IHDA
B
533/667 MHZ DDR II
(Symbol Rev.09)
USB2.0(P5)
CAMERA
SIM
CARD
CARD READER
1394/R5C833
BCM5906KMLG
PG 32,33,34
QFN-68 PG 47
B
EXPRESS-CARD
R5538
PG 28
SIM CARD Board
PG 35
AUDIO/AMP
MDC
PG 44,45,46
PG 36
SPI LPC
SATA
SATA-HDD
IDE
CD-ROM
RJ45/Magnetic
PG 48
PG 31
PG 31
S/PDIF
TO TV
CONN.
DIGITAL
MIC.
PG 30
PG 28
Speaker
CON
WtoB
CON
PG 46
PG 46
SIO
SIO
MEC5025
128KB Flash
TMKBC
128 Pins VTQFP
ECE5011
Expander
USB 2.0 Hub(4)
128 Pins VTQFP
BC
PG 37
Audio
Jacks
*3
JACK Board
PROJECT:
5
SPI
RJ11
RJ11 Board
REVISION
DATE:
1.2
SHEET
2
4
PS/2
CIR
FLASH
Touchpad
CON.
FAN &THERMAL
EMC4001
PG 40
PG 41
PG 43
OF
68
PG 41
PG 38
PG 41
Bluetooth
USER
INTERFACE
SNIFFER
PG 42
PG 42
DESCRIPTION:
BLOCK DIAGRAM
3
CAPBTN
CON.
PG 40
DESIGN ENGINEER :
RELEASE DATE :
2
INDEX
Pg#
Description
Description
Pg#
DNI LIST
DNI LIST
01
Cover Page
63
POWER CIRCUIT CHANGE LIST
02
Schematic Block Diagram
64
Modem board cover page
03
INDEX
65
RJ-11 CONN
04
Bus connection
66
Modem board change List
05
SMBUS BLOCK
67
USB board cover page
06
Power Rail
68
USB PORT ( SINGLE * 2 )
07-08
CPU ( Merom Penryn )
09-14
Crestline
15-18
ICH8M
19-20
DDRII SO-DIMM( 533MHz 667MHz )
21
Clock Generator ( CK410M+LP )
22-27
BLANK PAGE
28
LVDS CON & Camera & DMIC
29
RGB CON
30
TV OUT CON
31
SATA(HDD & CD_ROM)
32-34
MEDIA CARD READER / 1394 ( R5C833 )
35
PCI-Express Card
36
MDC CONN
37
EC
38
SIO ( ECE5011 )
39
USB PORT x 2
40
FLASH & RTC & CAPBTN CONN
41
TOUCH PAD & BT & CIR & LID
( MEC5025 )
42
SWITCH & LED
43
HARDWARE MONITOR ( EMC4001 )
44-46
AUDIO CODEC & AMP
47
LOM BCM5906
48
Magnetics and RJ-45
49
Power Control Switch
50
BtoB CON
51
Power Sequence Logic
52
XDP
53-59
Power Circuit
60
SCREW PAD
61
Change List 1
62
Change List 2
PROJECT: Lanai
A
REVISION
DATE:
1.2
SHEET
3
B
OF
68
DESCRIPTION:
INDEX
DESIGN ENGINEER :
RELEASE DATE :
C
PCI TABLE
Footprint Definition
Resistor
Footprint is 0402 if there is no description
Capacitor
Ferrite Bead
PCI
DEVICE
IDSEL
REQ#/GNT#
R5C833
PCI_AD17
PCI_REQ1#
PCI_GNT1#
PIRQ
PCI_PIRQC#
PCI_PIRQD#
Layout Note
For all of ESD diode, they should be placed as close as
possible to connectors and the signals from connectors
should be routed to ESD diodes first. There is no branch
or via before diodes
PCI Express TABLE

Lane 1
WWAN / Mini Card
Lane 2
WLAN / Mini Card
Lane 3
Lane 4
ExpressCard
Lane 5
Lane 6
LAN BCM5906KMLG
USB TABLE
3
ICH8-0
(EHCI#1)
User1
(Single port , in USB BD)
ICH8-1
(EHCI#1)
User2
(Single port , in USB BD)
ICH8-2
(EHCI#1)
User3
(Dual port-bottom , in I/O BD)
ICH8-3
(EHCI#1)
User4
(Dual port-top , in I/O BD)
ICH8-4
(EHCI#1)
4
ICH8-5
(EHCI#1)
Camera
ICH8-6
(EHCI#2)
ExpressCard
ICH8-7
(EHCI#2)
BT Module
ICH8-8
(EHCI#2)
ICH8-9
(EHCI#2)
WWAN / Mini Card

5
Note : No USB for WLAN
PROJECT: Lanai
A
REVISION
1.2
DATE:
SHEET
B
OF
68
DESCRIPTION:
Bus Connection
C
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
D
10K
ICH8-M
AJ26
AD19
ICH_SMBCLK
ICH_SMBDATA
AC17
AE19
AMT_SMBCLK
AMT_SMBDAT
+3.3V_SUS
+3.3V_SUS
2.2K
10K
2.2K
+3.3V_RUN
2.2K
+3.3V_RUN
2.2K
7002
7002
MEM_SCLK 197
MEM_SDATA 195
DIMM 0
MEM_SCLK 197
MEM_SDATA 195
DIMM 1
D
I/O Board
+5V_MEDIA
8.2K
6
5
7
8
8.2K
DOCK_SMBCLK
DOCK_SMBDAT
30
32 WWAN
30
32 WLAN
CAPBTN Board
+3.3V_ALW
+3.3V_RUN
2.2K
2.2K
C
2.2K
2.2K
C
+3.3V_RUN
13
12
CKG_SMBCLK
CKG_SMBDAT
4.7K
100
99
SIO
MEC5025
CLK_SCLK 16
CLK_SDATA 17
7002
7002
+3.3V_ALW
Express Card
CLK GEN.
4.7K
THRM_SMBCLK
THRM_SMBDAT
12
11
+3.3V_ALW
+3.3V_ALW
2.2K
10
9
2.2K
ECE4001
CHARGER
100
112
111
PBAT_SMBCLK
PBAT_SMBDAT
+3.3V_ALW
8
7
Battery
CONN.
100
+3.3V_ALW
8.2K
SMB_CLK 3
SMB_DAT 4
8.2K
LCD_SMBCLK
LCD_SMDDAT
34
35
+3.3V_ALW
+3.3V_RUN
2.2K
47pF
47pF
2.2K
LVDS
Connector
A
LCD_DDCCLK
LCD_DDCDAT
VGA
PROJECT: Lanai
5
REVISION
1.2
DATE:
+3.3V_RUN
SHEET
5
4
43
44
OF
68
DESCRIPTION:
SMBUS BLOCK
3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
ADAPTER
1
+RTC_CELL
+PWR_SRC
BATTERY
+5V_SUS
1.25V_RUN_ON
DDR_ON
1.05_RUN_ON
1.5V_RUN_ON
RUNPWROK
+3.3V_RUN
+1.5V_RUN
+1.05V_VCCP
DDR_ON
SI4800BDY
+1.8V_SUS
0.9V_DDR_VTT_ON
FDS6612A
+VCC_CORE
TPS51100
+3.3V_SUS
1.8V_RUN_ON
+15V_ALW
SUS_ON
SI4800BDY
3.3V_RUN_ON
BAT54S
3.3V_SUS_ON
+3.3V_ALW
+5V_ALW
SI4800BDY
+5V_RUN
SN0508073
SN0508073
+3.3V_RTC
_LDO
RUN_ON
+5V_
ALW2
ALWON
THERM_STP#
ALWON
THERM_STP#
ALWON
THERM_STP#
3
IMVP_VR_ON
ISL6260C
ISL6208
TPS51120
+0.9V_DDR_VTT
+1.25V_RUN
FDS6612A
4
+1.8V_RUN
EMC4001
EE
SIDE
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+2.5V_RUN
PROJECT: Lanai
A
REVISION
DATE:
1.2
SHEET
6
B
OF
68
DESCRIPTION:
Power Rail
C
DESIGN ENGINEER :
RELEASE DATE :
D
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
RSVD01
RSVD02
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
HIT#
HITM#
G6
E4
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
D21
A24
B25
5%
H_INIT#
+1.05V_VCCP
15
H_LOCK# 9
H_RESET#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
9,52
9
9
9
9
9 H_DSTBN#0
9 H_DSTBP#0
9 H_DINV#0
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
1
R160
CPU_PROCHOT#
H_THERMDA
H_THERMDC
2
56Ohm
5%
Layout note:
Place voltage
divider within
0.5" of GTLREF
pin
+1.05V_VCCP
R163
1KOhm
1%
+1.05V_VCCP
9
9
9
H_THERMDA
H_THERMDC
C7
43
43
1
R368
2
56Ohm
5%
H_DSTBN#1
H_DSTBP#1
H_DINV#1
V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
R164
2KOhm
1%
H_THERMTRIP# 43
+1.05V_VCCP
H CLK
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
BCLK0
BCLK1
A22
A21
AD26
C23
D25
C24
AF26
AF1
A26
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
B22
B23
C21
10,21 CPU_MCH_BSEL0
10,21 CPU_MCH_BSEL1
10,21 CPU_MCH_BSEL2
CLK_CPU_BCLK 21
CLK_CPU_BCLK# 21
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
R26
U26
AA1
Y1
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
H_DSTBN#2 9
H_DSTBP#2 9
H_DINV#2 9
H_D#[0..63]
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
9
9
XDP_BPM#0 52
XDP_BPM#1
52
XDP_BPM#2
52
XDP_BPM#3 52
XDP_BPM#4
52
XDP_BPM#5
52
XDP_TCK
52
XDP_TDI
52
XDP_TDO
52
XDP_TMS
52
XDP_TRST#
52
XDP_DBRESET# 17,38,52
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
MISC
BSEL0
BSEL1
BSEL2
C410
H_THERMDC
2200PF/50V
R395
MLCC/+/-10%
/*
R396
1
1
C409
SOCKET478
R399
CPU_TEST1
1KOhm
1% /*
1KOhm
1% /*
H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
CPU_TEST4
/*
CPU_TEST6
Place C close to the

CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.
1
R112
CPU_TEST3
CPU_TEST5
For the purpose of testability, route these signals

through a ground referenced Zo= 55 ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
FSB BCLK
BSEL2 BSEL1 BSEL0
133
667
166
COMP0
COMP1
COMP2
COMP3
533
R120
27.4Ohm
1%
R397
54.9Ohm
1%
27.4Ohm
1%
200
800
R398
R118
54.9Ohm
1%
Voltage Level Shift

+3.3V_ALW
H_PWRGD_XDP 52
T15
+1.05V_VCCP
2
1KOhm 5%
10,15,53
15
9
15
9
53
T27
CPU_TEST2
0.1UF/10V MLCC/+/-10%
2
0Ohm
5% /*
H_D#[0..63] 9
Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.
SOCKET478
H_THERMDA
H_D#[0..63] 9
H_D#[0..63]
9 H_D#[0..63]
H_HIT#
H_HITM#
DATA GRP 2
C1
F3
F4
G3
G2
2
56Ohm
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
15
15
15
15
RESET#
RS0#
RS1#
RS2#
TRDY#
1
R159
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
A20M#
FERR#
IGNNE#
H4
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
A6
A5
C4
LOCK#
H_IERR#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
H_A20M#
H_FERR#
H_IGNNE#
D20
B3
THERMAL
ICH
15
15
15
F1
IERR#
INIT#
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADSTB1#
H_DEFER# 9
H_DRDY# 9
H_DBSY# 9
H_BR0#
9
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
DATA GRP 1
H_ADSTB#1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
ADDR GROUP
1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
H5
F21
E1
H_D#[0..63]
9
9
9
H_D#[0..63]
H_A#[17..35]
BR0#
H_ADS#
H_BNR#
H_BPRI#
U25B
MOLEX/47387-4781
K3
H2
K2
J3
L1
DEFER#
DRDY#
DBSY#
H1
E2
G5
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#[17..35]
H_REQ#[0..4]
ADS#
BNR#
BPRI#
H_D#[0..63]
H_ADSTB#0
H_REQ#[0..4]
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB0#
CONTROL
9
9
DATA GRP 0
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP
0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
XDP/ITP SIGNALS
H_A#[3..16]
RESERVED
U25A
MOLEX/47387-4781
H_A#[3..16]
DATA GRP 3
R161
2.2KOhm
/*
+1.05V_VCCP
1
Comp0,2 connect with Zo=27.4ohm, Comp1,3

connect with Zo=55 ohm, make those traces
length shorter than 0.5". Trace should be
at least 25 mils away from any other
toggling signal.
XDP_TRST#
1%
CPU_PROCHOT#
EC_CPU_PROCHOT# 37
XDP_TCK
1
54.9Ohm
1
54.9Ohm
1
54.9Ohm
1
54.9Ohm
1
649Ohm
XDP_BPM#5
2
R122
2
R119
2
R121
2
R114
2
R117
2 S
XDP_TDI
XDP_TMS
1%
Q54
1%
2N7002
Id=280mA/Pd=300mW
/*
1%
1%
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
7
4
OF
68
DESCRIPTION:
MEROM CPU (1)

3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
+VCC_CORE
+VCC_CORE
+VCC_CORE
All use 10U 4V (+-20% , X6S , 0805)Pb-Free.
U25D
MOLEX/47387-4781
C176
10UF/4V
MLCC/+/-20%
pt_c0805
8 inside cavity, north side, secondary layer.
1
C383
10UF/4V
MLCC/+/-20%
pt_c0805
C159
10UF/4V
MLCC/+/-20%
pt_c0805
1
2
1
C157
10UF/4V
MLCC/+/-20%
pt_c0805
C187
10UF/4V
MLCC/+/-20%
pt_c0805
1
C391
10UF/4V
MLCC/+/-20%
pt_c0805
C152
10UF/4V
MLCC/+/-20%
pt_c0805
1
C386
10UF/4V
MLCC/+/-20%
pt_c0805
C402
10UF/4V
MLCC/+/-20%
pt_c0805
8 inside cavity, south side, secondary layer.
1
C397
10UF/4V
MLCC/+/-20%
pt_c0805
C145
10UF/4V
MLCC/+/-20%
pt_c0805
1
C398
10UF/4V
MLCC/+/-20%
pt_c0805
1
C399
10UF/4V
MLCC/+/-20%
pt_c0805
1
2
1
C181
10UF/4V
MLCC/+/-20%
pt_c0805
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA01
VCCA02
B26
C26
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
AF7 VCCSENSE
VCCSENSE
53
VSSSENSE
AE7 VSSSENSE
VSSSENSE
53
+ CE20
220UF/4V
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20%
+1.5V_RUN
53
53
53
53
53
53
53
SOCKET478
C414
0.01UF/25V
MLCC/+/-10%
pt_c0603
+VCC_CORE
+VCC_CORE
R128
100Ohm
1%
Remove to POWER CIRCUIT .

VCCSENSE
VSSSENSE
VSS082
VSS083
VSS084
VSS085
VSS086
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
SOCKET478
2
C158
10UF/4V
MLCC/+/-20%
pt_c0805
VSS001
VSS002
VSS003
VSS004
VSS005
VSS006
VSS007
VSS008
VSS009
VSS010
VSS011
VSS012
VSS013
VSS014
VSS015
VSS016
VSS017
VSS018
VSS019
VSS020
VSS021
VSS022
VSS023
VSS024
VSS025
VSS026
VSS027
VSS028
VSS029
VSS030
VSS031
VSS032
VSS033
VSS034
VSS035
VSS036
VSS037
VSS038
VSS039
VSS040
VSS041
VSS042
VSS043
VSS044
VSS045
VSS046
VSS047
VSS048
VSS049
VSS050
VSS051
VSS052
VSS053
VSS054
VSS055
VSS056
VSS057
VSS058
VSS059
VSS060
VSS061
VSS062
VSS063
VSS064
VSS065
VSS066
VSS067
VSS068
VSS069
VSS070
VSS071
VSS072
VSS073
VSS074
VSS075
VSS076
VSS077
VSS078
VSS079
VSS080
VSS081
R127
100Ohm
1%
1
C134
10UF/4V
MLCC/+/-20%
pt_c0805
1
C172
10UF/4V
MLCC/+/-20%
pt_c0805
1
C396
10UF/4V
MLCC/+/-20%
pt_c0805
1
2
1
C133
10UF/4V
MLCC/+/-20%
pt_c0805
100U/25V *4
10UF/4V
pt_c0805
MLCC/+/-20%
Layout Note:
Place 0.01U/25V near PIN
B26.
6 inside cavity, north side, primary layer.
C179
10UF/4V
MLCC/+/-20%
pt_c0805
C418
C126
10UF/4V
MLCC/+/-20%
pt_c0805
+VCC_CORE
VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
+1.05V_VCCP
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
C131
10UF/4V
MLCC/+/-20%
pt_c0805
+VCC_CORE
C180
10UF/4V
MLCC/+/-20%
pt_c0805
+VCC_CORE
C392
10UF/4V
MLCC/+/-20%
pt_c0805
1
C400
10UF/4V
MLCC/+/-20%
pt_c0805
1
C166
10UF/4V
MLCC/+/-20%
pt_c0805
1
C183
10UF/4V
MLCC/+/-20%
pt_c0805
+VCC_CORE
C390
10UF/4V
MLCC/+/-20%
pt_c0805
VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099
VCC100
C140
10UF/4V
MLCC/+/-20%
pt_c0805
VCC001
VCC002
VCC003
VCC004
VCC005
VCC006
VCC007
VCC008
VCC009
VCC010
VCC011
VCC012
VCC013
VCC014
VCC015
VCC016
VCC017
VCC018
VCC019
VCC020
VCC021
VCC022
VCC023
VCC024
VCC025
VCC026
VCC027
VCC028
VCC029
VCC030
VCC031
VCC032
VCC033
VCC034
VCC035
VCC036
VCC037
VCC038
VCC039
VCC040
VCC041
VCC042
VCC043
VCC044
VCC045
VCC046
VCC047
VCC048
VCC049
VCC050
VCC051
VCC052
VCC053
VCC054
VCC055
VCC056
VCC057
VCC058
VCC059
VCC060
VCC061
VCC062
VCC063
VCC064
VCC065
VCC066
VCC067
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
1
C132
10UF/4V
MLCC/+/-20%
pt_c0805
1
C385
10UF/4V
MLCC/+/-20%
pt_c0805
1
C403
10UF/4V
MLCC/+/-20%
pt_c0805
U25C
MOLEX/47387-4781
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
6 inside cavity, south side, primary layer.

+VCC_CORE
+1.05V_VCCP
CE6
CE5
CE19
C124
0.1UF/10V
MLCC/+/-10%
CE16
CE18
CE7
220UF/2V
pt_c7343d_h75
SANYO/2TPF220M7
/*
220UF/2V
pt_c7343d_h75
SANYO/2TPF220M7
220UF/2V
pt_c7343d_h75
SANYO/2TPF220M7
/*
220UF/2V
pt_c7343d_h75
SANYO/2TPF220M7
220UF/2V
pt_c7343d_h75
SANYO/2TPF220M7
C405
0.1UF/10V
MLCC/+/-10%
C193
0.1UF/10V
MLCC/+/-10%
C404
0.1UF/10V
MLCC/+/-10%
C380
0.1UF/10V
MLCC/+/-10%
No.43
C381
0.1UF/10V
MLCC/+/-10%
Route VCCSENSE and VSSSENSE

traces at 27.4ohms with 50
mils spacing and length
matched to within 25 mil.
Place PU and PD within
1 inch of CPU.
A
220UF/2V
pt_c7343d_h75
SANYO/2TPF220M7
Layout out:
Place these inside socket cavity on North side secondary.
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
8
4
OF
68
DESCRIPTION:
Merom CPU (2)

3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
+1.05V_VCCP
H_SWING
1
R367
221Ohm
1%
C371
0.1UF/10V
MLCC/+/-10%
R366
100Ohm
1%
R130
54.9Ohm
1%
+1.05V_VCCP
R129
54.9Ohm
1%
H_SCOMP
H_SCOMP#
H_RCOMP
Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
+1.05V_VCCP
H_SWING
H_RCOMP
B3
C2
H_SWING
H_RCOMP
R132
24.9Ohm
1%
H_A#[3..35]
U10A
H_D#[0..63]
H_D#[0..63]
H_SCOMP
H_SCOMP#
W1
W2
H_SCOMP
H_SCOMP#
B6
E5
H_CPURST#
H_CPUSLP#
R364
1KOhm
1%
HOST
7,52 H_RESET#
7
H_CPUSLP#
H_REF
1
B9
A9
H_A#[3..35]
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
H_ADS#
7
H_ADSTB#0 7
H_ADSTB#1 7
H_BNR#
7
H_BPRI#
7
H_BR0#
7
H_DEFER#
7
H_DBSY#
7
CLK_MCH_BCLK 21
CLK_MCH_BCLK# 21
H_DPWR#
7
H_DRDY#
7
H_HIT#
7
H_HITM#
7
H_LOCK#
7
H_TRDY#
7
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
K5
L2
AD13
AE13
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
7
7
7
7
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
M7
K3
AD2
AH11
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
7
7
7
7
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L7
K2
AC2
AJ10
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
7
7
7
7
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
M14
E13
A11
H13
B12
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
7
7
7
7
7
H_RS#_0
H_RS#_1
H_RS#_2
E12
D7
D8
H_RS#0
H_RS#1
H_RS#2
7
7
7
H_AVREF
H_DVREF
CRESTLINE_965GM
C367
0.1UF/10V
MLCC/+/-10%
R365
2KOhm
1%
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
Layout Note:
Place the 0.1uF
decoupling capacitor
within 100 mils from
GMCH pins.
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
9
4
OF
68
DESCRIPTION:
Crestline(HOST)
3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
+1.8V_SUS
U10C
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
19,20
19,20
19,20
19,20
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
BG20
BK16
BG16
BE13
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
19,20
19,20
19,20
19,20
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
BH18
BJ15
BJ14
BE16
M_ODT0
M_ODT1
M_ODT2
M_ODT3
L_IBG
43 THERMTRIP_MCH#
17,53 DPRSLPVR
PLTRST#_R
THERMTRIP_MCH#
1
2
R332 0Ohm 5%
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
16
16
16
16
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AM47
AJ39
AN41
AN45
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
16
16
16
16
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AJ46
AJ41
AM40
AM44
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
16
16
16
16
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AJ47
AJ42
AM39
AM43
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
16
16
16
16
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
H35
K36
G39
G40
TEST_1
TEST_2
A37
R32
CRESTLINE_965GM
T90
T13
T12
T11
T89
16,35,37 PLTRST#
1
R360
2
0Ohm 5%
PROJECT: Lanai
5
REVISION
1.2
R358
2
50
M35
P33
TV_DCONSEL_0
TV_DCONSEL_1
H32
G32
K29
J29
F29
E29
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
VGA_BLU
VGA_GRN
50
VGA_RED
R341
R330
R338
VGAVSYNC
C86
0.1UF/10V
MLCC/+/-10%
VGA_GRN
VGA_RED
K33
G35
2 30Ohm pt_r0603 1%
F33
2 1.3KOhm pt_r0603 0.5% C32
30Ohm
pt_r0603
1%
2
E33
1
1
1
R327
R324
R329
R334
LCTLA_CLK, LCTLB_DATA
connect to XDP CONN.
R327,R324 Stuff.
1
1
1
1
2
2
2
2
10KOhm 5%
10KOhm 5%
2.2KOhm 5%
2.2KOhm 5%
CFG9
CFG16
CFG19
R326
0Ohm
5%
CFG20
DMI X2 Select
PCI Express
Graphic Lane
FSB Dynamic
ODT
DMI Lane
Reversal
SDVO/PCIE
Concurrent
Operation
SDVO_CRTL_DATA SDVO Present.
SHEET
10
4
OF
68
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
VGA_BLU
VGA_GRN
VGA_RED
UMA
/* LCTLA_CLK
/* LCTLB_DATA
LCD_DDCCLK
LCD_DDCDATA
100Ohm 5%
PLTRST#_R
1
DATE:
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
CRESTLINE_965GM
+3.3V_RUN
R84
392Ohm
1%
pt_r0603
VGA_BLU
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
R0933,R0937
Intel 30.1
ohm 1%
R82
1KOhm
1%
CLK_3GPLLREQ# 21
MCH_ICH_SYNC# 17
2
0Ohm 5% /*
TVA_RTN
TVB_RTN
TVC_RTN
R344
150Ohm
1%
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
No.2
R536
0Ohm
5%
R343
R342
R340
150Ohm 150Ohm 150Ohm
1%
1%
1%
R537
0Ohm
5%
UMA
Layout Note:
Place 150 ohm
termination resistors
close to GMCH
MCH_CLVREF
R339
20KOhm
5%
1
R357
F27
J27
L27
R350
150Ohm
1%
CL_CLK0
17
CL_DATA0 17
ICH_CL_PWROK 17,37
ICH_CL_RST0# 17
16 SB_NB_PCIE_RST#
TVA_DAC
TVB_DAC
TVC_DAC
50
1
MCH_CLVREF
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
E27
G27
K27
50
50 G_CLK_DDC2
50 G_DAT_DDC2
50 VGAHSYNC
Non-iAMT
AM49
AK50
AT43
AN49
AM50
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
TV_CVBS
TV_Y
TV_C
CFG5
NC
T2
T4
T8
T7
T10
T16
T17
T22
T21
T20
T19
T3
T5
T6
T9
T18
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
E44
A47
A45
G41
L39
L36
J36
AW49
AV20
N20
G36
PM_EXTTS#0
PM_EXTTS#1
LCD_B0+
LCD_B1+
LCD_B2+
R345
150Ohm
1%
+1.25V_RUN
PM
17 PM_BMBUSY#
7,15,53 H_DPRSTP#
19
PM_EXTTS#0
19
PM_EXTTS#1
17,51 ICH_PWRGD
28
28
28
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
1
1
1
1
1
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
AN47
AJ38
AN42
AN46
E35
A39
C38
B39
E36
G44
B47
B45
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
LCD_B0LCD_B1LCD_B2-
2
2
28
28
28
CLK_MCH_3GPLL 21
CLK_MCH_3GPLL# 21
50
50
50
R333
R336
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
K44
K45
R359
+3.3V_RUN
CFG3
CFG4
1% /* CFG5
CFG6
CFG7
CFG8
1% /* CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
1% /* CFG16
CFG17
CFG18
1% /* CFG19
1% /* CFG20
G50
E50
F48
PEG_CLK
PEG_CLK#
DMI
1
1
4.02KOhm
1
1
1
4.02KOhm
1
1
1
1
1
1
4.02KOhm
1
1
4.02KOhm
4.02KOhm
MCH_DREFCLK 21
MCH_DREFCLK# 21
DREF_SSCLK 21
DREF_SSCLK# 21
GRAPHICS VID
R355
T111
T14
1
T110
T93
T113
1
T105
T107
T109
T100
T112
T98
1
T99
T91
1
1
LCD_A0+
LCD_A1+
LCD_A2+
B42
C42
H48
H47
ME
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
CFG
R356
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
28
28
28
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
MISC
7,21 CPU_MCH_BSEL0
7,21 CPU_MCH_BSEL1
7,21 CPU_MCH_BSEL2
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
VGA
V_DDR_MCH_REF
Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.
G51
E51
F49
THERMTRIP_MCH#
LCD_A0LCD_A1LCD_A2-
R363
20Ohm
1%
BK31 SM_RCOMP_VOH
BL31 SM_RCOMP_VOL
AR49
AW4
SM_VREF_0
SM_VREF_1
28
28
28
5%
BL15 SMRCOMPP
BK14 SMRCOMPN
R354
1
56Ohm
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
TV
No.10
SM_RCOMP_VOH
SM_RCOMP_VOL
SMRCOMPP
SMRCOMPN
+1.05V_VCCP
SM_RCOMP
SM_RCOMP#
R110
20Ohm
1%
19,20
19,20
19,20
19,20
19,20 DDR_A_MA14
19,20 DDR_B_MA14
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
2 10KOhm 5% PM_EXTTS#0
2 10KOhm 5% PM_EXTTS#1
1
1
LCD_ACLKLCD_ACLK+
LCD_BCLKLCD_BCLK+
L41
L43
N41
N40
D46
C45
D44
E42
+1.8V_SUS
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
Low=DMIx2
High=DMIx4 (Default)
Low=Reveise Lane
High=Normal operation
Low=Dynamic ODT Disable
High=Dynamic ODT Enable (default)
Low=Normal (default)
High=Lane Reversed
Low=Only SDVO or PCIEx1 is
operational (defaults)
High=SDVO and PCIEx1 are operating
sumultaneously via PEG port
R335
R337
28
28
28
28
+3.3V_RUN
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
DDR_A_MA14 BJ29
DDR_B_MA14 BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
MUXING
R352
1KOhm
0.1%
DDR
C109
2.2UF/10V
MLCC/+/-10%
c0603,pt_c0603
CLK
1
2
1
2
C108
0.01UF/25V
MLCC/+/-10%
T86
UMA
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
+VCC_PEG
R90
24.9Ohm 1%
1
2
BE29
AY32
BD39
BG37
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
19
19
19
19
PEG_COMPI
PEG_COMPO
N43 VCC3G_PCIE_R
M43
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
LCTLA_CLK
LCTLB_DATA
LCD_DDCCLK
LCD_DDCDATA
GRAPHICS
AW30
BA23
AW25
AW23
52
52
28
28
R325
2.4KOhm
1%
PCI-EXPRESS
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
19
19
19
19
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS
AV29
BB23
BA25
AV23
SM_RCOMP_VOL
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
J40
H39
E39
E40
C37
D35
K40
R348
3.01KOhm
1%
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
28
BIA_PWM
38 PANEL_BKEN
LCTLA_CLK
LCTLB_DATA
LCD_DDCCLK
LCD_DDCDAT
28
ENVDD
1
2
C353
2.2UF/10V
MLCC/+/-10%
c0603,pt_c0603
L_IBG
RSVD
C351
0.01UF/25V
MLCC/+/-10%
SM_RCOMP_VOH
P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20
U10B
R351
1KOhm
0.1%
Low=No SDVO Device Present

(defaults)
High=SDVO Device Prsent
DESCRIPTION:
Crestline(VGA,DMI)
3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
BL17
DDR_A_CAS#
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AT46 DDR_A_DQS0
BE48 DDR_A_DQS1
BB43 DDR_A_DQS2
BC37 DDR_A_DQS3
BB16 DDR_A_DQS4
BH6 DDR_A_DQS5
BB2 DDR_A_DQS6
AP3 DDR_A_DQS7
AT47 DDR_A_DQS#0
BD47 DDR_A_DQS#1
BC41 DDR_A_DQS#2
BA37 DDR_A_DQS#3
BA16 DDR_A_DQS#4
BH7 DDR_A_DQS#5
BC1 DDR_A_DQS#6
AP2 DDR_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
SA_RAS#
SA_RCVEN#
BE18
AY20
DDR_A_RAS#
T114
1
SA_WE#
BA19
DDR_A_WE#
19,20
19,20
19,20
DDR_A_CAS# 19,20
DDR_A_DM[0..7] 19
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
DDR_A_MA[0..13]
DDR_A_RAS#
DDR_A_WE#
19
19
19,20
19,20
19,20
CRESTLINE_965GM
U10E
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
19 DDR_B_D[0..63]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
MEMORY
BB19
BK19
BF29
SYSTEM
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
SA_BS_0
SA_BS_1
SA_BS_2
DDR
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
MEMORY
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
SYSTEM
U10D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR
19 DDR_A_D[0..63]
SB_BS_0
SB_BS_1
SB_BS_2
AY17
BG18
BG36
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
SB_CAS#
BE17
DDR_B_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
SB_RAS#
SB_RCVEN#
AV16
AY18
DDR_B_RAS#
T108
1
SB_WE#
BC17
DDR_B_WE#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
19,20
19,20
19,20
DDR_B_CAS# 19,20
DDR_B_DM[0..7] 19
DDR_B_DQS[0..7]
19
DDR_B_DQS#[0..7]
19
DDR_B_MA[0..13] 19,20
DDR_B_RAS#
19,20
DDR_B_WE#
19,20
CRESTLINE_965GM
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
11
4
OF
68
DESCRIPTION:
Crestline(DDR2)
3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37
1
2
C343
0.22UF/10V
MLCC/+/-10%
pt_c0603
C341
0.22UF/10V
MLCC/+/-10%
pt_c0603
C346
0.1UF/10V
MLCC/+/-10%
pt_c7343d_h79
Layout Note:
Inside GMCH
cavity
+1.05V_VCCP
CE9
220UF/2.5V
pt_c7343d_h75
+/-20%
CE10
220UF/2.5V
+/-20%
pt_c7343d_h75
/*
CE4
220UF/2.5V
pt_c7343d_h75
+/-20%
+VCC_AXG
CE8
220UF/2.5V
+/-20%
pt_c7343d_h75
/*
Layout Note:
Inside GMCH cavity for VCC_AXG.
1
2
1
2
C368
0.47UF/10V
MLCC/+/-10%
pt_c0603
1
2
C334
0.1UF/10V
MLCC/+/-10%
1
2
+VCC_AXG
C332
0.1UF/10V
MLCC/+/-10%
C340
C342
1UF/10V
10UF/6.3V
MLCC/+/-10% MLCC/+/-20%
pt_c0603
pt_c0805_h53
C326
22UF/4V
MLCC/+/-20%
pt_c0805_h53
VSS NCTF
1
2
C366
22UF/4V
MLCC/+/-20%
pt_c0805_h53
220UF/4V
1
CE15
2
TAN/Lf_T=2000hrs_105C/+/-20%
2
1
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50
AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33
C349
0.1UF/10V
MLCC/+/-10%
C347
0.1UF/10V
MLCC/+/-10%
C348
0.1UF/10V
MLCC/+/-10%
+VCC_AXM
C350
0.22UF/10V
MLCC/+/-10%
pt_c0603
C321
22UF/4V
MLCC/+/-20%
pt_c0805_h53
Non-iAMT
C337
0.22UF/10V
MLCC/+/-10%
pt_c0603
Layout Note:
Place close to GMCH edge.
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
POWER
Layout Note:
Inside GMCH cavity
+1.05V_VCCP
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS SCB
Layout Note:
370mils form edge.
VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
A3
B2
C1
BL1
BL51
A51
AT33 +VCC_AXM
AT31
AK29
AK24
AK23
AJ26
AJ23
CRESTLINE_965GM
C344
1UF/10V
MLCC/+/-10%
pt_c0603
C333
0.47UF/10V
MLCC/+/-10%
pt_c0603
C360
0.22UF/10V
MLCC/+/-10%
pt_c0603
C376
0.22UF/10V
MLCC/+/-10%
pt_c0603
C369
0.1UF/10V
MLCC/+/-10%
C370
0.1UF/10V
MLCC/+/-10%
Layout Note:
Place C1117 where LVDS
andDDR2 taps
C92
22UF/4V
MLCC/+/-20%
pt_c0805_h53
CE11
330UF/6.3V
pt_c7343d_h110
+/-20%
C95
0.1UF/10V
MLCC/+/-10%
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
+1.8V_SUS
1
AW45
BC39
BE39
BD17
BD4
AW8
AT6
Layout Note:
370 mils form edge.
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
+VCC_GMCH
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
+1.05V_VCCP
R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
VCC SM LF
+VCC_AXG
VCC GFX NCTF
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC SM
POWER
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
+1.8V_SUS
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_13
D11
2
RB751V_40
VCC CORE
R30
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC GFX
+VCC_GMCH AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
U10F
10Ohm 5%
2 +VCC_GMCH_L
VCC AXM
+3.3V_RUN
R143
1
U10G
VCC NCTF
VCC AXM NCTF
C91
22UF/4V
MLCC/+/-20%
pt_c0805_h53
Layout Note:
Place on the edge
C328
1UF/10V
MLCC/+/-10%
pt_c0603
CRESTLINE_965GM
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
12
4
OF
68
DESCRIPTION:
Crestline(VCC,NCTF)
3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
FB_180ohm+-25_100mHz_1500mA_0.09ohm DC
0Ohm /*
AN2
VCCD_HPLL
+VCCA_PEG_PLL
U48
VCCD_PEG_PLL
+VCCD_LVDS
J41
H42
VCCD_LVDS_1
VCCD_LVDS_2
C338
C329
1UF/10V
10UF/6.3V
MLCC/+/-10% MLCC/+/-20% CRESTLINE_965GM
pt_c0603
pt_c0805_h53
1
1
12
2
+
CE17
+3.3V_RUN
220UF/4V
Non-
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
BK24
BK23
BJ24
BJ23
2
2
Place caps close to

VCC_AXF
C320
0.1UF/10V
MLCC/+/-10%
+VCC_SM_CK
Place JP1206 for +1.8V_SUS
+VCC_TX_LVDS
1
+3.3V_RUN
AD51
W50
W51
V49
V50
VCC_RXR_DMI_1
VCC_RXR_DMI_2
AH50
AH51
C330
1000PF/50V
MLCC/+/-10%
0Ohm
JP3
+1.8V_RUN
0Ohm /*
JUMP
+1.05V_VCCP
L25
1
+VCC_RXR_DMI
CE1
220UF/4V
VTTLF1
VTTLF2
VTTLF3
1UH/300mA pt_l0805_h53
CE3
220UF/4V
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20%
+VCC_PEG
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
C90
0.1UF/10V
MLCC/+/-10%
C40
B40
1 +VCC_TX_LVDS_R 1
2
1
A43
+1.8V_SUS
JP2
L8
VCC_HV_1
VCC_HV_2
C117
10UF/6.3V
MLCC/+/-20%
pt_c0805_h53
+1.25V_RUN
1uH+-20%_300mA
VCC_TX_LVDS
+VCC_AXF
C116
1UF/10V
MLCC/+/-10%
pt_c0603
+VCC_AXF
AJ50
pad for
Place caps
close to
VCC_AXD
B23
B21
A21
VCC_DMI
1
2 +VCC_AXD_R 1
0Ohm
0Ohm
C355
pt_r0603 Reserved L1202
22UF/10V
5%
inductor
MLCC/+80%-20%
pt_c1206_h71
C354
1UF/10V
MLCC/+/-10%
pt_c0603
AXD
VCC_AXD_NCTF
AR29
+VCC_AXD_L
+1.25V_RUN
JP8
1
2
CRT
AT23
AU28
AU24
AT29
AT25
AT30
A7 +VTTLF1
F2 +VTTLF2
AH1 +VTTLF3
VCCD_CRT
VCCD_TVDAC
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
JUMP
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
C377
4.7UF/10V
MLCC/+/-10%
pt_c0805_h37
Place on the edge
91NH/1.5A
91nH+-20%_1.5A
C83
10UF/6.3V
MLCC/+/-20%
M08 CKT: 91uH+-20%_1.5A
pt_c0805_h53
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20%
need to be confirm
+1.05V_VCCP
L24
1
C25
B25
C27
B27
B28
A28
VCCD_QDAC
1
1
VCCA_SM_CK_1
VCCA_SM_CK_2
N28
JP6
+1.8V_RUN
BC29
BB29
M32
L29
0Ohm
C323
10UF/6.3V
MLCC/+/-20%
pt_c0805_h53
+1.8V_SUS
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
+VCCQ_TVDAC_R
JP5
C322
0.1UF/10V
MLCC/+/-10%
AT22
AT21
AT19
AT18
AT17
AR17
AR16
POWER
+VCCD_TVDAC_R
C122
0.1UF/10V
MLCC/+/-10%
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
R142
10Ohm 5%
/*
+1.05V_VCCP
CE2
2
B
91NH/1.5A
91nH+-20%_1.5A
C84
10UF/6.3V
220UF/4V
MLCC/+/-20%
pt_c7343d_h79
pt_c0805_h53
TAN/Lf_T=2000hrs_105C/+/-20%
2
JUMP
+VCC_TVDACB_R
VCCA_PEG_PLL
AW18
AV19
AU19
AU18
AU17
D12
RB751V_40
/*
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20% iAMT
+1.25V_RUN
+VCC_TVDACA_R
U51
C363
0.47UF/6.3V
MLCC/+/-10%
C104
0.1UF/10V
MLCC/+/-10%
Place JP1204 for

+1.8V_SUS
Non-iAMT
C325
0.1UF/10V
MLCC/+/-10%
R318
1Ohm 1%
pt_r0603
FB_220ohm+-25_100MHz
_2A_0.1ohm DC
pt_l0805_h41
+1.25V_RUN
+1.25V_RUN
VSSA_PEG_BG
C373
4.7UF/10V
MLCC/+/-10%
pt_c0805_h37
Place on the edge
C106
1UF/10V
MLCC/+/-10%
pt_c0603
C105
1UF/10V
MLCC/+/-10%
pt_c0603
1
2
C103
22UF/4V
MLCC/+/-20%
pt_c0805_h53
+VCC_TVDACC_R
L27
BLM21PG221SN1D
220Ohm/100Mhz
1
2 +VCCA_PEG_PLL
K49
C374
2.2UF/6.3V
MLCC/+/-10%
pt_c0603
+VCC_HV_L
+VCCA_SM_CK
JUMP
VCCA_PEG_BG
VTTLF
C362
1UF/10V
MLCC/+/-10%
pt_c0603
C358
22UF/4V
MLCC/+/-20%
pt_c0805_h53
C357
22UF/4V
MLCC/+/-20%
pt_c0805_h53
2
1
0Ohm
K50
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
L29
AXF
+VCCA_PEG_PLL
JP4
1
+1.25V_RUN
VSSA_LVDS
SM CK
C85
0.1UF/10V
MLCC/+/-10%
+VCCA_SM
C361
4.7UF/6.3V
MLCC/+/-10%
pt_c0603
Non-iAMT
JP7
1
2
0Ohm
+ CE14
100UF/6.3V
pt_c3528_h79
+/-20%
+1.25V_RUN
VCCA_LVDS
B41
HV
C324
0.1UF/10V
MLCC/+/-10%
JUMP
C121
0.1UF/10V
MLCC/+/-10%
VCCA_MPLL
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VCCA_HPLL
+VCCA_MPLL
AM2
C336
1000PF/50V
2
1 +VCC_TX_LVDS A41
VTT
VCCA_DPLLB
AL2
PEG
+ CE12
470UF/4V
pt_c7343d_h157
+/-20%
H49
+VCCA_HPLL
+3.3V_RUN
+VCCA_DPLLB
2
1
0.1Caps should be
placed 200 mils
with in its pins.
C382
22UF/10V
MLCC/+80%-20%
pt_c1206_h71
+VCCA_DPLLB
+VCCA_MPLL
BLM18AG121SN1D
R136
1
2
0.5Ohm 1%
pt_r0603
VCCA_DPLLA
MLCC/+/-10%
10uH
pt_l0805
+VCC_MPLL_L
C327
0.1UF/10V
MLCC/+/-10%
L26
+VCCA_DPLL
L16
120Ohm/100Mhz
1
2
B49
DMI
C375
0.1UF/10V
MLCC/+/-10%
C378
22UF/10V
MLCC/+80%-20%
pt_c1206_h71
BLM18AG121SN1D
+VCCA_HPLL
+ CE13
470UF/4V
pt_c7343d_h157
+/-20%
VSSA_DAC_BG
A PEG
10uH
pt_l0805
VCCA_DAC_BG
B32
+VCCA_DPLLA
+VCCA_DPLLA
2
1
L30
120Ohm/100Mhz
1
2
L23
+1.25V_RUN
A30
PLL
40mA MAx.
10uH+-20%_100mA
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
A CK
+1.25V_RUN
45mA MAX.
FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC
Non-iAMT
A33
B33
A LVDS
+VCC_TVBG_R
+VCCA_CRTDAC_R
C345
0.1UF/10V
MLCC/+/-10%
A SM
/*
VCCSYNC
D TV/CRT
GND 22NF/16V
+1.05V_VCCP
U10H
J32
+3.3V_RUN
3OUT
TV
0Ohm 5% pt_r0603
+VCCA_CRTDAC_R
2
R102
1
U7
IN1
C100
0.1UF/10V
MLCC/+/-10%
LVDS
180Ohm
+VCCA_CRTDAC
2
BLM18PG181SN1
L11
1
+3.3V_RUN
+VTTLF1
+VTTLF2
+VTTLF3
GND 22NF/16V
C127
0.47UF/10V
MLCC/+/-10%
pt_c0603
C372
0.47UF/10V
MLCC/+/-10%
pt_c0603
3OUT
0Ohm 5% pt_r0603
+VCC_TVDACA_R
2
C129
0.47UF/10V
MLCC/+/-10%
pt_c0603
/*
R349
1
U21
IN1
+VCC_SM_CK
/*
pt_l0805_h53
R109
1Ohm
1%
pt_r0603
1uH+-20%_300mA
GND 22NF/16V
C113
C111
0.1UF/10V
22UF/10V
MLCC/+80%-20%MLCC/+/-10%
pt_c1206_h71
2
C339
0.1UF/10V
MLCC/+/-10%
/*
R331
0Ohm 5% pt_r0603
+VCCD_TVDAC_R
1
2
U19
IN1
3OUT
3OUT
GND 22NF/16V
+1.8V_SUS
L13
1UH/300mA
+1.5V_RUN
0Ohm 5% pt_r0603
+VCC_TVDACB_R
2
R361
1
U24
IN1
2
0Ohm 5% pt_r0603
R111 30mOhm 1%
+VCC_TVDACB
+VCC_TVBG
2
1
2
pt_r0603
OUT
C365
C364
3
0.1UF/10V
0.1UF/10V
GND
MLCC/+/-10%
MLCC/+/-10%
22NF/16V
/*
1
R362
1
U23
IN1
C356
0.1UF/10V
MLCC/+/-10%
+VCC_TVBG_R
No.45
2
22nF & 0.1uF for

VCC_TVDACA:C_R should
be placed with in 250
mils from Crestline.
+VCC_TVDACA
C115
10UF/6.3V
MLCC/+/-20%
pt_c0805_h53
180Ohm
2
BLM18PG181SN1
L14
1
+3.3V_RUN
FB_180ohm+-25_100mHz_1500mA_0.09ohm DC
+VCC_SM_CK_L
/*
100mHz_1500mA_
0.09ohm DC
TV DAC Voltage Follower Circuit -700mV.
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
13
4
OF
68
1
GND 22NF/16V
Crestline(POWER)
3
C110
10UF/6.3V
MLCC/+/-20%
pt_c0805_h53
C538
/*
DESCRIPTION:
No.7
1
GND 22NF/16V
+VCCQ_TVDAC
1
2
100Ohm pt_r0603
C335
0.1UF/10V
MLCC/+/-10%
FB_180ohm+-25_
1UF/10V
MLCC/+/-10%
3OUT
R328
0Ohm 5% pt_r0603
+VCCQ_TVDAC_R
1
2
U18
IN1
3OUT
2
R538
R113 10Ohm
2
2+VCC_TVDAC_L 1
5% /*
/*
No.7
D10
1
RB751V_40
C359
0.1UF/10V
MLCC/+/-10%
0Ohm 5% pt_r0603
+VCC_TVDACC_R
2
+3.3V_RUN
+1.5V_RUN
+VCC_TVDACC
R353
1
U22
IN1
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
U10I
A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
U10J
C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
VSS
CRESTLINE_965GM
CRESTLINE_965GM
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
4
14
OF
68
DESCRIPTION:
Crestline(VSS)
3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
ICH_LAN100_SLP
ICH_INTVRMEN
ICH_RTCX1
5%
R190
0Ohm 5%
/*
R230
0Ohm 5%
/*
D
1
R210
56Ohm
5%
R203
56Ohm
5%
/*
2
R186
56Ohm
5%
/*
and VccCL1.05)
Low = Internal VR Disabled

High = Internal VR Enable(Default)
2
+RTC_CELL
ICH_LAN100_SLP
Low = Internal VR Disabled

High = Internal VR Enable(Default)
ICH8M LAN100SLP Strap

(Internal VR for VccLAN1.05
ICH8M Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5 and VccCL1.5)
ICH_INTVRMEN
+1.05V_VCCP
C412
15PF/50V
MLCC/+/-5%
/*
R231
332KOhm
1%
2
0Ohm
R187
332KOhm
1%
C424
15PF/50V
MLCC/+/-5%
/*
5%
1
R384
+RTC_CELL
X3
+/-10ppm/6PF
32.768KHZ
4
2
10MOhm
No.25
ICH_RTCX2
+RTC_CELL
R400
H_DPRSTP#
5%
R219
1 33Ohm
5%
C215
27PF/50V
MLCC/+/-5%
36 ICH_AZ_MDC_SYNC
44 ICH_AZ_CODEC_SYNC
36 ICH_AZ_MDC_RST#
44 ICH_AZ_CODEC_RST#
36 ICH_AZ_MDC_SDOUT
44 ICH_AZ_CODEC_SDOUT
2
2
1 33Ohm
1 33Ohm
5%
5%
ACZ_SYNC
2
2
1 33Ohm
1 33Ohm
5%
5%
ACZ_RST#
R213
R220
2
2
1 33Ohm
1 33Ohm
5%
5%
ACZ_SDOUT
D21
E20
C20
LAN_TXD0
LAN_TXD1
LAN_TXD2
AH21
2 GLAN_COMP
24.9Ohm 1%
ACZ_BIT_CLK
ACZ_SYNC
46 SPEAKER_DET#
40 RTC_BAT_DET#
SATA_RX0SATA_RX0+
MLCC/+/-10%
MLCC/+/-10%
Distance between the ICH-8 M and cap on the "P" signal

should be identical distance between the ICH-8 M and cap on
the "N" signal for same pair.
AE13
HDA_SDOUT
SPEAKER_DET#
RTC_BAT_DET#
AE10
AG14
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
SATA_ACT#
AF10
SATALED#
AF6
AF5
AH5
AH6
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AG3
AG4
AJ4
AJ3
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AF2
AF1
AE4
AE3
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
21 CLK_PCIE_SATA#
21 CLK_PCIE_SATA
Place within 500 mils

of ICH8 ball
+3.3V_RUN
The circuit is only

needed if the
platform has the
SNIFFER.
1
R198
HDA_BIT_CLK
HDA_SYNC
ACZ_SDOUT
SATA_TX0-_C
SATA_TX0+_C
1 3900PF/50V
1 3900PF/50V
2
2
SATABIAS
24.9Ohm 1%
AB7
AC6
SATA_CLKN
SATA_CLKP
AG1
AG2
SATARBIAS#
SATARBIAS
H_FERR#
CPUPWRGD/GPIO49
AG29
H_PWRGOOD 7
IGNNE#
AF27
H_IGNNE#
INIT#
INTR
RCIN#
AE24
AC20
AH14
H_INIT#
H_INTR
SIO_RCIN#
7
7
37
NMI
SMI#
AD23
AG28
H_NMI
H_SMI#
7
7
STPCLK#
AA24
H_STPCLK#
THRMTRIP#
AE27
TP8
AA23
H_DPRSTP#
H_DPSLP#
7,10,53
7
SIO_A20GATE
H_FERR#
SIO_RCIN#
C
+1.05V_VCCP
R194
56Ohm
5%
THERMTRIP#_ICH
THERMTRIP#_ICH
T42
1
IDE_DD[0..15]
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
DA0
DA1
DA2
AA4
AA1
AB3
IDE_DA0
IDE_DA1
IDE_DA2
Y6
Y5
IDE_DCS1#
IDE_DCS3#
DCS1#
DCS3#
R167
10KOhm
5%
R192
10KOhm
5%
SIO_A20GATE 37
H_A20M#
7
SIO_RCIN#
AD24
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
W4
W3
Y2
Y3
Y1
W5
IDE_DD[0..15]
31
IDE_DA0
IDE_DA1
IDE_DA2
31
31
31
IDE_DCS1#
IDE_DCS3#
31
31
IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_DIORDY
IDE_DDREQ
31
31
31
31
31
31
+3.3V_RUN
RSVD
Enter XOR chain
Normal operation (Default)
Set PCIE port config bit 1
ICH_RSVD
Q37 2N7002
Id=180mA/Pd=300mW
R181
1KOhm
5%
/*
REVISION
1.2
DATE:
SHEET
15
4
OF
68
R209
100KOhm
5%
SPEAKER_DET#
RTC_BAT_DET#
1
0Ohm 5% /*
R196
100KOhm
5%
17
0
SATA_ACT#
PROJECT: Lanai
+3.3V_RUN
S 2
1
3
D
AF26
AE26
FERR#
Description
ACZ_SDOUT
ACZ_SDOUT
DPRSTP#
DPSLP#
H_DPRSTP#
H_DPSLP#
Pull up for each detect line

R223
1KOhm
5%
/*
XOR Chain Entrance strap

ICH _RSVD
SIO_A20GATE
T65
T73
ICH8-M
R197
10KOhm
5%
R182
AF13
AG26
+3.3V_RUN
LPC_LFRAME# 37
1
1
+3.3V_RUN
38,41 LED_MASK#
42 SATA_ACT#_R
LPC_LDRQ0#
LPC_LDRQ1#
C427
C428
AJ16
AJ15
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
SATA_TX0-_C
SATA_TX0+_C
G9
E6
SATA_TX0SATA_TX0+
GLAN_COMPI
GLAN_COMPO
HDA_RST#
31
31
GLAN_DOCK#/GPIO13
D25
C25
AE14
1
1
C4
LDRQ0#
LDRQ1#/GPIO23
A20GATE
A20M#
AJ17
AH17
AH15
AD13
T121
T43
FWH4/LFRAME#
T71
T59
T75
1 LAN_TXD0
1 LAN_TXD1
1 LAN_TXD2
ACZ_RST#
31
31
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
44 ICH_AZ_CODEC_SDIN0
36 ICH_AZ_MDC_SDIN1
Place all series terms close to ICH8 except for SDIN input lines, which
should be close to source. Placement of R208, R201, R205, R213 should
equal distance to the T split trace point as R219, R202, R199, R220
respective. Basically, keep the same distance from T for all series
termination resistors.
GLAN_CLK
C21
B21
C22
R268
R201
R202
B24
D22
1 LAN_RXD0
1 LAN_RXD1
1 LAN_RXD2
+1.5V_PCIE_ICH
R205
R199
INTVRMEN
LAN100_SLP
T81
T131
T80
T122
C226
27PF/50V
MLCC/+/-5%
/*
INTRUDER#
ICH_INTVRMEN
AF25
ICH_LAN100_SLP AD21
H_FERR#
1 33Ohm
No.57
44 ICH_AZ_CODEC_BITCLK
R208
ICH_INTRUDER# AD22
1 GLAN_CLK
T133
ACZ_BIT_CLK
RTCRST#
37
37
37
37
36 ICH_AZ_MDC_BITCLK
C202
1UF/10V/X7R
MLCC/+/-10%
pt_c0603
AF23
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
ICH_INTRUDER#
ICH_RTCRST#
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
RTC
LPC
20KOhm
5%
ICH_RTCRST#
H_DPSLP#
RTCX1
RTCX2
LAN / GLAN
CPU
R183
E5
F5
G8
F6
IHDA
R229
1MOhm
5%
AG25
AF24
SATA
IDE
U32A
ICH_RTCX1
ICH_RTCX2
DESCRIPTION:
ICH8: IDE/AC97/LPC/RTCRELEASE DATE :

3
<OrgName>
2
DESIGN ENGINEER :
1
PCIE_TX2+
35
PCIE_TX4-
35
0.1UF/10V MLCC/+/-10%
PCIE_TXN1_C
0.1UF/10V MLCC/+/-10%
PCIE_TXP1_C
C475
0.1UF/10V MLCC/+/-10%
PCIE_TXN2_C
C473
0.1UF/10V MLCC/+/-10%
PCIE_TXP2_C
C483
0.1UF/10V MLCC/+/-10%
PCIE_TXN4_C
0.1UF/10V MLCC/+/-10%
PCIE_TXP4_C
50
50
PCIE_TXN1_C
PCIE_TXP1_C
PERN1
PERP1
PETN1
PETP1
PCIE_TXN2_C
PCIE_TXP2_C
M27
M26
L29
L28
PERN2
PERP2
PETN2
PETP2
K27
K26
J29
J28
PERN3
PERP3
PETN3
PETP3
H27
H26
G29
G28
PERN4
PERP4
PETN4
PETP4
F27
F26
E29
E28
PERN5
PERP5
PETN5
PETP5
D27
D26
C29
C28
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
ICH_EC_SPI_CLK_R
ICH_SPI_CS#
ICH_SPI_CS1#_R
C23
B23
E22
SPI_CLK
SPI_CS0#
SPI_CS1#
ICH_EC_SPI_DO_R
D23
F21
PCIE_RX1PCIE_RX1+
50
50
PCIE_RX2PCIE_RX2+
MiniWLAN
C485
PCIE_TX4+
47 PCIE_TX6-/GLAN_TX-
C494
0.1UF/10V MLCC/+/-10%
GLAN_TXN_C
C496
0.1UF/10V MLCC/+/-10%
GLAN_TXP_C
35
35
PCIE_RX4PCIE_RX4+
PCIE_TXN4_C
PCIE_TXP4_C
ExpressCard
47 PCIE_TX6+/GLAN_TX+
47 PCIE_RX6-/GLAN_RX47 PCIE_RX6+/GLAN_RX+
Layout Note:
Place 15 ohm within
500 mils from ICH.
R275
37 ICH_EC_SPI_CLK
R267
37 ICH_EC_SPI_DO
37 ICH_EC_SPI_DIN
2 15Ohm
T55
2 15Ohm
+3.3V_ALW
VCC
1
SPI_CS0#
R517 15Ohm5% /*
GLAN_TXN_C
GLAN_TXP_C
5%
5%
39
USB_OC0_1#
50
USB_OC2_3#
USB_OC0_1#
USB_OC2_3#
OC4#
OC5#
OC6#
OC7#
OC8#
OC9#
U36
B
A
40
C
2
1
R518
ICH_SPI_CS#_R
1
15Ohm 5%
2 ICH_SPI_CS#
SIO_SPI_CS# 37
AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18
SPI_MOSI
SPI_MISO
OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#
74AHC1G08GW
/*
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
10
10
10
10
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
10
10
10
10
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA29
AA28
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
10
10
10
10
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
10
10
10
10
DMI_CLKN
DMI_CLKP
T26
T25
CLK_PCIE_ICH# 21
CLK_PCIE_ICH 21
DMI_ZCOMP
DMI_IRCOMP
Y23
Y24
USB
GND
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
USBRBIAS#
USBRBIAS
F2
F3
DMI_COMP 2
R221
ICH_USBP4ICH_USBP4+
39
39
39
39
50
50
50
50
1
1
28
28
35
35
41
41
1
1
50
50
ICH_USBP5ICH_USBP5+
ICH_USBP6ICH_USBP6+
ICH_USBP7ICH_USBP7+
ICH_USBP8ICH_USBP8+
ICH_USBP9ICH_USBP9+
R519
R253
1
1
2
2
10KOhm
10KOhm
SB_NB_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_LOM_PCIE_RST#
SB_WWAN_PCIE_RST#
R520
R250
R280
R274
1
1
1
1
2
2
2
2
100KOhm 5%
100KOhm 5%
20KOhm 5%
20KOhm 5%
Place within 500 mils of ICH8
+1.5V_PCIE_ICH
USER1 Left side pair top/left

USER2 Left side pair bottom/right
PCI Pullups
USER3 Right side pair top/left
PCI_STOP#
R276
8.2KOhm
5%
PCIE_MCARD2_DET#
R548
1
RP4E
6
5%
RP4F
7
5%
RP4G
8
5%
RP4H
9
5%
100KOhm
5%
T60
T56
PCI_DEVSEL#
8.2KOhm
CCD
PCI_FRAME#
Express Card
8.2KOhm
BlueTooth
T48
T49
No.5
ICH_GPIO2_PIRQE#
8.2KOhm
PCI_SERR#
WWAN
8.2KOhm
Short F2 and F3 at the package

and keep length to less than
500mils. Trace Impedance
should be 60ohms +/- 15%.
R521 0Ohm 5%
22.6Ohm
1%
pt_r0603
8.2KOhm
PCI_REQ0#
8.2KOhm
PCI_PLOCK#
+3.3V_SUS
10KOhm
OC7#
10KOhm
PCI_PERR#
10 10
5
5
10 10
5
5
10
5
ICH_SPI_CS1#_R
RP1D
RP1C
RP1B
RP1A
OC5#
8.2KOhm
3
10KOhm 5%
OC8#
2
10KOhm 5%
USB_OC2_3#
1
10KOhm 5%
OC4#
RP3E
6
5%
RP3F
7
5%
RP3G
8
5%
RP3H
9
5%
R260
1KOhm
5%
/*
R272
1KOhm
5%
GNT0#
SPI_CS1#
LPC
11
No stuff
No stuff
PCI
10
No stuff
Stuff
SPI
01
Stuff
No stuff
PCI_PIRQB#
32 PCI_PIRQC#
32 PCI_PIRQD#
F9
B5
C5
A10
A4
D7
E18
C18
B19
F18
A11
C10
C/BE0#
C/BE1#
C/BE2#
C/BE3#
C17
E15
F16
E17
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
C8
D9
G6
D16
A7
B7
F10
C16
C9
A17
PCI_IRDY#
AG24
B10
G7
PCI_PLTRST#
CLK_PCI_ICH
PLTRST#
PCICLK
PME#
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
SB_WWAN_PCIE_RST#
PCI_GNT2#
SB_LOM_PCIE_RST#
PCI_GNT3#
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
1.2
+3.3V_RUN
10 10 RP3D
5
5
10 10 RP3C
5
5
10 10 RP3B
5
5
PCI_PIRQC#
5%
3
8.2KOhm
PCI_PIRQB#
5%
2
8.2KOhm
PCI_PIRQA#
5%
1
8.2KOhm
PCI_IRDY#
5%
+3.3V_SUS
0.047UF/10V
1
U14
R266
1KOhm
/*
T78
4
8.2KOhm
MLCC/+/-10%
T72
32
32
32
32
PCI_RST#_G
5%
1
2
3
A
VCC
B
GND
Y
5
4
PCI_RST#
32
SN74AHC1G32DBVR
A16 away override strap.

PCI_GNT3#
PCI_IRDY# 32
PCI_PAR 32
PCI_RST#_G
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
+3.3V_SUS
Low = A16 swap override enabled.

High = Default.
C199
2
F8
G11
F12
B3
PCI_DEVSEL# 32
PCI_PERR# 32
U12
CLK_PCI_ICH
PCI_PLTRST#
PCI_SERR# 32
PCI_STOP# 32
PCI_TRDY# 32
PCI_FRAME# 32
R5C833
REQ1 GNT1
R281
10Ohm
5%
/*
PIRQC
PIRQD
CLK_PCI_ICH 21
ICH_PME# 38
ICH_GPIO2_PIRQE#
SB_WLAN_PCIE_RST#
SB_NB_PCIE_RST#
PCIE_MCARD2_DET#
DATE:
1
2
3
16
4
OF
68
VCC
A
B
GND
Y
C542
10,35,37
0.047UF/10V
1
U40
C284
8.2PF/50V
MLCC/+/-0.25PF
/*
ICH8: PCI/INT/DMI/USB
PLTRST#
MLCC/+/-10%
PCI_PLTRST#
1
2
3
A
VCC
B
GND
Y
5
4
SN74AHC1G32DBVR
Reserved for EMI.

Place resister and cap
close to ICH.
DESCRIPTION:
5
4
SN74AHC1G32DBVR
+3.3V_SUS
SB_WLAN_PCIE_RST# 50
SB_NB_PCIE_RST# 10
PCIE_MCARD2_DET# 50
SHEET
0.047UF/10V
1
MLCC/+/-10%
No.14
REVISION
5%
No.37
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
ICH8-M
PROJECT: Lanai
PCI_GNT3#
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
32
PCI_GNT1#
32
SB_WWAN_PCIE_RST# 50
1
SB_LOM_PCIE_RST# 47
1
PCI
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
2
8.2KOhm
PLTRST_LAN_MINICARD# 47,50
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3
T79
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PIRQD#
3
8.2KOhm 5%
Add Buffers as needed for

Loading and fanout
concerns.
U32B
PCI_AD[0..31]
PCI_REQ1#
4
8.2KOhm 5%
10
5
Non-iAMT
32
No.14
PCI_TRDY#
1
8.2KOhm 5%
10 RP3A
5
C279
B
10 10 RP4B
5
5
Boot BIOS Strap
PCI_GNT0#
4
10KOhm 5%
10 10
5
5
10 10 RP4C
5
5
10KOhm
OC6#
8.2KOhm
10
5
10KOhm
OC9#
RP1E
6
5%
RP1F
7
5%
RP1G
8
5%
RP1H
9
5%
USB_OC0_1#
10 10 RP4D
5
5
10 RP4A
5
Non-iAMT
+3.3V_RUN
+3.3V_RUN
10
5
USBRBIAS
ICH8-M
+3.3V_RUN
USER3 Right side pair bottom/right
R492
1
5%
5%
1
24.9Ohm 1%
ICH_USBP0ICH_USBP0+
ICH_USBP1ICH_USBP1+
ICH_USBP2ICH_USBP2+
ICH_USBP3ICH_USBP3+
SB_NB_PCIE_RST#
SB_WLAN_PCIE_RST#
BIOS should not enable the internal GPIO pull up

resistor
+3.3V_RUN
PCIE_TX2-
50
2
2
MiniWWAN
PCIE_TX1+
50
C465
C469
V27
V26
U29
U28
PCI-Express
Direct Media Interface
50
PCIE_TX1-
P27
P26
N29
N28
SPI
50
U32D
Place TX DC blocking caps close ICH8.
<OrgName>
C553
No.54
47PF/50V
MLCC/+/-5%
/*
DESIGN ENGINEER :
RELEASE DATE :
2
Place these close to ICH8
1 2.2KOhm 2 5%
3 2.2KOhm 4 5%
RN37A
RN37B
ICH_SMBDATA
ICH_SMBCLK
2
2
2
2
2
2
CLK_ICH_48M
5% /* RSV_ICH_CL_RST1#
AMT_SMBCLK
5%
AMT_SMBDAT
5%
ICH_RI#
5%
LOM_ICH_SMBALERT#
5%
ICH_PCIE_WAKE#
5%
10KOhm
10KOhm
10KOhm
10KOhm
10KOhm
1KOhm
No.26
+3.3V_RUN
R261
10Ohm
5%
R422
8.2KOhm
5%
12
Non-iAMT
1
1
1
1
1
1
+3.3V_SUS
Non-iAMT
R191
R216
R217
R224
R215
R214
+3.3V_SUS
C270
4.7PF/50V
SUS_STAT#/LPCPD#
SYS_RESET#
AG12
BMBUSY#/GPIO0
LOM_ICH_SMBALERT# AG22
0Ohm 5% /*
AE20
AG18
10 PM_BMBUSY#
2
37 LOM_SMB_ALERT#
R173
R185
8.2KOhm
5%
21 H_STP_PCI#
21 H_STP_CPU#
32,37
CLKRUN#
CLKRUN#
38 ICH_PCIE_WAKE#
32,37 IRQ_SERIRQ
R184
10Ohm
5%
/*
T46
37,51,53 IMVP_PWRGD
T33
44
USB_IDE#
AH11
ICH_PCIE_WAKE#
IRQ_SERIRQ
RSV_THRM#
AE17
AF12
AC13
WAKE#
SERIRQ
THRM#
IMVP_PWRGD
AJ20
VRMPWRGD
AJ22
USB_IDE#
AJ8
RSVD_GPIO6
AJ9
SIO_EXT_WAKE#
AH9
38 SIO_EXT_WAKE#
SIO_EXT_SMI#
AE16
37 SIO_EXT_SMI#
SIO_EXT_SCI#
AC19
37 SIO_EXT_SCI#
PCIE_MCARD1_DET# AG8
50 PCIE_MCARD1_DET#
R543 1
2 4.7KOhm AH12
No.15 50 USB_MCARD1_DET#
RSVD_GPIO20
1 T134
AE11
No.14
USB_MCARD2_DET# AG10
50 USB_MCARD2_DET#
USB_MCARD3_DET# AH25
1 T31
AD16
31 IDE_RST_MOD
AG13
21 SATA_CLKREQ#
PLTRST_DELAY#
AF9
PLTRST_DELAY#
RSVD_GPIO39
1 T117
AJ11
CCD_VDD_ON
AD10
No.9
28 CCD_VDD_ON
Option to "Disable "

clkrun. Pulling it down
will keep the clks
running.
R419 1
2 8.2KOhm 5%
+3.3V_RUN
SIO_EXT_SCI# R227 1
2 10KOhm 5%
+3.3V_SUS
10 MCH_ICH_SYNC#
15
SPKR
SPKR
AD9
MCH_ICH_SYNC#_R
2
0Ohm 5%
1
R169
STP_PCI#/GPIO15
STP_CPU#/GPIO25
CLKRUN#
T120
SMBALERT#/GPIO11
AJ13
AJ21
ICH_RSVD
CLKRUN#/GPIO32
TP7
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SPKR
MCH_SYNC#
TP3
AG9
G5
CLK_ICH_14M
CLK_ICH_48M
SUSCLK
D3
ICH_SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
AG23
AF21
AD18
SIO_SLP_S4#
S4_STATE#/GPIO26
AH27
SIO_S4_STATE#
PWROK
AE23
ICH_PWRGD
DPRSLPVR/GPIO16
AJ14
DPRSLPVR
BATLOW#
AE21
ICH_BATLOW#
PWRBTN#
C2
CLK14
CLK48
LAN_RST#
RSMRST#
CK_PWRGD
1
R204
10Ohm
/*
5%
CLK_ICH_14M 21
CLK_ICH_48M 21
T76
SIO_SLP_S3# 37
1
SIO_SLP_S5# 37
1
1
R228
T36
T124
10,51
ICH_PWRGD
R200 1
2 10KOhm
DPRSLPVR
10,53
DPRSLPVR
R420 1
2 100KOhm
5%
+3.3V_SUS
WOL_EN
R193 1
2 100KOhm
5%
SIO_PWRBTN# 37
AH20 ICH_LAN_RST#
1
R189 1
AG27
R188
E1
2
2 0Ohm 5%
0Ohm 5% /*
ICH_RSMRST# 37
SUSPWROK
43,51
CLK_PWRGD
E3
SLP_M#
AJ25
RSV_SIO_SLP_M#
T123
CL_CLK0
CL_CLK1
F23
AE18
RSV_ICH_CL_CLK1
T39
CL_DATA0
CL_DATA1
F22
AF19
RSV_ICH_CL_DATA1 1
T38
CL_VREF0
CL_VREF1
D24
AH23
CL_VREF0
CL_VREF1
T32
CL_RST#
AJ23
CLGPIO0/GPIO24
CLGPIO1/GPIO10
CLGPIO2/GPIO14
WOL_EN/GPIO9
AJ27
AJ24
AF22
AG19
C212
4.7PF/50V
/*
MLCC/+/-0.25PF
ICH_PWRGD
2
8.2KOhm 5%
ICH_CL_PWROK
CLPWROK
MLCC/+/-0.25PF
CLK_ICH_14M
12
RI#
F4
AD15
AJ12
AJ10
AF11
AG11
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
AF17
7,38,52 XDP_DBRESET#
+3.3V_RUN
SMB
ICH_RI#
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
SATA
GPIO
T69
AJ26
AD19
AG21
AC17
AE19
Clocks
SYS
GPIO
Power MGT
T35
GPIO
MISC
Controller Link
35,50 ICH_SMBCLK
35,50 ICH_SMBDATA
U32C
ICH_SMBCLK
ICH_SMBDATA
RSV_ICH_CL_RST1#
AMT_SMBCLK
AMT_SMBDAT
21
5%
SUSPWROK
R176 1
2 10KOhm
5% /*
ICH_LAN_RST#
R174 1
2 1MOhm
5%
ICH_CL_PWROK R262 1
2 1MOhm
5%
Non-iAMT
ICH_CL_PWROK 10,37
C
CL_CLK0
10
+3.3V_SUS
CL_DATA0 10
EC_ME_ALERT R237
8.2KOhm
5%
ICH_CL_RST0# 10
PCIE_MCARD3_DET# 1
ME_EC_ALERT
1
EC_ME_ALERT
1
WOL_EN
T30
T119
T45
ICH8-M
Pull up for each detect line
Non-iAMT
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
100KOhm
SMBus address D2
5%
These are for

backdrive issue
+3.3V_RUN
100KOhm
USB_MCARD3_DET#
100KOhm
RN36B
2.2KOhm
5%
RN36A
2.2KOhm
5%
R212
1KOhm
/*
2
4
2
B
USB_MCARD2_DET#
100KOhm
2
2
2
2
2
1
1
1
1
1
10KOhm
10KOhm
10KOhm
10KOhm
10KOhm
10
5
10 10 RP2D
5
5
RSV_THRM#
5%
5% /* MCH_ICH_SYNC#_R
IRQ_SERIRQ
5%
RSVD_GPIO6
5%
RSVD_GPIO39
5%
10 10 RP2B
5
5
2
100KOhm
10 RP2A
5
MEM_SDATA 19
PCIE_MCARD3_DET#
3
100KOhm 5%
5%
PCIE_MCARD1_DET#
1
100KOhm 5%
Q36 2N7002
Id=180mA/Pd=300mW
No Reboot strap.
SPKR
USB_MCARD1_DET#
4
100KOhm 5%
10 10 RP2C
5
5
G
35,50 ICH_SMBDATA
S 2
R235
R168
R206
R424
R423
5% RSVD_GPIO20
2 100KOhm
R555 1
1
3
SPKR
No.14
RP2E
6
5%
RP2F
7
5%
RP2G
8
5%
RP2H
9
5%
Low=Default
High=No Reboot
+3.3V_RUN
+3.3V_RUN
+3.3V_SUS
MEM_SCLK 19
Q35 2N7002
Id=180mA/Pd=300mW
R277
3.24KOhm
1%
R180
3.24KOhm
1%
/*
2
CL_VREF1
C201
0.1UF/10V
MLCC/+80-20%
/*
R278
453Ohm
1%
PROJECT: Lanai
5
REVISION
DATE:
1.2
SHEET
17
4
OF
68
DESCRIPTION:
ICH8: SMB/PWR/CLK/GPIO
3
<OrgName>
2 10KOhm 5% SIO_EXT_SMI#
R226 1
C278
0.1UF/10V
MLCC/+80-20%
CL_VREF0
+3.3V_SUS
35,50 ICH_SMBCLK
Non-iAMT
No.9
5% CCD_VDD_ON
2 100KOhm
S 2
R544 1
PLTRST_DELAY#
2 10KOhm 5%
R195 1
DESIGN ENGINEER :
RELEASE DATE :
2
R179
453Ohm
1%
/*
C218
0.1UF/10V
MLCC/+/-10%
C219
0.1UF/10V
MLCC/+/-10%
C224
1UF/10V
MLCC/+/-10%
pt_c0603
+RTC_CELL
+1.05V_VCCP
T57
T61
1 TP_VCCSUSLAN1
1 TP_VCCSUSLAN2
+3.3V_RUN
Non-iAMT
Non-iAMT
C265
0.1UF/10V
MLCC/+/-10%
+VCCGLANPLL
VCCLAN1_05[1]
VCCLAN1_05[2]
F19
G20
VCCLAN3_3[1]
VCCLAN3_3[2]
A24
+1.5V_RUN
VCCGLANPLL
A26
A27
B26
B27
B28
+VCCGLANPLL
+1.5V_PCIE_ICH
C214
1UF/10V
MLCC/+/-10%
pt_c0603
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]
C281
4.7UF/6.3V
MLCC/+/-10%
pt_c0603
+3.3V_RUN
B25
J6
AF20
VCCSUS1_5[1]
VCCSUS1_5[2]
REVISION
DATE:
1.2
SHEET
18
4
OF
68
1
2
1
2
1
2
1
2
1
2
1
2
2
R218
0Ohm
5%
+3.3V_SUS
VCCHDA
1
1
T54
T37
AC16
+TP_VCCSUS1.5_1
T44
J7
+TP_VCCSUS1.5_2
T64
VCCSUS3_3[01]
C3
+VCCSUS3_3[0~6]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]
AC18
AC21
AC22
AG20
AH28
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6
C213
0.1UF/10V
MLCC/+/-10%
C225
0.1UF/10V
MLCC/+/-10%
+3.3V_SUS
Non-iAMT
1
+TP_VCCSUS1.05_1
+TP_VCCSUS1.05_2
C246
0.022UF/16V
MLCC/+/-10%
C242
0.022UF/16V
MLCC/+/-10%
+VCCSUS3_3[7~19]
C241
0.1UF/10V
MLCC/+/-10%
U32E
A23
A5
AA2
AA7
A25
AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29
AD3
AD4
AD6
AE1
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
J27
J4
J5
K23
K28
K29
K3
K6
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
ICH8-M
VCCCL1_05
G22
TP_VCCCL1.05
VCCCL1_5
A22
VCCCL1_5
VCCCL3_3[1]
VCCCL3_3[2]
F20
G21
VCCGLAN3_3
Non-iAMT
VCCSUS1_05[1]
VCCSUS1_05[2]
C236
0.1UF/10V
MLCC/+/-10%
+3.3V_RUN
1
AD11
T66
A
+3.3V_RUN
Non-iAMT
ICH8-M
PROJECT: Lanai
1
GLAN POWER
VCC1_5_A[25]
F17
G18
Place CAP
close to A24
W23
AC12
C274
0.1UF/10V
MLCC/+/-10%
VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
F1
L6
L7
M6
M7
VCCHDA
VCCSUSHDA
C280
0.1UF/10V
MLCC/+/-10%
C217
0.1UF/10V
MLCC/+/-10%
VCCUSBPLL
A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11
C269
0.1UF/10V
MLCC/+/-10%
+1.5V_RUN
VCC1_5_A[18]
VCC1_5_A[19]
D1
USB CORE
C272
0.1UF/10V
MLCC/+/-10%
+1.5V_RUN
VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]
C515
4.7UF/10V
MLCC/+/-10%
pt_c1206_h71
AC7
AD7
AA3
U7
V7
W1
W6
W7
Y7
VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]
VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
C232
0.1UF/10V
MLCC/+/-10%
C227
0.1UF/10V
MLCC/+/-10%
G12
G17
H7
AC8
AD8
AE8
AF8
C210
0.1UF/10V
MLCC/+/-10%
C228
0.1UF/10V
MLCC/+/-10%
C282
0.1UF/10V
MLCC/+/-10%
/*
VCC1_5_A[13]
VCC1_5_A[14]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
+1.5V_RUN
2
1Ohm 5%
pt_r0603
C220
22UF/10V
MLCC/+/-20%
pt_c1206_h75
AA5
AA6
AD2
VCC1_5_A[11]
VCC1_5_A[12]
VCC3_3[02]
5%
+1.05V_VCCP
+3.3V_RUN
AC10
AC9
AF29
Intel 20%
C229
0.1UF/10V
MLCC/+/-10%
AC23
AC24
VCC3_3[01]
C209
0.1UF/10V
MLCC/+/-10%
1
C420
10UF/6.3V
MLCC/+/-20%
pt_c0805_h53
1
2
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]
V_CPU_IO[1]
V_CPU_IO[2]
+V_CPU_IO
2
1
2
C426
1UF/10V
MLCC/+/-10%
pt_c0603
AC1
AC2
AC3
AC4
AC5
ATX
+1.5V_RUN
+VCCSATPLL
B
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
L34
10uH
Irat=100mA
pt_l0805
C252
0.1UF/10V
MLCC/+/-10%
VCCSATAPLL
+VCC_DMI
12
+VCCSATPLL_L
AJ6
AE7
AF7
AG7
AH7
AJ7
ARX
+1.5V_RUN
AE28
AE29
+VCCSATPLL
R414
0Ohm 5%
VCC_DMI[1]
VCC_DMI[2]
1
2
R252
10Ohm
pt_r0805_h24
BAT54C
+1.25V_RUN
+1.5V_RUN
R29
C264
2.2UF/10V
MLCC/+/-10%
pt_c0805_h53
VCCDMIPLL
3
2
C277
0.1UF/10V
MLCC/+/-10%
C234
22UF/10V
MLCC/+/-20%
pt_c1206_h75
C517
22UF/10V
MLCC/+/-20%
pt_c1206_h75
+1.5V_PCIE_ICH
+ CE21
220UF/4V
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20%
2
1 2
1
FB_330ohm+-25%_100mHz_
1.5A_0.09_ohm DC
L17
330Ohm/100Mhz
MURATA/BLM21PG331SN1D
pt_l0805_h41
VCCA3GP
+1.5V_RUN
C253
0.1UF/10V
MLCC/+/-10%
L39
0.1Ohm/100Mhz
pt_inductor_2p_126x98_tdk
+1.5V_DMIPLL
2
1 +1.5V_DMIPLL_R 1
R497
C250
C249
0.01UF/25V
10UF/6.3V
MLCC/+/-10% MLCC/+/-20%
pt_c0805_h53
C261
0.1UF/10V
MLCC/+/-10%
RB751V_40
+1.05V_VCCP
+ICH_V5REF_SUS
A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
+3.3V_SUS
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]
2
10Ohm5%
D14
V5REF_SUS
AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25
CORE
1
R255
V5REF[1]
V5REF[2]
VCCP_CORE
Non-iAMT
+5V_SUS
A16
T7
G4
C285
0.1UF/10V
MLCC/+/-10%
RB751V_40
VCCRTC
IDE
+ICH_V5REF_RUN
AD25
D13
PCI
D15
1
+3.3V_RUN
D
+1.5V_RUN
U32F
VCCPSUS
+5V_RUN
100Ohm 5%
2
VCCPUSB
R284
1
C283
1UF/10V
MLCC/+/-10%
pt_c0603
/*
DESCRIPTION:
ICH8-M(POWER,GND)
3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
A is required to route to Top

S0DIMM for AMT to function
Ch.A SODIMM needs to be
populated for Intel AMT support.
+1.8V_SUS
+1.8V_SUS
V_DDR_MCH_REF
DDR_A_DM[0..7] 11
DDR_A_D[0..63] 11
DDR_A_DQS[0..7] 11
DDR_A_DQS#[0..7] 11
DDR_A_MA[0..14] 10,11,20
TOP
+1.8V_SUS
+1.8V_SUS
DDR_B_DM[0..7] 11
DDR_B_D[0..63] 11
DDR_B_DQS[0..7] 11
DDR_B_DQS#[0..7] 11
DDR_B_MA[0..14] 10,11,20
BOT
V_DDR_MCH_REF
V_DDR_MCH_REF
DDR_A_D36
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D50
DDR_A_D54
DDR_A_D56
DDR_A_D60
DDR_A_DM7
DDR_A_D61
DDR_A_D59
MEM_SDATA
MEM_SCLK
+3.3V_RUN
Non-iAMT
MEM_SDATA
MEM_SCLK
SMbus address A0
M_ODT0
10,20
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
11,20 DDR_B_CAS#
10,20 DDR_CS3_DIMMB#
M_ODT3
10,20 M_ODT3
DDR_B_D38
DDR_B_D36
DDR_A_D32
DDR_A_D38
+3.3V_RUN
DDR_A_DM4
DDR_B_DQS#4
DDR_B_DQS4
Non-iAMT
DDR_A_D37
DDR_A_D35
DDR_A_D45
DDR_A_D44
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D41
DDR_A_D46
C445
2.2UF/6.3V
DDR_B_D34
DDR_B_D33
DDR_B_D45
DDR_B_D46
C200
DDR_B_DM5
0.1UF/10V
DDR_B_D44
DDR_B_D42
pt_c0805_h53
DDR_A_D53
DDR_A_D52
DDR_B_D53
DDR_B_D48
M_CLK_DDR1 10
M_CLK_DDR#1 10
DDR_A_DM6
DDR_B_DQS#6
DDR_B_DQS6
DDR_A_D51
DDR_A_D55
DDR_B_D51
DDR_B_D54
DDR_B_D56
DDR_B_D62
DDR_A_D58
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DM7
DDR_A_D63
DDR_A_D62
Non-iAMT
DDR_B_D63
DDR_B_D60
MEM_SDATA
MEM_SCLK
R178
+3.3V_RUN
R171
10KOhm
5%
SMbus address A4
10KOhm
5%
DATE:
1.2
SHEET
19
4
OF
68
DESCRIPTION:
DDR2 SO-DIMM (0)

3
1
2
C151
C142
+1.8V_SUS
C136
C153
C128
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
Please these Caps near So-Dimm1.
DDR_CKE3_DIMMB 10,20
DDR_B_MA14
C125
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
MLCC/+80-20%MLCC/+80-20%MLCC/+80-20%MLCC/+80-20%
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
+1.8V_SUS
DDR_B_BS1
DDR_B_RAS#
DDR_B_BS1
11,20
DDR_B_RAS# 11,20
DDR_CS2_DIMMB# 10,20
M_ODT2
DDR_B_MA13
M_ODT2
C167
10,20
C384
C388
C393
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
MLCC/+80-20%MLCC/+80-20%MLCC/+80-20%MLCC/+80-20%
DDR_B_D35
DDR_B_D32
DDR_B_DM4
DDR_B_D39
DDR_B_D37
B
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
+3.3V_RUN
Non-iAMT
DDR_B_D47
DDR_B_D43
DDR_B_D52
DDR_B_D49
M_CLK_DDR3 10
M_CLK_DDR#3 10
C435
2.2UF/6.3V
DDR_B_DM6
C429
0.1UF/10V
pt_c0805_h53
DDR_B_D55
DDR_B_D50
DDR_B_D57
DDR_B_D61
Non-iAMT
DDR_B_DQS#7
DDR_B_DQS7
+3.3V_RUN
DDR_B_D58
DDR_B_D59
R172
2
R170
STD
FOXCONN/AS0A426-NASN-7F
C379
DDR_B_D24
DDR_B_D26
10KOhm
5%
CLOCK 2 , 3
CKE 2 , 3
REVISION
C395
2.2UF/6.3V
2.2UF/6.3V
2.2UF/6.3V
2.2UF/6.3V
2.2UF/6.3V
MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
pt_c0603
pt_c0603
pt_c0603
pt_c0603
pt_c0603
M_ODT0
DDR_A_MA13
11,20 DDR_B_BS0
11,20 DDR_B_WE#
C138
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
C168
DDR_B_D29
DDR_B_D31
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
C147
+1.8V_SUS
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
C163
10
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
1
2
DDR_B_BS2
11,20 DDR_B_BS2
DDR_A_BS1
11,20
DDR_A_RAS# 11,20
DDR_CS0_DIMMA# 10,20
CLOCK 0 , 1
CKE 0 , 1
10,20 DDR_CKE2_DIMMB
DDR_A_BS1
DDR_A_RAS#
STD
FOXCONN/AS0A426-N2SN-7F
PROJECT: Lanai
DDR_CKE1_DIMMA 10,20
DDR_A_MA14
17
17
DDR_B_D27
DDR_B_D30
PM_EXTTS#1
DDR_B_D22
DDR_B_D17
MLCC/+80-20%
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D30
DDR_A_D26
PM_EXTTS#1
DDR_B_DM2
MLCC/+/-10%
DDR_A_D48
DDR_A_D49
DDR_B_DM3
MLCC/+80-20%
DDR_A_D40
DDR_A_D47
DDR_A_DQS#3
DDR_A_DQS3
MLCC/+/-10%
DDR_A_D39
DDR_A_D34
DDR_B_D25
DDR_B_D28
C119
10,20 M_ODT1
DDR_A_D28
DDR_A_D29
C154
2.2UF/6.3V
2.2UF/6.3V
2.2UF/6.3V
2.2UF/6.3V
2.2UF/6.3V
MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10% MLCC/+/-10%
pt_c0603
pt_c0603
pt_c0603
pt_c0603
pt_c0603
DDR_B_D21
DDR_B_D23
M_ODT1
DDR_B_D18
DDR_B_D19
DDR_B_D11
DDR_B_D15
DDR_A_CAS#
DDR_B_DQS#2
DDR_B_DQS2
10
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
pt_c0805_h53
+1.8V_SUS
M_CLK_DDR2 10
M_CLK_DDR#2 10
11,20 DDR_A_CAS#
10,20 DDR_CS1_DIMMA#
PM_EXTTS#0
DDR_A_D18
DDR_A_D23
VSS18
VSS20
DQ16
DQ20
DQ17
DQ21
VSS1
VSS6
DQS#2
NC3
DQS2
DM2
VSS19
VSS21
DQ18
DQ22
DQ19
DQ23
VSS22
VSS24
DQ24
DQ28
DQ25
DQ29
VSS23
VSS25
DM3
DQS#3
NC4
DQS3
VSS9
VSS10
DQ26
DQ30
DQ27
DQ31
VSS4
VSS8
CKE0
CKE1
VDD7
VDD8
NC1
A15
A16_BA2
A14
VDD9
VDD11
A12
A11
A9
A7
A8
A6
VDD5
VDD4
A5
A4
A3
A2
A1
A0
VDD10 VDD12
A10/AP
BA1
BA0
RAS#
WE#
S0#
VDD2
VDD1
CAS#
ODT0
S1#
A13
VDD3
VDD6
ODT1
NC2
VSS11
VSS12
DQ32
DQ36
DQ33
DQ37
VSS26
VSS28
DQS#4
DM4
DQS4
VSS42
VSS2
DQ38
DQ34
DQ39
DQ35
VSS55
VSS27
DQ44
DQ40
DQ45
DQ41
VSS43
VSS29 DQS#5
DM5
DQS5
VSS51
VSS56
DQ42
DQ46
DQ43
DQ47
VSS40
VSS44
DQ48
DQ52
DQ49
DQ53
VSS52
VSS57
NCTEST
CK1
VSS30
CK1#
DQS#6 VSS45
DQS6
DM6
VSS31
VSS32
DQ50
DQ54
DQ51
DQ55
VSS33
VSS35
DQ56
DQ60
DQ57
DQ61
VSS3
VSS7
DM7
DQS#7
VSS34
DQS7
DQ58
VSS36
DQ59
DQ62
VSS14
DQ63
SDA
VSS13
SCL
SA0
VDDSPD
SA1
GND0
GND1
NP_NC1NP_NC2
2.2UF/6.3V
DDR_B_DM1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
11,20 DDR_A_BS0
11,20 DDR_A_WE#
PM_EXTTS#0
DDR_A_DM2
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
0.1UF/10V
C97
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_B_D20
DDR_B_D16
DDR_B_D8
DDR_B_D12
C101
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_D17
DDR_A_D20
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_A_BS2
11,20 DDR_A_BS2
DDR_B_D10
DDR_B_D14
DDR_B_D5
DDR_B_D4
10,20 DDR_CKE0_DIMMA
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_A_D5
DDR_A_D0
V_DDR_MCH_REF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
10KOhm
5%
DDR_A_D31
DDR_A_D24
DDR_B_DQS#1
DDR_B_DQS1
M_CLK_DDR0 10
M_CLK_DDR#0 10
DDR_A_DM3
DDR_A_DM0
DDR_A_D25
DDR_A_D27
DDR_B_D9
DDR_B_D13
DDR_A_D19
DDR_A_D22
VSS18
VSS20
DQ16
DQ20
DQ17
DQ21
VSS1
VSS6
DQS#2
NC3
DQS2
DM2
VSS19
VSS21
DQ18
DQ22
DQ19
DQ23
VSS22
VSS24
DQ24
DQ28
DQ25
DQ29
VSS23
VSS25
DM3
DQS#3
NC4
DQS3
VSS9
VSS10
DQ26
DQ30
DQ27
DQ31
VSS4
VSS8
CKE0
CKE1
VDD7
VDD8
NC1
A15
A16_BA2
A14
VDD9
VDD11
A12
A11
A9
A7
A8
A6
VDD5
VDD4
A5
A4
A3
A2
A1
A0
VDD10 VDD12
A10/AP
BA1
BA0
RAS#
WE#
S0#
VDD2
VDD1
CAS#
ODT0
S1#
A13
VDD3
VDD6
ODT1
NC2
VSS11
VSS12
DQ32
DQ36
DQ33
DQ37
VSS26
VSS28
DQS#4
DM4
DQS4
VSS42
VSS2
DQ38
DQ34
DQ39
DQ35
VSS55
VSS27
DQ44
DQ40
DQ45
DQ41
VSS43
VSS29 DQS#5
DM5
DQS5
VSS51
VSS56
DQ42
DQ46
DQ43
DQ47
VSS40
VSS44
DQ48
DQ52
DQ49
DQ53
VSS52
VSS57
NCTEST
CK1
VSS30
CK1#
DQS#6 VSS45
DQS6
DM6
VSS31
VSS32
DQ50
DQ54
DQ51
DQ55
VSS33
VSS35
DQ56
DQ60
DQ57
DQ61
VSS3
VSS7
DM7
DQS#7
VSS34
DQS7
DQ58
VSS36
DQ59
DQ62
VSS14
DQ63
SDA
VSS13
SCL
SA0
VDDSPD
SA1
GND0
GND1
NP_NC1NP_NC2
pt_c0805_h53
DDR_A_DQS#2
DDR_A_DQS2
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_B_D3
DDR_B_D2
2.2UF/6.3V
DDR_A_D16
DDR_A_D21
0.1UF/10V
DDR_B_DQS#0
DDR_B_DQS0
C99
VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
DDR_A_D4
DDR_A_D6
DDR_A_D3
DDR_A_D1
C102
VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
MLCC/+/-10%
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DM1
DDR_A_D11
DDR_A_D10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DDR_B_D0
DDR_B_D1
MLCC/+80-20%
DDR_A_D7
DDR_A_D2
DDR_A_D13
DDR_A_D14
MLCC/+/-10%
DDR_A_D15
DDR_A_D9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
MLCC/+80-20%
DDR_A_DQS#1
DDR_A_DQS1
CON15
VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
DDR_A_D12
DDR_A_D8
VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
CON14
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
TOP
1
2
1
2
1
2
+0.9V_DDR_VTT
BOT
C130
C120
C165
C123
C191
C150
C146
C155
C143
C186
C164
C156
C185
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20%
1
2
1
2
Layout note : Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.
C169
C137
C144
C135
C149
C175
C170
C118
C189
C139
C148
C192
C190
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20% MLCC/+80-20%
+0.9V_DDR_VTT
10,11,19 DDR_A_MA[0..14]
11,19 DDR_A_BS1
11,19 DDR_A_RAS#
Please these resistor

closely DIMMA, all
trace length<750 mil.
11,19 DDR_A_BS2
11,19 DDR_A_BS0
11,19 DDR_A_WE#
11,19 DDR_A_CAS#
10,19
10,19
10,19
10,19
PROJECT: Lanai
5
DDR_A_MA6
DDR_A_MA7
RN19A
RN19B
1
3
56Ohm 2
5%
5%
56Ohm 4
RN21A
RN21B
1
3
56Ohm 2
4 5%
56Ohm
5%
DDR_B_MA14
DDR_B_MA7
DDR_A_MA0
DDR_A_BS1
RN26A
RN26B
1
3
56Ohm 2
5%
5%
56Ohm 4
RN18A
RN18B
1
3
56Ohm 2
5%
56Ohm 4
5%
DDR_B_MA6
DDR_B_MA11
DDR_A_RAS#
DDR_A_MA13
RN29A
RN29B
1
3
56Ohm 2
5%
56Ohm 4
5%
RN34A
RN34B
1
3
56Ohm 2
4 5%
5%
56Ohm
DDR_B_BS1
DDR_B_MA0
DDR_A_MA4
DDR_A_MA2
RN23A
RN23B
1
3
56Ohm 2
5%
56Ohm 4
5%
RN30A
RN30B
1
3
56Ohm 2
4 5%
5%
56Ohm
DDR_B_MA13
DDR_B_RAS#
DDR_A_MA8
DDR_A_MA5
RN24A
RN24B
1
3
56Ohm 2
5%
56Ohm 4
5%
RN17A
RN17B
1
3
56Ohm 2
4 5%
5%
56Ohm
DDR_A_MA11
DDR_A_MA14
DDR_A_MA12
DDR_A_BS2
RN16A
RN16B
1
3
56Ohm 2
5%
56Ohm 4
5%
RN28A
RN28B
1
3
56Ohm 2
5%
56Ohm 4
5%
DDR_B_MA3
DDR_B_MA1
DDR_A_MA9
DDR_A_MA3
RN27A
RN27B
1
3
56Ohm 2
4 5%
56Ohm
5%
RN31A
RN31B
1
3
56Ohm 2
5%
5%
56Ohm 4
DDR_B_WE#
DDR_B_BS0
DDR_A_MA10
DDR_A_BS0
RN33A
RN33B
1
3
56Ohm 2
4 5%
5%
56Ohm
RN20A
RN20B
1
3
56Ohm 2
4 5%
56Ohm
5%
DDR_B_MA9
DDR_B_MA12
DDR_A_WE#
DDR_A_CAS#
RN32A
RN32B
1
3
56Ohm 2
4 5%
56Ohm
5%
RN35A
RN35B
1
3
56Ohm 2
5%
5%
56Ohm 4
DDR_B_MA10
DDR_B_CAS#
DDR_B_MA4
DDR_B_MA5
RN25A
RN25B
1
3
56Ohm 2
5%
56Ohm 4
5%
RN22A
RN22B
1
3
56Ohm 2
5%
56Ohm 4
5%
DDR_B_MA2
DDR_B_MA8
1
1
1
1
1
1
1
2
2
2
2
2
2
2
M_ODT0
10,19 M_ODT0
10,19 M_ODT1
DDR_A_MA1
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
REVISION
DATE:
1.2
SHEET
5%
5%
5%
5%
5%
5%
5%
R147
R157
R152
R149
R158
R124
R126
20
4
DDR_B_MA[0..14] 10,11,19
+0.9V_DDR_VTT
OF
68
56Ohm
56Ohm
56Ohm
56Ohm
56Ohm
56Ohm
56Ohm
R153
R154
R133
R155
R156
R125
R131
1
1
1
1
1
1
1
2
2
2
2
2
2
2
5%
5%
5%
5%
5%
5%
5%
56Ohm
56Ohm
56Ohm
56Ohm
56Ohm
56Ohm
56Ohm
M_ODT2
DDR_B_BS1
11,19
DDR_B_RAS#
11,19
DDR_B_WE#
DDR_B_BS0
11,19
11,19
DDR_B_CAS#
11,19
Please these resistor

closely DIMMB, all
trace length<750 mil.
M_ODT2
10,19
M_ODT3
10,19
DDR_B_BS2
11,19
DESCRIPTION:
DDR2 SO-DIMM (1)

3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
+3.3V_RUN
X2
+3.3V_RUN
R61
C69
PCI_PCCARD
2 10KOhm
1
5%
27PF/50V
MLCC/+/-5%
PCIE_LOM_CLKREQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
CARD_CLK_REQ#
MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_XTAL_OUT
2
0Ohm
5%
C66
27PF/50V
MLCC/+/-5%
R79
R70
R80
R76
R42
R45
1
1
1
1
1
1
2
2
2
2
2
2
10KOhm
10KOhm
10KOhm
10KOhm
10KOhm
10KOhm
5%
5%
5%
5%
5%
5%
14.318MHz
10KOhm
5%
/*
No.25
R85
10KOhm
5%
/*
R78
2
14.31818Mhz
+3.3V_RUN
CLK_XTAL_IN
Non-iAMT
+3.3V_RUN
Non-iAMT
R52
/*
PGMODE
R43
2 10KOhm
5%
PCI_LOM
FSA
Populate for Napa platforms only

R77
R83
10KOhm
5%
1
10KOhm
5%
/*
U5
0=UMA
1=Disc. GRFX down
+CK_VDD_MAIN2
Non-iAMT
+3.3V_RUN
No.6
17
7,10
7,10
7,10
Enable ITP
R72
No.44
17 CLK_ICH_14M
10KOhm
5%
1
37 CLK_PCI_5025
32 CLK_PCI_PCCARD
12
VDDCPU
40
VDD48
2 2.2KOhm 5%
2 33Ohm
CLKREF
22
REF1
R55
R59
1
1
2 33Ohm 5%
2 33Ohm 5%
PCI_SIO
PCI_PCCARD
27
32
33
34
PCI1
*PCI2/TME
PCI3
PCI4/FCTSEL1
43
44
DOTT_96/27MHz_NS
DOTC_96/27MHz_SS
37
PCI_F0/ITP_EN
39
CK_PWRGD/PD#
16
17
SMBCLK
SMBDAT
27M_NSS
27M_SS
PCI_ICH
Place close to Clock Gen.
73
CLK_ICH_48M
CLK_PCI_ICH
CLK_ICH_14M
CLK_PCI_5025
6
5
RN4A
33Ohm 2
RN4B
33Ohm 4
*PG_MODE
PGMODE
5% 2 10KOhm 1 R75
3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
PCIE_MINI1
PCIE_MINI1#
5% 1
5% 3
RN5A
33Ohm 2
RN5B
33Ohm 4
PCIE_MINI2
PCIE_MINI2#
5% 1
5% 3
RN1A
33Ohm 2
RN1B
33Ohm 4
PCIE_ICH
PCIE_ICH#
5% 3
5% 1
RN7B
33Ohm 4
RN7A
33Ohm 2
PCIE_EXPCARD
PCIE_EXPCARD#
5% 3
5% 1
RN8B
33Ohm 4
RN8A
33Ohm 2
PCIE_LOM
PCIE_LOM#
5% 3
5% 1
RN9B
33Ohm 4
RN9A
33Ohm 2
PCIE_SATA
PCIE_SATA#
5% 3
5% 1
RN13B
22Ohm 4
22Ohm 2 RN13A
47
48
DOT96_SSC
DOT96_SSC#
5% 3
5% 1
RN12B
33Ohm 4
RN12A
33Ohm 2
SRCT9
SRCC9
CLKREQ9#
SRCT8
SRCC8
CLKREQ8#
SRCT7
SRCC7
CLKREQ7#
SRCT6
SRCC6
CLKREQ6#
SRCT5
SRCC5
CLKREQ5#
SRCT4
SRCC4
CLKREQ4#
SRCT3
SRCC3
CLKREQ3#
SRCT2
SRCC2
CLKREQ2#
SRCT1/SATAT
SRCC1/SATAC
CLKREQ1#
LCD100/SRCT0
LCD100/SRCC0
GND
MCH_3GPLL
MCH_3GPLL#
XDP_3GPLL
XDP_3GPLL#
5% 3
33Ohm
5% 1
33Ohm
1% 475Ohm 1
5% 3
33Ohm
5% 1
33Ohm
4
2
2
4
2
CLK_XDP
CLK_XDP#
/*
52
52
+3.3V_RUN
Non-iAMT
CLK_PCIE_MINI1 50
CLK_PCIE_MINI1# 50
MINI1CLK_REQ# 50
CLK_PCIE_MINI2 50
CLK_PCIE_MINI2# 50
MINI2CLK_REQ# 50
CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16
CLK_PCIE_EXPCARD 35
CLK_PCIE_EXPCARD# 35
CARD_CLK_REQ# 35
CLK_PCIE_LOM 47
CLK_PCIE_LOM# 47
PCIE_LOM_CLKREQ# 47
CLK_MCH_3GPLL 10
CLK_MCH_3GPLL# 10
CLK_3GPLLREQ# 10
CLK_PCIE_XDP_3GPLL 52
CLK_PCIE_XDP_3GPLL# 52
RN10B
RN10A
R57
RN14B
RN14A
CLK_PCIE_SATA 15
CLK_PCIE_SATA# 15
SATA_CLKREQ# 17
No.40
DREF_SSCLK 10
DREF_SSCLK# 10
No.28
+3.3V_RUN
Non-iAMT
2
4
+3.3V_ALW
No.57
FSC
1
0
0
0
0
1
1
1
2.2KOhm
5%
2.2KOhm
5%
RN6A
RN6B
C80
10UF/10V
MLCC/+80-20%
pt_c0805_h53
1
3
R88
CKG_SMBDAT
+3.3V_ALW
C78
CLK_SDATA
FSB
0
0
1
1
0
0
1
1
FSA
1
1
1
0
0
0
0
1
CPU
100
133
166
200
266
333
400
RSVD
SRC
100
100
100
100
100
100
100
100
PCI
33
33
33
33
33
33
33
33
10PF/50V
MLCC/+/-0.5PF
Q19
2N7002
0Ohm
1
2 /*
5%
+3.3V_RUN
R89
No.57
C77
4.7UF/6.3V
MLCC/+/-10%
pt_c0603
2.2KOhm
5%
37
1
2
C74
0.047UF/10V
MLCC/+/-10%
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
C64
2.2Ohm
+CK_VDD_48
5%
2
pt_r0603
RN2A
33Ohm 2
RN2B
33Ohm 4
5% 1
5% 3
ICS9LPR333CKLFT
CLK_PCI_PCCARD
R81
5% 1
5% 3
CPU_XTP
CPU_XTP#
1
2
C67
C73
0.1UF/10V 0.1UF/10V
MLCC/+80-20%
MLCC/+80-20%
120 OHM@100MHz
C70
10PF/50V
C72
10PF/50V
MLCC/+/-0.5PF MLCC/+/-0.5PF MLCC/+/-0.5PF MLCC/+/-0.5PF
330Ohm/100Mhz
pt_l0805_h41
C76
10PF/50V
10PF/50V
+CK_VDD_MAIN2
CPU_BCLK
CPU_BCLK#
GNDCPU
GNDPCI1
GNDPCI2
GNDREF
GNDSRC1
GND48
GNDSRC2
SMBus address D2
L10
1
14
13
17
17
C55
C62
0.047UF/10V 4.7UF/6.3V
MLCC/+/-10% MLCC/+/-10%
pt_c0603
1
B
2.2Ohm
5%
2 +CK_VDD_A
pt_r0603
CPUT0
CPUC0
H_STP_PCI#
H_STP_CPU#
R54
CLK_MCH_BCLK 9
CLK_MCH_BCLK# 9
S 2
+CK_VDD_MAIN
120
15
31
35
21
4
42
68
17 CLK_PWRGD
L9
330Ohm/100Mhz
C75
C71
C56
C81
C63
C54
pt_l0805_h41
0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
10UF/10V
MLCC/+80-20%
MLCC/+80-20% MLCC/+80-20%
OHM@100MHz
MLCC/+80-20%
MLCC/+80-20%
pt_c0805_h53
MLCC/+80-20%
RN3A
33Ohm 2
RN3B
33Ohm 4
USB_48MHz/FSLA
FSLB/TEST_MODE
REF0/FSLC/TEST_SEL
UMA without iAMT

1
5% 1
5% 3
41
45
23
R53
2 R62
MCH_BCLK
MCH_BCLK#
X1
X2
R69
33Ohm5% 1
11
10
20
19
FSA
FSB
FSC
RN11A
33Ohm 2
RN11B
33Ohm 4
CPUT1_MCH
CPUC1_MCH
CLK_XTAL_IN
CLK_XTAL_OUT
1
1
5% 1
5% 3
PCI_SRC_STOP#
CPU_STOP#
VDDREF
2 33Ohm 5%
2 2.2KOhm 5%
+CK_VDD_A
25
24
18
R67
R68
5%
7
8
VDDA
GNDA
+CK_VDD_REF
CLK_SCLK
CLK_SDATA
+3.3V_RUN
VDDPCI1
VDDPCI2
+CK_VDD_48
PCI_ICH
16 CLK_PCI_ICH
30
36
+CK_VDD_MAIN
PCI_LOM
10 MCH_DREFCLK
10 MCH_DREFCLK#
VDDSRC1
VDDSRC2
VDDSRC3
VDDSRC4
CLK_ICH_48M
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
1
49
54
65
C60
0.047UF/10V
MLCC/+/-10%
G
S 2
CKG_SMBCLK
2.2KOhm
5%
37
1Ohm
5%
pt_r0603
+CK_VDD_REF
Q18
CLK_SCLK
2
0Ohm
PCI_LOM=FCTSEL1
FCTSEL1(PIN 34)
0 = UMA
1 = Disc.
GRFX down
2N7002
R86
R87
R47
1
/*
Pin43
DOT96T
27Mout
Pin44
Pin47
DOT96C 96/100M_T
27M_SSout SRCT0
5%
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
21
4
OF
68
DESCRIPTION:
CLK GEN. CY28547

3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
Pin48
96/100M_C
SRCC0
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
23
OF
DESCRIPTION:
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
68
3
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
24
4
OF
DESCRIPTION:
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
68
3
PROJECT: Lanai
A
REVISION
DATE:
1.2
SHEET
25
B
OF
DESCRIPTION:
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
68
C
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
26
4
OF
DESCRIPTION:
DESIGN ENGINEER :
RELEASE DATE :
68
3
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
27
4
OF
DESCRIPTION:
DESIGN ENGINEER :
Sean Kuo
RELEASE DATE :
68
3
CON1
Q1
+3.3V_RUN
+15V_ALW
D2
ENVDD
3.3PF/50V
R1
3.3PF/50V
C307 /*
3.3PF/50V
DDTC124EUA-7-F
LCD_BCLK+
1
1
10
0Ohm 5%
2
8.2PF/50V
/*
LCD_ACLK-
R7
LCD_BCLK-_C
10
C1
C11
0Ohm 5%
2
No.23
8.2PF/50V
/*
LCD_BCLK-
L2
1
+3.3V_RUN
+3V_DMIC
600Ohm Irat=200mA
10
2
4
1
R312
C305
OE# Vcc
A
GND
Y
5
4
L44
80Ohm
pt_l0603
AUD_DMIC_CLK_L
2
R552
47Ohm
5%
C543
33PF/50V
MLCC/+/-5%
/*
R313
100KOhm
5%
V_DMIC IS DEPENDENT ON MIC SELECTION (1.8V - 3.3V TYP)

Verify to ensure operability with chosen mic supplier.
USBP5_DUSBP5_D+
D
Q48
Note1: If only 1 digital mic, use AUD_DMIC_IN0.
90OHM/100MHz
/*
MURATA/DLW21SN900SQ2L
37,49,51,54 RUN_ON
Note2: If using 2 dig mics, also use AUD_DMIC_IN0.

This input supports 2 digimics. AUD_DMIC_IN1 is only
used to support 4 dig mics.
2 0Ohm 5%
1
G
2 S
2N7002
GND
PROJECT: Lanai
5
GND
1
SN74LVC1G125DBVR
/*
No.52
3
1
2
3
2
R314
10KOhm
5%
/*
No.19
1.2
2.2UF/25V
pt_c0805_h53
B
R1
44 AUD_DMIC_CLK
3
2
FDC658P_NL
0.1UF/50V
MLCC/+/-10%
pt_c0603
100KOhm
5%
2 0Ohm 5%
1
U1
REVISION
0.1UF/50V
MLCC/+/-10%
pt_c0603
C310
Q49
3
C
R2
R551
L1
C309
+3.3V_RUN
No.27
40mils
2 0Ohm 5%
GFX_PWR_SRC
40mils
+PWR_SRC
Populate R6 for
platform without DPST
support. No Stuff for
Discrete DSPT support
due to back up plan.
C306
10UF/10V
MLCC/+80-20%
pt_c0805_h53
17 CCD_VDD_ON
BACKLITEON
2
0Ohm 5%
C540
R3
GND
R1
1UF/10V/X7R
pt_c0603 MLCC/+/-10%
DTC114EKA Q71
/* /*
ICH_USBP5+
0.1UF/10V
MLCC/+/-10%
BIA_PWM
10
ICH_USBP5-
C312
+5V_CCD
10KOhm
/*
R2
10UF/10V
MLCC/+/-20%
pt_c0805_h57
/*
11
2
R540
+5V_ALW
C5
10KOhm
5%
3 D
SI2301BDS
/*
C7
C2
0.1UF/10V
0.047UF/10V
MLCC/+80-20%MLCC/+/-10%
GND
GND
Populate R1 for
DPST implementation
only.
R6
0.1UF/10V
MLCC/+80-20%
No.9
1
R5
0Ohm
5% /*
No.23
+LCDVCC
+3.3V_RUN
0Ohm 5%
2
10
LCD_ACLK+
LCD_BCLK+_C
+3.3V_RUN
GND
R8
Q70
16
RB751S40T1G
LCD_B0-
0Ohm 5%
2
0Ohm
R539
pt_r0603
1
2
+5V_RUN
D1
1
3.3PF/50V
No.9 No.48
E
R2
C314 /*
C308 /*
C16
R15
LCD_ACLK-_C
LCD_B0+
R4
0Ohm
5% /*
GND
LCD_B1-
LCD_A0-
GND
3
C
Q2
10
C311 /*
LCD_A0+
R16
2N7002
10
10
GND
2 S
LCD_A0LCD_A0+
47KOhm
5%
10
10
S 2
LCD_A0LCD_A0+
10
10
LCD_A1LCD_A1+
WTOB_CON_56P
JAE/FI-M56SB1
16
3
2
1
LCD_B1+
LCD_A1LCD_A2LCD_A2+
R35
2 0Ohm 5%
RB751S40T1G
LCD_ACLK+_C
C539
1UF/10V/X7R
pt_c0603
MLCC/+/-10%
/*
2
1
LCD_B2-
LCD_A1+
/* 1
3.3PF/50V
37 LCDVCC_TST_EN
LCD_A1LCD_A1+
Q4
1
2
1
3.3PF/50V
LCD_A2-
LCD_BCLK-_C
LCD_BCLK+_C
LCD_A2LCD_A2+
Q3
2N7002
GND
NP_NC1
47KOhm
5%
C315 /*
R26
LCD_ACLK-_C
LCD_ACLK+_C
/*
67
10
10
0.01UF/25V
MLCC/+/-10%
GND
SIDE_9
10
10
LCD_B0LCD_B0+
65
LCD_B1LCD_B1+
C6
22UF/10V
0.1UF/16V
MLCC/+80%-20% MLCC/+/-10%
pt_c1206_h71
No.56
C15
SIDE_1
LCD_B0LCD_B0+
10
10
C316 /*
57
LCD_B1LCD_B1+
C10
LCD_B2+
LCD_A2+
SIDE_2
R20
58
LCD_B2LCD_B2+
GND
38
+3.3V_RUN
LCD_DDCDAT 10
LCD_DDCCLK 10
LCD_B2LCD_B2+
SIDE_3
/*
100KOhm
5%
+3.3V_ALW
+3.3V_RUN
59
47PF/50V
47PF/50V
MLCC/+/-5%
MLCC/+/-5%
/*
/*
GND
GND
GFX_PWR_SRC
LCD_TST
+LCDVCC
R23
SIDE_4
R17
150Ohm
pt_r0603_h22
5%
C3
60
C4
SIDE_5
FDC653N_NL
LCD_SMBCLK 37
LCD_SMBDAT 37
BACKLITEON
61
No.9
SIDE_6
+5V_ALW
62
330KOhm
5%
LCDVCC_ON
Adress: A9H --Contrast

AAH --Backlight
SIDE_7
63
R24
LCD_CBL_DET_R 37
INVERTER_CBL_DET# 37
T135
SIDE_8
LCD_CBL_DET_R
INVERTER_CBL_DET#
LAMP_STAT#
64
AUD_DMIC_IN0 44
AUD_DMIC_CLK_L
SIDE_10
AUX_LCD_CBL_DET# 37
66
AUX_LCD_CBL_DET#
+5V_CCD
+3V_DMIC
NP_NC2
6
5
2
1
68
+LCDVCC
USBP5_DUSBP5_D+
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DATE:
SHEET
28
4
OF
68
DESCRIPTION:
LVDS CON
3
DESIGN ENGINEER :
RELEASE DATE :
2
CON12
SATA Connector
25
NP_NC3
23
NP_NC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SATA_TX0+
SATA_TX0-
ODD Connector
15
15
SATA_RXN0_C
SATA_RXP0_C
+5V_MOD
26
NP_NC4
Place caps close to

connector.
+3.3V_RUN
+3.3V_RUN
R270
R263
IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
4.7KOhm 5%
2
1
2
1
8.2KOhm 5%
DASP#
MLCC/+/-10%
MLCC/+/-10%
2
2
1 3900PF/50V/X7R
1 3900PF/50V/X7R
15
C319
C318
SATA_RX0SATA_RX0+
15
15
IDE_DD[0:15]
IDE_DD[0:15]
15
15
15
15
15
15
15
15
15
15
15
IDE_DDREQ
IDE_DIOW#
IDE_DIOR#
IDE_DIORDY
IDE_DDACK#
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_DA2
IDE_DCS3#
IDE_DDREQ
IDE_DIOW#
IDE_DIOR#
IDE_DIORDY
IDE_DDACK#
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_DA2
IDE_DCS3#
R244
2
CSEL2
470Ohm
5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
53
SATA_RXN0_C
SATA_RXP0_C
+5V_MOD
52
54
SATA_CON_22P
FOXCONN/LD2822H-SA3L6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
NP_NC2
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0
NP_NC4
NP_NC2
R285
2 56Ohm 15%
17 IDE_RST_MOD
NP_NC1
24
CON19
BtoB_CON_50P
NP_NC3
Place caps close to

connector.
+5V_HDD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
IDE_DIOR#
22Ohm
1 R269
2 IDE_DDACK#
PDIAG#
IDE_DA2
IDE_DCS3#
51
100KOhm
5%
/*
+5V_MOD
1
C268
MLCC/+/-10%
+5V_MOD
1
C260
MLCC/+80-20%
R254
+3.3V_RUN
0.1UF/10V/Y5V
2
MLCC/+80-20%
/*
1000PF/50V
0.1UF/10V/Y5V
2
MLCC/+80-20%
C46
1
C254
0.1UF/10V/Y5V
pt_c0805_h57
10UF/10V/X5R
2
MLCC/+/-20%
/*
C58
+5V_HDD
1
2
3
4
5
6
7
SUYIN/800194MR050S520ZL
+5V_ALW
+5V_MOD
+5V_RUN
+5V_ALW
+5V_HDD
G
D
2 S
2N7002
Q12
2 S
D
Q44
G
3
2 S
2N7002
Q43
38
MODC_EN
1
G
C240
C45
1
HDDC_EN
5%
1
MLCC/+/-10%
Q11
38
1
100KOhm
pt_c0603
0.1UF/25V
2
1
R256
2
0Ohm
pt_r0805_h24
/*
MLCC/+/-10%
2
1
1
2
3
4
SI4800BDY
+15V_ALW
HDD_EN_5V
2
1
100KOhm 5%
R241
R46
R51
100KOhm
5%
Q41
D
0.01UF/25V/X7R
2
1
MLCC/+/-10% C267
2
R249
100KOhm
5%
8
7
6
5
pt_c0603
0.1UF/25V
2
1
+15V_ALW
+5V_ALW2
+5V_ALW2
0Ohm
pt_r0805_h24
R48
100KOhm
5%
1
C57
pt_c0805_h57
10UF/10V/X5R
2
1
G
SI3456BDV-T1-E3
/*
2
1
C231
R50
2
MLCC+/-10%
1UF/16V/X5R
pt_c0603
6
5
S 4
MLCC/+/-20%
pt_c0805_h57
10UF/10V/X5R
2
1
MLCC/+/-20%
C266
+5V_RUN
Q9
1
2
3
2N7002
2 S
2N7002
R248
100KOhm
5%
R58
100KOhm
5%
PROJECT: Lanai
A
REVISION
1.2
DATE:
SHEET
31
B
OF
68
DESCRIPTION:
SATA(HDD & CD_ROM)

C
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
D
Place these caps as close as

possible to the device pins.
C206
0.01UF/16V
MLCC/+/-10%
C208
0.01UF/16V
MLCC/+/-10%
C207
0.01UF/16V
MLCC/+/-10%
C205
0.01UF/16V
MLCC/+/-10%
+3.3V_RUN
C223
0.01UF/16V
MLCC/+/-10%
61
16
16
16
16
16
PCI_AD17
R207
PCI_PAR
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
1
2
R5C832_IDSEL
100Ohm 5%
Route to CLK GEN .

16
PCI_RST#
1
2
Reserve for EMI

C221
10PF/50V
MLCC/+/-0.5PF
/*
1.2
67
C245
0.01UF/16V
MLCC/+/-10%
C255
10UF/10V
MLCC/+80-20%
pt_c0805_h53
VCC_RIN
DATE:
CLKRUN#
32
B
2 0Ohm 5% /*
R222
2 0Ohm 5%
The ICH schematics need to

include a pull-up resistor
to implement CLKRUN#, and
the ICH schematics must
have a pull-down, or
constantly drive the
signal low, in order to
disable CLKRUN#.
REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
71
119
GBRST#
PCIRST#
121
PCICLK
70
117
4
13
22
28
54
62
63
68
118
122
AGND1
AGND3
AGND2
AGND4
AGND5
99
102
103
107
111
+3.3V_R5C832
R488
10KOhm
5%
PME#
HWSPND#
69
MSEN
58
XDEN
55
UDIO5
57
UDIO3
UDIO4
65
59
UDIO2
56
UDIO1
60
UDIO0/SRIRQ#
72
IRQ_SERIRQ
17,37
INTA#
115
PCI_PIRQD#
16
INTB#
116
PCI_PIRQC#
16
TEST
66
1
R239
2
10KOhm
5%
2
R236
1
100KOhm
5%
+3.3V_R5C832
Memory Stick Enable

XD Card Enable
+3.3V_R5C832
Serial ROM disable

SD Card Enable
MMC Card Enable
1394 : INTA#
Pull-up resistors
to +3.3V_RUN are
required on the ICH
schematics.
4
4in1 : INTB#
T129
CLKRUN#
R225
R487
100KOhm
5%
R5C833_TQFP128
C.S R5C833 TQFP128
10KOhm
5%
/*
No.24
Ricoh R5C832 Package Type : TQFP-128-P1 (1414)

5
SHEET
R486
124
123
23
24
25
26
29
30
31
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
17,37
SYS_PME#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL
86
38
VCC_ROUT1
VCC_ROUT2
VCC_ROUT3
VCC_ROUT4
VCC_ROUT5
125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
33
7
21
35
45
8
R211
10Ohm
5%
/*
Pull-up to
+3.3V_ALW
is required on
SYS_PME#
on SIO
schematics.
(From SIO).
0 ohm of PME#
is no-stuff
to prevent
backdrive
from this
signal
since the
controller
is powered of
the
RUN rail
21 CLK_PCI_PCCARD
REVISION
VCC_3V
VCC_MD
16 PCI_REQ1#
16 PCI_GNT1#
16 PCI_FRAME#
16 PCI_IRDY#
16 PCI_TRDY#
16 PCI_DEVSEL#
16 PCI_STOP#
16 PCI_PERR#
16 PCI_SERR#
5% pt_r0603
PCI_AD[0..31]
C238
1UF/10V/X7R
MLCC/+/-10%
pt_c0603
PCI_AD17
C204
0.01UF/16V
MLCC/+/-10%
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
Pull-up
resistors to
+3.3V_RUN are
required on
the ICH
schematics.
PROJECT: Lanai
0Ohm
0.47UF/10V
MLCC/+/-10%
pt_c0603
100KOhm
5%
16
16
34
64
114
120
C239
2
C216
0.01UF/16V
MLCC/+/-10%
0.47UF/10V
MLCC/+/-10%
pt_c0603
R238
VCC_PCI3V_1
VCC_PCI3V_2
VCC_PCI3V_3
VCC_PCI3V_4
VCC_PCI3V_5
VCC_PCI3V_6
PCI / OTHER
16
+3.3V_R5C832
1
C222
1
C211
0.01UF/16V
MLCC/+/-10%
0.1UF/10V
MLCC/+80-20%
C259
0.01UF/16V
MLCC/+/-10%
1
C244
2
+3.3V_R5C832
+3.3V_R5C832
U31B
10
20
27
32
41
128
C203
10UF/10V
MLCC/+80-20%
pt_c0805_h53
+3.3V_R5C832
R247
C258
10UF/10V
MLCC/+80-20%
pt_c0805_h53
+3.3V_R5C832
OF
68
DESCRIPTION:
R5C833 - PCI INTERFACE

C
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
D
For SD/MS Card Power

No.24
+3.3V_R5C832
+3.3V_RUN_CARD
U33
GND
OC#
EN
IN
OUT
TPS2051BDBVR
MC_PWR_CTRL_0
+3.3V_RUN_CARD
2
3
4
C472
C481
1UF/10V
MLCC/+80%-20%
pt_c0603
0.1UF/10V
MLCC/+80-20%
1
C459
0.01UF/16V
MLCC/+/-10%
R456
150KOhm
5%
C458
0.01UF/16V
MLCC/+/-10%
1
C461
0.01UF/16V
MLCC/+/-10%
U31A
Normal Frequency : 24.576 MHz

Frequency Tolerance : +/- 50ppm @ 25C
Driver Level : .1 mW
Load capacitance : 10pF
Equ. Resistance : 50 Ohm Max
No.25
Shunt Capacitance : 7.0pF Max
+3.3V_RUN_PHY
Recommended Crystal Specs from Data Sheet:
AVCC_PHY3V_1
AVCC_PHY3V_2
AVCC_PHY3V_3
AVCC_PHY3V_4
98
106
110
112
TPBIAS0
113
TPBIAS0
TPBN0
104
TPB0N
TPBP0
105
TPB0P
TPAN0
108
TPA0N
TPAP0
109
TPA0P
+3.3V_RUN_CARD
Place these components close to

the flash memory card connector
15PF/50V
MLCC/+/-5%
94
X5
15PF/50V
2
0Ohm 5%
95
XO
TPB0N
34
TPB0P
34
No.24
MLCC/+/-5%
R5C832
:
R5C833 :
0.01uF => stuff

0.01uF => No stuff
RICHO_FILO
101
REXT
100
VREF
TPA0P
34
10KOhm 1%
2
C243
RICHO_VREF
1
0.01UF/16V
SD/XD/MS_CMD
C457
2.2UF/16V
MLCC/+/-10%
pt_c0603
SD/XD/MS_DATA1
SD/XD/MS_DATA0
SD/XD/MS_DATA2
MS_INS#
SD/XD/MS_DATA3
SD/XD/MS_CLK
SD/XD/MS_DATA3
SD/XD/MS_CMD
SD/XD/MS_CLK
SD/XD/MS_DATA0
SD/XD/MS_DATA1
SD/XD/MS_DATA2
SD_CD#
SD_WP#
R474
FIL0
18
20
22
24
26
28
30
32
33
29
25
21
17
13
10
8
35
1
2
3
SD_WP#(XDR/B#)
RICHO_REXT
96
/*
MS_3(DATA1)
MS_4(DATA0)
MS_5(DATA2)
MS_6(INS)
MS_7(DATA3)
MS_8(SCLK)
MS_9(VCC)
MS_10(VSS)
SD_1(DAT3)
SD_2(CMD)
SD_3(VSS)
SD_4(VDD)
SD_5(CLK)
SD_6(VSS)
SD_7(DAT0)
SD_8(DAT1)
SD_9(DAT2)
SD(CD2/WP2/GND)
SD(CD1)
SD(WP1)
MLCC/+/-10%
34
XD_0(GND)
XD_1(CD)
XD_2(R/-B)
XD_3(-RE)
XD_4(-CE)
XD_5(CLE)
XD_6(ALE)
XD_7(-WE)
XD_8(-WP)
XD_9(GND)
XD_10(D0)
XD_11(D1)
XD_12(D2)
XD_13(D3)
XD_14(D4)
XD_15(D5)
XD_16(D6)
XD_17(D7)
XD_18(VCC)
MS_1(VSS)
MS_2(BS)
0.01UF/16V
TPA0N
+3.3V_RUN_CARD
SD/XD/MS_DATA0
SD/XD/MS_DATA1
SD/XD/MS_DATA2
SD/XD/MS_DATA3
XD_DATA4
XD_DATA5
XD_DATA6
XD_DATA7
41
40
39
38
37
36
34
31
27
23
19
15
12
11
9
7
6
5
4
14
16
S 2
C256
1
R483
XD_CDSW#
SD_WP#(XDR/B#)
SD/XD/MS_CLK
XD_CE#
XD_CLE
XD_ALE
SD/XD/MS_CMD
XD_WP#
XI
24.576Mhz
+/-50ppm/10PF
1394_XO
34
C477
TPBIAS0
CARD_READER_41P
42
43
44
45
1394_XI
IEEE1394/SD
NP_NC1
NP_NC2
P_GND1
P_GND2
CON20
TAISOL/144-2420000900
C478
Q72
2N7002
XD_CDSW#
MLCC/+/-10%
No.47
Place as close to
R5C832 as possible.
MDIO17
87
XD_DATA7
MDIO16
92
XD_DATA6
MDIO15
89
XD_DATA5
MDIO14
91
XD_DATA4
MDIO13
90
SD/XD/MS_DATA3
MDIO12
93
SD/XD/MS_DATA2
MDIO11
81
SD/XD/MS_DATA1
MDIO10
82
SD/XD/MS_DATA0
MDIO05
75
XD_WP#
MDIO08
88
SD/XD/MS_CMD
MDIO19
83
XD_ALE
MDIO18
85
XD_CLE
MDIO02
78
XD_CE#
SD_CD#
SD_WP#(XDR/B#)
MDIO03
77
MDIO00
80
D20
1
1N4148W-7-F
2
79
D21
1
1N4148W-7-F
2
MDIO01
XD_CDSW#
MS_INS#
97
84
1
R484
2 SD/XD/MS_CLK
0Ohm 5%
MDIO04
76
MC_PWR_CTRL_0
MDIO06
74
MS_LED#
MDIO07
73
RSV
No.51
MDIO09
C552
T130
2
TPC26T 1
10PF/50V
MLCC/+/-0.5PF
R5C833_TQFP128
C.S R5C833 TQFP128
No.24
PROJECT: Lanai
A
REVISION
DATE:
1.2
SHEET
33
B
OF
68
DESCRIPTION:
R5C833 - FLASH MEMORY PART RELEASE DATE :

C
<OrgName>
D
DESIGN ENGINEER :
E
Place these caps as close to the R5C832 as possible.

L18
1
0.1UF/10V
MLCC/+80-20%
C233
C257
10UF/10V
MLCC/+80-20%
pt_c0805_h53
+3.3V_R5C832
MURATA/BLM15HD601SN1D
600Ohm/100MHz Irat=0.3A
1
C230
1000PF/50V
MLCC/+/-10%
pt_c0603
+3.3V_RUN_PHY
C235
0.01UF/16V
MLCC/+/-10%
Place as close as possible to 1394 connector.

Also, place 0 ohm close to the
chokes to minimize stubs
3
Place as close as possible to R5C832

0Ohm 5%
0Ohm 5%
C453
0.33UF/25V
MLCC/+80%-20%
pt_c0603
4
3
2
1
TPXB1+
TPXB1-
IEEE_1394_CON_4P
R377
SIDE_G1
LTPB0+
2
R470
2
R459
0Ohm 5%
R455
56Ohm
1%
R454
56Ohm
1%
1
0.01UF/16V
MLCC/+/-10%
SIDE_G2
TPXA1+
TPXA1-
C456
R371
4
6
CON13
FOXCONN/UV31413-WR56P-7F
120OHM
/*
MURATA/DLW21HN121SQ2L
L31
LTPA0-
R375
LTPA0+
Common mode chokes should

be 110- ohms impedance.They
are reserved for EMI
1
56Ohm
1
56Ohm
1%
1%
TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N
TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N
33
33
33
33
33
1
2
R458
5.1kOhm 1%
1394_TPB1_R 2
1
C464
270PF/50V
MLCC/+/-10%
L32
1394 pairs should be

routed as 110-ohm
differential
R378
LTPB0-
120OHM
/*
MURATA/DLW21HN121SQ2L
2
0Ohm 5%
PROJECT: Lanai
A
REVISION
1.2
DATE:
SHEET
34
B
OF
68
DESCRIPTION:
R5C833 - IEEE1394 PART

C
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
D
USBP6_D-
ICH_USBP6-
16
Express Card
+1.5V_CARD
R412
0Ohm 5%
+1.5V_CARD Max. 650mA, Average 500mA.

+3V_CARD Max. 1300mA, Average 1000mA.
USBP6_D+
90OHM/100MHz
/*
0Ohm 5%
C438
0.1UF/10V
MLCC/+80-20%
R404
ICH_USBP6+
16
L33
C440
0.1UF/10V
MLCC/+80-20%
+1.5V_RUN
+3.3V_RUN
+3.3V_SUS
+3.3V_CARDAUX
+3.3V_CARD
+1.5V_CARD
D
U28
+3.3V_CARD
Please the cap

near connector.
R438
2 100KOhm
5%
R433
2 0Ohm 5% /*
15
3
5
11
13
SHDN#
STBY#
SYSRST#
PERST#
CPPE#
CPUSB#
OC#
8
10
9
19
NC
GND1
GND2
RCLKEN
21
18
AUX_IN
3.3VIN_1
3.3VIN_2
1.5VIN_2
1.5VIN_1
20
1
6
+3.3V_SUS
CARD_RESET#
5%
5%
+1.5V_RUN
+3.3V_RUN
+3.3V_SUS
+3.3V_CARDAUX
+3.3V_CARD
+1.5V_CARD
C437
0.1UF/10V
MLCC/+80-20%
C436
0.1UF/10V
MLCC/+80-20%
C444
0.1UF/10V
MLCC/+80-20%
C441
0.1UF/10V
MLCC/+80-20%
C432
0.1UF/10V
MLCC/+80-20%
16 PCIE_TX416 PCIE_TX4+
1 100KOhm
1 100KOhm
2
2
16 PCIE_RX416 PCIE_RX4+
R417
R418
EXPRCRD_PWREN#
21 CARD_CLK_REQ#
38 EXPRCRD_PWREN#
21 CLK_PCIE_EXPCARD#
21 CLK_PCIE_EXPCARD
CARD_RESET#
+3.3V_CARD
38,47,50 PCIE_WAKE#
+3.3V_CARDAUX
EXPRCRD_PWREN#
CPUSB#
R5538D001_TR_F
17,50 ICH_SMBCLK
17,50 ICH_SMBDATA
+1.5V_CARD
16
7
USBP6_DUSBP6_D+
CPUSB#
Please the cap

near connector.
38 EXPRCRD_STDBY#
10,16,37 PLTRST#
CON8
JAE/PX10ABSB00G-1
1 1 P_GND1 29
2 2 NP_NC1 27
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25 NP_NC2 28
26 26 P_GND2 30
C448
10UF/10V
MLCC/+80-20%
pt_c0805_h53
C446
0.1UF/10V
MLCC/+80-20%
1
C449
0.1UF/10V
MLCC/+80-20%
+3.3V_SUS
AUX_OUT
3.3VOUT_1
3.3VOUT_2
1.5VOUT_1
1.5VOUT_2
17
2
4
12
14
C431
0.1UF/10V
MLCC/+80-20%
EXPRESS_CARD_26P
PCI-Express TX and RX direct to connector .
Please the cap

near pin 12 &
14 (1.5VIN).
Please the cap

near pin 2 & 4
(3.3VIN).
Please the cap

near pin 17
(AUXIN).
Please the cap

near pin 15
(AUXOUT).
Please the cap

near pin 3 & 5
(3.3VOUT).
Please the cap

near pin 11 &
13 (1.5VOUT).
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
35
4
OF
68
DESCRIPTION:
PCI-Express Card
3
<OrgName>
DESIGN ENGINEER :
Terry_Lin
RELEASE DATE :
2
ICH_AZ_MDC_SDOUT
R243
/*
10Ohm
5%
C247
2
10PF/50V
MLCC/+/-0.5PF
/*
MDC
R245
1
2
0Ohm
5%
13
15
17
19
Q42
+5V_SUS
+3.3V_SUS
ICH_AZ_MDC_BITCLK 15
ICH_AZ_MDC_BITCLK
ICH_AZ_MDC_RST1#
2 S
D
3
15 ICH_AZ_MDC_RST#
2
4
6
8
10
12
R232
R240
10KOhm
5%
/*
100KOhm
5%
/*
MDC_CONN_12P
TYCO/1-1775844-2
BSS138
/*
2
4
6
8
10
12
ICH_AZ_MDC_SYNC
MDC_SDIN
ICH_AZ_MDC_RST1#
GND2
GND4
GND6
NP_NC2
15 ICH_AZ_MDC_SYNC
ICH_AZ_MDC_SDOUT
1
3
5
7
9
11
14
16
18
20
15 ICH_AZ_MDC_SDOUT
1
3
5
7
9
11
GND1
GND3
GND5
NP_NC1
CON18
43 MDC_RST_DIS#
Note: MDC DISABLE.

3
If platform requires MDC disable, populate this circuit.

If MDC disable isn't required, connect ICH_A2_MDC_RST# directly to JMDC connector.
10Ohm
5%
C237
1
pt_c0805_h53
/*
0.1UF/10V
2
R251
4.7UF/10V
2
C248
1
5%
2
33Ohm
MDC_SDIN
MLCC/+80-20%
1 R246
MLCC/+80-20%
+3.3V_SUS
ICH_AZ_MDC_BITCLK
15 ICH_AZ_MDC_SDIN1
C251
10PF/50V
MLCC/+/-0.5PF
/*
Place these caps near

MDC module.
PROJECT: Lanai
A
REVISION
DATE:
1.2
SHEET
36
B
OF
68
DESCRIPTION:
MDC CONN
C
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
D
R465
R441
R466
TPC26T T128
TPC26T T126
1
1
57
58
59
60
61
62
63
64
56
LRESET#
PCICLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
SER_IRQ
PCI POWER/LPC BUS
16 ICH_EC_SPI_CLK
16 ICH_EC_SPI_DIN
16 ICH_EC_SPI_DO
102
105
107
HSTCLK
HSTDATAIN
HSTDATAOUT
40 EC_FLASH_SPI_CLK
40 EC_FLASH_SPI_DIN
40 EC_FLASH_SPI_DO
103
106
108
FLCLK
FLDATAIN
FLDATAOUT
109
110
GPIO80
GPIO81
87
86
85
BC_CLK
BC_DAT
BC_INT#
1
1
CLK_PCI_5025
C447
4.7PF/50V
/*
MLCC/+/-0.25PF
17 SIO_PWRBTN#
42 SNIFFER_YELLOW#
38
38
38
SNIFFER_YELLOW#
BC_CLK
BC_DAT
BC_INT#
MEC5025_XTAL2
2
R429 1
2 10KOhm
5%
MEC5025_XTAL1
MEC5025_XTAL2
MEC5025_XOSEL
122
124
123
R432
2
2.2KOhm
IMVP_PWRGD 17,51,53
+3.3V_RUN
FAN1_TACH
43
OUT2/PWM3
OUT9/PWM2
OUT11/PWM1
OUT10/PWM0
48
47
46
45
AUX_EN_WOWL_1
3.3V_SUS_ON
nEC_SCI/SPDIN2
SGPIO45/MSDATA/SPDOUT2
SGPIO44/MSCLK/SPCLK2
SGPIO46/SPDIN1
SGPIO47/SPDOUT1
SGPIO31/TIN1/SPCLK1
66
55
54
69
68
67
70
71
SGPIO40
SGPIO41
SGPIO42
SGPIO43
91
90
89
4
1
2
3
52
11
nPWR_LED
nBAT_LED
nFWP
GPIOA3/WINDMON
GPIO83/32KHZ_OUT
PWRGD
nRESET_OUT/OUT6
TEST_PIN
115
114
84
73
117
49
53
72
32.768KHZ
+/-10ppm/6PF
MEC5025_XTAL2_R 4
+3.3V_ALW
1
1 MEC5025_XTAL1
L35
120Ohm/100Mhz
1
2
L36
120Ohm/100Mhz
MEC_VCC_PLL
C433
2
C434
MEC_AGND
XTAL1
XTAL2
XOSEL
15PF/50V
MLCC/+/-5%
12PF/50V
MLCC/+/-5%
C455
22
CLOCK
VR_CAP
125
AGND
104
VCC_PLL
VSS1
VSS2
VSS3
VSS4
VSS5
113
88
74
51
26
101
POWER PLANES
VSS_PLL
0.1UF/10V
MLCC/+/-10%
IMVP_VR_ON
53
R445
TPC26T
HOST_DEBUG_RX 50
+3.3V_ALW
INVERTER_CBL_DET# 28
AUX_LCD_CBL_DET# 28
SIO_SPI_CS#
LOM_SMB_ALERT#
SFPI_EN
DOCK_SMB_ALERT#
LCD_SMBCLK
R406
2
LCD_SMBDAT
R388
2
PBAT_SMBDAT
R440
2
PBAT_SMBCLK
R435
2
8.2KOhm
1
5%
8.2KOhm
1
5%
2.2KOhm
1
5%
2.2KOhm
1
5%
Pin 3
+3.3V_ALW
T125
HOST_DEBUG_TX 50
R464
2
1 1MOhm
LCD_CBL_DET
5%
INVERTER_CBL_DET#
AUX_LCD_CBL_DET#
SIO_SPI_CS#
R387
2
MLX_53398-0371
3
2
1
CON2
WTOB_CON_3P
/*
RN38B
RN38A
4.7KOhm
5%
pt_2r4p0402_h18
16
LOM_SMB_ALERT# 17
0.9V_DDR_VTT_ON 58
SIO_EXT_SMI# 17
BAT2_LED#
BAT1_LED#
FWP#
1
T136
42
42
4.7KOhm
5%
pt_2r4p0402_h18
THRM_SMBCLK
THRM_SMBDAT
TPC26T
2
2
RUNPWROK
51,53
RESET_OUT# 51
MEC_TEST_PIN
R467
0Ohm
5%
No.33
R549 0Ohm 5%
1
1
R550 0Ohm 5%
1
EC_PWM_2
EC_32KHZ
T127
54
38
+3.3V_ALW
TPC26T
1 = Enabled.
0 = Disabled
R391
Populate
for flash
corruption
issue.
1KOhm
5% /*
SFPI_EN
MEC5025-NU
L37
120Ohm/100Mhz
AUX_EN_WOWL 50
SIO_EXT_SCI# 17
59
15
44
1
DOCK_SMBDAT
8.2KOhm
1
5%
8.2KOhm
1
5%
Pin 1
1 0Ohm 5%
SIO_EXT_SCI#
PS_ID
SIO_RCIN#
BEEP
R402
2
+3.3V_ALW
3.3V_SUS_ON 49
BREATH_LED# 42
DEBUG_ENABLE#
DOCK_SMBCLK
No.25
1
5% /*
X4
1 4.7UF/10V VR_CAP
MLCC/+/-10%
0Ohm
5%
SGPIO35
SGPIO36(SFPI_EN)
SGPIO37
GPIO96/TOUT1
OUT7/nSMI
+5V_ALW
TPC26T
BC
R426
C419
2
pt_c0805_h37
GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1
43
42
41
MISCELLANEOUS
32KHz Clock
PBAT_SMBDAT
PBAT_SMBCLK
SBAT_DH_SMBDAT
SBAT_DH_SMBCLK
1.5V_RUN_ON 55
1.25V_RUN_ON 58
THRM_SMBDAT 43
THRM_SMBCLK 43
SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX
LCD_SMBCLK 28
LCD_SMBDAT 28
T29
TPC26T
T116
TPC26T
THRM_SMBDAT
THRM_SMBCLK
HOST/8051 SPI
Place these caps close to MEC5025

C422
1UF/10V
MLCC/+/-10%
pt_c0603
1.8V_RUN_ON 49
LCDVCC_TST_EN 28
T41 TPC26T
1
T40 TPC26T
1
PBAT_SMBDAT 57,59
PBAT_SMBCLK 57,59
LCDVCC_TST_EN
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
8051_RX
8051_TX
GPIO94/IMCLK
GPIO95/IMDAT
KCLK
KDAT
GPIOA6/EMCLK
GPIOA7/EMDAT
GPIO20/PS2CLK/8051RX
GPIO21/PS2DAT/8051TX
1
1
SGPIO34/A20M
OUT5/KBRST
75
76
77
78
79
80
81
82
93
94
95
96
111
112
9
10
97
98
99
100
92
50
GPIO
10Ohm
5% /*
8051_RX
8051_TX
10,16,35 PLTRST#
21 CLK_PCI_5025
15 LPC_LFRAME#
15
LPC_LAD0
15
LPC_LAD1
15
LPC_LAD2
15
LPC_LAD3
17,32 CLKRUN#
17,32 IRQ_SERIRQ
Place close to
pin 58
R450
CLK_TP_SIO
DAT_TP_SIO
50
50
CLK_PCI_5025
41
41
GPIO11/AB2_DATA
GPIO12/AB2_CLK
GPIO13/AB1G_DATA
GPIO14/AB1G_CLK
GPIO87/AB1C_DATA
GPIO86/AB1C_CLK
GPIO85/AB1D_DATA
GPIO84/AB1D_CLK
GPIO93/AB1F_DATA
GPIO92/AB1F_CLK
GPIO91/AB1E_DATA
GPIO90/AB1E_CLK
T34
LCD_SMBCLK
LCD_SMBDAT
DOCK_SMBCLK
DOCK_SMBDAT
SNIFFER_GREEN#
41
BC_A_INT#
BC_A_DAT
BC_A_CLK
15 SIO_A20GATE
42 SNIFFER_GREEN#
100KOhm100KOhm100KOhm100KOhm
5%
5%
5%
5%
/*
/*
AUX_LCD_CBL_DET#
INVERTER_CBL_DET#
SNIFFER_GREEN#
SNIFFER_YELLOW#
41
41
R444
Non
iAMT
8
7
6
5
C462
0.1UF/10V
MLCC/+/-10%
49,51
SUS_ON
28,49,51,54 RUN_ON
59
AC_OFF
AB1B_CLK/GPIOA4
ACCESS BUS AB1B_DATA/GPIOA2
AB1A_CLK
AB1A_DATA
ALWON
54
SNIFFER_PWR_SW# 42
INSTANT_POWER_SW# 41
MAIN_PWR_SW# 42
ACAV_IN
43,57
C443
0.1UF/10V
MLCC/+/-10%
AUX_ON
SUS_ON
RUN_ON
ALWON
120
119
126 INSTANT_ON_SW# R431 1
10KOhm 5%
127
128
118
SNIFFER_RTC_GPO
C442
0.1UF/10V
MLCC/+/-10%
TPC26T T118
+3.3V_ALW
58 DDR_ON
41 TP_DET#
54 ALW_PWRGD_3V_5V
17 SIO_SLP_S3#
17 SIO_SLP_S5#
49 3.3V_RUN_ON
ALWON
POWER_SW_IN2#/GPIO23
POWER_SW_IN1#/GPIO22
POWER_SW_IN0#
ACAV_IN
POWER SWITCH
BGPO0/GPIOA5
C423
0.1UF/10V
MLCC/+/-10%
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
RN39A
RN39B
RN39C
RN39D
100KOhm
5%
10UF/6.3V
MLCC/+/-20%
pt_c0805_h53
4.7KOhm2
4.7KOhm4
4.7KOhm6
4.7KOhm8
0.1UF/10V
MLCC/+/-10%
C463
1
3
5
7
POWER PLANES
R428
KSI7/GPIO19
KSI6/GPIO17
KSI5/GPIO10
KSI4/GPIO9
KSI3/GPIO8
KSI2/GPIO7/BC_A_INT#
KSI1/GPIO6/BC_A_DAT
KSI0/SGPIO30/BC_A_CLK
ICH_RSMRST#
+5V_RUN
+3.3V_ALW
MEC5025_VCC0
21
44
65
83
116
10,17 ICH_CL_PWROK
TPC26T T28
17 ICH_RSMRST#
121
33
34
35
36
37
38
39
40
58 1.8V_SUS_PWRGD
7 EC_CPU_PROCHOT#
Non
iAMT
VCC0
VCC1_1
VCC1_2
VCC1_3
VCC1_4
VCC1_5
KSO17/GPIOA1/AB1H_DATA
KSO16/GPIOA0/AB1H_CLK
GPIO5/KSO15
GPIO4/KSO14
KSO13/GPIO18
KSO12/OUT8
KSO11/GPIOC7
KSO10/GPIOC6
KSO9/GPIOC5
KSO8/GPIOC4
KSO7/GPIO3
KSO6/GPIO2
KEYBOARD/MOUSE
KSO5/GPIO1
KSO4/GPIO0
KSO3/GPIOC3
KSO2/GPIOC2
KSO1/GPIOC1
KSO0/GPIOC0
0Ohm
2
pt_r0603
12
13
14
15
16
17
18
19
20
23
24
25
27
28
29
30
31
32
CHIPSET_ID0
CHIPSET_ID1
R430
1
5%
C439
21 CKG_SMBDAT
21 CKG_SMBCLK
+RTC_CELL
2.7KOhm /*
AC_OFF
2 5%
+RTC_CELL
R427
1
+3.3V_ALW
Place cap close to pin 121.

U29
2.7KOhm
RUN_ON
2 5%
HOLD1
2.7KOhm
SUS_ON
2 5%
R393
1
HOLD2
R409
1
(GPIO4)
(GPIO5)
CHIPSET
CHIPSET_ID1
CHIPSET_ID0
Common Boot block sequence
------------------------------------------------------0
0
Intel-SR
0
1
ATI-RR
1
0
TBD
1
1
Parker(Intel/ATI)
R386
Flash Recovery
1KOhm
5%
For MEC5025 Rev. C : C4519= 22uF and

populate workaround circuit.
For MEC5025 Rev. D : C4519= 4.7uF and
depopulate workaround circuit.
R416
Pin 1
Debug Serial Port

Flash Recovery
Port.
CON4
1
7
100KOhm
5%
/*
6
SIDE2
SIDE1
5
4
3
2
1
5
4
3
2
1
WTOB_CON_5P
/*
28 LCD_CBL_DET_R
R73
R65
1MOhm
5%
10KOhm
5%
10KOhm
5%
8051_RX
8051_TX
R66
1
0Ohm
2
/* 5%
DEBUG_ENABLE#
Not Stuff 0 ohm when doing

Flash recovery.
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
37
OF
4
DESCRIPTION:
68
No.18
No.36
LOM_SMB_ALERT# R405
DOCK_SMB_ALERT#R403
SIO_SPI_CS#
R392
SBAT_DH_SMBDAT R389
SBAT_DH_SMBCLK R407
TP_DET#
R408
BC_DAT
R471
BC_A_DAT
R434
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
DDR_ON
ICH_RSMRST#
CHIPSET_ID0
CHIPSET_ID1
1
2
1
1
2 100KOhm 5%
1 100KOhm 5%
2 0Ohm 5%
/*
2 0Ohm 5%
MEC5025
R553
R394
R411
R554
100KOhm
5%
LCD_CBL_DET
R460
200KOhm
5%
DESIGN ENGINEER :
RELEASE DATE :
3
R461
100KOhm 5%
10KOhm 5%
10KOhm 5% /*
10KOhm 5%
10KOhm 5%
100KOhm5%
100KOhm5%
100KOhm5% /*
/*
R64
MLX_53398-0571
R439
2N7002
2
2 S
R453
100KOhm
5% /*
+3.3V_ALW
Pin 5
G
+3.3V_ALW
Q55
1
2
VR_CAP
B 1
PMBS3906
/*
3
C
RB500V-40
/*
0Ohm
1
5% /*
R390
2
10KOhm
5%
/*
FWP#
Flash Write
Protect bottom
4K of internal
bootblock flash
1
Q56
R410
1
C425
4.7UF/6.3V /*
2
1
pt_c0603 MLCC/+/-10%
E
2
D18
2
R452
100KOhm
5%
10KOhm
5% /*
R413
100KOhm
5% /*
ALWON
+3.3V_ALW
Low=
Write Protected.
+3.3V_ALW
External Work Around

Circuit.
STANLY_HSU
2
2 10kOhm
4 10kOhm
6 10kOhm
8
10kOhm
+3.3V_ALW
SYS_PME#
PCIE_WAKE#
+3.3V_ALW
No.16
2 10KOhm 5% DOCK_SMB_PME#
R545 1
+5V_ALW
RN40A
RN40B
RN40C
RN40D
1
3
5
7
U34
D
59 PBAT_PRES#
Discrete
R476
BID2
VGA_IDENTIFY
R469
10KOhm
5%
BID0
BID1
BID2
VGA_IDENTIFY
R468
10KOhm
5%
10KOhm
5%
10KOhm
5%
10KOhm
5%
R472
15,41 LED_MASK#
T83
1
R516 2
17 SIO_EXT_WAKE#
16 ICH_PME#
17 ICH_PCIE_WAKE#
50 WLAN_RADIO_DIS#
R475
35 EXPRCRD_PWREN#
35 EXPRCRD_STDBY#
53 IMVP6_PROCHOT#
51 5V_3V_1.8V_1.25V_RUN_PWRGD
UMA
VGA_IDENTIFY
1 = Discrete Gfx.
0 = UMA
BID2 BID1 BID0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
LOM_LOW_PWR
SC_DET#
47 LOM_LOW_PWR
10KOhm
/*
5%
10KOhm
5%
/*
SYS_PME#
PCIE_WAKE#
32
SYS_PME#
35,47,50 PCIE_WAKE#
50 USB_BACK_EN#
No.30
1
R473
R477
10KOhm
5%
/*
1
R478
Board ID Straps
+3.3V_ALW
SBAT_PRES#
T82
M08
ENG1(X00)
ENG2(X01)
ENG3(X02)
ENG4(X03)
QT(X04)
RAMP(A00)
28
R514 R479 , ECE5011 is suff ,

ECE5021 is not stuff
M08B
ENG1(X00)
ENG2(X01)
ENG3(X02)
ENG4(X03)
QT(X04)
RAMP(A00)
RBIAS
1 10KOhm 5%
1 10KOhm 5%
/*
/*
ECE5011_XTAL2
ECE5011_XTAL1
2 10KOhm
5%
2
2
1 R481
Note : for ECE5011 only

ECE5021 will be non_stuff
T58
T53
T50
T67
T70
T62
T52
T47
T63
T51
24MHz Clock
IMVP6_PROCHOT#
LCD_TST
R479
R514
+3.3V_ALW
1 0Ohm
5%
97
98
99
100
101
102
103
104
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
112
111
110
109
GPIOF[4]
GPIOF[5]
GPIOF[6]
GPIOF[7]
88
89
90
91
92
93
94
95
GPIOG[0]
GPIOG[1]
GPIOG[2]
GPIOG[3]
GPIOG[4]
GPIOG[5]
GPIOG[6]
GPIOG[7]
26
27
32
33
GPIOH[4]
GPIOH[5]
GPIOH[6]
GPIOH[7]
105
OUT65
127
126
GPIOJ[0]
GPIOI[7]
122
123
GPIOI[3]
GPIOI[4]
9
10
13
12
15
16
19
18
21
22
GPIOJ[2]
GPIOJ[3]
GPIOJ[6]
GPIOJ[5]
GPIOK[0]
GPIOK[1]
GPIOK[3]
GPIOK[2]
GPIOK[5]
GPIOK[6]
1
1
1
1
1
1
1
1
1
1
T74
1 ECE5011_XTAL2
5%
ECE5011_XTAL2_R
EC_VDDA
30PF/50V
MLCC/+/-5%
/*
R462 2
0Ohm
R489 2
0Ohm
R480 2 /*
R504 2 0Ohm
/*
0Ohm
R505 2 /*
/*
0Ohm
C471
4.7UF/6.3V
pt_c0603
MLCC/+/-10%
/*
0.1UF/10V
MLCC/+80-20%
4.7UF/6.3V
pt_c0603
MLCC/+/-10%
2
2
30PF/50V
MLCC/+/-5%
/*
C470
C474
C495
24Mhz
/*
C476
MODPRES#
DBAY_MODPRES#
31 HDDC_EN
31 MODC_EN
R462 R489 R480 , ECE5011 is

suff , ECE5021 is not stuff
0Ohm 5%
/*
X6
1
1MOhm
ECE5011_XTAL1_R
R485
2 /*
63
28
29
30
31
GPIOD[3]
GPIOD[4]
GPIOD[5]
GPIOD[6]
GPIOD[7]
125
8
14
20
11
17
23
36
51
72
87
96
121
128
34
57
85
108
119
GPIOI[6]
VCC1_1
GPIOJ[7]
GPIOK[4]
GPIOJ[4]
VSS1
GPIOK[7]
VSS2
VSS3
VSS4
VSS5
KHz_32
VSS6
GPIOJ[1]
VCC1_2
VCC1_3
VCC1_4
VCC1_5
GPIOI[1]
1 5%
1 5%
1 5%
1 5%
1 5%
/*
Crystal and surrounding

components not needed unless
SIO USB Hub is utilized
37
R504 R505 R463 , ECE5011 is

EC_32KHZ
EC_32KHZ
R463 2
1 5%
0Ohm
+3.3V_ALW
/*
+3.3V_ALW
R498 R493 R506, ECE5011 is

R498 2
0.1UF/10V
MLCC/+/-10%
C497
C479
0.1UF/10V
MLCC/+/-10%
0.1UF/10V
MLCC/+/-10%
C492
1 5%
1 5%
120
86
124
GPIOI[2]
CAP_LDO
GPIOI[5]
C509
4.7UF/6.3V
MLCC/+/-10%
pt_c0603
/*
0.1UF/10V
MLCC/+80-20%
/*
C525
4.7UF/6.3V
MLCC/+/-10%
pt_c0603
4.7UF/6.3V
MLCC/+/-10%
pt_c0603
/*
C486
C482
/*
0Ohm
0.1UF/10V
MLCC/+/-10%
0.1UF/10V
MLCC/+/-10%
C524
0.1UF/10V
MLCC/+/-10%
C484
0.1UF/10V
MLCC/+/-10%
1
2
C487
R493 2 /*
0Ohm
R506 2
C467
0.1UF/10V
MLCC/+/-10%
C466
0.1UF/10V
MLCC/+/-10%
C468
1
2
BLM18PG181SN1
pt_l0603
EC_VDDA
2 180Ohm
1 5%
0Ohm
L38
1
37
56
39
VSS10
VSS11
VSS12
VSS13
VCC1_6
VSS14
NC
VSS15
54
52
49
47
42
41
46
44
VSS16
VSS17
VSS18
VSS19
VCC1_7
VSS20
VSS21
VSS22
55
53
50
48
43
38
45
40
BC_CLK
BC_DAT
BC_INT#
60
59
58
GPIOB[0]
GPIOB[1]
GPIOB[2]
GPIOB[3]
GPIOB[4]
GPIOB[5]
GPIOB[6]
GPIOB[7]
65
66
82
81
80
79
78
77
GPIOC[0]
GPIOC[1]
GPIOC[2]
GPIOC[3]
GPIOC[4]
GPIOC[5]
GPIOC[6]
GPIOC[7]
76
75
67
68
69
70
71
73
BC_CLK
BC_DAT
BC_INT#
37
37
37
USB_SIDE_EN# 39
PWRUSB_OC#
HP_NB_SENSE
NB_MUTE#
45,46
C
ECE5011_XTAL1
R482
1
VSS7
VSS8
VSS9
GPIOD[0]
74
GPIOE[0]
GPIOE[1]
GPIOE[2]
GPIOE[3]
GPIOE[4]
GPIOE[5]
GPIOE[6]
GPIOE[7]
1
2
3
4
5
84
83
6
DOCK_SMB_PME#
DOCKED
ADAPT_OC
57
ADAPT_TRIP_SEL 57
PS_ID_DISABLE# 59
R522
2
CIRTX
CIRRX
GPIOD[1]/CIRTX
GPIOD[2]/CIRRX
GPIOF[0]
GPIOF[1]
GPIOF[2]
GPIOF[3]
113
114
61
62
118
117
116
115
GPIOH[0]
GPIOH[1]
GPIOH[2]
GPIOH[3]
24
25
106
107
100KOhm
5%
PANEL_BKEN
10
M_LED_BK# 42
No.13
FREE_CIRRX 41
LID_CL_SIO# 42
1.05V_RUN_ON 55
ATF_INT#
BID0
BID1
LOM_CABLE_DETECT
43
WIRELESS_ON/OFF# 42
BT_RADIO_DIS# 41
WWAN_RADIO_DIS# 50
T77
VSS23
64
TEST_PIN
PWRGD_PS
35
7
Reserved for Broadcom

LOM solution
RSV_TEST_PIN
1
T68
ECE5021-NU
/*
C505
0.1UF/10V
MLCC/+80-20%
/*
No.46
C501
+3.3V_ALW
0.1UF/10V
MLCC/+/-10%
Place these caps near ECE5011
SBAT_PRES#
PWRUSB_OC#
MODPRES#
SC_DET#
DBAY_MODPRES#
R513
R515
R500
R523
R501
1
1
1
1
1
2
2
2
2
2
LOM_CABLE_DETECT
R499
2 10KOhm 5%
10KOhm 5%
10KOhm 5%
100KOhm5%
10KOhm 5% /*
10KOhm 5%
+3.3V_RUN
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
38
OF
4
DOCKED
R524
2 100KOhm
5%
LCD_TST
R503
2 100KOhm
5%
DESCRIPTION:
68
SUPER IO ECE5011
3
IMVP6_PROCHOT#
R494
2 100KOhm
5%
HP_NB_SENSE
R512
2 100KOhm
5%
DESIGN ENGINEER :
STANLY_HSU
RELEASE DATE :
2
No.55
+5V_ALW
USB daughter board connector
F1
1
Place one 150uF cap by each

USB connector
2
/*
1.6A/6V
POLYSWITCH SMD1812P160TF
J1
U27
1 1 2 2
2 IN
GND
OUT1
OC1#
7
8
+USB_SIDE_PWR
OUT2
OC2#
6
5
+USB_SIDE_PWR
CON17
SUYIN/127153MA010G521ZR
2MM_OPEN_5mil
3
0.1UF/10V
MLCC/+/-10%
C417
2
EN1#
38 USB_SIDE_EN#
C416
10UF/10V
MLCC/+/-10%
/*
pt_c1206_h75
EN2#
USB_OC0_1#
16
16
ICH_USBP1ICH_USBP1+
16
16
ICH_USBP0ICH_USBP0+
ICH_USBP1ICH_USBP1+
ICH_USBP0ICH_USBP0+
16
11
1
3
5
7
9
NP_NC1
1
2
3
4
5
6
7
8
9
10
NP_NC2
+USB_SIDE_PWR
2
4
6
8
10
12
BTOB_CON_10P
TPS2062DR
Each channel is 1A
4
PROJECT: Lanai
A
REVISION
1.2
DATE:
SHEET
39
B
OF
68
DESCRIPTION:
USB PORT x 2
C
<OrgName>
DESIGN ENGINEER :
Terry_Lin
RELEASE DATE :
D
RTC BATTERY
+3.3V_SUS
+RTC_CELL
+3.3V_RTC_LDO
SHDN#
5/3#
1UF/25V
pt_c0805_h57
2
1
C411 /*
MLCC/+/-10%
IN
GND
OUT
MAX1615EUK
/*
D19
SPI_CLK
SPI_SI
R449 1
R451 1
2 15Ohm
2 15Ohm
EC_FLASH_SPI_CLK 37
EC_FLASH_SPI_DO 37
SST25VF016B
C460
1
RB751V_40
+RTC_1
+RTC
CON16
R421
1KOhm
5%
1
2
3
15 RTC_BAT_DET#
HOLD1
HOLD2
WTOB_CON_3P
MOLEX/53398-0371(P6497)
0.1UF/10V
MLCC/+80-20%
1UF/25V
pt_c0805_h57
2
1
C421
MLCC/+/-10%
SPI_DO
8
7
6
5
37 EC_FLASH_SPI_DIN
CE# VDD
SO HOLD#
WP# SCK
VSS
SI
2
R447 15Ohm5%
1
2
1
2
3
4
U30
pt_c0603
2
1
C408
2.2UF/6.3V/X5R
MLCC/+/-10%
10KOhm
5%
R437
10KOhm
5%
SPI_CS0#
RB751V_40
R457
1
2
3
16
+PWR_SRC
U26
D17
Layout Note:
Place R449 within 500 mils from
SPI flash. Place R449 & R451
within 500 mils of the MEC5025.
Pin 1
Pin 3
MLX_53398-0371
PROJECT: Lanai
A
REVISION
DATE:
1.2
SHEET
40
B
OF
68
DESCRIPTION:
FLASH & RTC

C
<OrgName>
DESIGN ENGINEER :
C.L. Ho
RELEASE DATE :
D
Touch Pad
CON5
MOLEX/48227-1511
WTOB_CON_15P
+3.3V_ALW
+5V_ALW
/*
/*
MLCC/+/-5%
refer to item 191 of issue_list_0517_TDC ,

plan to use 3V TP controller.
No need
" . So we delete this circuit which
TP_VCC power.
C550
C551
MLCC/+/-5%
Please
"Lanai
TP_VCC
supply
17
/*
/*
MLCC/+/-5%
2
MLCC/+/-5%
2
2
C549
MLCC/+/-5%
1
22PF/50V
1
22PF/50V
1
22PF/50V
1
22PF/50V
1
22PF/50V
C544
No.20
/*
No.17
C548
BC_A_CLK
BC_A_INT#
C547
37
37
BC_A_DAT
C546
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SIDE2
42 MEDIA_LED_R
42,43 POWER_SW#
37 INSTANT_POWER_SW#
1
22PF/50V MLCC/+/-5%
1
22PF/50V MLCC/+/-5%
1
22PF/50V MLCC/+/-5%
CN2D
CN2C
CN2B
CN2A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
37 TP_DET#
pt_l0603
pt_l0603
0.1UF/10V
MLCC/+/-10%
C112
0.1UF/10V
MLCC/+80-20%
C114
7 10PF/50V
5 10PF/50V
3 10PF/50V
1 10PF/50V
+5V_ALW
Irat=200mA
Irat=200mA
+3.3V_ALW
600Ohm
600Ohm
1
1
No.17
2
2
C545
BIO
8
6
4
2
Lid Switch(Hall)
L15
L12
DAT_TP_SIO
CLK_TP_SIO
pt_c_array_8p_79x49_h39
37
37
SIDE1
16
3
1
RN15A
4.7KOhm
4.7KOhm
RN15B
4
2
+3.3V_ALW
This circuit is only needed if

the platform has the SNIFFER.
BT_ACTIVE#_R 42
3
No.22 No.42
D
Q62
R528
1
10KOhm
BT_ACTIVE
5%
1
G
Bluetooth
BSS138N
Q63
MMBT3906LT1G
E
2
+3.3V_RUN
2 S
LED_MASK# 15,38
1 B
3
C
11
COEX2_WLAN_ACTIVE 50
COEX1_BT_ACTIVE 50
ICH_USBP7- 16
2
R527
10KOhm
5%
C523
100PF/50V
MLCC/+/-5%
R526
10KOhm
5%
10KOhm
5%
/*
R301
4
3
2
1
38 FREE_CIRRX
2
100Ohm 5%
REVISION
1.2
DATE:
1
2
C536
0.1UF/16V
MLCC/+/-10%
1
U39
+3.3V_CIR
C302
4.7UF/10V
MLCC/+/-10%
pt_c1206_h71
41
4
OF
42
LID_CL#
OUT
VS
GND2
GND1
CON6
MOLEX/48227-0311
1
SIDE1 4
2
3
SIDE2
5
A
WTOB_CON_3P
TSOP36136TR
SHEET
1
1
R300
0Ohm
5%
PROJECT: Lanai
+3.3V_ALW
R534
HALL SENSOR
CIR
+3.3V_ALW
R296
0Ohm
5%
/*
+3.3V_RUN
Vendor suggest :
Pin 7 of RC-Rxd is
open collector
output.it should be
add external pullup
resister
+3.3V_RUN
C518
33PF/50V
MLCC/+/-5%
2
4
6
8
10
C512
0.1UF/10V
MLCC/+80-20%
2
4
6
8
10
ICH_USBP7+
1
16
SIDE2 SIDE1
38 BT_RADIO_DIS#
12
T132
CON21
MOLEX/48226-1011
WTOB_CON_10P
1 1
3 3
5 5
7 7
9 9
68
DESCRIPTION:
<OrgName>
TOUCH PAD & BT & CIR & LID

RELEASE DATE :
3
DESIGN ENGINEER :
1
HDD activity LED
5%
R1
CON22
SNIFFER1
+3.3V_ALW
1
2
3
4
BAT1_LED_BLUE#
GND
SNIFFER2
Q46
R2
R2
2
3
DTC114EKA
R1
IN
BT_LED#
R2
R533
100KOhm 5%
pt_r0603
1
DTC114EKA
3
C
Q64
GND
R1
R531
2
C534
1UF/10V
MLCC/+/-10%
pt_c0603
/*
38 WIRELESS_ON/OFF#
+3.3V_ALW
R2
E
BT_LED
Q47
IN
R1
OUT
1
DTC114EKA
DDTA114YUA_7_F
0Ohm 5%
SNIFFER1
1
R2
41 BT_ACTIVE#_R
DDTA114YUA_7_F
Q65
1
5
7
8
6
+3.3V_RUN
BAT1_LED
R1
+3.3V_RUN
BAT1_LED#
OUT
37
GND1
NP_NC1
NP_NC2
GND2
IN
R1
OUT
DDTA114YUA_7_F
BT activity LED
3
C
Q68
R2
HDD_LED
1
2
3
4
SLIDE_SWITCH_4P
FOXCONN/1BS008-13130-042-7F
1
GND
Sniffer Switch
R175 0Ohm 5%
2
1
pt_r0603
15 SATA_ACT#_R
Battery status
3
C
Q39
Q38
R166
100KOhm
/*
HDD_LED#
+3.3V_RUN
1
GND
R2
1
R425
100KOhm
0Ohm 5%
1
SNIFFER2
C537
1UF/10V
MLCC/+/-10%
pt_c0603
74AHC1G04GW
C430
1UF/10V
MLCC/+/-10%
pt_c0603
/*
37 SNIFFER_PWR_SW#
R297 10KOhm
BREATH_PWRLED 1
5% 2
Y 4
VCC 5
5%
R415
2
E
PMBS3904 2
1 NC
2 A
3 GND
37 BREATH_LED#
BAT2_LED
DDTA114YUA_7_F
1 B
U17
IN
+3.3V_SUS
+RTC_CELL
BAT2_LED#
R1
37
3
C
Q69
OUT
BREATH_PWRLED#
Power&Suspend
No.8
+3.3V_WLAN
WLAN
+3.3V_ALW
LED_WLAN_OUT_R#
Sniffer LED driver circuit
Hall Switch
+3.3V_RUN
50 LED_WLAN_OUT#
10KOhm
5%
GND
2
3
IN
SNIFFER_GREEN#
B
E
R135 10Ohm
5% 2
1
38 LID_CL_SIO#
R2
DTC114EKA
37
R134
100KOhm
5%
LID_CL#
41
C141
0.047UF/10V
MLCC/+/-10%
R1
37
R1
GND
R2
SNIFFER_YELLOW#
IN
R1
OUT
OUT
DDTA114YUA_7_F
LED_WLAN_OUT_R
R2
2
MMBT3906LT1G
B 1
Q66
1
3
C
Q29
Q27
3
C
Q67
1
R542
10KOhm
5%
+3.3V_SUS
E
2
+3.3V_SUS
R541
DDTA114YUA_7_F
B
SNIFFER_Y_R
SNIFFER_G_R
SNIFFER_Y_R
SNIFFER_G_R
+RTC_CELL
LED_WLAN_OUT_R#
LITE-ON/LTST-C192TBKT-5A BLUE
2
2
R305
No.53
1
LED4
1
750Ohm 5%
+5V_RUN
R401
100KOhm
+5V_ALW
5%
Layout Note: C pad is used

as a Provision For External
Power Cycling, Must place C
on top to be accessed when
Keyboard is removed.
Media Bottom Board LED drive circuit

+5V_RUN
BAT2_LED
1
750Ohm 5%
+5V_RUN
C415
1UF/10V
MLCC/+/-10%
pt_c0603
C413
1UF/10V
MLCC/+/-10%
pt_c0603 /*
MEDIA_LED_O 2
MEDIA_LED_R 41
0Ohm
pt_r0805_h24
POWER_SW# 41,43
POWER_SW#
Q57
5%
DDTA114YUA_7_F
Package 0603
R1
+
Blue
LED1
BLUE&ORANGE
+
+
38
R532
SNIFFER_G_R
1
220Ohm 5%
2
pt_r0603
SG
SNIFFER_G_R
M_LED_BK#
No.13 No.35
1
M_LED_BK#
No.39
LED6
3
220Ohm 5%
2
pt_r0603
R529
1
SNIFFER_Y_R
SNIFFER_Y_R
IN
2
R299
Orange
750Ohm
5%
5%
R385 10KOhm
5% 2
1
+5V_RUN
R298
1
750Ohm 5%
2
R304
220Ohm
2
R303
37 MAIN_PWR_SW#
+
1
+5V_SUS
2
LED5
BT_LED#
1
750Ohm 5%
R2
HDD_LED#
2
R302
OUT
LED3
R546
No.53
2
GND
BREATH_PWRLED#
LED2
G&Y
BAT1_LED_BLUE#
PROJECT: Lanai
5
REVISION
DATE:
1.2
SHEET
42
4
OF
68
DESCRIPTION:
SWITCH & LED

3
<OrgName>
DESIGN ENGINEER :
RELEASE DATE :
2
+3.3V_RUN
REM_DIODE4_N
HOLD1
WTOB_CON_3P
MOLEX/53398-0371(P6497)
HOLD2
Put C198 close to Guardian.

Put C394 close Diode
Place under Skin.
UMA
C394
2200PF/50V
/*
MLCC/+/-10%
MMST3904
2
2
1
C387
2200PF/50V
/*
MLCC/+/-10%

Place near the bottom
SODIMM.
Place under CPU.
C317
22UF/10V
MLCC/+/-20%
pt_c1206_h75
2200PF/50V
MLCC/+/-10%
REM_DIODE4_P
2200PF/50V
MLCC/+/-10%
Q50
REM_DIODE3_P

1
2
1
2
3
MMST3904_7_F
CON11
FAN1_VOUT
FAN1_VOUT_FB
3
C
REM_DIODE1_P
0Ohm
pt_r0805_h24
5%
C197
3
C
B 2
MMST3904
Q52
REM_DIODE3_N
C389
2200PF/50V
/*
MLCC/+/-10%
B 2
E
1
Q51
E
1
MLX_53398-0371
RB751S40T1G
/*
2200PF/50V
MLCC/+/-10%
R315
D16
C195
B 2
37
C198
3
C
FAN1_TACH
E
1
Pin 3
REM_DIODE1_N
R316
10KOhm 5%
Pin 1
Layout Note:
R177 is put on BOT DIMM
sockett
+5V_SUS
Guardian
+RTC_CELL
R370 1
R141 1
17,51 SUSPWROK
51 ICH_PWRGD#
R162
C188
THERM_VEST
2
1KOhm 5%
1
R374
49.9Ohm
1%
5% THERM_PWRGO
5% +3V_PWROK#
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#
+RTC_CELL
1 +3VSUS_THRM
C162
0.1UF/10V
MLCC/+80-20%
0.1UF/10V
pt_c0402
MLCC/+/-10%
+3.3V_SUS
2 1KOhm
2 1KOhm
FAN1_VOUT
R148 1
T115
2 10KOhm /*
1
R146 1
2 10KOhm /*
36 MDC_RST_DIS#
SIO_GFX_PWR
5V_CAL_SIO1#
5V_CAL_SIO2#
+3.3V_SUS
45 AUDIO_AVDD_ON
T26
2
48
47
REM_DIODE4_P
REM_DIODE4_N
35
3V_SUS
DP5
DN5
2
1
21
RTC_PWR3V
23
16
VSUS_PWRGD
3V_PWROK#
ATF_INT#
POWER_SW#
ACAVAIL_CLR
THERMTRIP_SIO
SYS_SHDN#
17
18
19
THERMTRIP1#
THERMTRIP2#
THERMTRIP3# LDO_SHDN#/ADDR
42
26
34
VSET
XEN
VSS
R380
1
1
LDO_POK
33
LDO_SET
28
7
8
FAN_OUT1
FAN_OUT2
LDO_OUT2
LDO_OUT1
32
31
39
FAN_DAC1
LDO_IN2
LDO_IN1
30
29
10
13
14
15
22
36
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6/FAN_DAC2
VDD_3V
VDD_5V_1
VDD_5V_2
5
6
1
LDO_SHDN#_ADDR
R376
10KOhm
5%
10KOhm
5%
/*
20
3
4
25
24
27
10KOhm
1%
R372
R144
C406
T23
1 7.5KOhm
1%
R177
0.1UF/10V
MLCC/+/-10%
10KOHM
5%
THERMISTOR 10K OHM
2
T24
T25
DP4
DN4
DP2
DN2
GND
41
40
2.2KOhm
1%
ATF_INT#
38
POWER_SW# 41,42
ACAV_IN
37,57
THERM_STP# 54
D3
+3VSUS_THRM
REM_DIODE3_P
REM_DIODE3_N
H_THERMDC
45
44
53
+3.3V_SUS
Q53
+3.3V_SUS
2.5V_RUN_PWRGD
2
G
51
THERM_LDO_SET
S 1
+2.5V_RUN
5V_CAL_SIO1#
RHU002N06
H_THERMDA
H_THERMDC
DP3
DN3
+RTC_CELL
470PF/50V
MLCC/+/-10%
DP1
DN1
PWR_MON
VCP2
38
37
43
46
REM_DIODE1_P
REM_DIODE1_N
+3.3V_SUS
VCP2
R383
VCP1
VCP2
SMDATA
SMCLK
C196
2
7
U11
11
12
37 THRM_SMBDAT
37 THRM_SMBCLK
H_THERMDA
1
Note:
150K input impedance on VCP1 (Pin 43)
49
Put C196 close to

Guardian.
THERM_LDO_IN
+3.3V_SUS
+3.3V_RUN
5V_CAL_SIO2#
R140
2 10KOhm 5% /*
+5V_RUN
EMC4001_HZH
+3.3V_SUS
+2.5V_RUN
2
2
C161
31.6KOhm
1%
2
8.2KOhm
5%
THERMATRIP3#
R379
THERM_LDO_SET
0.1UF/10V
MLCC/+80-20%
R373
+3.3V_RUN
+3.3V_SUS
0.1UF/10V
MLCC/+80-20%
+3.3V_SUS
0603
Package.
Layout Note:
Place those capacitors close to
EMC4001.
C174
7 H_THERMTRIP#
C184
10UF/10V
MLCC/+80-20%
pt_c0805_h53
C178
C182
0.1UF/10V
MLCC/+80-20%
/*
0.1UF/10V
/*
MLCC/+80-20%
2
10UF/10V
MLCC/+/-20%
pt_c0805_h57
0.1UF/10V
MLCC/+80-20%
C194
0.1UF/10V
MLCC/+80-20%
C160
C177
2
118KOhm
1%
1
1
2
0.1UF/10V
MLCC/+80-20%
C407
Note:
2200PF/50V VSET = (Tp-70)/21, where Tp = 70
MLCC/+/-10% to 101 degree C.
Tp set at 88 degrees C.
Guardian temp tolerance = +-3
degrees C.
REVISION
1.2
DATE:
SHEET
4
43
OF
68
DESCRIPTION:
EMC4001
3
/*
This Value of R150 can

be 0.27 or 0 ohm and the
package is 1210
/*
10UF/4V
pt_c0805
MLCC/+/-20%
DESIGN ENGINEER :
RELEASE DATE :
2
+3.3V_RUN
1UF/10V pt_c0603
MLCC/+80%-20%
10 THERMTRIP_MCH#
PROJECT: Lanai
0Ohm pt_r1210_h24 /*
C171
C173
+2.5V_RUN
R381
E
1
MMST3904_7_F
332KOhm
C401 1%
+5V_RUN
2 B
THERM_B2
2
2.2KOhm 5%
3
C
THERM_VEST
1
R139
8.2KOhm
5%
THERMATRIP2#
+1.05V_VCCP
Q31
2
1
No.10
R382
R138
1KOhm
5%
/*
pt_r0603
R150
THERM_LDO_IN
C160 needs to be placed near

Guardian IC.
/*
2
E
MMST3904_7_F 1
R369
2 B
THERM_B1
2
2.2KOhm 5%
1
R145
3
C
+1.05V_VCCP
8.2KOhm
5%
THERMATRIP1#
R137
Q32
Voltage margining
circuit for LDO output.
For Vmargin stuff R379
and R373=30K. R373=1K
for production.
+3.3V_SUS
C161 needs to be placed near

Guardian IC.
VDDA
+3.3V_RUN
PORT C : LEAVE NC
IF NO INTERNAL MICS.
Port A---> HP1
Port D---> Speaker
Port E---> ext Mic
Port F---> HP2
SYNC
11
RESET#
28 AUD_DMIC_IN0
45 AUD_EAPD#
5% 1 0Ohm
2 R507
EAPD#_CODEC
2
3
28 AUD_DMIC_CLK
50 AUD_SPDIF_OUT
3
1
21
22
28
PORTC_L
PORTC_R
VREFOUT_C
23
24
29
PORTD_L
PORTD_R
VREFOUT_D
35
36
32
PORTE_L
PORTE_R
VREFOUT_E
14
15
31
PORTF_L
PORTF_R
VREFOUT_F
16
17
30
PORTG_L
PORTG_R
43
44
PORTH_L
PORTH_R
45
46
CD_L
CD_GND
CD_R
18
19
20
PCBEEP
12
CAP2
VREFFILT
33
27
AVSS1
AVSS2
26
42
SPDIF_IN/GPIO0/EAPD/DMIC_CLK
SPDIF_OUT/ADAT_OUT
For TV port
AVDD_CODEC
PLACE CLOSE TO U15
PIN13
No.41
2
If SENSE_A total length >6"

change C276 to 0.1uF
R271
5.1kOhm
1%
4
7
DVSS1
DVSS2
R279
No.41
39.2KOhm
1%
PLACE CLOSE TO U15
C276
2
1000PF/50V
MLCC/+/-10%
Q45
G
C516
0.1UF/16V/X7R
2
1
MLCC/+/-10%
MLCC/+/-10% C514
5.1kOhm
1%
2N7002
2 S
R495
45,46 AUD_HP1_NB_SENSE
4
AUD_EXT_MIC_R 46
AUD_EXT_MIC_L 46
AUD_PC_BEEP
AVDD_CODEC
If SENSE_B total length >6"

change C510 to 0.1uF
1
3
1UF/10V/X7R
2
C506
2
C502
1UF/10V/X7R
AUD_HP2_OUT_L 46
AUD_HP2_OUT_R 46
STAC9228
PIN34
pt_c0603
1UF/10V/X7R
2
1
MLCC/+/-20%
AUD_LINE_OUT_L 45
AUD_LINE_OUT_R 45
MLCC/+/-10%
pt_r0603 1 R511
2 AUD_EXT_MIC_L41
AUD_EXT_MIC_L3
5.1Ohm 1%
pt_c0603
AUD_EXT_MIC_R3
1 R508
2 AUD_EXT_MIC_R41
pt_c0603
5.1Ohm 1%
AUD_VREFOUT_E 46 pt_r0603
MLCC/+/-10%
AUD_SENSE_A
C519
VOLUME_UP/DMIC_0/GPIO1
VOLUME_DOWN/DMIC_1/GPIO2
5% 1 0Ohm /* 2 R502
47
48
PORTB_L
PORTB_R
VREFOUT_B
C513
10
15 ICH_AZ_CODEC_RST#
MLCC/+/-20%
15 ICH_AZ_CODEC_SYNC
AUD_HP1_OUT_L 45
AUD_HP1_OUT_R 45
pt_c0805_h57
10UF/10V/X5R
2
1
SDO
+3.3V_RUN
39
41
37
C503 /*
MLCC/+/-10%
15 ICH_AZ_CODEC_SDOUT
PORTA_L
PORTA_R
VREFOUT_A
AUD_SENSE_A
AUD_SENSE_B
C499 /*
MLCC/+/-10%
SDI
HDA_SDI
13
34
C522
BITCLK
5% 1 33Ohm 2 R257
15 ICH_AZ_CODEC_SDIN0
SENSE_A
SENSE_B
AVDD_CODEC
MLCC/+/-20%
15 ICH_AZ_CODEC_BITCLK
2
25
38
1000PF/50V
2
1
AUD_EAPD#
AVDD1
AVDD2
DVDD_CORE1
DVDD_CORE2
DVDD_CORE3
pt_c0805_h57
10UF/10V/X5R
2
1
45
U15
1
9
40
C507 /*
MLCC/+/-10%
DVDD_CORE3
1000PF/50V
2
1
DVDD_CORE1
2 R509
100KOhm
5% 1 0Ohm /* 2 R510
5% 1
1000PF/50V
2
1
2 R490
5% 1 0Ohm
No.4
C480
C541
MLCC/+/-10%
1000PF/50V
2
1
MLCC/+/-20%
pt_c0805_h57
10UF/10V/X5R
2
1
2.2KOhm
5%
600Ohm/100Mhz
Irat=500mA
MURATA/BLM18EG601SN1D
1000PF/50V
2
1
R265
L41
pt_c0805_h57
10UF/10V
2
1
MLCC/+/-10%
pt_c0402
VDDA
C493 /*
MLCC/+/-10%
600Ohm/100Mhz
Irat=500mA
MURATA/BLM18EG601SN1D
C490
DVDD_CORE
0.1UF/16V/X7R
AUD_PC_BEEP
2
0.1UF/16V/X7R
2
1
4
Y
SN74AHCT1G86DCKR
C273
1
MLCC/+/-10%
3 GND
5%
MLCC/+/-10% C489
10KOhm
R264
C488
FROM EC
VCC 5
pt_c0603
1UF/10V/X7R
2
1
2 B
pt_c0805_h57
10UF/10V/X5R /*
2
1
1 A
BEEP
L40
SPKR
37
0.1UF/16V/X7R
2 MLCC/+/-10%
pt_c0402
17
C275
1
MLCC/+/-20%
U13
FROM ICH
AUD_SENSE_B
PLACE BETWEEN U15 and

U16
PLACE CLOSE TO U15
PIN6
PLACE CLOSE TO U15
R491
PIN5
1
39.2KOhm
1%
ICH_AZ_CODEC_SDOUT
D
No.50
/*
R259
/*
2 S
2N7002
R496
20KOhm
1%
47Ohm
5%
C510
1000PF/50V
MLCC/+/-10%
C263
/*
0.1UF/16V/X5R
MLCC/+/-10%
PROJECT: Lanai
A
46 AUD_HP2_NB_SENSE
C262
/*
0.1UF/16V/X5R
MLCC/+/-10%
REVISION
DATE:
1.2
SHEET
44
B
OF
68
2 R273
5% 1 0Ohm /* 2 R535
JP9
1
5% 1 0Ohm /* 2 R287
SHORTPIN
/*
Q59
5% 1 0Ohm
47Ohm
5%
R258
Q58
46 AUD_MIC_SWITCH
ICH_AZ_CODEC_BITCLK
1
G
2 S
2N7002
DESCRIPTION:
STAC9228
DESIGN ENGINEER :
Yihao Yeh
RELEASE DATE :
C
Signal Inveter for Speaker Shutdown

+5V_SPK_AMP
MLCC/+/-10%
1UF/25V/X7R
2
1
pt_c1206_h49 C301
pt_c1206_h49 C297
2
1
HP1_INL_AMP1
Q60
FROM EC
NOTE:For TPA6040A, pop

C292 and C291(0402
X5R) and no pop R530
and R292. C292 and
C291 value should
match C299 and C298
38,46 NB_MUTE#
2 S
2N7002
/*
1UF/25V/X7R
MLCC/+/-10%
C293
C294 /*
MLCC/+/-5%
47PF/50V
2
1
MLCC/+/-5%
47PF/50V
2
1
HP1_INR_AMP1
No.49
AUD_AMP_GAIN1
AUD_HP1_OUT_L 44
AUD_HP1_OUT_R 44
+5V_SPK_AMP
R294
100KOhm
AUD_AMP_GAIN2
1
R530 2
0Ohm 5% /*
46
46
AUD_SPK_L2
LOUT-
SPVDD2
18
SPVDD1
HPVDD
17
GND1
33
1
2
R290
100KOhm
5%
1
2
1
R295 /*
100KOhm 5%
AUD_AMP_GAIN1
AUD_AMP_GAIN2
2
1
pt_c0603
C528
1UF/10V/X7R
MLCC/+/-10%
2
1
pt_c0603
C529
1UF/10V/X7R
MLCC/+/-10%
+5V_SPK_AMP
Gain
6
dB
10
dB
15.6 dB
21.6 dB
Recommend a star
connection for PVSS
and CPVSS at capacitor
C6613 of MAX9789A
46
ROUTE VIA TRACE BACK TO TIE POINT.
C287
1
MLCC/+/-20%
10UF/10V/X5R
2
1
pt_c0805_h57
C527
+3.3V_CPVDD_HPVDD
GAIN SETTING RESISTORS
MLCC/+/-10%
1UF/10V/X7R
2
1
pt_c0603
C290
MLCC/+/-20%
10UF/10V/X5R
2
1
pt_c0805_h57
C530
AUD_HP1_JACK_R
600Ohm
Irat=200mA
MURATA/BLM18AG601SN1(J5535)<G>
Gain1 Gain2
74AHC1G08GW
2
AUD_HP1_NB_SENSE 44,46
1
NB_MUTE#
38,46
AUD_HP1_JACK_L 46
+3.3V_RUN
2
R289
/*
100KOhm 5%
43
+5V_SPK_AMP
16
15
14
C1N
12
11
13
C1P
10
TPA6040A4RHBR
No.49
No.49
HP_OUTL
46
AUD_SPK_R2
HP_OUTR
AUD_SPK_R1
19
HPVSS
20
ROUT-
CPVSS
ROUT+
LOUT+
CPGND2
SPGND1
CPVDD1
L43
R293
100KOhm 5%
U38
AUD_SPK_ENABLE#
AUD_SPK_L1
+5V_SPK_AMP
C526
2
21
SPGND2
MLCC/+/-10%
1UF/10V/X7R
1
2
pt_c0603 C289
46
+5V_SPK_AMP
AUDIO_AVDD_ON
25
34
35
36
37
26
27
SPKR_LIN-
HP_INL
SGND
REG_EN
GND2
GND3
GND4
GND5
HP_INR
28
29
VDD
22
SPKR_INL_AMP1
REG_OUT
23
HP_EN
GAIN0
SPKR_EN#
SPKR_LIN+
GAIN1
SPKR_RIN+
SPKR_INR_AMP1
1 C298
0.033UF/100V
30
31
32
C292
MLCC/+/-10%
0.033UF/16V/X7R
2
1
24
SPKR_RIN-
pt_c0805_h57 C286
C291
NOTE:For TPA6040A,
pop C291 and no pop
R292
BYPASS
R292 /*
1
2
5% 0Ohm
FROM EC
MLCC/+/-10%
0.033UF/16V/X7R
2
1
1 C299
0.033UF/100V
FROM EC
2
5%
+3.3V_CPVDD_HPVDD
U16
MLCC/+/-20%
10UF/10V/X5R
2
1
43 AUDIO_AVDD_ON
MLCC/+/-5%
47PF/50V
2
1
C531 /*
MLCC/+/-5%
47PF/50V
2
1
C532 /*
pt_c1206_h59 2
MLCC/+/-10%
44 AUD_LINE_OUT_L
C520
pt_c0805_h57
10UF/10V/X5R
2
1
L42
1
2
60Ohm
Irat=3A
pt_l0805_h41
MURATA/BLM21PG600SN1(Y8220)<G>
pt_c1206_h59 2
MLCC/+/-10%
44 AUD_LINE_OUT_R
MLCC/+/-10%
1UF/10V/X7R
2
1
pt_c0603 C288
+5V_SPK_AMP
MLCC/+/-20%
+5V_RUN
0Ohm 1
GND
TEMPORARY VALUES. FINAL

VALUES CHOSEN IN PT
PHASE.
MUTE#_AMP1
R291
VCC
PLACE JUST BEFORE

+5V_MAX9789 CROSSES
MOAT
5%
/*
No.49
Note: For TPA6040A,

pop R291 and no pop
R294
0.1UF/16V
MLCC/+/-10%
2N7002
2 S
MLCC/+/-10%
1UF/10V/X7R
2
1
pt_c0603 C296
AUD_EAPD#
MLCC/+/-10%
1UF/10V/X7R
2
1
pt_c0603 C300
Q61
44
MLCC/+/-10%
0.1UF/16V/X7R
2
1
C295
100KOhm
5%
2
R525
1
3
+5V_AMP1
AUD_SPK_ENABLE#
Place C295 close

to Pin 30
100KOhm
5%
B
A
R288
MLCC/+/-10%
1UF/10V/X7R
2
1
pt_c0603
C535
600Ohm
2
+5V_SPK_AMP
1
VDDA
Irat=200mA L20
+5V_SPK_AMP
MLCC/+/-10%
1UF/10V/X7R
2
1
pt_c0603
C533
Allow speakers to work while class driver is

installed
1UF/10V/X7R
MLCC/+/-10%
pt_c0603
PROJECT: Lanai
A
REVISION
1.2
DATE:
SHEET
45
B
OF
68
DESCRIPTION:
AMP MAX9789
C
<OrgName>
DESIGN ENGINEER :
Yihao Yeh
RELEASE DATE :
D
L19
+3.3V_AMP2
MLCC/+/-10%
1UF/10V/X7R
2
1
pt_c0603
C271
NOTE: MAKE SURE THERMAL PAD

(Pin21)UNDER MAX4411 IS NOT
CONNECTED TO GND
Speaker CON
+3.3V_RUN
600Ohm Irat=200mA
CON7
7
C508
AUD_SPK_L1
AUD_SPK_L2
AUD_SPK_R1
AUD_SPK_R2
SGND
PGND
NC3
NC4
12
NC5
16
NC6
20
/*
C452
/*
MLCC/+/-5%
1
C451
/*
MLCC/+/-5%
1
C454
100PF/50V/NPO
2
4
6
Need to adjust EMI cap values as necessary.
17
SVSS
PVSS
C1N
C1P
2.2UF/10V/X5R
MLCC/+/-10%
2
1
pt_c0603
C500
No.49
C1N
NC1
NC2
INL
MLCC/+/-5%
47PF/50V
1
C498
C1P
TPA4411MRTJR
2.2UF/10V/X5R
MLCC/+/-10%
2
1
pt_c0603
C491
PVSS
C521
MLCC/+/-5%
47PF/50V
1
C504
44 AUD_HP2_OUT_L
2
C511
1
2.2UF/16V
1
2.2UF/16V
100PF/50V/NPO
2
AUD_HP2_JACK_L
/*
10
21
AUD_HP2_JACK_R
11
OUTL
MLCC/+/-5%
1
INR
13
OUTR
C450
15
HP2_INL_AMP2
MLCC/+/-5%
1
HP2_INR_AMP2
B
A
pt_c1206_h75
2
MLCC/+/-10%
2
MLCC/+/-10%
pt_c1206_h75
44 AUD_HP2_OUT_R
45
45
45
45
SPEAKER_DET# 15
100PF/50V/NPO
2
SHDNL#
GND
SHDNR#
18
GND
No.31
19
U35
14
SVDD
74AHC1G08GW
4
PVDD
VCC
U37
2
1
44 AUD_HP2_NB_SENSE
38,45 NB_MUTE#
1
2
3
4
5
6
WTOB_CON_6P
MOLEX/48227-0611
0.1UF/16V/X7R
MLCC/+/-10%
1
2
SIDE1 1
2
3
4
5
SIDE2 6
100PF/50V/NPO
2
Maxim:1.8V ~ 3.6V
TI:1.8V ~ 4.5V
No.50
2
100KOhm
2
100KOhm
2
100KOhm
44 AUD_MIC_SWITCH
44 AUD_VREFOUT_E
44 AUD_EXT_MIC_L
44 AUD_EXT_MIC_R
5%
5%
44 AUD_HP2_NB_SENSE
AUD_HP2_JACK_L
AUD_HP2_JACK_R
5%
CON9
WTOB_CON_15P
MOLEX/48227-1511
17
44,45 AUD_HP1_NB_SENSE
45 AUD_HP1_JACK_L
45 AUD_HP1_JACK_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SIDE1
1
R282
AUD_HP2_NB_SENSE
1
R283
AUD_HP1_NB_SENSE
1
R286
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SIDE2
+3.3V_RUN
AUD_MIC_SWITCH
16
PROJECT: Lanai
A
REVISION
DATE:
1.2
SHEET
46
B
OF
68
DESCRIPTION:
AMP MAX4411 & AUDIO JACK

RELEASE DATE :
C
<OrgName>
DESIGN ENGINEER :
Yihao Yeh
D
VDDP Power Decoupling
C30
4.7UF/10V
MLCC/+/-10%
pt_c0805_h37
2
1
C52
0.1UF/10V
MLCC/+80-20%
2
1
17
68
VDDP1
VDDP2
52
8
7
6
5
42
43
TDN
TDP
No.3
67
62
LINK_LED10# 48
LINK_LED100# 48
ACTLED#
48
54
53
3
VAUX_PRSNT
VMAIN_PRSNT
LOW_PWR
58
57
NC2
NC1
LOM_XOUT
LOM_XIN
XTALO
XTALI
37
RDAC
8
4
GPIO_1
EEPROM_WP
SCLK
65
LAN_SCLK
SO
64
LAN_SO
Layout note:
Place Close to LOM
1KOhm
1%
1 LAN_RDAC
UART_MODE
Layout note:
Place Close to LOM
NC3
63
REGCTL25
18
LAN_UART_MODE
No.12
0Ohm
5% /*
LAN_REGCTL25
R44
1
0Ohm 5%
11
59
CLKREQ#
ENERGY_DET
R93
10KOhm
5%
/*
REGCTL12
14
R49
1.5Ohm
1
2
pt_r2512_h26
5%
LAN_REGCTL12
GND
69
16
Q10
MMJT9435T1G
B 1
VSS1
MBT35200MT1G
+2.5V_LOM
No.12
BCM5906MKMLG
C.S BCM5906MKMLG A2 QFN68
Q15
2
C
2 PCIE_LOM_CLKREQ#_R
E
3
21 PCIE_LOM_CLKREQ#
+3.3V_LAN
C68
0.1UF/10V
MLCC/+80-20%
2
1
C37
27PF/50V
MLCC/+/-5%
2
1
R9
+3.3V_LAN
+3.3V_LAN
R41
25Mhz
+/-30ppm/18PF
1
2
5
6
22
21
GPIO_2
GPIO_0
48
48
C53
0.1UF/10V
MLCC/+80-20%
2
1
X1
2
1% VAUX_PRSNT
1% VMAIN_PRSNT
LOM_LOW_PWR
LOM_TXLOM_TX+
C82
0.1UF/10V
MLCC/+80-20%
2
1
SERIAL_DI
SERIAL_DO
LINK_LED10#
LINK_LED100#
ACTLED#
No.27
2
1
66
48
48
LINK_LED#
SPD100_LED#
TRAFFIC_LED#
LOM_RXLOM_RX+
C79
4.7UF/10V
MLCC/+/-10%
pt_c0805_h37
2
1
RDN
RDP
41
40
C61
4.7UF/10V
MLCC/+/-10%
pt_c0805_h37
2
1
2 1KOhm
2 1KOhm
1
1
AT24C02BN
R14
49.9Ohm 1%
2
1
LOM_PERST#
PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
WAKE
PERST#
PCIE_REFCLK_P
PCIE_REFCLK_N
48
47
1
2
3
4
C9
0.1UF/10V
MLCC/+/-10%
2
1
VSS2
DC7
DC6
R13
49.9Ohm 1%
2
1
24
49
50
R12
49.9Ohm 1%
2
1
PCIE_VDD1
PCIE_VDD2
DC8
DC9
+3.3V_LAN
No.25
C33
27PF/50V
MLCC/+/-5%
2
1
27
33
26
25
31
32
12
10
29
28
21 CLK_PCIE_LOM
21 CLK_PCIE_LOM#
38 LOM_LOW_PWR
2 LOM_XOUT_R
200Ohm 1%
PCIE_PLLVDD
VCC A0
WP
A1
SCL A2
SDA GND
4.7KOhm
R11
49.9Ohm 1%
2
1
2
R32 47Ohm 5%
1
2
R25
0Ohm 5% /*
30
C59
0.1UF/10V
MLCC/+80-20%
2
1
U2
2
DC11
4.7KOhm
EEPROM_WP
LAN_SCLK
LAN_SO
1
45
R19
4.7KOhm
2
DC4
C13
0.1UF/10V
MLCC/+80-20%
2
1
38
R21
C14
0.1UF/10V
MLCC/+/-10%
2
1
C22
0.1UF/10V
MLCC/+80-20%
2
1
C18
0.1UF/10V
MLCC/+80-20%
2
1
C24
4.7UF/10V
MLCC/+/-10%
pt_c0805_h37
2
1
C21
0.1UF/10V
MLCC/+80-20%
2
1
C19
4.7UF/10V
MLCC/+/-10%
pt_c0805_h37
2
1
1
2 0.1UF/10V MLCC/+/-10%
1
2 0.1UF/10V MLCC/+/-10%
16 PCIE_TX6+/GLAN_TX+
16 PCIE_TX6-/GLAN_TX35,38,50 PCIE_WAKE#
R22
R10
R37
LAN_PCIETXDP
LAN_PCIETXDN
C25
C28
+3.3V_RUN
DC1
DC2
LAN_XTALVDD
C32
0.1UF/10V
MLCC/+80-20%
2
1
C12
0.1UF/10V
MLCC/+80-20%
2
1
C8
4.7UF/10V
MLCC/+/-10%
pt_c0805_h37
2
1
35
LAN_PCIE_VDD
No.53
AVDDL
DC3
DC5
DC10
23
R18
16 PCIE_RX6+/GLAN_RX+
16 PCIE_RX6-/GLAN_RX-
16 SB_LOM_PCIE_RST#
39
44
46
51
+3.3V_LAN
+3.3V_LAN
L7
600Ohm
MURATA/BLM18AG601SN1
2
1
LAN_PCIE_PLLVDD
2 600Ohm
16,50 PLTRST_LAN_MINICARD#
LAN_AVDDL
L4
600Ohm
1
2
LAN_BIASVDD
L6
BIASVDD
XTALVDD
L3
600Ohm
1
2
L5
600Ohm
1
2
+2.5V_LOM
36
+1.2V_LOM
VDDC1
VDDC2
VDDC3
VDDC4
VDDC5
VDDC6
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
5
13
20
34
55
60
+3.3V_LAN
+2.5V_LOM
6
15
19
56
61
U3
+1.2V_LOM
C35
0.1UF/10V
MLCC/+80-20%
2
1
C43
0.1UF/10V
MLCC/+80-20%
2
1
C26
0.1UF/10V
MLCC/+80-20%
2
1
C20
0.1UF/10V
MLCC/+80-20%
2
1
C17
0.1UF/10V
MLCC/+80-20%
2
1
C39
0.1UF/10V
MLCC/+80-20%
2
1
C47
0.1UF/10V
MLCC/+80-20%
2
1
C50
0.1UF/10V
MLCC/+80-20%
2
1
+3.3V_LAN
+1.2V_LOM
VDDIO Power Decoupling
+2.5V_LOM
C48
0.1UF/10V
MLCC/+80-20%
2
1
C23
4.7UF/10V
MLCC/+/-10%
pt_c0805_h37
2
1
D
C51
0.1UF/10V
MLCC/+80-20%
2
1
Core Power Decoupling

+1.2V_LOM
C31
0.1UF/10V
MLCC/+80-20%
2
1
C49
0.1UF/10V
MLCC/+80-20%
2
1
C65
10UF/10V
MLCC/+80-20%
pt_c0805_h53
+1.2V_LOM
A
PROJECT: Lanai
5
REVISION
DATE:
1.2
SHEET
47
4
OF
68
DESCRIPTION:
LAN BCM5906MKMLG(QFN-68)
3
<OrgName>
1
2
C44
0.1UF/10V
MLCC/+80-20%
2
1
C38
10UF/10V
MLCC/+80-20%
pt_c0805_h53
DESIGN ENGINEER :
Ivan_Chou
RELEASE DATE :
2
+3.3V_LAN
R308
10KOhm
5% /*
CON10
LOM_TX+
LOM_TX-
LOM_TX-
47
LOM_RX+
47
LOM_RX-
47 LINK_LED100#
47 LINK_LED10#
L21
600Ohm
1
2
R306
TRD1+
TRCT1
TRD1-
4
6
5
TRD2+
TRDCT
TRD2-
3
1
2
NC_1
NC_2
NC_3
8
7
9
NC_4
NC_5
NC_6
LOM_CT
2 150Ohm 1% LINK_LED100#_R
2 150Ohm 1% LINK_LED10#_R
No Stuff
+3.3V_LAN
YELLOW-
11
12
10
LOM_RX-
LINK_LED100# R309 1
LINK_LED10# R310 1
R307
YELLOW+
13
LOM_RX+
+2.5V_LOM
150Ohm 1%
2 ACTLED#_R
2 10KOhm 5% /*
2 10KOhm 5% /*
15
17
ORANGEGREEN-
16
COMMON+
20
21
NP_NC1
NP_NC2
+3.3V_LAN Source Guideline:

1. Use +3.3V_SUS if
NOT required out of
2. Use +3.3V_SRC if
required out of S4,
LAN_JACK_17P
TYCO/1840427-2,TAB DOWN
+3.3V_SUS
+3.3V_LAN
JP1
1
Reserve Pull-up
0Ohm
pt_r0603
JUMP
Layout note:
C303 should be close to pin12
C304 should be close to pin6
No Stuff
Wake-on-LAN is
S4, S5
Wake-on_LAN is
S5
C
18
19
47
R311
1
LOM_TX+
C304
0.1UF/16V
MLCC/+/-10%
2
1
47
ACTLED#
ACTLED#
C303
0.1UF/16V
MLCC/+/-10%
2
1
47
14
SHIELD1
SHIELD2
No Stuff
Reserve Pull-up
PROJECT: Lanai
5
REVISION
DATE:
1.2
SHEET
48
4
OF
68
DESCRIPTION:
Magnetics and RJ-45

3
<OrgName>
DESIGN ENGINEER :
Ivan_Chou
RELEASE DATE :
2
+5V_ALW
+5V_RUN
+3.3V_ALW
+3.3V_SUS
+15V_ALW
28,37,51,54 RUN_ON
RUN_ON
2 S
1
2
3
4
1
2N7002
pt_sot23_philips
G
3
10UF/10V
MLCC/+/-20%
pt_c0805_h57
PQ27
SUS_ON_3.3V#
PR154
20KOhm
5%
PC168
SI4800BDY
PC167
4700PF/50V
MLCC/+/-10%
pt_c0603
PR99
100KOhm
5%
2
SUS_3.3V_ENABLE
2 S
PR100
100KOhm
5%
/*
PC92
4700PF/50V
pt_c0603
MLCC/+/-10%
/*
1
G
2 S
PQ39
D
S
PQ40
2N7002
pt_sot23_philips
8
7
6
5
RUN_ON_5V#
+5V_ALW2
PR155
20KOhm
5%
1
PC170
10UF/16V
MLCC/+/-10%
pt_c1206_h71
SI4800BDY
RUN_ENABLE
PR157
100KOhm
5%
PR101
100KOhm
5%
PR156
100KOhm
5%
+5V_ALW2
1
2
3
4
1
8
7
6
5
PQ42
D
S
+15V_ALW
PQ28
PQ49
2N7002
pt_sot23_philips
3.3V_SUS_ON
37 3.3V_SUS_ON
For iAMT Support
1
G
2N7002
pt_sot23_philips
2 S
+15V_ALW
+5V_SUS
PQ14
G
1
1
2
3
10UF/10V
MLCC/+/-20%
pt_c0805_h57
2N7002
pt_sot23_philips
2 S
PR152
100KOhm
5%
/*
PC166
4700PF/50V
pt_c0603
MLCC/+/-10%
/*
1
G
D
C
PQ26
37,51
PC52
0.047UF/25V
MLCC/+/-10%
/*
PQ24
SUS_ON_5V#
PR153
20KOhm
5%
PC169
SI4800BDY
SUS_ON
SUS_ON
1
G
2 S
2N7002
pt_sot23_philips
No.34
PR42
0Ohm
5%
D
PQ15
2N7002
pt_sot23_philips
37 1.8V_RUN_ON
2N7002
pt_sot23_philips
2 S
1
1
10UF/10V
MLCC/+/-20%
pt_c0805_h57
/*
FDS8884
RB751V_40
pt_sod323_h35
/*
PR97
100KOhm
5%
PR40
20KOhm
5%
PC53
2
PD9
2
1
2
3
4
SUS_5V_ENABLE
1
PR37
100KOhm
5%
PQ16
D
S
8
7
6
5
PR39
100KOhm
5%
+5V_ALW2
1
2
3
4
No.29
+15V_ALW
+1.8V_RUN
PR95
100KOhm
5%
+5V_ALW2
+1.8V_SUS
PQ41
S
8 D
7
6
5
G
+5V_ALW
2 S
+3.3V_RUN
+3.3V_ALW
No.29
G
3
2N7002
pt_sot23_philips
2 S
PQ25
1
+1.8V_SUS
+5V_SUS
+3.3V_SUS
Reserve discharge path
PR102
0Ohm
5%
R96
R60
30Ohm
1%
pt_r0603
/*
1KOhm
5% /*
pt_r0603
3
Q21
SUS_ON_5V#
PQ29
2 S
2N7002
/*
2 S
2N7002
/*
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.9V_DDR_VTT
Reserve discharge path
2 S
Q40
2N7002
/*
2N7002
pt_sot23_philips
2 S
Q13
1KOhm
5% /*
pt_r0603
1
G
37 3.3V_RUN_ON
1
G
R242
No.11
PC164
4700PF/50V
MLCC/+/-10%
pt_c0603
10UF/10V
MLCC/+/-20%
pt_c0805_h57
1
1
FDS8884
RB751V_40
pt_sod323_h35
/*
PR151
20KOhm
5%
PC162
1
2
3
4
PD11
2
PQ38
D
S
1
PR96
100KOhm
5%
B
8
7
6
5
PR98
100KOhm
5%
+5V_ALW2
+15V_ALW
+1.25V_RUN
3
Q33
3
Q34
1
G
2 S
2N7002
/*
PROJECT: Lanai
5
3
Q16
1
G
2 S
2N7002
1.2
2 S
2N7002
Q14
49
4
2 S
2N7002
OF
1
3
Q22
68
1KOhm
5% /*
pt_r0603
Q17
A
1
G
/*
SHEET
1KOhm
5% /*
pt_r0603
1
G
/*
DATE:
1
G
/*
REVISION
1KOhm
5% /*
pt_r0603
1KOhm
5% /*
pt_r0603
R74
R94
R63
10Ohm
5% /*
pt_r0603
1KOhm
5% /*
pt_r0603
RUN_ON_5V#
R71
R165
2
3
For iAMT Support

R151
2 S
2N7002
/*
2 S
2N7002
/*
DESCRIPTION:
Power Control Switch

3
RELEASE DATE :
2
DESIGN ENGINEER :
Eric Ko
1
No.21
+PWR_SRC
5
6
7
8
+3.3V_ALW
Q28
R107
470KOhm
5%
/*
1
C107
4700PF/50V
MLCC/+/-10%
pt_c0603
/*
+3.3V_WLAN
R104
0Ohm
5%
pt_r1206_h26
2
R116
200KOhm
5%
/*
2N7002
/*
2 S
R115
100KOhm
5%
/*
G
1
2 S
2N7002
/*
1
G
SI4800BDY
/*
Q30
1
37 AUX_EN_WOWL
U9
4
3
2
1
1
3
R106
100KOhm
5%
/*
R108
100KOhm
5%
/*
+3.3V_RUN
C
CON3B
CON3A
21 CLK_PCIE_MINI2#
21 CLK_PCIE_MINI2
10 G_DAT_DDC2
10 G_CLK_DDC2
10
10
10
10
10
10
VGA_RED
VGA_BLU
VGA_GRN
TV_CVBS
TV_Y
TV_C
+3.3V_RUN
T1
+3.3V_RUN
17 USB_MCARD2_DET#
16 PCIE_MCARD2_DET#
17 PCIE_MCARD1_DET#
38 WWAN_RADIO_DIS#
YPRPB_DET# 44 AUD_SPDIF_OUT
16
16
PCIE_TX1PCIE_TX1+
16
16
16
16
PCIE_RX1PCIE_RX1+
ICH_USBP3ICH_USBP3+
16
ICH_USBP216
ICH_USBP2+
37 HOST_DEBUG_RX
37 HOST_DEBUG_TX
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
CLK_PCIE_MINI1# 21
CLK_PCIE_MINI1 21
MINI2CLK_REQ# 21
VGAVSYNC
10
VGAHSYNC
10
+5V_ALW
+5V_RUN
+1.5V_RUN
USB_MCARD1_DET# 17
USB_BACK_EN# 38
USB_OC2_3# 16
PLTRST_LAN_MINICARD# 16,47
PCIE_WAKE# 35,38,47
COEX2_WLAN_ACTIVE 41
COEX1_BT_ACTIVE 41
ICH_SMBCLK 17,35
ICH_SMBDATA 17,35
WLAN_RADIO_DIS# 38
SB_WWAN_PCIE_RST# 16
LED_WLAN_OUT# 42
SB_WLAN_PCIE_RST# 16
MINI1CLK_REQ# 21
+3.3V_WLAN
ICH_USBP9- 16
ICH_USBP9+ 16
PCIE_TX2PCIE_TX2+
16
16
PCIE_RX2PCIE_RX2+
8051_RX
8051_TX
16
16
37
37
PCB_SCK_2X37P
SUYIN/127216FA074G500ZR
NP_NC2
NP_NC40
NP_NC41
NP_NC42
NP_NC43
NP_NC44
NP_NC45
NP_NC46
NP_NC47
NP_NC48
NP_NC49
NP_NC50
NP_NC51
NP_NC52
NP_NC53
NP_NC54
NP_NC55
NP_NC56
NP_NC57
NP_NC58
NP_NC59
NP_NC60
NP_NC61
NP_NC62
NP_NC63
NP_NC64
NP_NC65
NP_NC66
NP_NC67
NP_NC68
NP_NC69
NP_NC70
NP_NC71
NP_NC72
NP_NC73
NP_NC74
NP_NC75
NP_NC76
NP_NC1
NP_NC3
NP_NC4
NP_NC5
NP_NC6
NP_NC7
NP_NC8
NP_NC9
NP_NC10
NP_NC11
NP_NC12
NP_NC13
NP_NC14
NP_NC15
NP_NC16
NP_NC17
NP_NC18
NP_NC19
NP_NC20
NP_NC21
NP_NC22
NP_NC23
NP_NC24
NP_NC25
NP_NC26
NP_NC27
NP_NC28
NP_NC29
NP_NC30
NP_NC31
NP_NC32
NP_NC33
NP_NC34
NP_NC35
NP_NC36
NP_NC37
NP_NC38
NP_NC39
75
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
PCB_SCK_2X37P
A
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
4
50
OF
68
DESCRIPTION:
BtoB CON
3
<OrgName>
DESIGN ENGINEER :
STANLY_HSU
RELEASE DATE :
2
Discrete
+3.3V_SUS
R40
2 0Ohm 5%
R56
R317
R99
1
1
1
2 0Ohm 5%
2 0Ohm 5%
2 0Ohm 5% /*
58 1.25V_RUN_PWRGD
R105
100KOhm
5%
2
55 1.5V_RUN_PWRGD
55 1.05V_RUN_PWRGD
43 2.5V_RUN_PWRGD
ICH_PWRGD#
+5V_RUN
+5V_ALW
3
D7
1
2
C27
Q26
+3.3V_ALW
R27
1
2200PF/50V
MLCC/+/-10%
4.7KOhm
2
5%
3
C Q5
PMBS3904
1 B
E
2
17,37,53 IMVP_PWRGD
37 RESET_OUT#
D9
4.7KOhm
2
5%
+3.3V_ALW
1
MLCC/+80-20%
0.1UF/10V
2
U6B
1
1 B
4
+3.3V_ALW
C94
NC7WZ14P6X_NL
NC7WZ14P6X_NL
2
3
C Q23
PMBS3904
4.7KOhm
2
5%
2200PF/50V
MLCC/+/-10%
U6A
1
R95
1
C87
0.01UF/25V
MLCC/+/-10%
C96
1
MLCC/+80-20%
E
2
0.1UF/10V
2
14
0.1UF/10V
MLCC/+80-20%
20KOhm
5%
Q20
PMBS3906
B 1
R92
200KOhm
5%
+3.3V_ALW
C88
R100
3
C
RB751V_40
C89
10KOhm
2
5%
10,17
+3.3V_SUS
E
2
E
2
R91
1
ICH_PWRGD
Keep Away from high speed buses
3
C Q24
PMBS3904
1 B
+3.3V_ALW
ICH_PWRGD
11
GND
7
R103
1
2200PF/50V
MLCC/+/-10%
0.1UF/10V
MLCC/+80-20%
U8D
VCC
Q25
PMBS3906
C93
2
R98
200KOhm
5%
1
1
2
RB751V_40
D8
13
74AHC08PW
3
C
C98
10KOhm
2
5%
B 1
R97
1
+3.3V_RUN
12
RESET_OUT#
2N7002
2 S
E
2
IMVP_PWRGD
+1.8V_SUS
+1.8V_RUN
14
1
1
2
R33
200KOhm
5%
0.1UF/10V
MLCC/+80-20%
43
Q6
PMBS3906
3
C
RB751V_40
C36
10KOhm
2
5%
ICH_PWRGD#
R28
1
B 1
E
2
1
28,37,49,54 RUN_ON
R101
1
0Ohm
2
5%
U8A
VCC
3
GND
74AHC08PW
+3.3V_ALW
38
14
5V_3V_1.8V_1.25V_RUN_PWRGD
U8B
VCC
6
RUNPWROK
37,53
SUSPWROK
17,43
GND
7
74AHC08PW
14
+3.3V_ALW
37,49
SUS_ON
3V_5V_SUS_PWRGD
+3.3V_ALW
+3.3V_ALW
C41
D4
74AHC08PW
0.1UF/10V
2
D6
2200PF/50V
MLCC/+/-10%
NC
GND
VCC
0.1UF/10V
MLCC/+80-20%
8
GND
U4
C29
2
1
R36
200KOhm
5%
U8C
VCC
Q8
PMBS3906
3
C
10KOhm
2
5%
B 1
R31
1
2
RB751V_40
C42
E
2
1
MLCC/+80-20%
10
+3.3V_SUS
RB751V_40
R39
200KOhm
5%
2
NC7SZ14P5X_NL
+5V_SUS
+5V_ALW
D3
D5
2200PF/50V
MLCC/+/-10%
1
1
0.1UF/10V
MLCC/+80-20%
C34
2
RB751V_40
R38
200KOhm
5%
3
C
Q7
PMBS3906
B 1
2
RB751V_40
C40
10KOhm
2
5%
E
2
R34
1
R30
200KOhm
5%
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
R29
200KOhm
5%
A
51
OF
4
DESCRIPTION:
68
Power Sequence Logic

3
DESIGN ENGINEER :
C.L. Ho
RELEASE DATE :
2
XDP
U20
SAMTEC/BSH-030-01-L-D-A-TR
5%
5%
T88
T85
1 XDP_OBS4
1 XDP_OBS5
R323
T84
T87
54.9Ohm
1%
/*
7 H_PWRGD_XDP
1 XDP_OBS6
1 XDP_OBS7
2
1
XDP_OBS2
XDP_OBS3_R
+1.05V_VCCP
XDP_OBS0
XDP_OBS1
5%
5%
C331
0.1UF/10V
MLCC/+/-10%
/*
H_PWRGD_XDP
XDP_OBS20
21 CLK_PCIE_XDP_3GPLL
21 CLK_PCIE_XDP_3GPLL#
10
LCTLB_DATA
10 LCTLA_CLK
7
XDP_TCK
XDP_TCK
XDP_OBS16 1
XDP_OBS17 1
T97
T106
XDP_OBS10 1
XDP_OBS11 1
T94
T102
XDP_OBS12 1
XDP_OBS13 1
T95
T104
XDP_OBS14 1
XDP_OBS15 1
T96
T103
+1.05V_VCCP
+3.3V_RUN
C352
0.1UF/10V
MLCC/+/-10%
/*
CLK_XDP
CLK_XDP#
RST_SNS1
21
21
1
2
R123 100Ohm 5%
H_RESET#
R321
R322
2
2 0Ohm
0Ohm
2 /*
/*
2 0Ohm
0Ohm
/*
/*
1
1
Layout note:R123 should

connect to H_RESET# with
no stub
T92
T101
1
1
R346
1KOhm
5%
R347
54.9Ohm
1%
/*
1
7
XDP_BPM#1
XDP_BPM#0
1
1
XDP_OBS8
XDP_OBS9
XDP_BPM#0
R319
R320
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
XDP_BPM#3
XDP_BPM#2
GND0
GND1
OBSFN_A0
OBSFN_C0
OBSFN_A1
OBSFN_C1
GND2
GND3
OBSDATA_A0
OBSDATA_C0
OBSDATA_A1
OBSDATA_C1
GND4
GND5
OBSDATA_A2
OBSDATA_C2
OBSDATA_A3
OBSDATA_C3
GND6
GND7
OBSFN_B0
OBSFN_D0
OBSFN_B1
OBSFN_D1
GND8
GND9
OBSDATA_B0
OBSDATA_D0
OBSDATA_B1
OBSDATA_D1
GND10
GND11
OBSDATA_B2
OBSDATA_D2
OBSDATA_B3
OBSDATA_D3
GND12
GND13
PWRGOOD/HOOK0 ITPCLK/HOOK4
HOOK1
ITPCLK#/HOOK5
VCC_OBS_AB
VCC_OBS_CD
HOOK2
RESET#/HOOK6
HOOK3
DBR#/HOOK7
GND14
GND15
SDA
TDO
SCL
TRSTN
TCK1
TDI
TCK0
TMS
GND16
GND17
NP_NC1
NP_NC2
7
7
XDP_BPM#5
XDP_BPM#4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
7
7
XDP_BPM#5
XDP_BPM#4
7,9
/*
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
7
7
7
BtoB_CON_60P
/*
CAD NOTE:
Place the XDP connector on the
primary side of the CRB and place
all components near the connector.
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
52
4
OF
68
DESCRIPTION:
XDP
<OrgName>
DESIGN ENGINEER :
Terry_Lin
RELEASE DATE :
3
PCE2
100uF/25V
EL/Lf_T=3000hrs_105c/+/-20%
PCE4
100uF/25V
EL/Lf_T=3000hrs_105c/+/-20%
2
1
PCE3
100uF/25V
EL/Lf_T=3000hrs_105c/+/-20%
2
1
PCE1
100uF/25V
EL/Lf_T=3000hrs_105c/+/-20%
2
1
PC147
10UF/25V
MLCC/+/-10%
1
pt_c1206_h71
2
PC77
10UF/25V
MLCC/+/-10%
2
1
pt_c1206_h71
4
3
2
1
PQ17
SI4386DY_T1_E3
PC76
10UF/25V
pt_c1206_h71 MLCC/+/-10%
2
1
PC80
0.1UF/50V
pt_c0603
MLCC/+/-10%
2
1
5
6
7
8
PC79
2200PF/50V
MLCC/+/-10%
2
1
1
2
PC81
2
/*
+VCC_CORE
GND
CORE_HG1
+VCC_CORE_L1
REVISION
1.2
DATE:
SHEET
4
53
1
2
PC85
10UF/25V
pt_c1206_h71 MLCC/+/-10%
PC151
10UF/25V
pt_c1206_h71 MLCC/+/-10%
2
1
PC84
10UF/25V
pt_c1206_h71 MLCC/+/-10%
2
1
4
3
2
1
1
2
2
GND
1
2
PC74
0.22UF/10V
pt_c0603
MLCC/+/-10%
VSUM
ISEN2
PR84
10Ohm
pt_r0603
1%
PR75
7.68KOhm
pt_r0805_h24
1%
PR86
0Ohm
pt_r0603
5%
VO_CORE
B
1
2
1
1
FDS7088SN3
GND
1
PR82
10Ohm
pt_r0603
1%
PR78
10KOhm
1%
GND
GND
PR73
7.68KOhm
pt_r0805_h24
1%
PC73
0.22UF/10V
pt_c0603
MLCC/+/-10%
PR92
2.2Ohm
pt_r1206_h26
5%
PQ22
CORE_LG3
PL14
0.45UH
Irat=25A
pt_inductor_4p_453x394_spe
PC159
1500PF/50V
pt_c0603
MLCC/+/-5%
PC155
1UF/10V
pt_c0603
MLCC/+/-10%
5
6
7
8
PR85
0Ohm
pt_r0603
5%
6
5
1
FCCM
VCC
+VCC_CORE
2
4
3
2
1
+5V_ALW
9
D
GND2
UGATE
PHASE
9
8
7
PU9
ISL6208CRZ
3
4
GND1
LGATE
BOOT
PWM
43
GND
PC89
10UF/25V
pt_c1206_h71 MLCC/+/-10%
PC156
10UF/25V
MLCC/+/-10%
pt_c1206_h71
pt_c1206_h71
PC90
10UF/25V
MLCC/+/-10%
2
1
PC157
10UF/25V
MLCC/+/-10%
1
2
pt_c1206_h71
2
4
3
2
1
PC87
0.1UF/50V
pt_c0603
MLCC/+/-10%
2
1
5
6
7
8
PC88
2200PF/50V
MLCC/+/-10%
2
1
1
PC91
12
2
PQ21
SI4386DY_T1_E3
+VCC_CORE_L3
PWR_MON
PR65
30KOhm
5%
/*
3
1
9
1
9
8
7
GND2
UGATE
PHASE
GND1
LGATE
3
4
2
GND
CORE_HG3
2
2
PL13
0.45UH
Irat=25A
OF
2
1
PC82
pt_c0603
0.1UF/50V
MLCC/+/-10%
2
1
PC83
2200PF/50V
MLCC/+/-10%
2
1
5
6
7
8
1500PF/50V
pt_c0603
MLCC/+/-5%
PC86
1
PR77
10KOhm
1%
6.8KOHM
5% pt_r0603
VO_CORE
PC158
0.22UF/10V
pt_c0603
MLCC/+/-10%
1
2
PC66
0.1UF/10V
MLCC/+/-10%
/*
2
1
PR72
2.43KOhm
1%
1
2
+VCC_CORE
PC153
1500PF/50V
pt_c0603
MLCC/+/-5%
PR90
2.2Ohm
pt_r1206_h26
5%
FDS7088SN3
GND
PR91
2.2Ohm
pt_r1206_h26
5%
1
2
2
PR147
5
6
7
8
PQ20
PC150
1UF/10V
pt_c0603
MLCC/+/-10%
GND
PC71
0.01UF/50V
MLCC/+/-10%
1
4MM_OPEN_5MIL
/*
+CPU_PWR_SRC
PR66
15KOhm
1%
/*
CGND
4MM_OPEN_5MIL
/*
PJP15
1
2
ISEN3
ISEN2
ISEN1
6
5
CORE_LG2
CGND
PROJECT: Lanai
+5V_ALW
FCCM
VCC
1500PF/50V
pt_c0603
MLCC/+/-5%
1
2
1
PR70
15KOhm
1%
PR69
4.53KOhm
1%
1
2
PC68
0.33UF/16V
pt_c0603
MLCC/+/-10%
2
1
Intersil request to
change.
PR150
0Ohm
pt_r0603 GND
5%
PC67
0.1UF/16V
MLCC/+/-10%
1
2
VO_CORE
PC70
0.01UF/25V
MLCC/+/-10%
2
1
PR76
0Ohm
pt_r0603
5%
1
ISL6208CRZ
CGND
PC69
0.033UF/16V
MLCC/+/-10%
2
1
45
41
40
39
38 CLK_ENABLE#
PR62
37
2
1
36
1%
35 499Ohm
34
33
32
31
GND4
GND
PGOOD
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
GND1
11
12
13
14
15
16
17
18
19
20
42
2
CGND
2
1
PC64
330PF/50V
MLCC/+/-10%
2
1
PR67
1KOhm
1%
VSUM
BOOT
PWM
D
4
3
2
1
/*
CGND
Close to Phase 1
Inductor
1
2
PU8
PR74
GND
10Ohm +CPU_PWR_SRC
pt_r0603
1 1%
2
VIN
CGND
CGND
PR60
0Ohm
pt_r0603
5%
PC72
1UF/10V
pt_c0603
MLCC/+/-10%
CGND
PR68
10.5KOhm
1%
VSSSENSE
PR53
0Ohm
pt_r0603
1 5%
2
PQ19
SI4386DY_T1_E3
+VCC_CORE_L2
PR149
0Ohm
pt_r0603 GND
5%
/*
1
ISEN1
PR80
0Ohm
pt_r0603+PWR_SRC
5%
VO_CORE
PJP16
1 1 2 2
GND
GND
2
1
30
29
28
27
26
25
24
23
22
21
44
43
CORE_HG2
VCCSENSE
PR89
2.2Ohm
pt_r1206_h26
5%
CGND
VID2
VID1
VID0
PWM1
PWM2
PWM3
FCCM
ISEN1
ISEN2
ISEN3
GND3
GND2
PC154
0.22UF/10V
pt_c0603
MLCC/+/-10%
PR81
+5V_ALW
10Ohm
pt_r0603
VDD_CORE 1 1%
2
2 PR51
1
4.99KOhm 1% /*
1 PR54
2
0Ohm 5%
PR45
1.69KOhm
1 1%
2
2
PR44
0Ohm
5%
/*
GND
PC58
680PF/50V
MLCC/+/-10%
PU4
ISL6260CCRZ_T
MLCC/+/-10%
PSI#
PMON
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB
PC189
1000PF/50V
MLCC/+/-10%
PR47
332Ohm
1%
PC57
0.01UF/16V
2
1
1
2
3
4
5
6
7
8
9
10
PC190
1000PF/50V
MLCC/+/-10%
1%
PR43
82.5KOhm
1%
1
PC63
1000PF/50V
MLCC/+/-10%
MLCC/+/-10%
PC65
1000PF/50V
MLCC/+/-10%
PR50
1KOhm
1 PR55
2
0Ohm 5%
1000PF/50V
MLCC/+/-10%
PC61
2
1
2
1
PR48
6.34kOhm
1 1%
2
PC55
220PF/50V
2
1
PR56
226KOhm
1%
/*
1
2
PR46
11.5KOhm
1%
GND
PSI#
PMON
PC56
1500PF/50V
MLCC/+/-10%
2
1
VO_CORE 2
PR58
0Ohm
pt_r0603
5%
PR144 10KOHM
pt_r0603
1
5% /*
VDD_CORE
2
PR49
13KOhm
1% /*
1
5% pt_r0603
38 IMVP6_PROCHOT#
PR52
10KOhm
5%
GND
/*
Close to Phase 1
Inductor
CGND
PR57
147KOhm
1%
VSUM
GND
PR145
470KOHM
1
2
2
1
PR146
0Ohm
5%
/*
PC75
0.22UF/10V
pt_c0603
MLCC/+/-10%
PC59
0.015UF/16V
MLCC/+/-10%
+CPU_PWR_SRC
PC152
10UF/25V
pt_c1206_h71 MLCC/+/-10%
2
1
8
8
8
8
VID2
VID1
VID0
GND
CGND
1
PR71
7.68KOhm
pt_r0805_h24
1%
+CPU_PWR_SRC
PC62
2200PF/50V
MLCC/+/-10%
/*
PR83
10Ohm
pt_r0603
1%
PR79
10KOhm
1%
PR87
2.2Ohm
pt_r1206_h26
5%
FDS7088SN3
GND
CORE_LG1
VID6
VID5
VID4
VID3
9
8
7
3
4
ISL6208CRZ
PQ18
PC148
1UF/10V
pt_c0603
MLCC/+/-10%
PL12
0.45UH
Irat=25A
PC78
1500PF/50V
pt_c0603
MLCC/+/-5%
PC60
1UF/10V
pt_c0603
MLCC/+/-10%
7,10,15
10,17
PR59
1.91KOhm
pt_r0603
1%
6
5
8
8
8
PWR_MON
PWR_MON
PT1
TPC32T
1
H_DPRSTP#
DPRSLPVR
43
FCCM
VCC
5
6
7
8
H_PSI#
BOOT
PWM
D
4
3
2
1
+5V_ALW
1
2
PU7
GND2
UGATE
PHASE
+3.3V_RUN
17,37,51 IMVP_PWRGD
GND1
LGATE
2
2
PMON
PR148
0Ohm
pt_r0603 GND
5%
PR63
0Ohm
1 5% /*
37 IMVP_VR_ON
PC149
0.22UF/10V
pt_c0603
MLCC/+/-10%
1500PF/50V
pt_c0603
MLCC/+/-5%
PR64
0Ohm
1 5%
PR88
2.2Ohm
pt_r1206_h26
5%
2
PR61
0Ohm
1 5% /*
37,51 RUNPWROK
PC146
10UF/25V
pt_c1206_h71 MLCC/+/-10%
2
1
+CPU_PWR_SRC
Design Current:35.2A
Maximum current:44A
OCP point min.50A
VSUM
ISEN3
GND
DESCRIPTION:
POWER_VCORE
68
3
<OrgName>
DESIGN ENGINEER :
JEFF
RELEASE DATE :
2
+15V_ALWP
+5V_ALW2
1
2
1
2
21
2
PC180
1UF/25V
pt_c0603
MLCC/+/-10%
+5V_PMP
+VCC_TPS51120
1
2
PD20
BAT54
PC165
0.1UF/25V
pt_c0603
MLCC/+/-10%
1
2
GND
PC163
330UF/6.3V
pt_c7343d_h118
TAN/Lf_T=2000hrs_105C/+/-20%
5
6
7
8
1
1
2
2
3
PC181
1UF/25V
pt_c0603
MLCC/+/-10%
3.3UH
Irat=8.8A
pt_inductor_2p_453x394
PD18
BAT54S
pt_sot23_philips
3
1
2
2
4
3
2
1
GND
PC95
10UF/25V
pt_c1206_h71
MLCC/+/-10%
PC174
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
+3.3V_ALWP
PL15
3V_5V_POK
PC173
1000PF/50V
pt_c0603
MLCC/+/-10%
1
2
PC176
0.1UF/50V
pt_c0603
MLCC/+/-10%
2
1
PC175
2200PF/50V
MLCC/+/-10%
2
1
1
2
PC179
0.1UF/25V
pt_c0603
MLCC/+/-10%
pt_r0603
5%
2
PQ44
SI4392DY-T1-E3
5
4
3
6
2
7
1
8
PC183
1UF/10V
pt_c0603
MLCC/+/-10%
1
1
2
3
4
5
6
7
8
GND
GND
+3.3V_ALWP_L
PQ48
FDS6676AS
+3.3V_DH
+3.3V_VBST
VO1
COMP1
VFB1
VREF2
GND1
VFB2
COMP2
VO2
FDS6690AS
PQ43
CS2
2
CS1
24
23
22
21
20
19
18
17
PR177
0Ohm
pt_r0603
5%
1
2
3
4
8
7
6
5
D
S
1
2
3
4
1
PR160
40.2KOhm
1%
+3.3V_DL
PR159
0Ohm
pt_r0603
5%
PC94
330UF/6.3V
pt_c7343d_h118
TAN/Lf_T=2000hrs_105C/+/-20%
2
1
/*
16
15
14
13
12
11
10
9
+VCC_TPS51120
DRVL1
DRVL2
LL1
LL2
DRVH1
VBST1 TPS51120RHBR DRVH2
VBST2
EN1
EN2
PGOOD1
PGOOD2
TONSEL
EN3
SKIPSEL
EN5
GND2
GND
PR185
0Ohm
5%
PD19
BAT54S
pt_sot23_philips
PC96
0.1UF/25V
pt_c0603
MLCC/+/-10%
2
1
+5V_ALWP_L
PGND1
CS1
VIN
VREG5
V5FILT
VREG3
CS2
PGND2
25
26
27
28
29
3V_5V_POK 30
TONSEL 31
32
33
+5V_DH
+5V_VBST
GND
PC178
0.1UF/25V
pt_c0603
MLCC/+/-10%
2
1
SI4800BDY
PQ46
8
7
6
5
S
+5V_DL
PL3
3.3UH
Irat=8.8A
PU10A
GND
GND
PC188
1UF/25V
pt_c0603
MLCC/+/-10%
+5V_ALWP
+5V_ALWP
PC185
1UF/25V
pt_c0603
MLCC/+/-10%
+10V_ALWP
PC172
2200PF/50V
MLCC/+/-10%
PC177
0.1UF/50V
pt_c0603
MLCC/+/-10%
2
1
PC93
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
PC171
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
4MM_OPEN_5MIL
/*
PR178
0Ohm
PC182
0.1UF/50V
pt_c0603
MLCC/+/-10%
2
1
PLACE THESE CAPS CLOSE TO FETS
GND
PJP8
1
+DC1_PWR_SRC
GND
+3.3V_RTC_LDO
PC98
10UF/16V
pt_c1206_h71
MLCC/+/-10%
+DC1_PWR_SRC
GND
+3.3V_BS
+5V_BS
+PWR_SRC
3.3 Volt +/-5%

Maximum current:8.78A
OCP point min. 13.14A
34
35
36
37
38
39
40
41
42
PC186
1UF/10V
pt_c0603
MLCC/+/-10%
2
1
PLACE THESE CAPS CLOSE TO FETS
PR183
47Ohm
pt_r0603
5%
2
TPS51120RHBR
PD12
RB717F
pt_sot323
/*
PC99
10UF/16V
pt_c1206_h71
MLCC/+/-10%
2
1
5 Volt +/-5%
OCP point min. : 8.82A
PU10B
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
+VCC_TPS51120
GND
PC184
1
2
1000PF/50V
pt_c0603
MLCC/+/-10%
11
PR170
0Ohm
/* 5%
EC_PWM_2
2 S
PQ47
2N7002
/*
PU11
1 A
2 S
VCC
PR186
4
Y
SN74LVC1G00DCKR
+5V_DL
3
D
2 S
ALW_PWRGD_3V_5V 37
PROJECT: Lanai
5
1.2
SHEET
4
54
OF
68
DESCRIPTION:
POWER_SYSTEM 5V_ALW&3.3V_ALW
1
0Ohm
pt_r0603
5% /*
<OrgName>
DESIGN ENGINEER :
JEFF
RELEASE DATE :
2
1
120Ohm
5%
A
GND
GND
PR179
3V_5V_POK
DATE:
2 B
GND
GND
REVISION
1UF/25V
pt_c0603
MLCC/+/-10%
PC187
1
2
1
G
PR176
100KOhm
5%
GND
2
2
1
PR187
47KOhm
5%
1
0Ohm
5%
1
3
3 GND
GND
28,37,49,51 RUN_ON
PQ50
2N7002
1
PD10
BAT54
/*
PR93
2.2MOhm
5%
/*
PC160
4.7UF/10V
pt_c1206_h71
MLCC/+/-10%
G
11
/*
0.01UF/25V
pt_c0603
MLCC/+/-10%
/*
PR188
37
+3.3V_ALWP
1
2
PQ23
2N7002
/*
PR94
4.7KOhm
5%
/*
2
THERM_STP#
PR181
0Ohm
5%
GND
PR166
200KOhm
5%
/*
2
1
3 D
PC161
1
+3.3V_ALW
PQ37
FDN340P_NL
/*
3 D
PR171
0Ohm
5%
TONSEL
+3.3V_RTC_LDO
GND
GND
PQ45
BSS84LT1G
/*
4MM_OPEN_5MIL
/*
PC192
0.1UF/25V
pt_c0603
MLCC/+/-10%
2
1
+VCC_TPS51120
PJP17
+5V_ALWP
PR180
0Ohm
5%
/*
+5V_ALWP
/*
PR165
0Ohm
5% /*
PR175
0Ohm
/* 5%
+3.3V_ALW
PR182
9.76KOhm
1% 1
+VCC_TPS51120
+3.3V_ALWP
1
1000PF/50V
pt_c0603
MLCC/+/-10%
4MM_OPEN_5MIL
/*
GND
2
PC97
1
PR103
12.4KOhm
1%
2
1
1
PR164
0Ohm
5% /*
1
PJP7
1
PR163
23.2KOhm
1%
1
2
CS2
+3.3V_VFB
+5V_ALW
GND
+5V_ALW2
2
1
+5V_ALWP
PR161
0Ohm
pt_r0603
5%
/*
PR162
10KOhm
pt_r0603
1%
For debug
2MM_OPEN_5mil
/*
B
CS1
PR168
0Ohm
/* 5%
PR172
0Ohm
5%
PR169
0Ohm
5% /*
GND
+VCC_TPS51120
43 THERM_STP#
GND
PJP18
1
ALWON
PR167
0Ohm
5%
+15V_ALW
37
PC191
0.1UF/25V
pt_c0603
MLCC/+/-10%
2
1
+15V_ALWP
PR174
1KOhm
1%
/*
PR158
10KOhm
pt_r0603
1%
GND
PR173
200KOhm
5%
1
+5V_VFB
PC32
10UF/25V
pt_c1206_h71
MLCC/+/-10%
PC127
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
PC28
0.1UF/50V
pt_c0603
MLCC/+/-10%
2
1
1
2
PC33
2200PF/50V
MLCC/+/-10%
2
1
PJP11
PC124
0.1UF/10V
MLCC/+/-10%
PC128
10UF/6.3V
pt_c1206_h35
MLCC/+/-10%
2
1
PQ10
PC135
330UF/2.5V
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20%
2
1
1
2
+1.05V_VCCP_P
FDS7088SN3
4MM_OPEN_5MIL
/*
PC125
330UF/2.5V
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20%
2
1
9
MLCC/+/-10%
4MM_OPEN_5MIL
/*
1
2
1
PR36
15KOhm
pt_r0603
1%
1UF/10V
pt_c0603
MLCC/+/-10%
PC39
1
2
PC37
0.1UF/10V
MLCC/+/-10%
/*
GND
PC41
100PF/50V
MLCC/+/-5%
PR35
15KOhm
pt_r0603
1%
2
1
GND
10Ohm
pt_r0603
5%
PR131
5.6KOhm
1%
5
6
7
8
+1.5V_RUN_P
PR34
+1.5V_V5FILT
+5V_SUS
4
3
2
1
1UH
Irat=14.3A
D
1UF/10V
pt_c0603
MLCC/+/-10%
PC126
1
+1.05V_LG
+1.05V_V5FILT
PR130
10Ohm
pt_r0603
5%
1
5
6
7
8
4
3
2
1
PJP10
GND
PR23
29.4KOhm
pt_r0603
1%
+1.05V_VCCP
+1.05V_VCCP_P
PL8
+1.05V_VCCP_P_L
PQ8
FDS8880
+1.05V_HG
+5V_SUS
+1.05V_V5FILT2_L
PC31
39PF/50V
MLCC/+/-5%
PR25
11.8KOhm
pt_r0603
1%
2
1
PC36
0.1UF/10V
MLCC/+/-10%
/*
2
1
+1.05V_VBST
PC120
1
2
GND
RUN_1.5VO
SN0508073PWR
+1.05V_VCCP_P
GND
1UF/10V
pt_c0603
MLCC/+/-10%
2
1
+1.5V_PG1
+1.5V_LG
GND
+DC2_PWR_SRC
+1.5V_V5FILT2_L
+1.5V_VBST
PQ7
FDS8880
8
7
6
5
D
PQ9
FDS6670AS
8
7
6
5
D
+1.5V_RUN_P
S
1
2
PC137
330UF/2.5V
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20%
1UH
Irat=14.3A
PC136
10UF/6.3V
pt_c1206_h35
MLCC/+/-10%
2
1
4MM_OPEN_5MIL
/*
+1.5V_RUN_P_L
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC118
1UF/10V
pt_c0805_h33
1
2
GND
PGND1
GND1
DRVL1 PGOOD1
V5DRV1
VFB1
TRIP1
V5FILT1
LL1
VOUT1
DRVH1
TON1
VBST1 EN_PSV1
EN_PSV2 VBST2
TON2
DRVH2
VOUT2
LL2
V5FILT2
TRIP2
VFB2
V5DRV2
PGOOD2 DRVL2
GND2
PGND2
1
2
3
4
PU2
PL9
PC133
0.1UF/10V
MLCC/+/-10%
2
1
GND
1
2
3
4
5
+1.5V_HG
6
7
RUN_1.05VO
8
9
10
11
12
+1.05V_PG2 13
14
1.05 Volt +/-5%

OCP point min. 11.91A
(OCP point typ.: 15.71A)
2
PR142
9.53KOhm
1%
PJP12
1
1
PR30
0Ohm
5%
TI request to change.
+1.5V_RUN_P
+5V_SUS
PC40
1UF/10V
pt_c0805_h33
MLCC/+/-10%
1
2
3
4
1
2
PC26
2200PF/50V
MLCC/+/-10%
PC122
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
PC30
0.1UF/50V
pt_c0603
MLCC/+/-10%
PC29
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
4MM_OPEN_5MIL
/*
+1.5V_RUN
PD17
BAT54A
pt_sot23_philips
/*
1
PR31
0Ohm
5%
+DC2_PWR_SRC
PC35
0.1UF/25V
pt_c0805_h53
MLCC/+/-10%
1
2
+1.05V_BS
1
+1.5V_BS
2
PC129
0.1UF/25V
pt_c0805_h53
MLCC/+/-10%
1
2
PJP9
1
PR134
200KOhm
1%
2
PR140
210KOhm
1%
1
2
1.5 Volt +/-5%

Design Current: 3.02A
+PWR_SRC
GND
51 1.5V_RUN_PWRGD
51 1.05V_RUN_PWRGD
+1.5V_PG1
GND
+1.05V_PG2
For debug
PR141
0Ohm
5%
37 1.5V_RUN_ON
38 1.05V_RUN_ON
RUN_1.5VO
RUN_1.05VO
PR133
0Ohm
5%
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET

OF
55
4
68
DESCRIPTION:
POWER_I/O_1.5VS & 1.05VS

3
<OrgName>
DESIGN ENGINEER :
JEFF
RELEASE DATE :
2
TOTAL POWER=65W
-->3.34A
TABLE3
PIN NAME DIFFERENCES
MAXIM
PIN
+PBATT
+VCHGR
CHRG_IN
PR109
10mOhm
pt_r2512_4p_h33
1%
1
2
4
3
SI4835BDY-T1-E3
+DC_IN_SS
2
CHG_CSSN_L
2 ACAV_IN
CHG_CSSP_L
PQ34
RHU002N06
GND
PR116
0Ohm
pt_r0603
5%
GND
1
GND
PC16
1UF/10V
pt_c0603
MLCC/+/-10%
1
2
CHG_BST_L
PR19
1Ohm
pt_r0603
1%
PD16
RB751V_40
1
2
PC15
0.1UF/25V
pt_c0603
MLCC/+/-10%
0, 0402, 5%
10, 0402, 5%
No Stuff
0.22uF
PC19
No Stuff
0.22uF
PC22
0.01uF
No Stuff
PC18
0.1uF, 0402, 10V
No Stuff
PC8
220pF, 0402, 50V
No Stuff
PD16
RB751V-40
No Stuff
PC13
3.3nF
No Stuff
PR19
1, 0603, 1%
0, 0603, 5%
0.01uF
PC21
0.01uF
0.01uF
VDDP
23
LX
PHASE
24
DHI
UGATE
25
BST
BOOT
PR124
INP
PR121
57.6KOhm
1%
PC108
100PF/50V
MLCC/+/-5%
2
0Ohm
5%
PC115
0.01UF/16V
MLCC/+/-10%
PC109
10UF/25V
pt_c1206_h71
MLCC/+/-10%
1
2
PC6
10UF/25V
pt_c1206_h71
MLCC/+/-10%
PC7
0.1UF/50V
pt_c0603
MLCC/+/-10%
PC11
2200PF/50V
MLCC/+/-10%
2
1
2
2
PQ6
SI4800BDY
5
6
7
8
5
6
7
8
1
PC4
0.22UF/10V
pt_c0603
MLCC/+/-10%
/*
1
2
PQ4
SI4810BDY-T1-E3
1
2
3
PR12
1KOhm
5%
pt_r0603
/*
PR189
1.8KOhm
5%
pt_r1206_h26
/*
3
3D
1 S
GND
PC107
0.01UF/16V
MLCC/+/-10%
GND_CHA
GND_CHA
GND_CHA
PR123
13KOhm
1%
1
2
3
4
V=0.975V,I=3.25A
PC112
100PF/50V
MLCC/+/-5%
VOUT1
VIN1VIN1+
GND
VCC
VOUT2
VIN2VIN2+
8
7
6
5
ADAPT_OC
38
PR121
PR123
PR126
PR122
65
3.17
57.6K
13.0K
105
N/A
90
4.43
51.1K
17.8K
348
33.2K
130
6.43
32.4K
20.5K
100
27.4K
88.7K
ADAPTOR (W)
TRIP CURRENT (A)
150
7.43
30.9K
24.9K
432
PQ35
200
9.75
19.1K
28K
301
2 S
36.5K
2N7002
230
11.28
32.4K
6.49K
115
N/A
Note 1: PR122 is populated if ADAPT_TRIP_SET is

used to program for the next lower adaptor
ADAPT_TRIP_SET is floating for the higher
adaptor, grounded for the lower adaptor
Note 2: 24.9K at PR122 allows the 65W adaptor
setting to switch down to 45W. (now is N/A)
Note 3: PR109 must be 5m ohm instead of 10m ohm
for the 230W adaptor
LM393DR
PC114
100PF/50V
MLCC/+/-5%
PC113
0.01UF/16V
MLCC/+/-10%
1
PR126
105Ohm
1%
PU5
GND
PR118
1MOhm
1%
GND_CHA
OC TRIP
PR117
100KOhm
1%
2
PR122
33.2KOhm
1%
/*
TABLE1
PR128
100KOhm
1%
38 ADAPT_TRIP_SEL
FOR GPRS IMMUNITY PLACE

AS CLOSE TO THE IC AS
POSSIBLE
GND_CHA
GND_CHA
GND_CHA
PROJECT: Lanai
5
PD3
1SS355
/*
4
3
2
1
PQ5
SI4800BDY
5
6
7
8
4
3
2
1
PC13
3300PF/50V
MLCC/+/-10%
2
1
CHG_CSIN_L
2
BAT_REF 2
No stuff
LDO
+3.3V_ALW
FOR GPRS IMMUNITY
PLACE AS CLOSE TO THE
IC AS POSSIBLE
No stuff
1K, 0603, 5%
LGATE
21
1SS355
PR12
DLO
+5V_ALW
Maxim request
to add
PD3
20
NC
4.7K, 0402, 5%
0.01uF
CSOP
PR113
0Ohm
pt_r0603
5%
0, 0402, 5%
4.7K, 0402, 5%
PC23
CSON
CSIP
PQ51
RHU002N06
/*
ACAV_IN
2 2
G
37,59 PBAT_SMBCLK
100, 0402, 5%
PR22
CSIN
18
GND
PR9
17
37,59 PBAT_SMBDAT
PR21
PC4
FBSB
10, 0402, 5%
VFB
16
GND
PR127
1KOhm
1%
/*
0, 0402, 5%
NC
FBSA
PR8
0Ohm
5%
PR8
5.2UH
Irat=5.5A
215K, 0402, 1%
VDDSMB
BATSEL
15
+5V_ALW
365K, 0402, 1%
VDD
14
PR108
2 +VCHGR_LX
GND_CHA
PC116
100PF/50V
MLCC/+/-5%
/*
No Stuff
11
GND
No Stuff
1.0uF, 0603, 10V
ICM
CHG_CSIP_L
No Stuff
0.1uF, 0402, 10V
1
PR10
15.8KOhm
1%
PC10
0.1UF/10V
MLCC/+/-10%
0.01uF
PC17
PC24
PC115
37,43
CHG_DLO_L
16.0K, 0402, 1%
CHG_DHI_L
2
1
ACAV_IN
INTERSIL
8.45K, 0402, 1%
+VCHGR_L
1
PR13
0Ohm
5%
PR125
8.45KOhm
1%
MAXIM
PR125
IINP
PR119
10mOhm
pt_r2512_4p_h33
1%
1
2
4
3
PL7
2
2
2
2
REF DES
CHG_LX_L
GND3
CSSP
CSSN
VCC
BST
DHI
LX
DCIN
8
9
10
11
12
13
14
PC18
0.1UF/10V
MLCC/+/-10%
MAXIM & INTERSIL BOM DIFFERENCES

B
GND
GND
PR11
10KOhm
1%
INP
PC17
0.1UF/10V
MLCC/+/-10%
NC
+VCHGR
LDO
1
1
TABLE2
DAC
Charge Current:4.68A
Discharge current:6.6A
2
PR9
100Ohm
5%
+5V_ALW
PC23
0.01UF/25V
MLCC/+/-10%
VCOMP
+VCHGR
1
1
2
1
2
PC22
0.01UF/25V
MLCC/+/-10%
IINP
SDA
SCL
VDD
GND2
ACOK
BATSEL
2
1
2
PC21
0.01UF/25V
MLCC/+/-10%
PC24
1UF/10V
pt_c0603
MLCC/+/-10%
PR22
10KOhm
5%
GND_CHA
LDO
DLO
PGND
CSIP
CSIN
FBSB
FBSA
MAX8731AETI
PC1
1UF/10V
pt_c0603
MLCC/+/-10%
1
2
LDO
GND
21
20
19
18
17
16
15
PR120
49.9KOhm
1%
GND1
ACIN
REF
CCS
CCI
CCV
DAC
PR114
33Ohm
pt_r0603
5%
PC5
1UF/25V
pt_c0805_h57
MLCC/+/-10%
29
28
27
26
25
24
23
22
PC8
220PF/50V
MLCC/+/-10%
BAT_REF
PC20
0.01UF/25V
MLCC/+/-10%
NC
CCV
1
2
3
4
5
6
7
CCI
"NC" means no-connect
2
1
PU1
GND_CHA
ICOMP
CHG_VCC_L
PR108
365KOhm
1%
CCS
PC111
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
2
G
VREF
1
PR112
470KOhm
5%
D3
S 1
8
7
6
5
REF
PC117
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
PC2
0.1UF/50V
pt_c0603
MLCC/+/-10%
/*
PQ3
D
PC19
0.22UF/10V
pt_c0603
MLCC/+/-10%
/*
1
2
PR21
0Ohm
5%
PR110
100KOhm
5%
PR111
10KOhm
5%
PC3
2200PF/50V
MLCC/+/-10%
/*
4MM_OPEN_5MIL
/*
SI4835BDY-T1-E3
1
2
3
4
1
NC
PC110
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
+DC_IN_SS_X
1
2
3
4
PJP1
PQ33
D
S
8
7
6
5
+PWR_SRC
GND
PC14
0.1UF/25V
pt_c0603
MLCC/+/-10%
2
1
+DC_IN_SS
INTERSIL
REVISION
1.2
DATE:
SHEET

OF
57
4
68
DESCRIPTION:
POWER_CHARGER
3
<OrgName>
DESIGN ENGINEER :
JEFF
RELEASE DATE :
2
1.25Volt +/-5%
5%
1
PC131
0.1UF/25V
pt_c0805_h53
MLCC/+/-10%
1
2
1
2
PC42
10UF/25V
pt_c1206_h71
MLCC/+/-10%
1
2
PC138
10UF/25V
pt_c1206_h71
MLCC/+/-10%
1
2
PC44
0.1UF/50V
pt_c0603
MLCC/+/-10%
1
2
4
3
2
1
PC45
2200PF/50V
MLCC/+/-10%
5
6
7
8
+1.8V_VBST
1
2
2
1
PC38
0.1UF/10V
MLCC/+/-10% /*
PC132
100PF/50V
MLCC/+/-5%
1
PR143
15KOhm
pt_r0603
1%
2
1
2
1
pt_c0603
MLCC/+/-10%
PC130
1UF/10V
2
1
+1.8V_SUSP
GND
PJP13
1
+
4MM_OPEN_5MIL
/*
PC142
0.1UF/10V
MLCC/+/-10%
+1.25V_SRC_MP
PC141
330UF/2.5V
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20%
2
1
0.88UH
Irat=17A
PQ12
FDS6676AS
1
PC144
330UF/2.5V
pt_c7343d_h79
TAN/Lf_T=2000hrs_105C/+/-20%
2
1
5
6
7
8
+5V_SUS
PR137
10Ohm
5%
PR26
12.4KOhm
1%
2
1
PC27
1UF/10V
1
2
4
3
2
1
PC119
1UF/10V
pt_c0805_h33
MLCC/+/-10%
1
2
+1.8V_DL
+1.8V_V5FILT
PR28
10Ohm 5%
2
1
2
2
PC121
39PF/50V
MLCC/+/-5%
2
1
PR132
14KOhm
pt_r0603
1%
+1.8V_SUS_L
For debug
GND
PJP14
PL11
PJP5
PR129
10KOhm
pt_r0603
1%
PC25
0.1UF/10V
MLCC/+/-10%
/*
2
1
+1.25V_SRC_MP
+1.8V_SUS
+1.8V_SUSP
1.25V_RUN_ON 37
+1.8V_DH
SN0508073PWR
GND
PQ13
FDS8880
GND
2 PR136 1
0Ohm 5%
+5V_SUS
For debug
+1.8V_SUSP
+1.25V_SRC_MP
+1.25V_V5FILT
PR138
9.53KOhm
1%
2
1
S2
DDR_ON_P
GND
+1.25V_RUN
PC123
1UF/10V
pt_c0603
MLCC/+/-10%
2
1
VGA_1.25V_VBST
PC47
0.1UF/50V
pt_c0603
MLCC/+/-10%
PC43
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
1
2
PC46
2200PF/50V
MLCC/+/-10%
G2
VGA_1.25V_L
S1
Q1
D2
G1
Q2
VGA_1.25V_DL
FDS6982AS
+1.25V_PG1
PC145
220UF/2.5V
pt_c7343d_h75
TAN/Lf_T=2000hrs_105C/+/-20%
D2
GND
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC140
10UF/6.3V
pt_c1206_h35
MLCC/+/-10%
2
1
PGND1
GND1
DRVL1 PGOOD1
V5DRV1
VFB1
TRIP1
V5FILT1
LL1
VOUT1
DRVH1
TON1
VBST1 EN_PSV1
EN_PSV2 VBST2
TON2
DRVH2
VOUT2
LL2
V5FILT2
TRIP2
VFB2
V5DRV2
PGOOD2 DRVL2
GND2
PGND2
PC143
0.1UF/10V
MLCC/+/-10%
2
1
+DC3_PWR_SRC
GND
PU6
1
2
3
4
PC134
5
1UF/10V
6
pt_c0805_h33
7
MLCC/+/-10%
8
9
10
11
12
+1.8V_PG2 13
14
2
D1
D1
PR135
0Ohm
5%
1UH
Irat=14.3A
1.8Volt +/-5%
Design Current: 6.59A
Maximum current: 9.42A
PR29
0Ohm
5%
2
PQ11
4
PL10
PD8
BAT54A
pt_sot23_philips
+1.25V_SRC_MP
VGA_1.8V_BS
+5V_SUS
VGA_1.25V_DH
TI request to change.
VGA_1.25V_BS
PR139
22.6KOhm
pt_r0603
1%
+DC3_PWR_SRC
PC139
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
4MM_OPEN_5MIL
/*
PC34
0.1UF/25V
pt_c0805_h53
MLCC/+/-10%
1
2
PJP3
1
PR32
150KOhm
1%
1
2
+PWR_SRC
PR27
200KOhm
pt_c0603
MLCC/+/-10%
4MM_OPEN_5MIL
/*
Change to low profile

FOR LAYOUT ISSUE
GND
4MM_OPEN_5MIL
/*
GND
GND
B
0.9Volt +/-5%
+5V_ALW
+0.9V_P
1
2
PR38
0Ohm 5%
PC48
10UF/6.3V
pt_c0805_h53
MLCC/+/-10%
/*
GND1
GND2
11
S3
S5
2MM_OPEN_5mil
/*
V_DDR_MCH_REF
No.38
/*
TPS51100DGQ
PC49
0.1UF/10V
MLCC/+/-10%
PC51
1UF/10V
pt_c0603
MLCC/+/-10%
PC54
10UF/6.3V
pt_c0805_h53
MLCC/+/-10%
PC50
10UF/6.3V
pt_c0805_h53
MLCC/+/-10%
DDR_ON
PGND
For debug
+1.25V_PG1
51 1.25V_RUN_PWRGD
PR24
100KOhm
1%
37
+3.3V_SUS
PR33
100KOhm
1%
1
DDR_ON_P
3
5
6
VTT
VIN
VLDOIN VTTSNS
VDDQSNS VTTREF
PR41
0Ohm 5%
10
2
1
+1.8V_SUSP_VLDOIN&VDDQSNS
37 0.9V_DDR_VTT_ON
2MM_OPEN_5mil
/*
2
1
For debug
+3.3V_ALW
+0.9V_DDR_VTT
PJP6
PU3
PJP4
+1.8V_SUSP
No.32
GND
GND
A
37 1.8V_SUS_PWRGD
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET

OF
58
4
68
DESCRIPTION:
POWER_VGA_1.25V & DDR & VTT RELEASE DATE :

3
<OrgName>
+1.8V_PG2
DESIGN ENGINEER :
Jeff
2
+3.3V_ALW
ESD DIODES
PD7
PD6
PD4
PD5
DA204U
pt_sot323_rohm
3
GND
DA204U
pt_sot323_rohm
/*
DA204U
pt_sot323_rohm
DA204U
pt_sot323_rohm
TDC REQUSET TO CHANGE
+3.3V_ALW
+3.3V_ALW
PCON2
PBAT_SMBCLK 37,57
PBAT_SMBDAT 37,57
PR16
100Ohm
5%
PR17
100Ohm
5%
2
1
11
P_GND2
2
2
/*
PR15
10KOhm
5%
PR18
100Ohm
5%
BATT+_IN
Z4304
SMB_CLK
Z4305
SMB_DAT
Z4306
BATT_PRES#
SYSPRES#
BATT_VOLT
BATT1BATT2-
PC9
0.1UF/50V
pt_c0603
MLCC/+/-10%
2
1
PC12
2200PF/50V
MLCC/+/-10%
2
1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
PR20
100KOhm
5%
+PBATT
10
P_GND1
PBAT_PRES#
2
BATT_CON_9P
38
PBAT_ALARM#
PR14
100Ohm
5%
PS_ID_DISABLE# 38
S 2
2
3
37
PC100
10UF/25V
pt_c1206_h71
MLCC/+/-10%
2
1
GND
1
PQ2
SI2301BDS
/*
PR107
240KOhm
1%
PR6
0Ohm
5%
/*
PC101
0.47UF/25V
pt_c0805_h53
MLCC/+/-10%
2
1
PC105
0.1UF/25V
pt_c0603
MLCC/+/-10%
/*
DC_PWR_JACK_5P
pt_dc_pwr_jack_5p_6hold_lf2
8
7
6
5
PQ32
FDS6679_NL
1
2
3
4
5
PC104
0.1UF/50V
pt_c0603
MLCC/+/-10%
2
1
PC103
0.1UF/50V
pt_c0603
MLCC/+/-10%
2
1
1
2
3
4
PR106
4.7KOhm
pt_r0805_h24
5%
1
2
+DC_IN_SS
+DC_IN
60Ohm/100Mhz
pt_l1806
MURATA/BLM41PG600SN1L
PCON1
1
2
3
4
5
PS_ID
2
PR1
33Ohm
5%
/*
PL6
P_NC3
P_NC1
NP_NC1
NP_NC2
P_NC2
P_NC4
1 1
1
+DCIN_JACK
10
6
7
8
9
11
2
PR3
33Ohm
5%
1000Ohm/100MHz
pt_l0603
FERRITE BEAD(0603)1000OHM/0.1A
PC102
0.01UF/25V
MLCC/+/-10%
2
1
D3
PL4
PR7
2.2KOhm
5%
PQ31
pt_sot23
FDV301N_NL
GND
PD2
DA204U
pt_sot323_rohm
B 1
PR104
100KOhm
pt_r0603
5%
GND
PD1
DA204U
pt_sot323_rohm
/*
PR5
10KOhm PR2
10KOhm
5%
5%
/*
1
2
+3.3V_ALW
PR4
15KOhm
PQ30
PMBS3904
3
C
PD15
MBRS2040LT3G
pt_smb_h101
/*
+5V_ALW
GND
E
2
pt_r0603
5%
+5V_ALW
C
11
3 D
GND
PR105
47KOhm
5%
GND
1
PD14
VZ0603M260APT
pt_varistor_0603
/*
1
CONFIRM JAY EE
DE-POP
37
AC_OFF
R1
B
E
R2
GND
REQUEST TO
3
C
PQ1
DTC115EUA
pt_umt3_rohm_h39
/*
GND
GND
PROJECT: Lanai
5
REVISION
1.2
DATE:
SHEET
59
4
OF
68
DESCRIPTION:
POWER_CONNECTOR
3
<OrgName>
DESIGN ENGINEER :
JEFF
RELEASE DATE :
2
GM screw pad
D
13G021049200DE
13G021049200DE
H8
C98D98N
H6
H1
H2
H3
H4
C256I138D118
CT315B295I158D118
CRT354X315B394D138
CRT337X413B394D138
O118X98DO118X98N
H7
ESA1-1A_NUT_M2_H2.5_2
13G021052020DE
CPU
H14
H15
RT197X413D91
CT315B394I158D138
CT315B394I158D138
CT295B276I158D138 CT295B276I162D142 CT295B276I162D142 CT295B276DO138X154
H32
H31
H30
ESA1-1A_NUT_M2_H7_2
ESA1-1A_NUT_M2_H7
H13
O47X31DO47X31N
H12
H11
H10
H9
13G021052020DE
H5
13G021052010DE
ESA1-1A_NUT_M2_H8
H20
H33
H21
CT236B217D102
CT236B217D102
CT138B295D118
SATA
H18
H17
13G021049200DE
Header2 13G021052030DE
B
H36
H29
CT315B394I158D138
CT315B394I158D138
crt413x394b394d138
H28
O43X98DO20X75
H27
CRT394X413B394D138
H35
CRT394X413B394D138
H26
ESA1-1A_NUT_H0.4
H34
ESA1-1A_NUT_H0.4
H25
CRT335X386B276D138
H24
H37
O43X98DO20X75
SPRING1
EMI_SPRING_PAD
/*
PROJECT: Lanai
5
REVISION
4
1.2
DATE:
SHEET
60
OF
68
DESCRIPTION:
3
SCREW PAD
DESIGN ENGINEER :
Sean Kuo
RELEASE DATE :
2
ASUS CONFIDENTIAL
MODEL NAME : Elsa
D
Lanai:Modem Board
RJ11 BOARD
WtoB
2P
control signals
Jack
2P
REV : 1.1(DELL: X01)
PROJECT: Lanai
5
REVISION
DATE:
1.2
SHEET
64
4
OF
68
DESCRIPTION:
BLOCK DIAGRAM
3
DESIGN ENGINEER :
Stanly_Hsu
RELEASE DATE :
2
Irat=0.2A
MCON2
1
RJ_TIP
SIDE2 2
RJ_RING
ML1
1
MCON1
470Ohm
2
3
1
RJ_TIP_R
MURATA/BLM18RK471SN1D
RJ_RING_R
MC2
MLCC/+/-10%
pt_c1808_h65
330PF/3KV
P_GND1
NP_NC1
1
2
NP_NC2
P_GND2
MODULAR_JACK_2P
MGND
JOHANSON is
not in the QVL
MH1
C276D165
CT217BDO91X106
MGND
No. 1.
MH2
MURATA/BLM18RK471SN1D
330PF/3KV
2
4
470Ohm
MLCC/+/-10%
pt_c1808_h65
ML2
MC1
Irat=0.2A
RJ_RING
WTOB_CON_2P
MOLEX/53398-0271
RJ_TIP
SIDE1 1
MGND
MGND
PROJECT: Lanai
A
REVISION
DATE:
1.2
SHEET
65
B
OF
68
DESCRIPTION:
RJ-11 CONN
C
<OrgName>
DESIGN ENGINEER :
Stanly_Hsu
RELEASE DATE :
D
ASUS CONFIDENTIAL
1
MODEL NAME : Elsa

PCB NO : ???
ASUS P/N : ???
Lanai PP2 USB Board
REV : 1.1(DELL: X01)
MB PCB
Part Number
DA800004H0L
Description
PCB 00B LA-3071P REV0 M/B
BOM NO. ???

PCB P/N: ???
PROJECT: Lanai
A
REVISION
DATE:
1.2
SHEET
67
B
OF
68
DESCRIPTION:
Cover Page
C
DESIGN ENGINEER :
Terry_Lin
RELEASE DATE :
D
External USB PORT hookup reference. Your design may

need more or less external ports and may be mapped
differently .
USBP0_D-
UICH_USBP01
UL2
90OHM/100MHz
USBP0_D+
/*
UR4
1
1
4
UICH_USBP1-
11
1
3
5
7
9
12
UICH_USBP1UICH_USBP1+
USBP1_D-
UICH_USBP0UICH_USBP0+
UL1
90OHM/100MHz
USBP1_D+
/*
UR1
UR2
NP_NC1
1
2
3
4
5
6
7
8
9
10
NP_NC2
2
4
6
8
10
C244DO134X150
1
UGND
U+USB_SIDE_PWR
UH1
C244D134
1
UGND
BTOB_CON_10P
UICH_USBP1+
UH2
UCON2
2
0Ohm 5%
2
0Ohm 5%
3
UR3
Screw hole
USB daughter board connector
UICH_USBP0+
2
0Ohm 5%
2
0Ohm 5%
UGND
UGND
U+USB_SIDE_PWR
USBP0_DUSBP0_D+
1
UCE1
150UF/6.3V
pt_c7343d_h79
/*
UCE2
150UF/6.3V
pt_c7343d_h79
USB_CON_1X4P
5
6
UC2
0.1UF/10V
MLCC/+/-10%
UGND
1
2
V1+
DATA1_L
DATA1_H
GND1
U+USB_SIDE_PWR
Platforms should put in PADS for the USB chokes if they

have the room. Chokes should be NOPOP.
1
2
3
4
UU1
UGND
6
USBP1_D+
U+USB_SIDE_PWR
UGND
UGND
UCON3
TYCO/1759528-1
U+USB_SIDE_PWR
USBP1_DUSBP1_D+
USBP1_D-
V1+
DATA1_L
DATA1_H
GND1
USBP0_D-
1
2
3
4
SRV05-4
/*
UGND
UC1
0.1UF/10V
MLCC/+/-10%
P_GND1
P_GND2
USB_CON_1X4P
5
6
USBP0_D+
P_GND1
P_GND2
UCON1
TYCO/1759528-1
Place one 150uF cap by each

USB connector
UGND
UGND
Each channel is 1A
4
Consult you ESD Engineer if you think you may need to

add ESD Supression Components to your USB lines.
Add PADS ONLY until proven diodes are really needed.
Place ESD diodes as close as USB connector. Semtech

SRV05-4 can also be used but the Philips IP42220CZ6 have
a lower input C ( 1pf vs 3pf ).
PROJECT: Lanai
A
REVISION
1.2
DATE:
SHEET
68
B
OF
68
DESCRIPTION:
USB PORT ( SINGLE * 2 )

C
<OrgName>
DESIGN ENGINEER :
Terry_Lin
RELEASE DATE :
D

DELL Inspiron 1420 ELSA LANAI UMA Laptop Schematics

Uploaded by

Document Informationclick to expand document information

Copyright:

Available Formats

DELL Inspiron 1420 ELSA LANAI UMA Laptop Schematics

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DELL Inspiron 1420 ELSA LANAI UMA Laptop Schematics

Uploaded by

Copyright:

Available Formats

A

MODEL NAME : Elsa

Lanai UMA Schematics Document

BOM NO. ???

Monday, March 19, 2007

SCHEMATIC FILE NAME :

533/667 MHZ DDR II

533/667 MHZ DDR II

SIM CARD Board

Monday, March 19, 2007

POWER CIRCUIT CHANGE LIST

Schematic Block Diagram

Modem board cover page

Modem board change List

USB board cover page

USB PORT ( SINGLE * 2 )

CPU ( Merom Penryn )

DDRII SO-DIMM( 533MHz 667MHz )

Clock Generator ( CK410M+LP )

LVDS CON & Camera & DMIC

SATA(HDD & CD_ROM)

MEDIA CARD READER / 1394 ( R5C833 )

FLASH & RTC & CAPBTN CONN

TOUCH PAD & BT & CIR & LID

SWITCH & LED

HARDWARE MONITOR ( EMC4001 )

AUDIO CODEC & AMP

Magnetics and RJ-45

Power Control Switch

Power Sequence Logic

Monday, March 19, 2007

SCHEMATIC FILE NAME :

Footprint is 0402 if there is no description

Footprint is 0402 if there is no description

Footprint is 0603 if there is no description

PCI Express TABLE

WWAN / Mini Card

WLAN / Mini Card

WWAN / Mini Card

Note : No USB for WLAN

Monday, March 19, 2007

SCHEMATIC FILE NAME :

Monday, March 19, 2007

SCHEMATIC FILE NAME :

Monday, March 19, 2007

SCHEMATIC FILE NAME :

Place C close to the

For the purpose of testability, route these signals

BSEL2 BSEL1 BSEL0

Voltage Level Shift

Comp0,2 connect with Zo=27.4ohm, Comp1,3

Monday, March 19, 2007

SCHEMATIC FILE NAME :

MEROM CPU (1)

All use 10U 4V (+-20% , X6S , 0805)Pb-Free.

8 inside cavity, north side, secondary layer.

8 inside cavity, south side, secondary layer.

Remove to POWER CIRCUIT .

6 inside cavity, north side, primary layer.