MSP 430 G 2553

MSP430G2x53 MSP430G2x13
www.ti.com SLAS735E APRIL 2011 REVISED JANUARY 2012
MIXED SIGNAL MICROCONTROLLER

1
FEATURES
Low Supply-Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption Active Mode: 230 A at 1 MHz, 2.2 V Standby Mode: 0.5 A Off Mode (RAM Retention): 0.1 A Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 s 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations Internal Frequencies up to 16 MHz With Four Calibrated Frequency Internal Very-Low-Power Low-Frequency (LF) Oscillator 32-kHz Crystal External Digital Clock Source Two 16-Bit Timer_A With Three Capture/Compare Registers Up to 24 Touch-Sense-Enabled I/O Pins Universal Serial Communication Interface (USCI) Enhanced UART Supporting Auto Baudrate Detection (LIN) IrDA Encoder and Decoder Synchronous SPI I2C On-Chip Comparator for Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion 10-Bit 200-ksps Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan (See Table 1) Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse On-Chip Emulation Logic With Spy-Bi-Wire Interface Family Members are Summarized in Table 1 Package Options TSSOP: 20 Pin, 28 Pin PDIP: 20 Pin QFN: 32 Pin For Complete Module Descriptions, See the MSP430x2xx Family Users Guide (SLAU144)
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s. The MSP430G2x13 and MSP430G2x53 series are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, up to 24 I/O touch-sense-enabled pins, a versatile analog comparator, and built-in communication capability using the universal serial communication interface. In addition the MSP430G2x53 family members have a 10-bit analog-to-digital (A/D) converter. For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 20112012, Texas Instruments Incorporated
SLAS735E APRIL 2011 REVISED JANUARY 2012 www.ti.com
Table 1. Available Options (1) (2)

Device MSP430G2553IRHB32 MSP430G2553IPW28 MSP430G2553IPW20 MSP430G2553IN20 MSP430G2453IRHB32 MSP430G2453IPW28 MSP430G2453IPW20 MSP430G2453IN20 MSP430G2353IRHB32 MSP430G2353IPW28 MSP430G2353IPW20 MSP430G2353IN20 MSP430G2253IRHB32 MSP430G2253IPW28 MSP430G2253IPW20 MSP430G2253IN20 MSP430G2153IRHB32 MSP430G2153IPW28 MSP430G2153IPW20 MSP430G2153IN20 MSP430G2513IRHB32 MSP430G2513IPW28 MSP430G2513IPW20 MSP430G2513IN20 MSP430G2413IRHB32 MSP430G2413IPW28 MSP430G2413IPW20 MSP430G2413IN20 MSP430G2313IRHB32 MSP430G2313IPW28 MSP430G2313IPW20 MSP430G2313IN20 MSP430G2213IRHB32 MSP430G2213IPW28 MSP430G2213IPW20 MSP430G2213IN20 MSP430G2113IRHB32 MSP430G2113IPW28 MSP430G2113IPW20 MSP430G2113IN20 (1) (2) 1 1 1 256 2x TA3 8 1 LF, DCO, VLO 1 1 2 256 2x TA3 8 1 LF, DCO, VLO 1 1 4 256 2x TA3 8 1 LF, DCO, VLO 1 1 8 512 2x TA3 8 1 LF, DCO, VLO 1 1 16 512 2x TA3 8 1 LF, DCO, VLO 1 1 1 256 2x TA3 8 8 1 LF, DCO, VLO 1 1 2 256 2x TA3 8 8 1 LF, DCO, VLO 1 1 4 256 2x TA3 8 8 1 LF, DCO, VLO 1 1 8 512 2x TA3 8 8 1 LF, DCO, VLO 1 1 16 512 2x TA3 8 8 1 LF, DCO, VLO BSL EEM Flash (KB) RAM (B) Timer_A COMP_A+ Channel ADC10 Channel USCI A0/B0 Clock I/O 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 Package Type 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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Device Pinout, MSP430G2x13 and MSP430G2x53, 20-Pin Devices, TSSOP and PDIP
DVCC P1.0/TA0CLK/ACLK/A0/CA0 P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1 P1.2/TA0.1/UCA0TXD/PUCA0SIMO/A2/CA2 P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1
1 2 3 4 5 6 7 8 9 10
20 19 18 17
N20 PW20 (TOP VIEW)
16 15 14 13 12 11
DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK P2.5/TA1.2 P2.4/TA1.2 P2.3/TA1.0
NOTE: ADC10 is available on MSP430G2x53 devices only. NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.
Device Pinout, MSP430G2x13 and MSP430G2x53, 28-Pin Devices, TSSOP
DVCC P1.0/TA0CLK/ACLK/A0/CA0 P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1 P1.2/TA0.1/UCA0TXD/PUCA0SIMO/A2/CA2 P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS P3.1/TA1.0 P3.0/TA0.2 P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P3.2/TA1.1 P3.3/TA1.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
PW28 (TOP VIEW)
22 21 20 19 18 17 16 15
DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK P3.7/TA1CLK/CAOUT P3.6/TA0.2 P3.5/TA0.1 P2.5/TA1.2 P2.4/TA1.2 P2.3/TA1.0 P3.4/TA0.0
NOTE: ADC10 is available on MSP430G2x53 devices only.
Device Pinout, MSP430G2x13 and MSP430G2x53, 32-Pin Devices, QFN

NC P1.0/TA0CLK/ACLK/A0/CA0 DVCC AVCC DVSS AVSS XIN/P2.6/TA0.1 XOUT/P2.7
32 31 30 29 28 27 26 25
P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1 P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2 P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS P3.1/TA1.0 P3.0/TA0.2 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22
RHB32 (TOP VIEW)
21 20 19 18 17
TEST/SBWTCK RST/NMI/SBWTDIO P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK P3.7/TA1CLK/CAOUT P3.6/TA0.2 P3.5/TA0.1 P2.5/TA1.2
NOTE: ADC10 is available on MSP430G2x53 devices only.
P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P3.2/TA1.1 P3.3/TA1.2 P3.4/TA0.0 P2.3/TA1.0 P2.4/TA1.2
Functional Block Diagram, MSP430G2x53

XIN XOUT DVCC DVSS P1.x 8 P2.x 8 P3.x 8
ACLK Clock System MCLK Flash SMCLK 16KB 8KB 4KB 2KB MAB MDB RAM 512B 256B 10-Bit 8 Ch. Autoscan 1 ch DMA ADC Port P1 8 I/O Interrupt capability pullup/down resistors Port P2 8 I/O Interrupt capability pullup/down resistors Port P3 8 I/O pullup/ pulldown resistors
16MHz CPU incl. 16 Registers
Emulation 2BP JTAG Interface Spy-BiWire RST/NMI Brownout Protection
Comp_A+ 8 Channels
Watchdog WDT+ 15-Bit
Timer0_A3 3 CC Registers
USCI A0 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
Functional Block Diagram, MSP430G2x13

XIN XOUT DVCC DVSS P1.x 8 P2.x 8 P3.x 8
ACLK Clock System MCLK SMCLK Flash RAM 16KB 8KB 4KB 2KB MAB MDB 512B 256B Port P1 8 I/O Interrupt capability pullup/down resistors Port P2 8 I/O Interrupt capability pullup/down resistors Port P3 8 I/O pullup/ pulldown resistors
16MHz CPU incl. 16 Registers
Emulation 2BP JTAG Interface Spy-BiWire RST/NMI Brownout Protection
Comp_A+ 8 Channels
Watchdog WDT+ 15-Bit
USCI A0 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
Table 2. Terminal Functions

TERMINAL NO. NAME P1.0/ TA0CLK/ ACLK/ A0 CA0 P1.1/ TA0.0/ UCA0RXD/ UCA0SOMI/ A1/ CA1 P1.2/ TA0.1/ UCA0TXD/ UCA0SIMO/ A2/ CA2 P1.3/ ADC10CLK/ A3/ VREF-/VEREF-/ CA3/ CAOUT P1.4/ SMCLK/ UCB0STE/ UCA0CLK/ A4/ VREF+/VEREF+/ CA4/ TCK P1.5/ TA0.0/ UCB0CLK/ UCA0STE/ A5/ CA5/ TMS 7 7 5 I/O 6 6 4 I/O 5 5 3 I/O 4 4 2 I/O 3 3 1 I/O 2 2 31 I/O PW20, N20 PW28 RHB32 General-purpose digital I/O pin Timer0_A, clock signal TACLK input ACLK signal output ADC10 analog input A0 (1) Comparator_A+, CA0 input General-purpose digital I/O pin Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit USCI_A0 receive data input in UART mode, USCI_A0 slave data out/master in SPI mode ADC10 analog input A1 (1) Comparator_A+, CA1 input General-purpose digital I/O pin Timer0_A, capture: CCI1A input, compare: Out1 output USCI_A0 transmit data output in UART mode, USCI_A0 slave data in/master out in SPI mode, ADC10 analog input A2 (1) Comparator_A+, CA2 input General-purpose digital I/O pin ADC10, conversion clock output (1) ADC10 analog input A3 (1) ADC10 negative reference voltage Comparator_A+, CA3 input Comparator_A+, output General-purpose digital I/O pin SMCLK signal output USCI_B0 slave transmit enable USCI_A0 clock input/output ADC10 analog input A4 (1) ADC10 positive reference voltage (1) Comparator_A+, CA4 input JTAG test clock, input terminal for device programming and test General-purpose digital I/O pin Timer0_A, compare: Out0 output / BSL receive USCI_B0 clock input/output, USCI_A0 slave transmit enable ADC10 analog input A5 (1) Comparator_A+, CA5 input JTAG test mode select, input terminal for device programming and test
(1)
I/O
DESCRIPTION
(1) 6
MSP430G2x53 devices only Submit Documentation Feedback

Table 2. Terminal Functions (continued)

TERMINAL NO. NAME P1.6/ TA0.1/ A6/ CA6/ UCB0SOMI/ UCB0SCL/ TDI/TCLK P1.7/ A7/ CA7/ CAOUT/ UCB0SIMO/ UCB0SDA/ TDO/TDI P2.0/ TA1.0 P2.1/ TA1.1 P2.2/ TA1.1 P2.3/ TA1.0 P2.4/ TA1.2 P2.5/ TA1.2 XIN/ P2.6/ TA0.1 XOUT/ P2.7 P3.0/ TA0.2 P3.1/ TA1.0 P3.2/ TA1.1 P3.3/ TA1.2 P3.4/ TA0.0 18 26 9 8 13 14 15 25 7 6 12 13 14 I/O I/O I/O I/O I/O I/O 19 27 26 I/O 15 23 22 I/O 14 22 21 I/O PW20, N20 PW28 RHB32 General-purpose digital I/O pin Timer0_A, compare: Out1 output ADC10 analog input A6 (1) Comparator_A+, CA6 input USCI_B0 slave out/master in SPI mode, USCI_B0 SCL I2C clock in I2C mode JTAG test data input or test clock input during programming and test General-purpose digital I/O pin ADC10 analog input A7 (1) Comparator_A+, CA7 input Comparator_A+, output USCI_B0 slave in/master out in SPI mode USCI_B0 SDA I2C data in I2C mode JTAG test data output terminal or test data input during programming and test (2) 8 9 10 11 12 13 10 11 12 16 17 18 9 10 11 15 16 17 I/O I/O I/O I/O I/O I/O General-purpose digital I/O pin Timer1_A, capture: CCI0A input, compare: Out0 output General-purpose digital I/O pin Timer1_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin Timer1_A, capture: CCI1B input, compare: Out1 output General-purpose digital I/O pin Timer1_A, capture: CCI0B input, compare: Out0 output General-purpose digital I/O pin Timer1_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin Timer1_A, capture: CCI2B input, compare: Out2 output Input terminal of crystal oscillator General-purpose digital I/O pin Timer0_A, compare: Out1 output Output terminal of crystal oscillator (3) General-purpose digital I/O pin General-purpose digital I/O pin Timer0_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin Timer1_A, compare: Out0 output General-purpose digital I/O pin Timer1_A, compare: Out1 output General-purpose digital I/O Timer1_A, compare: Out2 output General-purpose digital I/O Timer0_A, compare: Out0 output I/O DESCRIPTION
(2) (3)
TDO or TDI is selected via JTAG instruction. If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Submit Documentation Feedback 7
Table 2. Terminal Functions (continued)

TERMINAL NO. NAME P3.5/ TA0.1 P3.6/ TA0.2 P3.7/ TA1CLK/ CAOUT RST/ NMI/ SBWTDIO TEST/ 17 SBWTCK AVCC DVCC DVSS NC QFN Pad NA 1 20 NA NA NA 1 28 NA NA 29 30 27, 28 8, 32 Pad NA NA NA NA NA 25 24 I 16 24 23 I 21 20 I/O PW20, N20 PW28 19 20 RHB32 18 19 I/O I/O General-purpose digital I/O Timer0_A, compare: Out1 output General-purpose digital I/O Timer0_A, compare: Out2 output General-purpose digital I/O Timer1_A, clock signal TACLK input Comparator_A+, output Reset Nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test Analog supply voltage Digital supply voltage Ground reference Not connected QFN package pad. Connection to VSS is recommended. I/O DESCRIPTION
SHORT-FORM DESCRIPTION CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Instruction Set
The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 3 shows examples of the three types of instruction formats; Table 4 shows the address modes.
Table 3. Instruction Word Formats

INSTRUCTION FORMAT Dual operands, source-destination Single operands, destination only Relative jump, un/conditional EXAMPLE ADD R4,R5 CALL R8 JNE OPERATION R4 + R5 ---> R5 PC -->(TOS), R8--> PC Jump-on-equal bit = 0
Table 4. Address Mode Descriptions (1)

ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate (1) S = source, D = destination S D SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV &MEM,&TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 -- --> R11 M(2+R5) -- --> M(6+R6) M(EDE) -- --> M(TONI) M(MEM) -- --> M(TCDAT) M(R10) -- --> M(Tab+R6) M(R10) -- --> R11 R10 + 2-- --> R10 #45 -- --> M(TONI)
Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: Active mode (AM) All clocks are active Low-power mode 0 (LPM0) CPU is disabled ACLK and SMCLK remain active, MCLK is disabled Low-power mode 1 (LPM1) CPU is disabled ACLK and SMCLK remain active, MCLK is disabled DCO's dc generator is disabled if DCO not used in active mode Low-power mode 2 (LPM2) CPU is disabled MCLK and SMCLK are disabled DCO's dc generator remains enabled ACLK remains active Low-power mode 3 (LPM3) CPU is disabled MCLK and SMCLK are disabled DCO's dc generator is disabled ACLK remains active Low-power mode 4 (LPM4) CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO's dc generator is disabled Crystal oscillator is stopped
10
Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the CPU goes into LPM4 immediately after power-up. Table 5. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE Power-Up External Reset Watchdog Timer+ Flash key violation PC out-of-range (1) NMI Oscillator fault Flash memory access violation Timer1_A3 Timer1_A3 Comparator_A+ Watchdog Timer+ Timer0_A3 Timer0_A3 USCI_A0/USCI_B0 receive USCI_B0 I2C status USCI_A0/USCI_B0 transmit USCI_B0 I2C receive/transmit ADC10 (MSP430G2x53 only) I/O Port P2 (up to eight flags) I/O Port P1 (up to eight flags) INTERRUPT FLAG PORIFG RSTIFG WDTIFG KEYV (2) NMIIFG OFIFG ACCVIFG (2) (3) TA1CCR0 CCIFG (4) TA1CCR2 TA1CCR1 CCIFG, TAIFG (2) (4) CAIFG
(4)
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Reset
0FFFEh
31, highest
(non)-maskable (non)-maskable (non)-maskable maskable maskable maskable maskable

(4)
0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 to 0, lowest
WDTIFG TA0CCR0 CCIFG

(5) (4)
maskable maskable maskable maskable maskable
TA0CCR2 TA0CCR1 CCIFG, TAIFG UCA0RXIFG, UCB0RXIFG (2) (5) UCA0TXIFG, UCB0TXIFG ADC10IFG (4)
(2) (6)
P2IFG.0 to P2IFG.7
(2) (4)
maskable maskable
0FFE6h 0FFE4h 0FFE2h 0FFE0h
P1IFG.0 to P1IFG.7 (2) (4)
See See (1) (2) (3) (4) (5) (6) (7) (8)
(7) (8)
0FFDEh 0FFDEh to 0FFC0h
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges. Multiple source flags (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Interrupt flags are located in the module. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG. This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary.
11
Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.
Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written. It is reset or set by POR. SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2

Address 00h 7 6 5 ACCVIE rw-0 WDTIE OFIE NMIIE ACCVIE Address 01h 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable 7 6 5 4 3 UCB0TXIE rw-0 2 UCB0RXIE rw-0 1 UCA0TXIE rw-0 0 UCA0RXIE rw-0
UCA0RXIE UCA0TXIE UCB0RXIE UCB0TXIE
USCI_A0 receive interrupt enable USCI_A0 transmit interrupt enable USCI_B0 receive interrupt enable USCI_B0 transmit interrupt enable
Table 7. Interrupt Flag Register 1 and 2

Address 02h 7 6 5 4 NMIIFG rw-0 WDTIFG OFIFG PORIFG RSTIFG NMIIFG Address 03h 3 RSTIFG rw-(0) 2 PORIFG rw-(1) 1 OFIFG rw-1 0 WDTIFG rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault. Power-On Reset interrupt flag. Set on VCC power-up. External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up. Set via RST/NMI pin 7 6 5 4 3 UCB0TXIFG rw-1 2 UCB0RXIFG rw-0 1 UCA0TXIFG rw-1 0 UCA0RXIFG rw-0
UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG
USCI_A0 receive interrupt flag USCI_A0 transmit interrupt flag USCI_B0 receive interrupt flag USCI_B0 transmit interrupt flag
12
Memory Organization
Table 8. Memory Organization
MSP430G2153 MSP430G2113 Memory Main: interrupt vector Main: code memory Information memory Size Flash Flash Size Flash RAM Size 1kB 0xFFFF to 0xFFC0 0xFFFF to 0xFC00 256 Byte 010FFh to 01000h 256 Byte 0x02FF to 0x0200 Peripherals 16-bit 8-bit 8-bit SFR 01FFh to 0100h 0FFh to 010h 0Fh to 00h MSP430G2253 MSP430G2213 2kB 0xFFFF to 0xFFC0 0xFFFF to 0xF800 256 Byte 010FFh to 01000h 256 Byte 0x02FF to 0x0200 01FFh to 0100h 0FFh to 010h 0Fh to 00h MSP430G2353 MSP430G2313 4kB 0xFFFF to 0xFFC0 0xFFFF to 0xF000 256 Byte 010FFh to 01000h 256 Byte 0x02FF to 0x0200 01FFh to 0100h 0FFh to 010h 0Fh to 00h MSP430G2453 MSP430G2413 8kB 0xFFFF to 0xFFC0 0xFFFF to 0xE000 256 Byte 010FFh to 01000h 512 Byte 0x03FF to 0x0200 01FFh to 0100h 0FFh to 010h 0Fh to 00h MSP430G2553 MSP430G2513 16kB 0xFFFF to 0xFFC0 0xFFFF to 0xC000 256 Byte 010FFh to 01000h 512 Byte 0x03FF to 0x0200 01FFh to 0100h 0FFh to 010h 0Fh to 00h
Bootstrap Loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319). Table 9. BSL Function Pins
BSL FUNCTION Data transmit Data receive 20-PIN PW PACKAGE 20-PIN N PACKAGE 3 - P1.1 7 - P1.5 28-PIN PACKAGE PW 3 - P1.1 7 - P1.5 32-PIN PACKAGE RHB 1 - P1.1 5 - P1.5
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. Segments 0 to n may be erased in one step, or each segment may be individually erased. Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also called information memory. Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.
13
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144). Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 s. The basic clock module provides the following clock signals: Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator. Main clock (MCLK), the system clock used by the CPU. Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A. Main DCO Characteristics All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage = 32 fDCO(RSEL,DCO) fDCO(RSEL,DCO+1) MOD fDCO(RSEL,DCO) + (32 MOD) fDCO(RSEL,DCO+1)
14
Calibration Data Stored in Information Memory Segment A Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure. Table 10. Tags Used by the ADC Calibration Tags
NAME TAG_DCO_30 TAG_ADC10_1 TAG_EMPTY ADDRESS 0x10F6 0x10DA VALUE 0x01 0x10 0xFE ADC10_1 calibration tag Identifier for empty memory areas DESCRIPTION DCO frequency calibration at VCC = 3 V and TA = 30C at calibration
Table 11. Labels Used by the ADC Calibration Tags

LABEL CAL_ADC_25T85 CAL_ADC_25T30 CAL_ADC_25VREF_FACTOR CAL_ADC_15T85 CAL_ADC_15T30 CAL_ADC_15VREF_FACTOR CAL_ADC_OFFSET CAL_ADC_GAIN_FACTOR CAL_BC1_1MHZ CAL_DCO_1MHZ CAL_BC1_8MHZ CAL_DCO_8MHZ CAL_BC1_12MHZ CAL_DCO_12MHZ CAL_BC1_16MHZ CAL_DCO_16MHZ ADDRESS OFFSET 0x0010 0x000E 0x000C 0x000A 0x0008 0x0006 0x0004 0x0002 0x0009 0x0008 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002 SIZE word word word word word word word word byte byte byte byte byte byte byte byte CONDITION AT CALIBRATION / DESCRIPTION INCHx = 0x1010, REF2_5 = 1, TA = 85C INCHx = 0x1010, REF2_5 = 1, TA = 30C REF2_5 = 1, TA = 30C, IVREF+ = 1 mA INCHx = 0x1010, REF2_5 = 0, TA = 85C INCHx = 0x1010, REF2_5 = 0, TA = 30C REF2_5 = 0, TA = 30C, IVREF+ = 0.5 mA External VREF = 1.5 V, fADC10CLK = 5 MHz External VREF = 1.5 V, fADC10CLK = 5 MHz -
Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. Digital I/O Up to three 8-bit I/O ports are implemented: All individual I/O bits are independently programmable. Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible. Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available). Read/write access to port-control registers is supported by all instructions. Each I/O has an individually programmable pullup/pulldown resistor. Each I/O has an individually programmable pin oscillator enable bit to enable low-cost touch sensing. WDT+ Watchdog Timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.
15
Timer_A3 (TA0, TA1) Timer0/1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 12. Timer0_A3 Signal Connections
INPUT PIN NUMBER PW20, N20 P1.0-2 PW28 P1.0-2 RHB32 P1.0-31 DEVICE INPUT SIGNAL TACLK ACLK SMCLK PinOsc P1.1-3 PinOsc P1.1-3 PinOsc P1.1-1 TACLK TA0.0 ACLK VSS VCC P1.2-4 P1.2-4 P1.2-2 TA0.1 CAOUT VSS VCC P3.0-9 PinOsc PinOsc P3.0-7 PinOsc TA0.2 TA0.2 VSS VCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 CCR1 TA1 P1.2-4 P1.6-14 P2.6-19 P1.2-4 P1.6-22 P2.6-27 P3.5-19 P3.0-9 P3.6-20 P1.2-2 P1.6-21 P2.6-26 P3.5-18 P3.0-7 P3.6-19 CCR0 TA0 P1.1-3 P1.5-7 P1.1-3 P1.5-7 P3.4-15 P1.1-1 P1.5-5 P3.4-14 Timer NA MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER PW20, N20 PW28 RHB32
Table 13. Timer1_A3 Signal Connections

INPUT PIN NUMBER PW20, N20 PW28 P3.7-21 RHB32 P3.7-20 DEVICE INPUT SIGNAL TACLK ACLK SMCLK P2.0-8 P2.3-11 P3.7-21 P2.0-10 P2.3-16 P3.7-20 P2.0-9 P2.3-12 TACLK TA1.0 TA1.0 VSS VCC P2.1-9 P2.2-10 P2.1-11 P2.2-12 P2.1-10 P2.2-11 TA1.1 TA1.1 VSS VCC P2.4-12 P2.5-13 P2.4-17 P2.5-18 P2.4-16 P2.5-17 TA1.2 TA1.2 VSS VCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 P2.4-12 P2.5-13 P2.4-17 P2.5-18 P3.3-14 P2.4-16 P2.5-17 P3.3-13 CCR1 TA1 P2.1-9 P2.2-10 P2.1-11 P2.2-12 P3.2-13 P2.1-10 P2.2-11 P3.2-12 CCR0 TA0 P2.0-8 P2.3-11 P2.0-10 P2.3-16 P3.1-8 P2.0-9 P2.3-15 P3.1-6 Timer NA MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER PW20, N20 PW28 RHB32
16
Universal Serial Communications Interface (USCI) The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. Not all packages support the USCI functionality. USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. USCI_B0 provides support for SPI (3 or 4 pin) and I2C. Comparator_A+ The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. ADC10 (MSP430G2x53 Only) The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention.
17
Peripheral File Map Table 14. Peripherals With Word Access

MODULE ADC10 (MSP430G2x53 devices only) REGISTER DESCRIPTION ADC data transfer start address ADC memory ADC control register 1 ADC control register 0 Timer1_A3 Capture/compare register Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector Timer0_A3 Capture/compare register Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector Flash Memory Flash control 3 Flash control 2 Flash control 1 Watchdog Timer+ Watchdog/timer control REGISTER NAME ADC10SA ADC10MEM ADC10CTL1 ADC10CTL0 TA1CCR2 TA1CCR1 TA1CCR0 TA1R TA1CCTL2 TA1CCTL1 TA1CCTL0 TA1CTL TA1IV TA0CCR2 TA0CCR1 TA0CCR0 TA0R TA0CCTL2 TA0CCTL1 TA0CCTL0 TA0CTL TA0IV FCTL3 FCTL2 FCTL1 WDTCTL OFFSET 1BCh 1B4h 1B2h 1B0h 0196h 0194h 0192h 0190h 0186h 0184h 0182h 0180h 011Eh 0176h 0174h 0172h 0170h 0166h 0164h 0162h 0160h 012Eh 012Ch 012Ah 0128h 0120h
18
Table 15. Peripherals With Byte Access

MODULE USCI_B0 REGISTER DESCRIPTION USCI_B0 transmit buffer USCI_B0 receive buffer USCI_B0 status USCI B0 I2C Interrupt enable USCI_B0 bit rate control 1 USCI_B0 bit rate control 0 USCI_B0 control 1 USCI_B0 control 0 USCI_B0 I2C slave address USCI_B0 I2C own address USCI_A0 USCI_A0 transmit buffer USCI_A0 receive buffer USCI_A0 status USCI_A0 modulation control USCI_A0 baud rate control 1 USCI_A0 baud rate control 0 USCI_A0 control 1 USCI_A0 control 0 USCI_A0 IrDA receive control USCI_A0 IrDA transmit control USCI_A0 auto baud rate control ADC10 (MSP430G2x53 devices only) ADC analog enable 0 ADC analog enable 1 ADC data transfer control register 1 ADC data transfer control register 0 Comparator_A+ Comparator_A+ port disable Comparator_A+ control 2 Comparator_A+ control 1 Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control Port P3 (28-pin PW and 32-pin RHB only) Port P3 selection 2. pin Port P3 resistor enable Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 Port P2 selection 2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input
REGISTER NAME UCB0TXBUF UCB0RXBUF UCB0STAT UCB0CIE UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 UCB0SA UCB0OA UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL1 UCA0CTL0 UCA0IRRCTL UCA0IRTCTL UCA0ABCTL ADC10AE0 ADC10AE1 ADC10DTC1 ADC10DTC0 CAPD CACTL2 CACTL1 BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL P3SEL2 P3REN P3SEL P3DIR P3OUT P3IN P2SEL2 P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN
OFFSET 06Fh 06Eh 06Dh 06Ch 06Bh 06Ah 069h 068h 011Ah 0118h 067h 066h 065h 064h 063h 062h 061h 060h 05Fh 05Eh 05Dh 04Ah 04Bh 049h 048h 05Bh 05Ah 059h 053h 058h 057h 056h 043h 010h 01Bh 01Ah 019h 018h 042h 02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 19
Table 15. Peripherals With Byte Access (continued)

MODULE Port P1 REGISTER DESCRIPTION Port P1 selection 2 Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 REGISTER NAME P1SEL2 P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN IFG2 IFG1 IE2 IE1 OFFSET 041h 027h 026h 025h 024h 023h 022h 021h 020h 003h 002h 001h 000h
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Absolute Maximum Ratings (1)

Voltage applied at VCC to VSS Voltage applied to any pin (2) Diode current at any device pin Storage temperature range, Tstg (1) (2) (3)
(3)
0.3 V to 4.1 V 0.3 V to VCC + 0.3 V 2 mA Unprogrammed device Programmed device 55C to 150C 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions

MIN During program execution VCC VSS TA Supply voltage Supply voltage Operating free-air temperature I version VCC = 1.8 V, Duty cycle = 50% 10% fSYSTEM Processor frequency (maximum MCLK frequency using the USART module) (1) (2) VCC = 2.7 V, Duty cycle = 50% 10% VCC = 3.3 V, Duty cycle = 50% 10% (1) (2) 40 dc dc dc During flash programming/erase 1.8 2.2 0 85 6 12 16 MHz NOM MAX 3.6 3.6 V V C UNIT
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend : 16 MHz
System Frequency - MHz
Supply voltage range , during flash memory programming 12 MHz Supply voltage range , during program execution 6 MHz
1.8 V
2.7 V 2.2 V Supply Voltage - V
3.3 V 3.6 V
Note:
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Safe Operating Area
21
Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER TEST CONDITIONS fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 0 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 TA VCC 2.2 V MIN TYP 230 A MAX UNIT
IAM,1MHz
Active mode (AM) current at 1 MHz
3V
330
420
(1) (2)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics, Active Mode Supply Current (Into VCC)

5.0 4.0
4.0 Active Mode Current mA
f DCO = 16 MHz Active Mode Current mA 3.0
TA = 85 C TA = 25 C
3.0 f DCO = 12 MHz 2.0
2.0
VCC = 3 V TA = 85 C TA = 25 C
1.0
f DCO = 8 MHz f DCO = 1 MHz
1.0 VCC = 2.2 V 0.0 0.0
0.0 1.5
2.0
2.5
3.0
3.5
4.0
4.0
8.0
12.0
16.0
VCC Supply Voltage V
f DCO DCO Frequency MHz
Figure 2. Active Mode Current vs VCC, TA = 25C
Figure 3. Active Mode Current vs DCO Frequency
22
Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 TA VCC MIN
(2)
TYP
MAX
UNIT
ILPM0,1MHz
Low-power mode 0 (LPM0) current (3)
25C
2.2 V
56
ILPM2
25C
2.2 V
22
ILPM3,LFXT1
25C
2.2 V
0.7
1.5
ILPM3,VLO
Low-power mode 3 current, (LPM3) (4)
25C 25C 85C
2.2 V
0.5 0.1
0.7 0.5 1.7
ILPM4
2.2 V
0.8
(1) (2) (3) (4) (5)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included.
Typical Characteristics, Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
3.00 2.75
2.50
ILPM3 Low-Power Mode Current A
2.50 2.25 2.00 1.75 1.50 1.25 Vcc = 3 V 1.00 0.75 0.50 0.25 0.00 -40 -20 0 20 40 Vcc = 1.8 V Vcc = 2.2 V Vcc = 3.6 V
ILPM4 Low-Power Mode Current A
2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00 -40 Vcc = 1.8 V -20 0 20 40 60 80 Vcc = 3.6 V Vcc = 3 V Vcc = 2.2 V
60
80
TA Temperature C
TA Temperature C
Figure 4. LPM3 Current vs Temperature
Figure 5. LPM4 Current vs Temperature
23
Schmitt-Trigger Inputs, Ports Px

PARAMETER VIT+ VIT Vhys RPull CI Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ VIT) Pullup/pulldown resistor Input capacitance For pullup: VIN = VSS For pulldown: VIN = VCC VIN = VSS or VCC TEST CONDITIONS VCC 3V 3V 3V 3V MIN 0.45 VCC 1.35 0.25 VCC 0.75 0.3 20 35 5 TYP MAX 0.75 VCC 2.25 0.55 VCC 1.65 1 50 UNIT V V V k pF
Leakage Current, Ports Px

PARAMETER Ilkg(Px.y) (1) (2) High-impedance leakage current
(1) (2)
TEST CONDITIONS
VCC 3V
MIN
MAX 50
UNIT nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.
Outputs, Ports Px
PARAMETER VOH VOL (1) High-level output voltage Low-level output voltage TEST CONDITIONS I(OHmax) = 6 mA (1) I(OLmax) = 6 mA (1) VCC 3V 3V MIN TYP VCC 0.3 VSS + 0.3 MAX UNIT V V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed 48 mA to hold the maximum voltage drop specified.
Output Frequency, Ports Px

PARAMETER fPx.y fPort_CLK (1) (2) Port output frequency (with load) Clock output frequency TEST CONDITIONS Px.y, CL = 20 pF, RL = 1 k Px.y, CL = 20 pF (2)
(1) (2)
VCC 3V 3V
MIN
TYP 12 16
MAX
UNIT MHz MHz
A resistive divider with two 0.5-k resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics, Outputs

TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
30 I OL Typical Low-Level Output Current mA I OL Typical Low-Level Output Current mA VCC = 2.2 V P1.7 25 TA = 85C TA = 25C 50 VCC = 3 V P1.7 40 TA = 85C 30 TA = 25C
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
20
15
20
10
10
0 0 0.5 1 1.5 2 2.5 VOL Low-Level Output Voltage V
0 0 0.5 1 1.5 2 2.5 3 3.5 VOL Low-Level Output Voltage V
Figure 6. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE

0 I OH Typical High-Level Output Current mA I OH Typical High-Level Output Current mA VCC = 2.2 V P1.7 5 0 VCC = 3 V P1.7 10
Figure 7. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
10
20
15 TA = 85C 20
30 TA = 85C 40 TA = 25C 50 0 0.5 1 1.5 2 2.5 3 3.5
25 0
TA = 25C 0.5 1 1.5 2 2.5 VOH High-Level Output Voltage V
VOH High-Level Output Voltage V
Figure 8.
Figure 9.
25
Pin-Oscillator Frequency Ports Px

PARAMETER foP1.x foP2.x foP2.6/7 foP3.x (1) (2) Port output oscillation frequency Port output oscillation frequency Port output oscillation frequency Port output oscillation frequency TEST CONDITIONS P1.y, CL = 10 pF, RL = 100 k
(1) (2)
VCC 3V
MIN
TYP 1400 900 1800 1000 700 1800 1000
MAX
UNIT kHz kHz kHz kHz
P1.y, CL = 20 pF, RL = 100 k (1) (2) P2.0 to P2.5, CL = 10 pF, RL = 100 k (1) (2) P2.0 to P2.5, CL = 20 pF, RL = 100 k (1) (2) P2.6 and P2.7, CL = 20 pF, RL = 100 k (1) (2) P3.y, CL = 10 pF, RL = 100 k P3.y, CL = 20 pF, RL = 100 k
(1) (2) (1) (2)
3V 3V
A resistive divider with two 0.5-k resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Typical Characteristics, Pin-Oscillator Frequency

TYPICAL OSCILLATING FREQUENCY vs LOAD CAPACITANCE
1.50 fosc Typical Oscillation Frequency MHz 1.35 1.20 1.05 0.90 0.75 0.60 0.45 0.30 0.15 0.00 10 50 100 CLOAD External Capacitance pF P1.y P2.0 ... P2.5 P2.6, P2.7 fosc Typical Oscillation Frequency MHz VCC = 3.0 V 1.50 1.35 1.20 1.05 0.90 0.75 0.60 0.45 0.30 0.15 0.00 10 50 100 CLOAD External Capacitance pF P1.y P2.0 ... P2.5 P2.6, P2.7 VCC = 2.2 V
TYPICAL OSCILLATING FREQUENCY vs LOAD CAPACITANCE
A. One output active at a time. Figure 10.
A. One output active at a time. Figure 11.
26
POR/Brownout Reset (BOR) (1)

PARAMETER VCC(start) V(B_IT) Vhys(B_IT) td(BOR) t(reset) (1) See Figure 12 See Figure 12 through Figure 14 See Figure 12 See Figure 12 Pulse length needed at RST/NMI pin to accepted reset internally 2.2 V 2 TEST CONDITIONS dVCC/dt 3 V/s dVCC/dt 3 V/s dVCC/dt 3 V/s VCC MIN TYP 0.7 V(B_IT--) 1.35 140 2000 MAX UNIT V V mV s s
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT) + Vhys(B_IT)is 1.8 V.
VCC Vhys(B_IT) V(B_IT) VCC(start)
0 t d(BOR)
Figure 12. POR/Brownout Reset (BOR) vs Supply Voltage
27
Typical Characteristics, POR/Brownout Reset (BOR)

2 VCC = 3 V Typical Conditions VCC(drop) V 1.5 1 0.5 0 0.001 VCC(drop) VCC 3V t pw
1 t pw Pulse Width s
1000 1 ns 1 ns t pw Pulse Width s
Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC 2 VCC = 3 V VCC(drop) V 1.5 1 VCC(drop) 0.5 0 0.001 t f = tr 1 t pw Pulse Width s 1000 tf tr Typical Conditions 3V t pw
t pw Pulse Width s
Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
28
DCO Frequency
PARAMETER RSELx < 14 VCC fDCO(0,0) fDCO(0,3) fDCO(1,3) fDCO(2,3) fDCO(3,3) fDCO(4,3) fDCO(5,3) fDCO(6,3) fDCO(7,3) fDCO(8,3) fDCO(9,3) fDCO(10,3) fDCO(11,3) fDCO(12,3) fDCO(13,3) fDCO(14,3) fDCO(15,3) fDCO(15,7) SRSEL SDCO Supply voltage DCO frequency (0, 0) DCO frequency (0, 3) DCO frequency (1, 3) DCO frequency (2, 3) DCO frequency (3, 3) DCO frequency (4, 3) DCO frequency (5, 3) DCO frequency (6, 3) DCO frequency (7, 3) DCO frequency (8, 3) DCO frequency (9, 3) DCO frequency (10, 3) DCO frequency (11, 3) DCO frequency (12, 3) DCO frequency (13, 3) DCO frequency (14, 3) DCO frequency (15, 3) DCO frequency (15, 7) Frequency step between range RSEL and RSEL+1 Frequency step between tap DCO and DCO+1 Duty cycle RSELx = 14 RSELx = 15 RSELx = 0, DCOx = 0, MODx = 0 RSELx = 0, DCOx = 3, MODx = 0 RSELx = 1, DCOx = 3, MODx = 0 RSELx = 2, DCOx = 3, MODx = 0 RSELx = 3, DCOx = 3, MODx = 0 RSELx = 4, DCOx = 3, MODx = 0 RSELx = 5, DCOx = 3, MODx = 0 RSELx = 6, DCOx = 3, MODx = 0 RSELx = 7, DCOx = 3, MODx = 0 RSELx = 8, DCOx = 3, MODx = 0 RSELx = 9, DCOx = 3, MODx = 0 RSELx = 10, DCOx = 3, MODx = 0 RSELx = 11, DCOx = 3, MODx = 0 RSELx = 12, DCOx = 3, MODx = 0 RSELx = 13, DCOx = 3, MODx = 0 RSELx = 14, DCOx = 3, MODx = 0 RSELx = 15, DCOx = 3, MODx = 0 RSELx = 15, DCOx = 7, MODx = 0 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) Measured at SMCLK output 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 4.30 6.00 8.60 12.0 16.0 1.35 1.08 50 7.8 0.54 0.80 1.6 2.3 3.4 4.25 7.30 9.60 13.9 18.5 26.0 TEST CONDITIONS VCC MIN 1.8 2.2 3 0.06 0.07 0.15 0.21 0.30 0.41 0.58 1.06 1.50 TYP MAX 3.6 3.6 3.6 0.14 0.17 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ratio ratio % V UNIT
29
Calibrated DCO Frequencies, Tolerance

PARAMETER 1-MHz tolerance over temperature (1) 1-MHz tolerance over VCC TEST CONDITIONS BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30C and 3 V BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30C and 3 V TA 0C to 85C VCC 3V MIN -3 TYP 0.5 MAX +3 UNIT %
30C
1.8 V to 3.6 V
-3
+3
1-MHz tolerance overall 8-MHz tolerance over temperature (1) 8-MHz tolerance over VCC
-40C to 85C
1.8 V to 3.6 V
-6
+6
0C to 85C
3V
-3
0.5
+3
30C
2.2 V to 3.6 V
-3
+3
-40C to 85C
2.2 V to 3.6 V
-6
+6
0C to 85C
3V
-3
0.5
+3
30C
2.7 V to 3.6 V
-3
+3
-40C to 85C
2.7 V to 3.6 V
-6
+6
0C to 85C
3V
-3
0.5
+3
30C
3.3 V to 3.6 V
-3
+3
16-MHz tolerance overall (1)
-40C to 85C
3.3 V to 3.6 V
-6
+6
This is the frequency change from the measured frequency at 30C over temperature.
30
Wake-Up From Lower-Power Modes (LPM3/4)

PARAMETER tDCO,LPM3/4 tCPU,LPM3/4 (1) (2) DCO clock wake-up time from LPM3/4 (1) CPU wake-up time from LPM3/4 (2) TEST CONDITIONS BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz VCC 3V MIN TYP 1.5 1/fMCLK + tClock,LPM3/4 MAX UNIT s
The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics, DCO Clock Wake-Up Time From LPM3/4
10.00 DCO Wake Time s
RSELx = 0...11 1.00 RSELx = 12...15
0.10 0.10
1.00 DCO Frequency MHz
10.00
Figure 15. DCO Wake-Up Time From LPM3 vs DCO Frequency
31
Crystal Oscillator, XT1, Low-Frequency Mode (1)

PARAMETER fLFXT1,LF fLFXT1,LF,logic LFXT1 oscillator crystal frequency, LF mode 0, 1 TEST CONDITIONS XTS = 0, LFXT1Sx = 0 or 1 VCC 1.8 V to 3.6 V 1.8 V to 3.6 V 10000 MIN TYP 32768 32768 500 k 200 1 5.5 8.5 11 2.2 V 2.2 V 30 10 50 70 10000 % Hz pF 50000 MAX UNIT Hz Hz
LFXT1 oscillator logic level square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 LF mode Oscillation allowance for LF crystals XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 6 pF XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 12 pF XTS = 0, XCAPx = 0 XTS = 0, XCAPx = 1 XTS = 0, XCAPx = 2 XTS = 0, XCAPx = 3 Duty cycle, LF mode XTS = 0, Measured at P2.0/ACLK, fLFXT1,LF = 32768 Hz XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
OALF
CL,eff
Integrated effective load capacitance, LF mode (2)
fFault,LF (1)
Oscillator fault frequency, LF mode (3)
(2)
(3) (4)
To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)

PARAMETER fVLO dfVLO/dT VLO frequency VLO frequency temperature drift TA -40C to 85C -40C to 85C 25C VCC 3V 3V 1.8 V to 3.6 V MIN 4 TYP 12 0.5 4 MAX 20 UNIT kHz %/C %/V
dfVLO/dVCC VLO frequency supply voltage drift
Timer_A
PARAMETER fTA tTA,cap Timer_A input clock frequency Timer_A capture timing TEST CONDITIONS SMCLK, duty cycle = 50% 10% TA0, TA1 3V 20 VCC MIN TYP fSYSTEM MAX UNIT MHz ns
32
USCI (UART Mode)

PARAMETER fUSCI fmax,BITCLK t (1) (2) USCI input clock frequency Maximum BITCLK clock frequency (equals baudrate in MBaud) (1) UART receive deglitch time (2) TEST CONDITIONS SMCLK, duty cycle = 50% 10% 3V 3V 2 50 100 600 VCC MIN TYP fSYSTEM MAX UNIT MHz MHz ns
The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16 and Figure 17)
PARAMETER fUSCI tSU,MI tHD,MI tVALID,MO USCI input clock frequency SOMI input data setup time SOMI input data hold time SIMO output data valid time UCLK edge to SIMO valid, CL = 20 pF
1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO
TEST CONDITIONS SMCLK, duty cycle = 50% 10%
VCC 3V 3V 3V
MIN 75 0
TYP
MAX fSYSTEM
UNIT MHz ns ns
20
ns
Figure 16. SPI Master Mode, CKPH = 0

1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI SOMI tHD,MO tVALID,MO SIMO
tHD,MI
Figure 17. SPI Master Mode, CKPH = 1

33
USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 18 and Figure 19)
PARAMETER tSTE,LEAD tSTE,LAG tSTE,ACC tSTE,DIS tSU,SI tHD,SI tVALID,SO STE lead time, STE low to clock STE lag time, Last clock to STE high STE access time, STE low to SOMI data out STE disable time, STE high to SOMI high impedance SIMO input data setup time SIMO input data hold time SOMI output data valid time
tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tHD,SO tVALID,SO
TEST CONDITIONS
VCC 3V 3V 3V 3V 3V 3V
MIN 10
TYP 50 50 50
MAX
UNIT ns ns ns ns ns ns
15 10 50 75
UCLK edge to SOMI valid, CL = 20 pF
3V
tSTE,LAG
ns
tSTE,ACC SOMI
tSTE,DIS
Figure 18. SPI Slave Mode, CKPH = 0

tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,LAG
tSTE,ACC SOMI
tHD,MO tVALID,SO
tSTE,DIS
Figure 19. SPI Slave Mode, CKPH = 1
34
USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20)
PARAMETER fUSCI fSCL tHD,STA tSU,STA tHD,DAT tSU,DAT tSU,STO tSP USCI input clock frequency SCL clock frequency Hold time (repeated) START Setup time for a repeated START Data hold time Data setup time Setup time for STOP Pulse width of spikes suppressed by input filter
tHD,STA SDA tLOW SCL tHIGH tSP tSU,STA tHD,STA
TEST CONDITIONS SMCLK, duty cycle = 50% 10%
VCC 3V
MIN 0 4.0 0.6 4.7 0.6 0 250 4.0 50
TYP
MAX fSYSTEM 400
UNIT MHz kHz s s ns ns s
fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz
3V 3V 3V 3V 3V 3V
100
600
ns
tBUF
tSU,DAT tHD,DAT
tSU,STO
Figure 20. I2C Mode Timing
Comparator_A+
PARAMETER I(DD) (1) I(Refladder/
RefDiode)
TEST CONDITIONS CAON = 1, CARSEL = 0, CAREF = 0 CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at CA0 and CA1
VCC 3V 3V 3V 3V 3V 3V 3V
MIN
TYP 45 45
MAX
UNIT A A
V(IC) V(Ref025) V(Ref050) V(RefVT) V(offset) Vhys
Commonmode input voltage (Voltage at 0.25 VCC node) / VCC (Voltage at 0.5 VCC node) / VCC See Figure 21 and Figure 22 Offset voltage
(2)
CAON = 1 PCA0 = 1, CARSEL = 1, CAREF = 1, No load at CA0 and CA1 PCA0 = 1, CARSEL = 1, CAREF = 2, No load at CA0 and CA1 PCA0 = 1, CARSEL = 1, CAREF = 3, No load at CA0 and CA1, TA = 85C CAON = 1 TA = 25C, Overdrive 10 mV, Without filter: CAF = 0 TA = 25C, Overdrive 10 mV, With filter: CAF = 1
0 0.24 0.48 490 10 0.7 120
VCC-1
mV mV mV ns s
Input hysteresis Response time (low-high and high-low)
3V
t(response)
3V 1.5
(1) (2)
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The two successive measurements are then summed together.
35
Typical Characteristics Comparator_A+

650 VCC = 3 V
V(RefVT) Reference Voltage mV
650 VCC = 2.2 V

V(RefVT) Reference Voltage mV
600 Typical 550
600 Typical 550
500
500
450
450
400 -45 -25 -5 15 35 55 75 TA Free-Air Temperature C 95 115
400 -45 -25 -5 15 35 55 75 TA Free-Air Temperature C 95 115
Figure 21. V(RefVT) vs Temperature, VCC = 3 V

100
Figure 22. V(RefVT) vs Temperature, VCC = 2.2 V
Short Resistance kW
VCC = 1.8 V VCC = 2.2 V 10 VCC = 3 V
VCC = 3.6 V
1 0 0.2 0.4 0.6 0.8 1 VIN/VCC Normalized Input Voltage V/V Figure 23. Short Resistance vs VIN/VCC
36
10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x53 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER VCC VAx Analog supply voltage Analog input voltage
(2)
TEST CONDITIONS VSS = 0 V All Ax terminals, Analog inputs selected in ADC10AE register fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV = 0 fADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 0, REFON = 1, REFOUT = 0 fADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 1, REFON = 1, REFOUT = 0
TA
VCC
MIN 2.2
TYP
MAX 3.6 VCC
UNIT V V
3V
IADC10
ADC10 supply current
(3)
25C
3V
0.6
mA
0.25 25C 3V 0.25 mA
IREF+
Reference supply current, reference buffer disabled (4)
IREFB,0
fADC10CLK = 5.0 MHz, Reference buffer supply ADC10ON = 0, REFON = 1, current with ADC10SR = 0 (4) REF2_5V = 0, REFOUT = 1, ADC10SR = 0 fADC10CLK = 5.0 MHz, Reference buffer supply ADC10ON = 0, REFON = 1, current with ADC10SR = 1 (4) REF2_5V = 0, REFOUT = 1, ADC10SR = 1 Input capacitance Input MUX ON resistance Only one terminal Ax can be selected at one time 0 V VAx VCC
25C
3V
1.1
mA
IREFB,1
25C
3V
0.5
mA
CI RI (1) (2) (3) (4)
25C 25C
3V 3V 1000
27
pF
The leakage current is defined in the leakage current table with Px.y/Ax parameter. The analog input voltage range must be within the selected reference voltage range VR+ to VR for valid conversion results. The internal reference supply current is not included in current consumption parameter IADC10. The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
37
10-Bit ADC, Built-In Voltage Reference (MSP430G2x53 Only)

PARAMETER VCC,REF+ VREF+ ILD,VREF+ TEST CONDITIONS VCC MIN 2.2 2.9 3V 3V IVREF+ = 500 A 100 A, Analog input voltage VAx 0.75 V, REF2_5V = 0 IVREF+ = 500 A 100 A, Analog input voltage VAx 1.25 V, REF2_5V = 1 IVREF+ = 100 A900 A, VAx 0.5 VREF+, Error of conversion result 1 LSB, ADC10SR = 0 IVREF+ 1 mA, REFON = 1, REFOUT = 1 IVREF+ = const with 0 mA IVREF+ 1 mA IVREF+ = 0.5 mA, REF2_5V = 0, REFON = 0 1 IVREF+ = 0.5 mA, REF2_5V = 1, REFON = 1, REFBURST = 1, ADC10SR = 0 1.41 2.35 1.5 2.5 1.59 2.65 1 2 3V 2 LSB TYP MAX UNIT V V mA IVREF+ 1 mA, REF2_5V = 0 Positive built-in reference analog supply voltage range IVREF+ 1 mA, REF2_5V = 1 Positive built-in reference voltage Maximum VREF+ load current IVREF+ IVREF+max, REF2_5V = 0 IVREF+ IVREF+max, REF2_5V = 1
VREF+ load regulation
VREF+ load regulation response time CVREF+ TCREF+ tREFON Maximum capacitance at pin VREF+ Temperature coefficient Settling time of internal reference voltage to 99.9% VREF Settling time of reference buffer to 99.9% VREF
3V
400
ns
3V 3V 3.6 V
100 100 30
pF ppm/ C s
tREFBURST
3V
38
10-Bit ADC, External Reference (1) (MSP430G2x53 Only)

PARAMETER Positive external reference input voltage range (2) Negative external reference input voltage range (4) Differential external reference input voltage range, VEREF = VEREF+ VEREF TEST CONDITIONS VEREF+ > VEREF, SREF1 = 1, SREF0 = 0 VEREF VEREF+ VCC 0.15 V, SREF1 = 1, SREF0 = 1 (3) VEREF+ > VEREF VEREF+ > VEREF
(5)
VCC
MIN 1.4 1.4 0 1.4
TYP
MAX VCC
UNIT
VEREF+
V 3 1.2 VCC 1 A 3V 3V 0 1 A V V
VEREF VEREF
IVEREF+
Static input current into VEREF+
0 V VEREF+ VCC, SREF1 = 1, SREF0 = 0 0 V VEREF+ VCC 0.15 V 3 V, SREF1 = 1, SREF0 = 1 (3) 0 V VEREF VCC
3V
IVEREF (1) (2) (3) (4) (5)
Static input current into VEREF
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.
10-Bit ADC, Timing Parameters (MSP430G2x53 Only)

PARAMETER fADC10CLK fADC10OSC ADC10 input clock frequency ADC10 built-in oscillator frequency TEST CONDITIONS For specified performance of ADC10 linearity parameters ADC10SR = 0 ADC10SR = 1 VCC 3V 3V 3V MIN 0.45 0.45 3.7 2.06 13 ADC10DIV 1/fADC10CLK 100 TYP MAX 6.3 1.5 6.3 3.51 s UNIT MHz MHz
ADC10DIVx = 0, ADC10SSELx = 0, fADC10CLK = fADC10OSC ADC10 built-in oscillator, ADC10SSELx = 0, fADC10CLK = fADC10OSC
tCONVERT
Conversion time
fADC10CLK from ACLK, MCLK, or SMCLK: ADC10SSELx 0

(1)
tADC10ON (1)
Turn-on settling time of the ADC
ns
The condition is that the error in a conversion started after tADC10ON is less than 0.5 LSB. The reference and input signal are already settled.
10-Bit ADC, Linearity Parameters (MSP430G2x53 Only)

PARAMETER EI ED EO EG ET Integral linearity error Differential linearity error Offset error Gain error Total unadjusted error Source impedance RS < 100 TEST CONDITIONS VCC 3V 3V 3V 3V 3V 1.1 2 MIN TYP MAX 1 1 1 2 5 UNIT LSB LSB LSB LSB LSB
39
10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x53 Only)

PARAMETER ISENSOR TCSENSOR tSensor(sample) IVMID VMID tVMID(sample) (1) (2) Sample time required if channel 10 is selected (3) Current into divider at channel 11 VCC divider at channel 11 Sample time required if channel 11 is selected (5) Temperature sensor supply current (1) TEST CONDITIONS REFON = 0, INCHx = 0Ah, TA = 25C ADC10ON = 1, INCHx = 0Ah
(2)
VCC 3V 3V 3V 3V 3V 3V
MIN
TYP 60 3.55
MAX
UNIT A mV/C s
ADC10ON = 1, INCHx = 0Ah, Error of conversion result 1 LSB ADC10ON = 1, INCHx = 0Bh ADC10ON = 1, INCHx = 0Bh, VMID 0.5 VCC ADC10ON = 1, INCHx = 0Bh, Error of conversion result 1 LSB
30
(4)
A V ns
1.5 1220
(3) (4) (5)
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor input (INCH = 0Ah). The following formula can be used to calculate the temperature sensor output voltage: VSensor,typ = TCSensor (273 + T [C] ) + VOffset,sensor [mV] or VSensor,typ = TCSensor T [C] + VSensor(TA = 0C) [mV] The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on). No additional current is needed. The VMID is used during sampling. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Flash Memory
PARAMETER VCC(PGM/ERASE) fFTG IPGM IERASE tCPT tCMErase tRetention tWord tBlock, tBlock, tBlock,
0 1-63 End
TEST CONDITIONS
VCC
MIN 2.2 257
TYP
MAX 3.6 476
UNIT V kHz mA mA ms ms cycles years tFTG tFTG tFTG tFTG tFTG tFTG
Program and erase supply voltage Flash timing generator frequency Supply current from VCC during program Supply current from VCC during erase Cumulative program time (1) Cumulative mass erase time Program/erase endurance Data retention duration Word or byte program time Block program time for first byte or word Block program time for each additional byte or word Block program end-sequence wait time Mass erase time Segment erase time TJ = 25C
(2) (2) (2) (2) (2) (2)
2.2 V/3.6 V 2.2 V/3.6 V 2.2 V/3.6 V 2.2 V/3.6 V 20 104 100
1 1
5 7 10
105 30 25 18 6 10593 4819
tMass Erase tSeg Erase (1) (2)
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
40
RAM
PARAMETER V(RAMh) (1) RAM retention supply voltage
(1)
TEST CONDITIONS CPU halted
MIN 1.6
MAX
UNIT V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface

PARAMETER fSBW tSBW,Low tSBW,En tSBW,Ret fTCK RInternal (1) (2) Spy-Bi-Wire input frequency Spy-Bi-Wire low clock pulse length Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) Spy-Bi-Wire return to normal operation time TCK input frequency (2) Internal pulldown resistance on TEST TEST CONDITIONS VCC 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 15 0 25 60 MIN 0 0.025 TYP MAX 20 15 1 100 5 90 UNIT MHz s s s MHz k
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge. fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)

PARAMETER VCC(FB) VFB IFB tFB (1) Supply voltage during fuse-blow condition Voltage level on TEST for fuse blow Supply current into TEST during fuse blow Time to blow fuse TEST CONDITIONS TA = 25C MIN 2.5 6 7 100 1 MAX UNIT V V mA ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to bypass mode.
41
PORT SCHEMATICS Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger
To Comparator From Comparator To ADC10 * INCHx = y * CAPD.y or ADC10AE0.y *
PxSEL2.y PxSEL.y
PxDIR.y From Timer 1 From USCI PxSEL2.y PxSEL.y PxREN.y 1
0 1 2 3 Direction 0: Input 1: Output
0 1 0 1 DVSS DVCC 0 1 2 Bus Keeper EN 0 1 1
PxSEL2.y PxSEL.y PxOUT.y From Timer
0 TAx.y TAxCLK PxIN.y
P1.0/TA0CLK/ACLK/ A0*/CA0 P1.1/TA0.0/UCA0RXD/ UCA0SOMI/A1*/CA1 P1.2/TA0.1/UCA0TXD/ UCA0SIMO/A2*/CA2
EN To Module D PxIE.y PxIRQ.y Q PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select EN Set
* Note: MSP430G2x53 devices only. MSP430G2x13 devices have no ADC10.
42
Table 16. Port P1 (P1.0 to P1.2) Pin Functions

PIN NAME (P1.x) P1.0/ TA0CLK/ ACLK/ A0 / CA0/ Pin Osc P1.1/ TA0.0/ UCA0RXD/ UCA0SOMI/ A1 (2)/ CA1/ Pin Osc P1.2/ TA0.1/ UCA0TXD/ UCA0SIMO/ A2 (2)/ CA2/ Pin Osc (1) (2)
(2)
CONTROL BITS / SIGNALS (1) x P1.x (I/O) TA0.TACLK 0 ACLK A0 CA0 Capacitive sensing P1.x (I/O) TA0.0 TA0.CCI0A 1 UCA0RXD UCA0SOMI A1 CA1 Capacitive sensing P1.x (I/O) TA0.1 TA0.CCI1A 2 UCA0TXD UCA0SIMO A2 CA2 Capacitive sensing FUNCTION P1DIR.x I: 0; O: 1 0 1 X X X I: 0; O: 1 1 0 from USCI from USCI X X X I: 0; O: 1 1 0 from USCI from USCI X X X P1SEL.x 0 1 1 X X 0 0 1 1 1 1 X X 0 0 1 1 1 1 X X 0 P1SEL2.x 0 0 0 X X 1 0 0 0 1 1 X X 1 0 0 0 1 1 X X 1 ADC10AE.x INCH.x=1 (2) 0 0 0 1 (y = 0) 0 0 0 0 0 0 0 1 (y = 1) 0 0 0 0 0 0 0 1 (y = 2) 0 0 CAPD.y 0 0 0 0 1 (y = 0) 0 0 0 0 0 0 0 1 (y = 1) 0 0 0 0 0 0 0 1 (y = 2) 0
X = don't care MSP430G2x53 devices only
43
Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger

SREF2 * To ADC10 VREF- * To Comparator from Comparator To ADC10 * INCHx = y * CAPD.y or ADC10AE0.y * PxDIR.y 0 1 VSS
PxSEL2.y PxSEL.y 0,2,3 1 Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC PxOUT.y From ADC10 * 0 1 2 From Comparator TAx.y TAxCLK 3 Bus Keeper EN P1.3/ADC10CLK*/CAOUT/ A3*/VREF-*/VEREF-*/CA3 0 1 1
PxSEL2.y PxSEL.y
PxIN.y EN To Module D PxIE.y PxIRQ.y Q PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select EN Set
44
Table 17. Port P1 (P1.3) Pin Functions

PIN NAME (P1.x) P1.3/ ADC10CLK (2)/ CAOUT/ A3 / VREF- (2)/ VEREF- (2)/ CA3/ Pin Osc (1) (2)
(2)
CONTROL BITS / SIGNALS (1) x P1.x (I/O) ADC10CLK CAOUT 3 A3 VREFVEREFCA3 Capacitive sensing FUNCTION P1DIR.x I: 0; O: 1 1 1 X X X X X P1SEL.x 0 1 1 X X X X 0 P1SEL2.x 0 0 1 X X X X 1 ADC10AE.x INCH.x=1 (2) 0 0 0 1 (y = 3) 1 1 0 0 CAPD.y 0 0 0 0 0 0 1 (y = 3) 0
45

From/To ADC10 Ref+ * To Comparator from Comparator To ADC10 * INCHx = y * CAPD.y or ADC10AE0.y * PxDIR.y
PxSEL.y 0 1 Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC 0 1 2 3 Bus Keeper EN P1.4/SMCLK/TA0.2/A4*/ VREF+*/VEREF+*/CA4/TCK 0 1 1
PxSEL2.y PxSEL.y PxOUT.y SMCLK From Module TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y PxIFG.y PxSEL.y PxIES.y From JTAG To JTAG Interrupt Edge Select EN Q Set
46

PIN NAME (P1.x) P1.4/ SMCLK/ UCB0STE/ UCA0CLK/ VREF+ (2)/ VEREF+ (2)/ A4 / CA4 TCK/ Pin Osc (1) (2)
(2)
CONTROL BITS / SIGNALS (1) x FUNCTION P1.x (I/O) SMCLK UCB0STE UCA0CLK VREF+ 4 VEREF+ A4 CA4 TCK Capacitive sensing P1DIR.x I: 0; O: 1 1 from USCI from USCI X X X X X X P1SEL.x 0 1 1 1 X X X X X 0 P1SEL2.x 0 0 1 1 X X X X X 1 ADC10AE.x INCH.x=1 (2) 0 0 0 0 1 1 1 (y = 4) 0 0 0 JTAG Mode 0 0 0 0 0 0 0 0 1 0 CAPD.y 0 0 0 0 0 0 0 1 (y = 4) 0 0
47
Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger

To Comparator From Comparator To ADC10 * INCHx = y * CAPD.y ADC10AE0.y *
PxSEL2.y PxSEL.y
PxDIR.y From Module
0 1 2 3 Direction 0: Input 1: Output
From Module PxSEL2.y PxSEL.y PxREN.y
0 1 0 1 DVSS DVCC 0 1 1
PxSEL2.y PxSEL.y
PxOUT.y From Module From Module
0 1 2 3 Bus Keeper EN
TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y PxIFG.y PxSEL.y PxIES.y From JTAG To JTAG * Note: MSP430G2x53 devices only. MSP430G2x13 devices have no ADC10. Q EN Set Interrupt Edge Select
P1.5/TA0.0/UCB0CLK/UCA0STE/ A5*/CA5/TMS P1.6/TA0.1/UCB0SOMI/UCB0SCL/ A6*/CA6/TDI/TCLK P1.7/CAOUT/UCB0SIMO/UCB0SDA/ A7*/CA7/TDO/TDI
48

PIN NAME (P1.x) P1.5/ TA0.0/ UCB0CLK/ UCA0STE/ A5 (2)/ CA5 TMS Pin Osc P1.6/ TA0.1/ UCB0SOMI/ UCB0SCL/ A6 / CA6 TDI/TCLK/ Pin Osc P1.7/ UCB0SIMO/ UCB0SDA/ A7 (2)/ CA7 CAOUT TDO/TDI/ Pin Osc (1) (2) 7
(2)
CONTROL BITS / SIGNALS (1) x FUNCTION P1.x (I/O) TA0.0 UCB0CLK UCA0STE 5 A5 CA5 TMS Capacitive sensing P1.x (I/O) TA0.1 UCB0SOMI UCB0SCL 6 A6 CA6 TDI/TCLK Capacitive sensing P1.x (I/O) UCB0SIMO UCB0SDA A7 CA7 CAOUT TDO/TDI Capacitive sensing P1DIR.x I: 0; O: 1 1 from USCI from USCI X X X X I: 0; O: 1 1 from USCI from USCI X X X X I: 0; O: 1 from USCI from USCI X X 1 X X P1SEL.x 0 1 1 1 X X X 0 0 1 1 1 X X X 0 0 1 1 X X 1 X 0 P1SEL2.x 0 0 1 1 X X X 1 0 0 1 1 X X X 1 0 1 1 X X 0 X 1 ADC10AE.x INCH.x=1 (2) 0 0 0 0 1 (y = 5) 0 0 0 0 0 0 0 1 (y = 6) 0 0 0 0 0 0 1 (y = 7) 0 0 0 0 JTAG Mode 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 CAPD.y 0 0 0 0 0 1 (y = 5) 0 0 0 0 0 0 0 1 (y = 6) 0 0 0 0 0 0 1 (y = 7) 0 0 0
49
Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger

PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 PxSEL2.y PxSEL.y 1 DVSS DVCC PxOUT.y From Timer 0 1 2 0 3 P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P2.3/TA1.0 P2.4/TA1.2 P2.5/TA1.2 0 1 1
TAx.y TAxCLK
PxIN.y EN To Module D PxIE.y PxIRQ.y PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select EN Q Set
50

PIN NAME (P2.x) P2.0/ TA1.0/ Pin Osc P2.1/ TA1.1/ Pin Osc P2.2/ TA1.1/ Pin Osc P2.3/ TA1.0/ Pin Osc P2.4/ TA1.2/ Pin Osc P2.5/ TA1.2/ Pin Osc (1) X = don't care 5 4 3 2 1 0 x P2.x (I/O) Timer1_A3.CCI0A Timer1_A3.TA0 Capacitive sensing P2.x (I/O) Timer1_A3.CCI1A Timer1_A3.TA1 Capacitive sensing P2.x (I/O) Timer1_A3.CCI1B Timer1_A3.TA1 Capacitive sensing P2.x (I/O) Timer1_A3.CCI0B Timer1_A3.TA0 Capacitive sensing P2.x (I/O) Timer1_A3.CCI2A Timer1_A3.TA2 Capacitive sensing P2.x (I/O) Timer1_A3.CCI2B Timer1_A3.TA2 Capacitive sensing FUNCTION CONTROL BITS / SIGNALS (1) P2DIR.x I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X P2SEL.x 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 P2SEL2.x 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
51
LF off PxSEL.6 and PxSEL.7 BCSCTL3.LFXT1Sx = 11
XOUT/P2.7
LFXT1CLK PxSEL.y PxDIR.y 0 1
0 1
Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC PxOUT.y From Module 0 1 2 3 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select Q EN Set XIN/P2.6/TA0.1 0 1 1
PxSEL2.y PxSEL.y
52

PIN NAME (P2.x) XIN P2.6 6 TA0.1 Pin Osc (1) X = don't care Timer0_A3.TA1 Capacitive sensing 1 X CONTROL BITS / SIGNALS (1) x FUNCTION P2DIR.x 0 I: 0; O: 1 P2SEL.6 P2SEL.7 1 1 0 X 1 0 0 X P2SEL2.6 P2SEL2.7 0 0 0 0 0 0 1 X
XIN P2.x (I/O)
53
LF off PxSEL.6 and PxSEL.7 BCSCTL3.LFXT1Sx = 11
XIN
LFXT1CLK PxSEL.y PxDIR.y 0 1
0 1
from P2.6
Direction 0: Input 1: Output
PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 1 DVSS DVCC 0 1 2 3 TAx.y TAxCLK XOUT/P2.7 0 1 1
PxSEL2.y PxSEL.y PxOUT.y From Module
PxIN.y EN To Module D PxIE.y PxIRQ.y Q PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select EN Set
54

PIN NAME (P2.x) XOUT/ P2.7/ Pin Osc (1) X = don't care 7 CONTROL BITS / SIGNALS (1) x FUNCTION P2DIR.x 1 I: 0; O: 1 X P2SEL.6 P2SEL.7 1 1 0 X 0 X P2SEL2.6 P2SEL2.7 0 0 0 0 1 X
XOUT P2.x (I/O) Capacitive sensing
55
Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB Package Only)
PxSEL.y PxDIR.y 0 1 PxSEL2.y PxSEL.y PxREN.y 1 0 1 0 PxSEL2.y PxSEL.y 1 DVSS DVCC PxOUT.y From Module 0 1 2 3 P3.0/TA0.2 P3.1/TA1.0 P3.2/TA1.1 P3.3/TA1.2 P3.4/TA0.0 P3.5/TA0.1 P3.6/TA0.2 P3.7/TA1CLK/CAOUT 0 1 1 Direction 0: Input 1: Output
TAx.y TAxCLK
PxIN.y EN To Module D
56
Table 23. Port P3 (P3.0 to P3.7) Pin Functions (RHB Package Only)
PIN NAME (P3.x) P3.0/ TA0.2/ Pin Osc P3.1/ TA1.0/ Pin Osc P3.2/ TA1.1/ Pin Osc P3.3/ TA1.2/ Pin Osc P3.4/ TA0.0/ Pin Osc P3.5/ TA0.1/ Pin Osc P3.6/ TA0.2/ Pin Osc P3.7/ TA1CLK/ CAOUT/ Pin Osc (1) X = don't care 7 6 5 4 3 2 1 0 x P3.x (I/O) Timer0_A3.CCI2A Timer0_A3.TA2 Capacitive sensing P3.x (I/O) Timer1_A3.TA0 Capacitive sensing P3.x (I/O) Timer1_A3.TA1 Capacitive sensing P3.x (I/O) Timer1_A3.TA2 Capacitive sensing P3.x (I/O) Timer0_A3.TA0 Capacitive sensing P3.x (I/O) Timer0_A3.TA1 Capacitive sensing P3.x (I/O) Timer0_A3.TA2 Capacitive sensing P3.x (I/O) Timer1_A3.TACLK Comparator output Capacitive sensing FUNCTION CONTROL BITS / SIGNALS (1) P3DIR.x I: 0; O: 1 0 1 X I: 0; O: 1 1 X I: 0; O: 1 1 X I: 0; O: 1 1 X I: 0; O: 1 1 X I: 0; O: 1 1 X I: 0; O: 1 1 X I: 0; O: 1 0 1 X P3SEL.x 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 P3SEL2.x 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1
57
REVISION HISTORY
REVISION SLAS735 SLAS735A Initial release Changed Control Bits / Signals column in Table 18 Changed Pin Name and Function columns in Table 23 Changed Storage temperature range limit in Absolute Maximum Ratings Added BSL functions to P1.1 and P1.5 in Table 2. Added CAOUT information to Table 17. Changed Tstg, Programmed device, to -55C to 150C in Absolute Maximum Ratings. Changed TAG_ADC10_1 value to 0x10 in Table 10. Added AVCC (RHB package only, pin 29) to Table 2 Terminal Functions. Corrected typo in P3.7/TA1CLK/CAOUT description in Table 2. Corrected PW28 terminal assignment in Input and Output Pin Number columns in Table 13. Changed all port schematics (added buffer after PxOUT.y mux) in Port Schematics. Table 5 and Table 14, Corrected Timer_A register names. DESCRIPTION
SLAS735B
SLAS735C
SLAS735D
SLAS735E
58
PACKAGE OPTION ADDENDUM
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18-Jan-2012
PACKAGING INFORMATION
Orderable Device MSP430G2153IN20 MSP430G2153IPW20 MSP430G2153IPW20R MSP430G2153IPW28 MSP430G2153IPW28R MSP430G2153IRHB32R MSP430G2153IRHB32T MSP430G2213IN20 MSP430G2213IPW20 MSP430G2213IPW20R MSP430G2213IPW28 MSP430G2213IPW28R MSP430G2213IRHB32R MSP430G2213IRHB32T MSP430G2253IN20 MSP430G2253IPW20 MSP430G2253IPW20R MSP430G2253IPW28 Status
(1)
Package Type Package Drawing PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP N PW PW PW PW RHB RHB N PW PW PW PW RHB RHB N PW PW PW
Pins 20 20 20 28 28 32 32 20 20 20 28 28 32 32 20 20 20 28
Package Qty 20 70 2000 50 2000 3000 250 20 70 2000 50 2000 3000 250 20 70 2000 50
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
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18-Jan-2012
Orderable Device MSP430G2253IPW28R MSP430G2253IRHB32R MSP430G2253IRHB32T MSP430G2313IN20 MSP430G2313IPW20 MSP430G2313IPW20R MSP430G2313IPW28 MSP430G2313IPW28R MSP430G2313IRHB32R MSP430G2313IRHB32T MSP430G2353IN20 MSP430G2353IPW20 MSP430G2353IPW20R MSP430G2353IPW28 MSP430G2353IPW28R MSP430G2353IRHB32R MSP430G2353IRHB32T MSP430G2413IN20 MSP430G2413IPW20
Status
(1)
Package Type Package Drawing TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP PW RHB RHB N PW PW PW PW RHB RHB N PW PW PW PW RHB RHB N PW
Pins 28 32 32 20 20 20 28 28 32 32 20 20 20 28 28 32 32 20 20
Package Qty 2000 3000 250 20 70 2000 50 2000 3000 250 20 70 2000 50 2000 3000 250 20 70
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 2
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18-Jan-2012
Orderable Device MSP430G2413IPW20R MSP430G2413IPW28 MSP430G2413IPW28R MSP430G2413IRHB32R MSP430G2413IRHB32T MSP430G2453IN20 MSP430G2453IPW20 MSP430G2453IPW20R MSP430G2453IPW28 MSP430G2453IPW28R MSP430G2453IRHB32R MSP430G2453IRHB32T MSP430G2513IN20 MSP430G2513IPW20 MSP430G2513IPW20R MSP430G2513IPW28 MSP430G2513IPW28R MSP430G2513IRHB32R MSP430G2513IRHB32T
Status
(1)
Package Type Package Drawing TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PW PW PW RHB RHB N PW PW PW PW RHB RHB N PW PW PW PW RHB RHB
Pins 20 28 28 32 32 20 20 20 28 28 32 32 20 20 20 28 28 32 32
Package Qty 2000 50 2000 3000 250 20 70 2000 50 2000 3000 250 20 70 2000 50 2000 3000 250
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR
Addendum-Page 3
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18-Jan-2012
Orderable Device MSP430G2553CY MSP430G2553CYS MSP430G2553GACYS MSP430G2553IN20 MSP430G2553IPW20 MSP430G2553IPW20R MSP430G2553IPW28 MSP430G2553IPW28R MSP430G2553IRHB32R MSP430G2553IRHB32T
Status
(1)
Package Type Package Drawing DIESALE Y YS YS N PW PW PW PW RHB RHB
Pins 0 0 0 20 20 20 28 28 32 32
Package Qty 405 1 1 20 70 2000 50 2000 3000 250
Eco Plan
(2)
Lead/ Ball Finish Call TI Call TI Call TI
MSL Peak Temp N / A for Pkg Type Call TI Call TI
(3)
PREVIEW
Green (RoHS & no Sb/Br) TBD TBD Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
PREVIEW WAFERSALE PREVIEW WAFERSALE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 4
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18-Jan-2012
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
IMPORTANT NOTICE
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MSP 430 G 2553

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MSP430G2x53 MSP430G2x13

www.ti.com SLAS735E APRIL 2011 REVISED JANUARY 2012

MIXED SIGNAL MICROCONTROLLER

Copyright 20112012, Texas Instruments Incorporated

Table 1. Available Options (1) (2)

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N20 PW20 (TOP VIEW)

Device Pinout, MSP430G2x13 and MSP430G2x53, 28-Pin Devices, TSSOP

PW28 (TOP VIEW)

NOTE: ADC10 is available on MSP430G2x53 devices only.

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Device Pinout, MSP430G2x13 and MSP430G2x53, 32-Pin Devices, QFN

P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1 P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2 P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS P3.1/TA1.0 P3.0/TA0.2 NC

RHB32 (TOP VIEW)

TEST/SBWTCK RST/NMI/SBWTDIO P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK P3.7/TA1CLK/CAOUT P3.6/TA0.2 P3.5/TA0.1 P2.5/TA1.2

NOTE: ADC10 is available on MSP430G2x53 devices only.

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P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P3.2/TA1.1 P3.3/TA1.2 P3.4/TA0.0 P2.3/TA1.0 P2.4/TA1.2

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Functional Block Diagram, MSP430G2x53

16MHz CPU incl. 16 Registers

Emulation 2BP JTAG Interface Spy-BiWire RST/NMI Brownout Protection

Watchdog WDT+ 15-Bit

USCI A0 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C

NOTE: Port P3 is available on 28-pin and 32-pin devices only.

Functional Block Diagram, MSP430G2x13

16MHz CPU incl. 16 Registers

Emulation 2BP JTAG Interface Spy-BiWire RST/NMI Brownout Protection

Watchdog WDT+ 15-Bit

USCI A0 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C

NOTE: Port P3 is available on 28-pin and 32-pin devices only.

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Table 2. Terminal Functions

MSP430G2x53 devices only Submit Documentation Feedback

Table 2. Terminal Functions (continued)

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Table 2. Terminal Functions (continued)

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SHORT-FORM DESCRIPTION CPU

Table 3. Instruction Word Formats

Table 4. Address Mode Descriptions (1)

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Interrupt Vector Addresses

(non)-maskable (non)-maskable (non)-maskable maskable maskable maskable maskable

WDTIFG TA0CCR0 CCIFG

maskable maskable maskable maskable maskable

0FFE6h 0FFE4h 0FFE2h 0FFE0h

P1IFG.0 to P1IFG.7 (2) (4)

0FFDEh 0FFDEh to 0FFC0h

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Special Function Registers (SFRs)