UNIT-01

1. micro processor with a 16 bit address bus is used in a linear memory selection configuration address bus lines are directly used as chip selects of memory chips with four memory chips. The maximum addressable memory space is a) 64K b) 16 K c) 8K d) 4K

2. The No. of control lines are 3. The length of A register is - bits 4. The memory word addressing capability is K 5. The No. of input output ports can be accessed by direct method 6. In 8085 the direction of address business is a)bidirectional c)unidirectional int MP 7. A NOR gate is ON only when all its inputs are (a) ON (b) positive (c) high (d) OFF b)unidirectional out of MP d)none of the above

8. The First Microprocessor was__________ a) Intel 4004 b) 8080 c) 8085 d ) 4008

9. 8085 was introduced in __________ a) 1971 b) 1976 c) 1972 d) 1978

10 .In 1978 Intel introduced the 16 bit Microprocessor 8086 now called as________ a) M6 800 b) APX 80 c) Zylog z8000 d) Intel 8086

11. Which is a 8 bit Microprocessor __________ a) Intel 4040 b) Pentium I c) 8088 d) Motorala MC-6801

12. Pentium-I, Pentium-II, Pentium-III and Pentium-IV are recently introduced

microprocessor by__________ a) Motorala b) Intel c) Stephen Mors d) None

13. The address bus flow in __________ a) bidirection b) unidirection c) Mulidirection d) Circular

14. Status register is also called as ___________ a) Accumulator b) Stack c) Counter d) flags

15. The 8085 is based in a _____ pin DIP a) 40 b) 45 c) 20 d) 35

16.The 8085 Microprocessor uses__________ V power supply a) +5V b) -5V c) +12v d) -12v

17. The address / data bus in 8085 is __________ a) Multiplexed b) demultiplexed c) decoded d) loaded

18.The Stack pointer holds__________ a) 16 bit address b) 16 bit data c) 8 bit address d) 8 bit data

19. The First electronic computer was completed in __________ a) 1946 b) 1938 c) 1941 d) 1950

20. The First Generation of computer appeared during the period__________ a) 1945 to 1954 b) 1964 to 1974 c) 1934 to 1944 d) 1937 to 1949

UNIT-02

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1. The Second Generation of computers used __________ a) IC-Chip b) Transistors c) Vaccum tubes

d) Microprocessor chip

2. The fourth Generation began in __________ a) 1974 b) 1935 c) 1965 d) 1975

3. What will be the hexadecimal equivalent of decimal number (54977) a. D6C1 b. DC61 c. D6C5 d. none

4. Hexadecimal number system has .. symbols. a. 15 b.12 c.16 d.10

5. An interrupt instruction a) causes an unconditional transfer of control (b) causes a conditional transfer of Control (c) modifies the status register (d) is an I/O instruction 6 A data movement instruction will a) modify the status register (b) modify the stack pointer c) modify the program counter\ d) transfer data from one location to another

7. An assembly language directive is (a) the same as an instruction (b) used to define space for variables (c) used to start a program (d) to give commands to an assembler

8 Which of the following is not part of the processor (a) the ALU
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(b) the CU (c) the registers (d) the system bus

9. When TRAP interrupt is triggered program control is transferred to - location.

10. What is the purpose of using ALE signal high ? a) To latch low order address from bus to separate A0 A7 b) To latch data Do D 7 from bus go separate data bus c) To disable data bus latch

11. What is the purpose of READY signal? a) It is used to indicate to user that microprocessor is working and ready to use b) It is used to provide for proper WAIT states when microprocessor is communicating with slow peripheral device. c) It is used to provide for proper showing down of fast peripheral devices so as to communicate at micro processors speed.

13. The memory address register is used to store (a) data to be transferred to memory (b) data that has been transferred from memory (c) the address of a memory location (d) an instruction that has been transferred from memory.

14. The memory data register is used to store (a) data to be transferred to or from memory (b) data to be transferred to the stack (c) the address of a memory location (d) an instruction that has been transferred from memory

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15. The instruction register stores (a) an instruction that has been decoded (b) an instruction that has been fetched from memory (c) an instruction that has been executed (d) the address of the next instruction to be executed

16. The program counter (a) stores the address of the instruction that is currently being executed (b) stores the next instruction to be executed (c) stores the address of the next instruction to be executed (d) stores the instruction that is being currently executed.

17. The stack pointer stores (a) the address of the stack in memory (b) address of the last item pushed on the stack (c) the address of the next free stack location (d) the address of the last item popped from the stack

18. The read/write line is (a) belongs to the data bus (b) belongs to the control bus (c) belongs to the address bus (d) CPU bus

19. The instruction INC I where I is a memory variable involves (a) a memory read operation (b) a memory write operation (c) a memory read and a memory write operation (d) only an arithmetic operation

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20. In 8085 microprocessor, the value of the most significant bit of the result following the execution of any arithmetic operation is stored in a) carry status flag b) auxiliary carry status flag c) sign status flag d) zero status flag

UNIT-03
1. In Synchronous data Transfer type both Transmitter and Receiver will operate in. a) Same Clock pulse b) Different Clock pulse c) None of the above

2. In micro processors like 8080 and the 8085, the ..cycle may have from one to live machine cycle

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a) micro instruction c) instruction

b) source program d) fetch cycle

3. Repeated addition is one way to do multiplication, programmed multiplication is used in most microprocessors because a) that ALUs can only add and subtract c) a separate set of instructions is needed for the two b) this saves on memory d) None of the above.

4. Addressing in which the instructions contains the address of the data to the operated on is known as a) immediate addressing c) register addressing b) implied addressing d) direct addressing

5. Resart is a special type of CALL in which a) the address is programmed but not built into the hardware b) the address is programmed built into the hardware c) the address is not programmed but built into the hardware d) None of the above

6. 8085 has software restarts and .. hardware restarts a) 10, 5 b) 8,4 c) 7,5 d) 6,6

7. Serial input data of 8085 can be loaded into bit 7 of the accumulator by a) executing a RIM instruction c) using TRAP b) executing RST1 c) None of the above

8. The address to which a software or hardware restart branches is known as

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a) vector location

b) SID

c) SOD

d) TRAP

9. The stack is a specialized temporary access memory during .. and instructions a) random, store, load c) sequential, store, pop b) random, push, load d) sequential, push, pop

10. If instruction RST is written in a program the program will jump - location. 11. The RST 5.5 interrupt service routine start from location.

12. What is the addressing mode used in instruction MOV M, C? a) Direct b) Indirect c) Indexed d) Immediate

13. In 8085 the hardware interrupts are a)TRAP,RST 6.5,RST 7.5, RST 5.5 and INTR c)both a b b)RST o, RST 1..RST 7 d)none of the above

14. In the TRAP, RST 7.5, RST 6.5, RST 5.5, which is having top priority

a)TRAP

b)RST 7.5

c)RST 6.5

d)RST 5.5

15.In 8085 the no . of software interrupts are a) 8 b)7 c)5 d)4

16. In the following interrupts which is the non-vectored interrupt a)TRAP b)INTR c)RST 7.5 d)RST 6.5

17. Vector address for the TRAP interrupt is a)0024 H b)003C H c)0034 H d)002C H

18. In the following interrupt which is non-maskable interrupt

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(a) Rst7.5

b) Rst 6.5

c) TRAP

d) INTR

19. Vector location Address for RST O Instruction is inflex (a) ooooH b) ooo8H c) oo01 H d)oo18H

20. In 8085 the Interput Acknowledge is represended by _______ (a) INTA b)INT c) INTR d) none of the above

UNIT-04
1. Interaction between a CPU and a peripheral device that takes place during and imput output operation is known as a) handshaking b) flagging c) relocating d) subroutine

2. A hardware interrupt is (a) also called an internal interrupt (b) also called an external interrupt (c) an I/O interrupt (d) a clock interrupt

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3. An assembly language program is typically (a) non-portable (b) shorter than an equivalent HLL program (c) harder to read than a machine code program (d) slower to execute than a compiled HLL program

4. Programs are written in assembly language because they (a) run faster than HLL programs (b) are portable (c) easier to write than machine code programs (d) they allow the programmer access to registers or instructions that are not usually provided by a HLL

5. Reading and writing to the memory unit (RAM or off-processor memory) takes place via the: a) ALU and the register unit b) Memory address and memory data registers c) Program counter and the memory data register d) Input/output

6. An interrupt in which the external device supplies its address as well as the interrupt request, is known as a) vectored interrupt c) polled interrupt b) maskable interrupt d? non-maskable interrupt

7. The instructions used to create indefinite loops are a) conditional JUMP c) ADD b) unconditional JUMP d) SHLD

8. The first machine cycle for every read/write operation is a) read b) opcode fetch c) opcode decode d) write

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9. One machine may have a) 8-10 T-states b) 3-6 T-states c) 1-5 instruction cycles d) 1 T-state

10. STA F505 has .. machine cycles a) 1 b) 2 c) 3 d) 4

11. Programmable Interrupt Controller is a) 8255 b) 8254 c) 8257 c) 8259

12. 8085 is called an 8-bit microprocessor because of a) an 8-bit address bus c) 8 control signals b) an 8-bit data bus d) none of these

13. One T-state is a) 2 clock cycles b) 1 clock cycle c) 5 clock cycles d) clock cycle

14. TRAP is a a) maskable interrupt c) none of these b) non-maskable interrupt d) both a and b

15. The opcode is fed into the .. for reading and decoding a) instruction register and machine cycle decoder c) flag register b) accumulator d) timing and control unit

16. The ALE is used to provide multiplexing/demultiplexing of a) control signals c) input/output ports b) address bus d) none of these

17. The machine control operations are used to a) skip normal execution of program b) read a memory address

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c) continue normal execution of program

d) create a condition of high impedance

18. An assembly language program is translated to machine code by (a) an assembler (b) a compiler (c) an interpreter (d) a linker

19. An assembly language program is typically (a) non-portable (b) shorter than an equivalent HLL program (c) harder to read than a machine code program (d) slower to execute than a compiled HLL program

20. Programs are written in assembly language because they (a) run faster than HLL programs (b) are portable (c) easier to write than machine code programs (d) they allow the programmer access to registers or instructions that are not usually provided by a HLL.

UNIT-05 1.In 8085 the MAR, or .. register, latches the address from the program counter. A bit later
the MAR applies this address to the , where a read operations performed a) Memory address, ROM c) Memory address, PROM b) Memory address, RAM d) Memory address EPROM

2 How many outputs are there in the output of a 10-bit D/A converter? a) 1000 b) 1023 c) 1024 d) 1224

3 . The memory address of the last location of a 1K byte memory chip is given as OFBFFH what will be the address of the first location ?

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a) OF817H

b) OF818H

c) OF8OOH

d) OF801H

4. The No. of input output ports can be accessed by memory mapped method K 5. The maximum number of I\o devices can be interfaced with 8085 in the I\o mapped I\o technique are a) 128 b) 256 c) 64 d) 1024

6. The maximum number of I\o devices which can be interfaced in the memory mapped I\o technique are a) 256 b) 128 c) 65536 d) 32768

7. Shadow Address will exist in a) absolute decoding c) partical decoding b) linear decoding d) none of the above

8. The Instructions used for data transfer in I\o mapped I\O are a) IN, OUT c) STA add b) IN, LDA add d) None of the above

9. Number of Address lines required to interface 1KB of memory are a) 10 b)11 c) 12 d) 13

10. Memory mapped I/O involves (a) transferring information between memory locations (b) transferring information between registers and memory (c) transferring information between the CPU and I/O devices in the same way as between the CPU and memory (d) transferring information between I/O devices and memory

11. Busy waiting is a technique (a) to allow the CPU wait for a busy device

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(b) to allow a busy device wait for the CPU (c) to keep an idle device busy (d) improve CPU performance

12. A data movement instruction will a) modify the status register c) modify the program counter\ (b) modify the stack pointer d) transfer data from one location to another

13. The memory address register is used to store (a) data to be transferred to memory (c) the address of a memory location memory. (b) data that has been transferred from memory (d) an instruction that has been transferred from

14. The memory data register is used to store (a) data to be transferred to or from memory (b) data to be transferred to the stack (c) the address of a memory location memory (d) an instruction that has been transferred from

15. The instruction register stores (a) an instruction that has been decoded (b) an instruction that has been fetched from memory (c) an instruction that has been executed (d) the address of the next instruction to be executed

16. The program counter (a) stores the address of the instruction that is currently being executed (b) stores the next instruction to be executed (c) stores the address of the next instruction to be executed (d) stores the instruction that is being currently executed.

17. The stack pointer stores

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(a) the address of the stack in memory (b) address of the last item pushed on the stack (c) the address of the next free stack location (d) the address of the last item popped from the stack

18. The read/write line is (a) belongs to the data bus (c) belongs to the address bus (b) belongs to the control bus (d) CPU bus.

19. The instruction INR M where M is a memory variable involves (a) a memory read operation (b) a memory write operation

(c) a memory read and a memory write operation (d) only an arithmetic operation

20. Memory mapped I/O involves (a) transferring information between memory locations (b) transferring information between registers and memory (c) transferring information between the CPU and I/O devices in the same way as between the CPU and memory (d) transferring information between I/O devices and memory

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