Logic Design

Digital Logic Design
Nguyen Thanh Kien

Department of Computer Engineering
Faculty of Information Technology
Hanoi University of Technology
About
 Author: Nguyen Thanh Kien

 Office:
Department of Computer Engineering
Faculty of Information Technology
Hanoi University of Technology
 Mobile: +84 983 588 135
 Email: [email protected]
[email protected]
ftp://dce.hut.edu.vn/kiennt
Page  2
Content
1. Introduction
2. Function Minimization Methods
3. Larger Combinational Systems
4. Sequential Systems
5. Hardware Design Languages
Page  3
Acknowledge
 The following materials are used as reference for this slide:

– “Logic Circuits” slide, Dr. Trinh Van Loan.
– Introduction to Logic Design, 2nd Ed, Alan B. Marcovitz, Mc. Graw
Hill,2005
– Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott,
World Scientific, 1998
Page  4
Reference textbooks
 Introduction to Logic Design, 2nd Ed,, Alan B, Marcovitz, Mc.

Graw Hill,2005
 Foundation of Digital Logic Design, G.Langholz, A. Kandel, J.
Mott, World Scientific, 1998
Page  5
Grading policy
 Homework: 20%
 Lab work: 20%
 Midterm: 30%
 Final Exam (multichoice and writing): 30%
Page  6
1. Introduction
1.1. Review of Number Systems

1.2. Switching Algebra and Logic Circuits
Page  7
Chapter 1. Introduction
Page  8
1.1.1 Number Representation

1.1.2 Binary Addition
1.1.3 Signed Numbers
1.1.4 Binary Subtraction
1.1.5 Binary Coded Decimal (BCD)
1.1.6 Other Codes
Page  9
 1.1.1 Number Representation

 1.1.2 Binary Addition
 1.1.3 Signed Numbers
 1.1.4 Binary Subtraction
 1.1.5 Binary Coded Decimal (BCD)
 1.1.6 Other Codes
Page  10
1.1.1. Number Representation
 Numbers are normally written using a positional number system:
N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m

– Base/radix: b (the number of digits)
– Digits: 0..(b-1)
• 0 ≤ ai ≤ (b-1)
– Binary: b=2, digits:0,1

– Decimal: b=10, digits: 0,1,2,3,4,5,6,7,8,9
– Octal: b=8, digits: 0,1,2,3,4,5,6,7
– Hexadecimal: b=16, digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Page  11
N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m
N (10 ) = an .b n + an −1.b n −1 + ... + a1.b1 + a0 .b 0 + a−1.b −1 + ... + a− m .b − m
n
N (10 ) = ∑ a .b
i =− m
i
i
11101.11(2) = 1x24+1x23+1x22+0x21+1x20+1x2-1+1x2-2=
29.75(10)
Page  12
 Decimal:
– b=10
– Digits: 0,1,2,3,4,5,6,7,8,9
N (10 ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a−m ai = 0..9
– Eg:
539.45(10) = 5x102+3x101+9x100+4x10-1+5x10-2
Page  13
 Binary:
– b=2
– Digits: 0,1
bit – binary digit
N ( 2 ) = an an −1an −2 ...a1a0 .a−1a− 2 ...a−m ai = 0,1
– Eg:
N (10 ) = ∑ a .2
i =− m
i
i
1011.011(2) = 11 + 0*2-1 + 1*2-2+1*2-3=11 + 0 + 0.25 + 0.125

= 11.375(10)
Page  14
 Binary (cnt’)
– n-bit binary number can represent which range?
• an-1...a1a0 from 0 to 2n-1
– MSB – Most Significant Bit

– LSB – Least Significant Bit
0001 = 1 1001 = 9
0010 = 2 1010 = 10
0011 = 3 1011 = 11
0100 = 4 1100 = 12
0101 = 5 1101 = 13
0110 = 6 1110 = 14
0111 = 7 1111 = 15
1000 = 8
Page  15
 Octal:
– b=8 N (8) = an an −1...a1a0 .a−1a− 2 ...a− m
– Digits: 0,1,2,3,4,5,6,7
– Eg: ai = 0..7
503.071(8) = 5x82 + 0x81 + 3x80 + 0x8-1 + 7x8-2 + 1x8-3
 Hexadecimal:
N (16 ) = an an −1...a1a0 .a−1a− 2 ...a− m
– b=16
ai = 0..F
– Digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
– Eg:
1010 0011(2)= A3(16)
Page  16
503.071(16) = 5x162 + 0x161 + 3x160 + 0x16-1 + 7x16-2 + 1x16-3
Convert from base b to base 10
Base b to base 10 conversion

N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m
N (10 ) = an .b n + an −1.b n −1 + ... + a1.b1 + a0 .b 0 + a−1.b −1 + ... + a− m .b − m

Eg:0
– 1010.11(2)= 10.75
– 1010.11(8)= 0*80+1*81+0*82+1*83 + 1*8-
1
+1*8-2 = 0+8+0+512+0.125+0.015625
– A12(16)= 10572 = 2*160 + 1*161 + 10*162 =
Page  17
110.011(2)=?(10) 6.375
110.011(8)=?(10) 72.0175
110.011(16)=?(10) 272.039...
Page  18
Convert from base 10 to base b
 Base 10 to base b conversion

– For integer part:
• Divide integer part by b until the result is 0
• Write remainders in reverse order to get the converted result.
– For the odd part after “.”
• Multiply by b until the result is 0
Page  19
Convert from base 10 to base 2
 Eg1: 6.625(10) = ?(2)

– The integer part – The odd part after “.”
• 0.625 x 2 = 1.25
6 2 • 0.25 x 2 = 0.5
0 3 2 • 0.5 x 2 = 1.0
1 1 2
1 0 6.625(10) = 110.101(2)
 Eg2: 20.75(10) = ?(2)

Page  20
 20.75(10) = ?(2) 10100.11(2)
 20 2 0.75 * 2 = 1.5
 0 10 2 0.5 * 2 = 1.0
 0 5 2
 1 2 2
 0 1 2
 1 0
Page  21
 20.75(10)=?(8) =10100.11(2) = 24.6(8)
 20 8 0.75 * 8 = 6.0
4 2 8
 2 0
Page  22
Convert from base 2 to base 2n
 Group from right to left n-bit groups and replace the

equivalent values in base 2n
 Eg:
 101011(2) = ?(8) 1010.110(2)=12.6(8)

 101011(2) = ?(16) 1010.110(2)=A.C(16)
Page  23
Convert from base 2n to base 2
 Each digit in base 2n is replaced by n bit in base 2.
 Eg:
 37A.B(16)=?(2) = 0011 0111 1010 . 1011(2)
Page  24
Convert from base i to base j
 If both i and j are powers of 2, use base 2 as an intermediate

base:
– Eg: base 8 → base 2 → base 16
– 735.37(8)= 000111011101.01111100(2) = 1DD.7C ?(16)
 Else, use base 10 as an intermediate base:

– Eg: base 5 → base 10 → base 2
Page  25
 1.1.1 Number Representation

 1.1.2 Binary Addition
 1.1.3 Signed Numbers
 1.1.4 Binary Subtraction
 1.1.5 Binary Coded Decimal (BCD)
 1.1.6 Other Codes
Page  26
 Binary long addition similar to decimal long addition.

decimal binary
carry 110 11110
A 2565 10110
B 6754 11011
sum 9319 110001
Eg: 10101(2) + 11011(2) = 110000 ? (2)
Page  27
 Overflow:
– Occur when the result of addition is out of range of representation
(the result can not be stored in the predefined number of bits)
– In 8-bit computer, the result of addition of two binary numbers

10101010 and 11010011 is 9-bit binary number which can not be
stored in 8-bit => overflow
Page  28
 n-bit adder in computer:

 A = an-1an-2...a1a0
 B = bn-1bn-2...b1b0
Page  29

1.1.6 Other Codes
Page  30
 Represent sign and amplitude

 Use the most-left-bit to represent sign:
– 0: positive, 1: negative
 Eg: represent signed numbers using 4 bit:
– +5 = 0101, -5 = 1101, -3 = 1011
– Using 3 right bits to represent amplitude, we can represent from -7 to
+7.
– Drawbacks:
• +0 = 0000, -0 = 1000 => complex when calculating
Page  31 => need an other representation

2’s complement representation
 Most left bit is still sign bit

 Positive and 0 numbers are expressed in usual binary
format.
– The largest number can be represented is 2n-1-1
– n=8 => largest signed number: 28-1-1 = 127
 Negative number a is stored as the binary equivalent of 2n-
a in a n-bit system.
– -3 is stored as 28-3=11111101 in a 8-bit system
– The most negative number can be stored is -2n-1
Page  32
 +10 = 0000 1010

 - 10 = 28-10 = 1 0000 0000
– 0000 1010
1111 0110
- 10 = 1111 0110
 +10 + (-10) = ? 0000 1010

 1111 0110
 1 0000 0000
Page  33
 Procedure to find binary representation of negative number

in 2’s complement:
– Find the binary equivalent of the magnitude
– Complement each bit (0=>1, 1=>0)
– Add 1
 Eg: find representation of -13 in 8-bit signed number

system using 2’s complement:
• Magnitude: 13 = 0000 1101
• Complement: 1111 0010
• Add 1: 1
+
• -13 = 1111 0011
Page  34
 Range of representation:
– Use n bit to represent 2’s complement numbers
– Range: -2n-1 => 2n-1-1
Page  35
4 bit representation of unsigned and signed (2’s complement)
Binary format Unsigned Signed
0000 0 0
0001 1 +1
0010 2 +2
0011 3 +3
0100 4 +4
0101 5 +5
0110 6 +6
0111 7 +7
1000 8 -8
1001 9 -7
1010 10 -6
1011 11 -5
1100 12 -4
1101 13 -3
1110 14 -2
Page  36
1111 15 -1
 To find the magnitude of a negative number:

– Complement each bit
– Add 1
 Eg: 1001 0110(2) = -106?

 0110 1001
 + 1
 01101010 = 106
Page  37
Addition of signed numbers
 The reason that 2’s complement is so popular is the simplicity

of addition.
 To add any two numbers, no matter what the sign of each is,
we just do binary addition on their representation.
-5 1011 -5 1011 -5 1011
+7 0111 +5 0101 +3 0011
+2 0010 0 0000 -2 1110

Page  38
Addition of signed numbers
 Overflow
– Occur when?
– Add two numbers of the opposite sign?
– Add two positive numbers?
– Add two negative numbers?
maybe
⇒Overflow occurs when adding two numbers with the

same sign and the result is in different sign
0110 0101 = 101
+ 0101 0010 = 82
Page  39 1011 0111

1.1.6 Other Codes
Page  40
 Find the 2’s complement of the second operand, then add.

 a – b = a + (-b)
 Eg: 7 – 5 = ?
5 0101 7 0111
1010 -5 +1011
+ 1 2 0010
-5 1011
Page  41

1.1.6 Other Codes
Page  42
Binary-Coded Decimal - BCD
 BCD:
Decimal Binary BCD
– Use four bits (a nibble) to represent
0 0000 0000
each of the decimal digits 0 through
1 0001 0001
9.
2 0010 0010
– Eg:
3 0011 0011
375 = 0011 0111 0101(BCD) 4 0100 0100
5 0101 0101
6 0110 0110
7 0111 0111
8 1000 1000
9 1001 1001
10 1010 0001 0000
11 1011 0001 0001
12 1100 0001 0010
13 1101 0001 0011
14 1110 0001 0100

Page  43
15 1111 0001 0101

1.1.6 Other Codes
Page  44
ASCII
 American Standard Code for Information Interchange - ASCII

 Use seven bits to represent various characters on the
standard keyboard as well as a number of control signal
Page  45
Page  46
Problems
1. Convert the following unsigned numbers:

 98.625(10)=?(2)
 11011.011(2)=?(10)
 6A1.1E(16)=?(8)
2. Represent the following signed numbers:

a. -74 in 8-bit signed 2’s complement.
b. -74 in 16-bit signed 2’s complement.
Page  47
1. Introduction

Page  48
1.2.1 Definition of Switching Algebra

1.2.2 Basic Properties of Switching Algebra
1.2.3 Manipulation of Algebraic Functions
1.2.4 Representations of Algebraic Functions
1.2.5 Implementation of Functions with AND, OR, NOT, NAND,
NOR, XOR Gates
Page  49

NOR, XOR Gates
Page  50
 Switching algebra is binary:

– All variables and constant take on 0 or 1.
• Light on/off, switch: up/down, voltage: low/high...
– Quantities which are not naturally binary must be coded into binary
format.
– Three operators:
• OR: a+b
• AND: a.b
• NOT: a’
Page  51

NOR, XOR Gates
Page  52
Basic Properties of Switching Algebra
 P1: Commutative:
• a+b=b+a a.b = b.a
 P2: Associative:
• a + (b + c) = (a + b) + c a.(b.c) = (a.b).c
 P3:
• a+0=a a.1=a
 P4:
• a+1=1 a.0=0
Page  53
 P5:
• a + a’ = 1 a . a’ = 0
 P6: no coefficient and no exponent
• a+a=a a.a=a
• n.a=a (a)n=a
 P7: complement
• (a’)’ = a
 P8: distributive:
• a.(b+c) = a.b + a.c a + b.c = (a+b).(a+c)
Page  54

 P9: adjacency
• ab + ab’ = a (a+b)(a+b’)=a
 P10:
• a + a’b = a +b a(a’+b) = ab
 P11: De Morgan
• (a + b)’ = a’b’ (ab)’ = a’ + b’
 P12: absorption
• a + ab = a a(a+b) = a
Page  55
 P13: redundant
• ab+b’c+ac = ab+b’c
A B
Page  56
Problems
1. Prove the following equalities:

a. xy’+y=x+y
b. xy+xz’+yz=xy+x’z => prove it incorrect
c. x’y’z+yz+xz=z
d. (x+y)[x’(y’+z’)]’+x’y’+x’z’ = 1
Page  57

NOR, XOR Gates
Page  58
Manipulation of Algebraic Functions
 A literal:
– Is the appearance of a variable or its complement
– Eg: x and x’ are two different literals
– Expression ab’+bc’d+a’d+e’ has 8 literals
 A product term:
– Is one or more literal connected by AND operators
– Expression ab’+bc’d+a’d+e’has 4 product terms
– Note: A single literal is also a product term
Page  59

 A standard product term - minterm:
– Is a product term which includes every variable of the
function, either uncomplemented or complemented.
– Eg: for a function of four variables a,b,c,d:
• the product term a’bc’d is a standard product term
• the product term a’bd’ is not
Page  60

 A sum of product - SOP:
– Is one or more product terms connected by OR operators
– Eg: ab’c+abc’+a’c+a’
»d
 A canonical sum – sum of standard product term
– Is a sum of products expression where all terms are
standard product terms.
– Eg: A function of three variables a,b,c:
• ab’c + abc’ + abc is a canonical sum
• ab’c + abc’ + a is not
Page  61

 A minimum sum of products:
– Is one of those SOP expression for a function that has
the fewest number of product terms.
– If there is more than one expression with fewest number
of terms, then minimum is defined as one or more of
those expressions with the fewest number of literals.
– Eg:
• F1(x,y,z) = x’yz’+x’yz+ xy’z’+xy’z+xyz
• F2(x,y,z) = x’y+xy’+xyz
• F3(x,y,z) = x’y+xy’+xz
• F4(x,y,z) = x’y+xy’+yz
F3,F4 are minimum SOP of F1
Page  62

 A sum term:
– Is one or more literals connected by OR operators
– Eg:
• a + b’ + c’
• b’
 A standard sum term - maxterm:
– Is a sum term that includes each variable of the problem,
either uncomplemented or complemented
– Eg: For a function of four variables x,y,z,t
• x+y+z’+t’ is a maxterm
• x+y+t’ is not
Page  63

 A product of sum – POS:
– Is one or more sum terms connected by AND
– Eg:
• (w+x’+y’)(w+y+z’)(w+x+z)
•w
 A canonical product – product of standard sum
terms:
– Is a product of sum term where all sum terms are standard
Page  64

 A minimum POS is defined the same way as SOP:
– fewest number of terms
– the same number of terms => fewest number of literals
Page  65
Canonical forms
 Three-variable minterm and Maxterm
Decimal x y z minterm Maxterm

0 0 0 0 x’y’z’ (m0) x+y+z (M0)
1 0 0 1 x’y’z (m1) x+y+z’ (M1)
2 0 1 0 x'yz’ (m2) x+y’+z (M2)
3 0 1 1 x'yz (m3) x+y’+z’ (M3)
4 1 0 0 xy’z’ (m4) x’+y+z (M4)
5 1 0 1 xy'z (m5) x'+y+z’ (M5)
6 1 1 0 xyz' (m6) x'+y’+z (M6)
7 1 1 1 xyz (m7) x'+y’+z’ (M7)
Page  66
Canonical forms
 Properties of minterm/Maxterm:
– mimj=0 if i≠j
=mi if i=j
– Mi+Mj=1 if i≠j
= Mi if i=j
– mi=Mi’ and Mi=mi’ for every i
Page  67
Canonical forms
 An algebraic expression of a Boolean function can

be derived from a given truth table in two ways:
– By summing (ORing) those minterm for which the function
takes a value 1.
– By multiplying (ANDing) those maxterm for which the
function takes a value 0.
Page  68
Canonical forms
Decimal x2 x1 x0 f
0 0 0 0 0 f(x2,x1,x0)=m1+m4+m5+m6+m7
1 0 0 1 1 =Σ(1,4,5,6,7)
2 0 1 0 0 Canonical sum-of-products (SOP)
3 0 1 1 0
4 1 0 0 1
5 1 0 1 1
f(x2,x1,x0)=M0M2M3
6 1 1 0 1
7 1 1 1 1 = Π(0,2,3)
Canonical product-of-sums (POS)
Page  69
F(a,b,c)= abc’+a’b’
Decimal a b c f
0 0 0 0 1
1 0 0 1 1 F(a,b,c)=m0+m1+m6
2 0 1 0 0
3 0 1 1 0 – ∑(0,1,6)
4 1 0 0 0
5 1 0 1 0
6 1 1 0 1
7 1 1 1 0
Page  70

NOR, XOR Gates
Page  71
 Truth table
 Venn diagram
 Karnaugh map
Page  72
Truth table
 List all the possible binary combinations of the independent

variables and display the corresponding binary values of
dependant variables.
Page  73
Truth table
 n independent variables and m dependant functions:

2n rows
n+m columns 3 independent 2 dependent
variables functions
23 rows
Page  74
Venn diagram
 Venn diagram using ‘space’ to present logic

 F(A,B)=A.B
A B
F(A,B,C)=C.not(B)
Page  75
Venn diagram
A A
A+B A.B
A+B
A.B
Page  76
Karnaugh map
 A Karnaugh map is a graphical method for

representing the true table of a Boolean function.
 K-map may be used for any variables number, but
often at most six.
C
BC
AB
A 0 1
00 01 11 10
00 0 1
0 0 1 3 2
01 2 3
1 4 5 7 6 11 6 7
Page  77 10 4 5
Karnaugh map (K-map)
 If variables number is n => 2n cells in K-map.

 2n cells are arranged in logical pattern for minimization
purpose.
BC
A
00 01 11 10
0 0 1 3 2
1 4 5 7 6
Page  78
Two-variable K-map
 F(A,B)
B 0 1 A 0 1
A B
0 0 1 0 0 2
1 2 3 1 1 3
Page  79
Two-variable K-map
 F(A,B) = AB
B 0 1
A
0 0 0
1 0 1
Page  80
Three-variable K-map
 F(A,B,C)
BC
AB 0 1
A
00
00 01 11 10 0 1
0 0 1 3 2
01 2 3
11 6 7
1 4 5 7 6
10 4 5
Page  81
Three-variable K-map
 F(x,y,z) = xyz + yz’ + x
z
x y z F
0 0 0 0
yz xy 0 1
0 0 1 0
x 0 0
0 1 0 1 00 01 11 10 00
0 1 1 0 0 0 0 1
0 1 0
1 0 0 1 01
1 0 1 1 1 1 1 1 1 1
1 11
1 1 0 1
1 1 1 1 1 1
10
Page  82
Four-variable K-map
 F(A,B,C,D)
CD
AB
00 01 11 10
00
01
11
10
Page  83
Four-variable K-map
 F(A,B,C,D) = AB + CD’ + BCD
CD
AB
00 01 11 10
0 0 0 1
00
0 0 1 1
01
1 1 1 1
11
0 0 0 1
10
Page  84
Five-variable K-map
E 0 1
CD 00 01 11 10 CD 00 01 11 10
AB AB
00 00
01 01
11 11
10 10
5 variables Karnaugh Map consists of two

4 variables Karnaugh Map connected up/down.
Page  85
Six-variable K-map
F 0 1
E
CD 00 01 11 10 CD 00 01 11 10
AB AB
00 1 1 00 1 1
0
01 1 1 01
11 1 1 11 1 1
10 10 1 1
CD 00 01 11 10 CD 00 01 11 10
AB AB
00 1 1 00 1 1
1 01 1 1 01
11 1 1 11 1 1
10 10 1 1
Page  86
Karnaugh map with don’t care
CD
00 01 11 10
AB
00 1 1
01 1 1
11 − − − −
10 − −
don’t care ~ input conditions that not occur
Page  87

NOR, XOR Gates
Page  88
Basic logic gates
 AND OR NOT
A B out A B out
A out
0 0 0 0 0 0
0 1
0 1 0 0 1 1
1 0
1 0 0 1 0 1
1 1 1 1 1 1
Page  89
Basic logic gates
NAND NOR XOR
A B out A B out A B out

0 0 1 0 0 1 0 0 0
0 1 1 0 1 0 0 1 1
1 0 1 1 0 0 1 0 1
1 1 0 1 1 0 1 1 0
Page  90
Implementation of Functions with AND, OR
 Assume all inputs are available in uncomplemented and

complemented
F2 = x’y+xy’+xz
Page  91
F1 = x’yz’+x’yz+xy’z’+xy’z+xyz
Implementation of Functions with AND, OR, NOT
 Complemented inputs can be produced using inverters NOT:
Y F
Page  92
Multilevel circuits
 A circuit is called n-level circuit if the maximum number of

gates through which one signal must pass from input to
output
two-level circuit three-level circuit

Page  93
Implementation of Functions with NAND
 Using equivalent change steps, every expression can be

represented using only NAND gates.
OR
A
NOT
A B
A.B (A’.B’)’
=A+B
B
AND
Page  94
Implementation of Functions with NAND
 Represent the following expression using only NAND:

– F(a,b,c) = ab + bc’ + b’
=
ab + bc + b = ab + bc + b = ab.bc.b
Page  95
Implementation of Functions with NOR
 Using equivalent change steps, every expression can be

represented using only NOR gates.
U8A
A'
U7A
A 7402N ( A' +B' ) ' =A. B
U9A
7402N
B'
B 7402N U3A
A
7402N ( A+A) ' =A'

U10A U11A
Page  96 7402N 7402N

Implementation of Functions with NOR
 Represent the following expression using only NOR:

– F(a,b,c) = ab + bc’ + b’
Page  97
Chapter 2.
Logic Function Minimization Methods
Page  98
2.1 Algebraic Method

2.2 The Karnaugh Map Method
2.3 Quine-McCluskey Method
Page  99
 What is minimization?
– Number of operands is minimal and number of literal in each operand is
minimal
 Why minimization needed?
– Minimize electronic components used to construct the circuit to
implement that expression
Page  100

Page  101
2.1. Algebraic Method
 Use algebraic properties to minimize expressions
 Drawback:
– Heuristic, depending on experience – no formal method/procedure
– Manually
– Not sure whether the last expression is minimal or not
Page  102
2.1. Algebraic Method
 Eg: Minimize these expressions using algebraic method:

– F0(x,y,z)=xyz+x’yz+xy’z+xyz’
– F1(a,b,c,d)=ab+abc+a’cd+a’c’d+a’bcd’
– F2(A,B,C,D)= ( A + BC ) + A.( B + C )( AD + C )
– F3(x,y,z)=(x+y)(x+y+z’)+y’
– F4(a,b,c,d)=(a+b’+c)(a+c’)(a’+b’+c)(a+c+d)
Page  103

Page  104
1. Minimum Sum of Product Expressions Using the Karnaugh

Map
2. Don’t Cares
3. Product of Sums
4. Minimum Cost Gate Implementation
5. Five- and Six-Variable Maps
6. Multiple Output Problems
Page  105
Implicant, Prime Implicant
 An implicant of a function is a product term that can be used in a SOP
CD
AB
00 01 11 10 Implicants of F
00 1 1 Minterm Groups of 2 Groups of 4

A’B’C’D’ A’CD AB
A’B’CD BCD
01 1 A’BCD ABC’
ABC’D’ ABD
11 1 1 1 1 ABCD’ ABC
ABC’D ABD’
ABCD
10
Page  106
Implicant, Prime Implicant
 A prime Implicant is an implicant which can not be contained

in any other implicants.
CD
CD BC
AB
* 00 01 11 10
B D
00 1 1 1
01 1 1
B D*
11 1 1
AD
AB 10 1 1 1 1
Page  107
Essential Prime Implicant
 Essential PI is a PI which contains at least one minterm which

is not contained in other PI.
CD
CD BC
AB
* 00 01 11 10
B D
minterm 0 is only contained in PI B’D’ 00 1 1 1
minterm 5 is only contained in PI BD
=> BD & B’D’ are two Essential PI
01 1 1
B D*
11 1 1
AD
AB 10 1 1 1 1
Page  108
2.2.1 Minimum Sum of Product Expressions
 Rules to minimize using K-map:

– Rule 1: Fill K-map cells with corresponding values
– Rule 2: Group adjacent cells whose values are 1. Number of cells is 2n.
– Rule 3: Each group will be a part of result. Variables in each group will
be excluded: 2n cells => exclude n variables.
Page  109
 Step 2: Group adjacent cells whose values are 1. Number

of cells is 2n.
CD CD
AB AB
00 01 11 10 00 01 11 10
00 00 1 1
01 1 1 01 1 1
11 1 1 11 1 1
10 1 1 10 1 1
Page  110
 Step 3: Each group will be a part of result. Variables in each

group will be excluded: 2n cells => exclude n variables.
CD
AB
00 01 11 10
21 cells => eliminate 1 variable
00
01 1 1 F(A,B,C,D) = A’BC’ + AC
11 1 1
22 cells => eliminate 2 variables
10 1 1
Page  111
 Example 1: Minimize these functions using K-map:

– a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)
– b. F(A,B,C,D) = R(1,3,5,8,9,13,14,15)
– c. F(A,B,C,D) = R(2,4,5,6,7,9,12,13)
– d. F(A,B,C,D)= R(1,3,4,5,7,9,13,14,15)
– e. F(A,B,C,D)=R(1,3,4,6,9,11,12,14)
Page  112
– a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)
= BC’D + AB’D + BCD’ + A’B’D’
CD
AB
00 01 11 10
00 1 1
01 1 1
1
11 1
10 1 1
Page  113
– b. F(A,B,C,D) = R(1,3,4,6,9,11,12,14)
= B’D + BD’
CD
AB
00 01 11 10
1 1
00
1
01 1
1
11 1
10 1 1
Page  114
2.2 The Karnaugh Map
1. Minimum Sum of Product Expressions Using the Karnaugh

Map
2. Don’t Cares
3. Product of Sums
4. Minimum Cost Gate Implementation
5. Five- and Six-Variable Maps
6. Multiple Output Problems
Page  115
2.2.2 Don’t care
 If the function has don’t care values in cells:

– Cells with don’t care values
can be grouped with ‘1’ cells
– Do not group only don’t CD
00 01 11 10
AB
care cells in one group.
00 1 1
01 1 1
11 − − − −
10 − −
F ( A, B, C , D) = BC + BC
Page  116
Examples:
F(a,b,c,d)=R(1,3,5,7,12,13)
don’t care (0,4,10,15)
CD
AB
00 01 11 10
00 - 1 1
01 - 1 1
11 1 1 -
10 -
Page  117

Page  118
1. Quine-McCluskey Method for One Output

2. Iterated Consensus for One Output
3. Prime Implicant Tables for One Output
4. Quine-McCluskey for Multiple Output Problems
5. Iterated Consensus for Multiple Output Problems
6. Prime Implicant Tables for Multiple Output Problems
Page  119
2.3. Quine-Mcluskey method
Karnaugh map cannot handle more than 6 variables.

Quine-McCluskey method has no limitation with number of
variables, and is suitable for computer algorithm.
ABC+ABC+ABC+ABC+ABC
C 010 110 111 100 101

AB 0 1
00
01 1 *10 11* 1*0 1*1 10*
11 1 1
10 1 1
1**
Page  120
find a pair of numbers of 1 bit difference
Quine-Mcluskey Procedure
 1: Represent minterms in binary numbers

 2: Group each minterm by the number of ‘1’ appearance
 3: Make set of 1 bit different numbers between neighboring
group
• write the difference within parenthesis
• mark * to the number which is not included in a set
 4: Make set of 1 bit different sets with the same number in a
parenthesis
• append the difference to parenthesis
• mark + to the set which is not included in a set
 5: Iterate these step until all the generated set is marked *
 6: Select prime implicants
Page7: 121Convert to logic variable
S1. Represent minterms in binary numbers
f = ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF
+ABCDEF+ABCDEF +ABCDEF+ABCDEF+ABCDEF
f(A,B,C,D,E,F)=Σ(0,2,6,7,14,8,41,12,15,10)
f = 000000+000010+000110+000111+001110
+001000+101001+001100+001111+001010
Page  122
S2. Grouping
f = 000000+000010+000110+000111+001110
+001000+101001+001100+001111+001010
group each term by the appearance of 1

group 0 group 1 group 2 group 3 group 4
no times once twice three times four times
000000 000010 000110 000111 001111

001000 001100 001110
001010 101001
Page  123
S3 & S4. Making set (1)
group 0 000000 0 0,2 (2)

0,8 (8) find a pair of 1 bit difference
group 1 000010 2 between neighboring group
001000 8 2,6(4) write difference within ( )
2,10(8)
group 2 000110 6
8,10(2)
001010 10
001100 12 8,12(4) mark
to the number
6,7(1)
000111 7 not included in any set
group 3 6,14(8)
001110 14 10,14(4)
101001 41
12,14(2)
group 4 001111 15 7,15(8)
Page  124 14,15(1)
S3 & S4. Making set (2)
find a pair of 1 bit different sets

0,2 (2) 0,2,8,10(2,8) with the same value in ( )
0,8 (8) between neighboring group
append difference within ( )
2,6(4)
2,10(8) 2,6,10,14(4,8) Each pair appears in duplicate
8,10(2) 8,10,12,14(2,4)
8,12(4)
mark to the set
6,7(1)
not involved
6,14(8) in the next level set
10,14(4)
12,14(2) 6,7,14,15(1,8) when all the set is marked
finish
7,15(8)
14,15(1)
Page  125
S6. Selecting Prime Implicants (1)
minterms (given at first)

Prime implicant
0 2 6 7 8 10 12 14 15 41
41 x
0,2,8,10(2,8) x x x x
2,6,10,14(4,8) x x x x
8,10,12,14(2,4) x x x x
6,7,14,15(1,8) x x x x
（
　
marked
write x into the position where minterm is included

inevitable
in the prime implicant implicant
） If only one x in a column, then the row is inevitable implicant
Page  126
S6. Selecting Prime Implicants (2)
mini term
0 2 6 7 8 10 12 14 15 41
x
prime implicants
41
0,2,8,10(2,8) x x x x
2,6,10,14(4,8) x x x x
8,10,12,14(2,4) x x x x
6,7,14,15(1,8) x x x x
mark minterms involved in the

inevitable implicants inevitable
implicants
Page  127
S7. Conversion to logic variables
41 101001 ABCDEF
000000
000010 ABDF
0,2,8,10(2,8)
001000
001010
F=ABCDEF
001000 +ABDF
8,10,12,14(2,4) 001010 +ABCF
ABCF
001100 +ABDE
001110
000110
6,7,14,15(1,8) 000111 ABDE
Page  128
001110
001111
Examples:
 Minimize the following functions using Quine-

Mcluskey method:
– a.
F(a, b, c, d, e, f) = ab d ef + abce f + bcd f + ab d e f
– b. F(a,b,c,d,e,f) =
∑(17,21,25,29, 44,45,46,47,49,52,53,54,55,47,61)
Page  129
Quine-Mcluskey method with don’t care
 1: Represent logic function in sum of mini terms ==>A

 2: Represent don’t care in sum of mini terms ==>B
 3: If there exist duplication in A and B, remove from A
 4: Apply Quine-McCluskey method for A and B
 5: Be careful not to include B in selecting prime implicants
Page  130
f=ABCD+BCD+ACD+ABCD+ABCD
don’t care AD
mini term decimal first comparison second comparison
ABCD 0,1(1)
0000 0 0,2(2)
0,1,2,3(1,2)
0001 1 1,3(2)
0010 2 1,5(4)
0011 3 2,3(1) 1,3,5,7(2,4)
0101 5 3,7(4)
0111 7 3,11(8)
1011 11 5,7(2) 3,7,11,15(4,8)
1101 13 5,13(8) 5,7,13,15(2,8)
1111 15 7,15(8)
11,15(4)
Page  131
13,15(2)
0 2 11 13 15 ABCD
0,1,2,3(1,2) x x 00**
1,3,5,7(2,4) 0**1
3,7,11,15(4,8) x x **11
5,7,13,15(2,8) x x *1*1
f=AB+CD+BD
Page  132
Chapter 3.
Larger Combinational Systems
Page  133
Introduction
 Logic circuits are divided into two classes:

– Combinational logic circuits
• Output signals only depend on current input signals
• Memoryless circuits
– Sequential logic circuits
• Output signals not only depend on current input signals, but also
depend on those input signals in the past
• Memory circuits
Page  134
 3.1 Delay in Combinational Logic Circuits

 3.2 Adders and Other Arithmetic Circuits
 3.3 Decoders
 3.4 Encoders
 3.5 Multiplexers
 3.6 Demultiplexers
 3.7 Three-State Gates
 3.8 Gate Arrays-ROMs, PLAs and PALs
 3.9 Larger Examples
Page  135
3.1 Delay in Combinational Logic Circuits
 Delay through logic gates

– When the input to a gate changes, the output of that gate doesn’t
change immediately; but there is a small delay Δ.
– The output is stable after the longest delay path
A
X
B
F
C
Page  136

 3.3 Decoders
 3.4 Encoders
Page  137
Half Adder
a b Σ r
0 0 0 0 Σ=a ⊕
b
a
HA
Σ (Result) 0 1 1 0
b r (Carry-out) 1 0 1 0 r = ab
1 1 0 1
a =1
Σ
Half Adder b
&
r
Page  138
Addition of two n-bit numbers
r3 r2 r1 r0
A= a3 a2 a1 a0
+B = b3 b2 b1 b0
r4 Σ3 r3 Σ2 r2 Σ1 r1 Σ 0
Summation Σ4 Σ3 Σ2 Σ1 Σ0
Page  139
Full Adder
Σi
ai Σi aibi
FA 00 01 11 10
ri ri
bi ri+1
0
1 1
1
ai bi ri Σi ri+1 1 1
0 0 0 0 0
aibi ri+1
0 0 1 1 0 ri 00 01 11 10
0 1 0 1 0
0
1
0 1 1 0 1
1 0 0 1 0 1
1 1 1
1 0 1 0 1
1 1 0 0 1
Σi = ai ⊕ bi ⊕ ri
1 1 1 1 1
ri+1 = ai bi + ri (ai ⊕ bi)
Page  140
Combinational logic circuit design procedure
 Problems: design a combinational logic circuit to do smth.

 Design procedure:
– S1: Find inputs, outputs and relations.
– S2: Construct truth table
– S3: For each output, using K-map to minimize from truth table.
– S4: Draw the circuit.
Page  141
Example 1
 Problem: Design a combinational logic circuit to implement

this operation: M=N+3, N is 3-bit binary number, the number
of bit of M is selected properly.
 Solution:
– S1: three inputs: n2n1n0
four outputs: m3m2m1m0
Page  142
Example 1
 S1: three inputs: n2n1n0

four outputs: m3m2m1m0
n2 m3
 S2: truth table n1 m2
n0 m1
m0
n2 n1 n0 m3 m2 m1 m0
0 0 0 0 0 1 1  S3:
0 0 1 0 1 0 0
0 1 0 0 1 0 1
m3 = n2n0 + n2n1
0 1 1 0 1 1 0
n1n0 00 01 11 10
1 0 0 0 1 1 1 n2
1 0 1 1 0 0 0
0 0 0 0 0
1 1 0 1 0 0 1
1 0 1 1 1
1 1 1 1 0 1 0
Page  143
Example 2
 Problem: design a combinational logic circuit to calculate

square of a 2-bit binary number.
 Solution:
– Step1: find inputs, outputs
• Inputs: a1,a0
• Outputs: b3,b2,b1,b0
Ex2
Page  144
Example 2
– Step 2: truth table
a1 a0 b3 b2 b1 b0
0 0 0 0 0 0
0 1 0 0 0 1
1 0 0 1 0 0
1 1 1 0 0 1
– Step3: using K-map to minimize outputs

• b3 = a1.a0 b1 = 0
• b2 = a1.a0’ b0 = a0
Page  145
Example 2
– Step 4: Draw circuit

• b3 = a1.a0 b1 = 0
• b2 = a1.a0’ b0 = a0
X1
2.5 V
b3 X2
U1A
2.5 V
J1
b2 X3
a1 7408N
V1Key = A R1 U1B 2.5 V

5V 100
b1 X4
a0
7408N 2.5 V
b0
U2A
J2
7404N
V2Key = B R2
12 V 100
Page  146
Full Adder
ri
=1 =1
ai Σi
bi
& &
≥1
ri+1
Page  147
Full Adder
ri
=1 =1
ai Σi
bi
HA HA
& &
≥1
ri+1
Page  148
n-bit Adder
 Serial n-bit adder

A = an-1an-2...a1a0 , B = bn-1bn-2...b1b0
an-1 bn-1 an-2 bn-2 a1 b1 a0 b0

rn-1 rn-2 r1 r 0= 0
FA FA FA FA
rn
r2
Σn Σ n-1 Σ n-2 Σ1 Σ0
Page  149 Delay = n x Δ?

n-bit Adder
 Parallel n-bit adder:
ri+1 = aibi + ri(ai ⊕ bi)

Pi = ai ⊕ bi and Gi = aibi → ri+1 = Gi + ri Pi
G0 ≥ 1 r1
r1 = G0 + r0P0
G1 ≥ 1 r2
P0 &
r0
G0 & τ1 τ2
P1
&
r2 = G1 + G0P1 + r0P0P1
P0
r0
Page  150
τ1 τ2
Parallel 4-bit addition
a3 b3 a2 b2 a 1 b1 a0 b0 r0
Calculate Pi and Gi
P3 G3 P2 G2 P1 G1 P0 G0
Carry calculation
r4 r3 r2 r1 r0
a 3 b3 a2 b2 a1 b1 a0 b0
Sum calculation
r4 = Σ 4 Σ3 Σ2 Σ1 Σ0
Page  151
Subtractor
 To subtract a-b, simply add a to 2’s complement of b.
 Second choice:
Half Subtractor => Full Subtractor => n-bit Subtractor
Page  152
Subtractor
 Subtractor by using 2’s complement
B3 B2 B1 B0
A3 A2 A1 A0
A B A B A B A B
C4 C+ FA C C+ FA C C+ FA C C+ FA C 1
S
C3 S
C2 S
C1 S
S3 S2 S1 S0
Page  153
Adder and Subtractor
A3 B3 A2 B2 A1 B1 A0 B0
MPX MPX MPX MPX

sel
A B A B A B A B
C4 C+ FA C C+ FA C C+ FA C C+ FA C
S
C3 S
C2 S
C1 S
S3 S2 S1 S0
Page  154

 3.3 Decoders
 3.4 Encoders
Page  155
Decoder
 An nxm decoder is a combinational circuit that converts

binary information from n input lines to m output lines, where
m≤2n.
– m = 2n => complete decoder
 Fundamental property: only one output is 1 for any given

input combination.
Page  156
Decoder
 Complete decoders: m=2n
D0
x1
D1 D0
x2
. . x1
nxm 3x8 .. D1
. decoder .
x2
decoder
.
. x3
xn . Dm-1
D7
Eg:
+ 3 bit inputs x1,x2,x3.
+ 8 bit outputs Y0,Y1…Y7
Page  157
Design 3x8 decoder
D0
x1
x2
3x8 .. D1
x3
decoder
. D7
En
if (En=0)
Disable or D0...D7=0
else if (En=1)
Function as a 3x8 decoder
Page  158
BCD-to-decimal decoder
N A B C D Y0 Y1 . Y9
.
0 0 0 0 0 1 0 . 0
.
1 0 0 0 1 0 1 . 0
Y0 .
2 0 0 1 0 0 0 . 0
A BCD Y1 .
B to : 3 0 0 1 1 0 0 . 0
C .
decimal Yi 4 0 1 0 0 0 0 . 0
D Decoder : .
5 0 1 0 1 0 0 . 0
Y9 .
6 0 1 1 0 0 0 . 0
.
7 0 1 1 1 0 0 . 0
.
8 1 0 0 0 0 0 . 0
.
9 1 0 0 1 0 0 . 1
Page  159
BCD-to-decimal decoder
Y0  A B C D Y1  A B C D
CD
AB
00 01 11 10 Y2  BCD
00 1 Y3  BCD
01 Y4  BC D
Y5  BC D
11 − − − −
Y6  BC D
10 − −
Y7  BCD
Y8  AD
Y9  AD
Page  160
Decoder
 4x16 decoder using two 3x8 decoders
D0
x2
x3
3x8 .. D1
x4
decoder
. D7
x1
D8
3x8 .. D9
decoder
. D15
Page  161
Decoder implementation of arbitrary functions
D0 F1
D1
D2
D3
D4
D5
x1 D6
4x16 D7
x2
D8
decoder
x3 D9
D10
x4 D11
D12
D13
D14
D15
F1(x1,x2,x3,x4)=Σ(0,1,3,8,12)
Page  162
BCD-to-7segment decoder
a
f g b
N A B C D a b c d e f g
e c 0 0 0 0 0 1 1 1 1 1 1 0
d 1 0 0 0 1 0 1 1 0 0 0 0
Each segment is a Light 2 0 0 1 0 1 1 0 1 1 0 1
Emitting Diode (LED) 3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
A K 6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
Page  163
BCD-to-7segment decoder
CD
AB
00 01 11 10 &
B
00 1 0 1 1 D
01 0 1 1 1
11 − − − − &
≥1
10 1 1 − − A
C
a  A  C BD  B D
Page  164

 3.3 Decoders
 3.4 Encoders
Page  165
Encoder
 An encoder is a circuit that performs the function of a decoder in reverse.

 An mxn encoder has m inputs, n outputs where m≤2n. The outputs
generate the binary codes corresponding to m inputs.
 For example: encoder for PC’s keyboard

Key <=> Character <=> Key code
102 keys, 8 bit ASCII
Page  166
Keyboard encoder
‘1’ P1
1
P2 A
2
B
Pi N=i
i Encoder
C
P9 D
9
 9 keys
 4-bit key code.
Page  167
Keyboard encoder
N ABCD
1 0001
2 0010 A = 1 if (N=8) or (N=9)

3 0011
B = 1 if (N=4) or (N=5) or (N=6)
or (N=7)
4 0100
C = 1 if (N=2) or (N=3) or (N=6)
5 0101
or (N=7)
6 0110
D = 1 if (N=1) or (N=3) or (N=5)
7 0111 or (N=7) or (N=9)
8 1000
9 1001
Page  168
Keyboard encoder
N=1
≥ 1
D
N=2
N=3
≥ 1
N=4 C
N=5
N=6 ≥ 1
B
N=7
N=8 ≥ 1
A
N=9
Page  169

 3.3 Decoders
 3.4 Encoders
 3.5 Multiplexors
 3.6 Demultiplexors
Page  170
Multiplexor
 Multiplexor has one output and more than one input.

 Function: select one of input for output
MUX 2-1 MUX 4-1

X0
X0 X1 Y
Y
X2
X1 X3
C0 C0
C1
control inputs C1 C0 Y
C0 Y 0 0 X0
0 X0 0 1 X1
1 0 X2
Page  171
1 X1
1 1 X3
2-to-1 Multiplexor
MUX 2-1
C0 X1 X0 Y
X0
Y
C0 Y 0 0 0 0
X1 0 X0 0 0 1 1
0 1 0 0
1 X1
C0
0 1 1 1
X1X0
1 0 0 0
C0 00 01 11 10
1 0 1 0
0 1 1 1 1 0 1
1 1 1 1
1 1 1
Y  X0C 0  X1C 0
Page  172
2-to-1 Multiplexor
Page  173
4-to-1 Multiplexor
Y = s1’s0’I0 + s1’s0I1 +s1s0’I2+ s1s0I3
Page  174
Application of multiplexor
 Select source
Source 1 Source 2
A = a3 a2 a1 a0 B = b3 b2 b1 b0
C0
Receiver
Y3 Y2 Y1 Y0
Page  175
 Convert parallel-serial
A
C0
a0 1
a1 Y
0
a2 C1 t
a3 1
0
t
C0 Y
C1 a0 a1 a2 a3
Page  176
 Implementation of arbitrary functions:
f(A,B)  A Bf(0,0)  A Bf(0,1)  A Bf(1,0)  A Bf(1,1)
Y  C1C 0X 0  C1C 0X1  C1C 0X 2  C1C 0X 3
f(0,0) x0
f(0,1) x1 Y = f(A,B)
Inputs to
select f(1,0)
function
x2
f(1,1)
x3
C1 C0
A
Page  177 Variables
B
Example
0 x0
1 x1 Y = f(A,B)
Inputs to
select 1
function
x2
0
x3
C1 C0
A
Variables
B
 F(A,B) = A’B + AB’
Page  178

 3.3 Decoders
 3.4 Encoders and Priority Encoders
Page  179
Demultiplexor
 Demultiplexor has one input and more than one output

 Function: select one of outputs for input
DeMUX 1-2
S0
S1
C0
S 0 = C0 E
S1 = C0 E
Page  180
Demultiplexor 1-4
S0
S1
E
S2
S3
C1
C0
Page  181

 3.3 Decoders
Page  182
3.7 Three-State Gates (Tristate)
 Three state gates exhibit three states instead of two states.

The three states are:
– High : 1
– Low : 0
– High impedance : z
• In this state the output is disconnected which is equal to open circuit.
In the other words in that state circuit has no logic significant. We can
have AND or NAND three-state gates but the most common is three-
state buffer gate
Page  183
3.7 Three-State Gates (Tristate)
 We may use conventional gates such as AND or NAND as

three-state gates but the most common is three-state buffer
gate.
 Note that buffer produces transfer function and can be used
for power amplification. Three state buffer has extra input
control line entering the bottom of the gate symbol (see next
slide)
Page  184
Three-State buffer
Three-state buffer
C A Y
----------------------
0 0 z
0 1 z
7 0 0
1 1 1
Page  185
Application of three-state buffer
 Three-state buffers can be used to implement

multiplexer
Page  186

 3.3 Decoders
 3.8 Gate Arrays - ROMs, PLAs and PALs
Page  187
3.8 Gate Arrays - ROM, PLA and PAL
 PLA - Programmable Logic Arrays

 PAL - Programmable Array Logic
 ROM
Page  188
PLA - Programmable logic arrays
 Pre-fabricated building block of many AND/OR gates

– actually NOR or NAND
– "personalized" by making or breaking connections among the gates
– programmable array block diagram for sum of products form
A B C Z1 Z2 • • •
m0 0 0 0 0 1 inputs
m1 0 0 1 0 0
m2 0 1 0 1 1
m3 0 1 1 0 0 OR
m4 1 0 0 0 1 AND
product array
m5 1 0 1 1 0 array
terms
m6 1 1 0 1 1
m7 1 1 1 1 0
outputs
Page  189 • • •
Before programming
 All possible connections are available before "programming"

– in reality, all AND and OR gates are NANDs
Page  190
After programming
 Unwanted connections are "blown"

– fuse (normally connected, break unwanted ones)
– anti-fuse (normally disconnected, make wanted connections)
A B C
AB
B'C
AC'
B'C'
Page  191
F0 F1 F2 F3
PLA example
 Multiple functions of A, B, C
– F1 = A B C full decoder as for memory address
– F2 = A + B + C bits stored in memory
A B C
– F3 = A' B' C'
A'B'C'
– F4 = A' + B' + C'
A'B'C
– F5 = A xor B xor C A'BC'
– F6 = A xnor B xnor C A'BC
AB'C'
A B C F1F2F3F4F5 F6
AB'C
0 000 0 1 1 0 0
0 010 1 0 1 1 1 ABC'
0 100 1 0 1 1 1 ABC
0 110 1 0 1 0 0
1 000 1 0 1 1 1
1 010 1 0 1 0 0 F1 F2 F3 F4 F5
1
Page  192 100 1 0 1 0 0 F6
PALs and PLAs
 Programmable logic array (PLA)

– what we've seen so far
– unconstrained fully-general AND and OR arrays
 Programmable array logic (PAL)
– constrained topology of the OR array
– innovation by Monolithic Memories
– faster and smaller OR plane
a given column of the OR array

has access to only a subset of
the possible product terms
Page  193
ROM – Read Only Memories
 Two dimensional array of 1s and 0s

– entry (row) is called a "word" word lines (only one
is active – decoder is
– width of row = word-size just right for this)
– index is called an "address" 1 1 1 1

– address is input
n
– selected word is output 2 -1
Example: i word[i] = 0011
10 address x 8 data ROM decoder
210 words x 8 ROM j word[j] = 1010
1024 words x 8 ROM
1k x 8 ROM 0
internal organization
0 n-1
Address
bit lines (normally pulled to 1 through
resistor – selectively connected to 0
Page  194
by word line controlled switches)
ROM – Read Only Memories
 Combinational logic implementation (two-level canonical

form) using a ROM
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A B C F0 F1 F2 F3
0 0 0 0 0 1 0 ROM
0 0 1 1 1 1 0 8 words x 4 bits/word
0 1 0 0 1 0 0
0 1 1 0 0 0 1
1 0 0 1 0 1 1
1 0 1 1 0 0 0 A B C F0 F1 F2 F3
1 1 0 0 0 0 1 address outputs
1 1 truth
1 0 table
1 0 0 block diagram
Page  195
ROM structure
 Similar to a PLA structure but with a fully decoded AND array

– completely flexible OR array (unlike PAL)
n address lines
• • •
inputs
memory
decoder 2n word
array
lines (2n words
by m bits)
outputs
• • •
m data lines
Page  196

 3.3 Decoders
Page  197
3.9 Larger Examples
 1. Seven-segment displays
 2. Comparator
Page  198
Comparator
 1-bit full comparator:
Gi
ai 1bit
Full Li
bi Comparator
Ei
ai > bi Gi=1 Gi = ai .bi

ai < bi Li=1 Li = ai .bi
ai = bi Ei=1
Ei = ai ⊕ bi
Page  199
Comparator
 N-bit parallel comparator:
Page  200
Midterm examination (90’)
 1. Represent the following function in the canonical form SOP:

F(A,B,C)=(A+B’)C
 2. Use the Quine-McCluskey method to obtain the minimal sum for the
following function:
F(A,B,C,D,E)= ∑(1,4,6,7,8,9,10,11,15)
 3. Design 4x16 decoder using only 2x4 decoders.
 4. Design a combinational logic circuit to calculate the following function:
M=N+3 where N is BCD number (Binary-Coded Decimal).
Page  201
Midterm examination 2 (90’)
 1. Represent the following function in the canonical form SOP and POS:
F(A,B,C)=C
 2. Use the Quine-McCluskey method to obtain the minimal sum for the
following function:
F(A,B,C,D,E)= ∑(1,4,6,7,8,11,12,13,15)
 3. Using 3x8 decoder to implement the following function:
F(A,B,C) = AB + B’C
 4. Design a combinational logic circuit to calculate the following function:
M=N+5 where N is BCD number (Binary-Coded Decimal).
Page  202
Chapter 4.
Sequential Systems
Page  203
 4.1 Definitions
 4.2 State Tables and Diagrams
 4.3 Latches and Flip Flops
 4.4 Analysis of Sequential Systems
 4.5 Design of Sequential Systems
 4.6 Solving Larger Sequential Problems
Page  204
4.1 Definitions
 Combinatorial circuit is memoryless.
 In a circuit with memory, an output value at tn+1 must be a

function not only of the inputs at tn+1 but also of the outputs at
tn .
 To achieve this, the circuit must have some feedback
connections from its outputs to its inputs.
A circuit with memory is a combinatorial circuit

Page  205 incorporating some feedback connections.
Feedback and memory devices
 To implement feedback, signals are fed back from outputs to

inputs using memory devices.
 A memory device stores an output value at time tn so that it
can be input to the circuit at tn+1.
 But then, output at tn depends on input at tn-1, which in turn
depends on tn-2…
The circuit maps input sequences to output sequences
Page  206
Sequential circuit model
 Circuits with memory are called sequential circuits.
x1 z1
Circuit inputs
x2
.. .. z2
Circuit outputs
. Combinatorial
circuit
.
xn
yk Memory Yk
device
.. Next state
Present state
.
y1 Memory Y1
Page  207 device
Sequential circuit model
 Mealy model:
• X : finite inputs. m inputs: x1,x2...,xm
• S : finite states. n states: s1,s2...,sn
• Y: finite outputs.l outputs: y1,y2...,yl
• Fs: state function. s = Fs(X,S)
• Fy : output function. y = Fy(X,S)
 Moore: ~Mealy
• Difference: Fy = Fy(S)
Page  208
Asynchronous/Synchronous sequential circuits
 The timing of the signal in the circuit determine two types of

sequential circuits:
– Synchronous
– Asynchronous.
Page  209
Synchronous sequential circuits
 In a synchronous sequential circuit, the state can change only at

discrete instants of time.
 To achieve that, the circuit uses a timing device, called a clock
generator, that produce trains of periodic or aperiodic clock pulses.
 The clock pulses are input to the memory devices so that they can
change state only in response to the arrival of a pulse and only
once for each pulse occurrence.
The operation of the circuit is synchronized with the clock pulse input.
Page  210
Asynchronous sequential circuits
 The behavior of an asynchronous sequential circuit depends

only on the order in which the inputs change and can be
affected at any instant of time.
 There is no timing device in asynchronous sequential circuit
(unclocked memory).
Page  211
 4.1 Definitions
Page  212
State diagram
 Depict graphically the operation of a sequential circuit.

– Mealy state diagram
0/0
0/0
0/0 1/0 0/0

a b c d
1/0 1/1
Page  213
Example of state diagram
 Example: a sequential circuit is used to detect the string

“0101” from one input.
1 /0 0 /0
0 /0
0 /0 1 /0 0 /0
A B C D
1 /0
1 /1
Page  214
State diagram
 Depict graphically the operation of a sequential circuit.

– Moore state diagram
1
a/0
0 0
1
0
f/1 b/0
0 1
e/1 c/0
1
1
0
1 d/0
Page  215
0
State table
 State table presents in a tabular form the same information

contained in the state diagram.
– Mealy state table
– Moore state table
Page  216
Mealy state table
0/0
0/0
PS: Present State

0/0 1/0 0/0
NS: Next State a b c d
1/0 1/1
PS NS Output (z)
x=0 x=1 x=0 x=1

PS NS/Output (z)
a b a 0 0 x=0 x=1
b b c 0 0 a b/0 a/0
b b/0 c/0
c d a 0 0
c d/0 a/0
d b c 0 1 d b/0 c/1
k memory devices => 2k rows

n circuit inputs => NS portion contains 2n columns
Page  217
Output portion also contains 2n columns
Moore state table
PS NS Output a/0
0
1 0
0
x=0 x=1 z
f/1 b/0
a b a 0
b b c 0 0 1
c d c 0
e/1 c/0
1
d d e 0
1
0
e f e 1 1 d/0
f f a 1
0
The output portion always contains a single column.
The entry at the intersection of any row with the output column indicates the
output values corresponding to the PS associated with that row.
Page  218
Incompletely specified Mealy state table
 Two inputs: x1,x2

 A single output: z
PS NS/Output (z)
00 01 11 10
a -/- c/1 b/- e/1
b e/0 -/- -/- -/-
c f/0 f/1 -/- -/-
d a/- -/- e/- b/1
e -/- f/0 d/1 a/0
f c/0 -/- c/1 b/0
Page  219
 4.1 Definitions
Page  220
4.3. Latches and Flip-Flops
 Simplest memory devices: Delay element
Yi yi
ΔT Yi
yi
yi(t+ΔT) = Yi(t)
ΔT
In practice, we don’t have to actually insert delay elements

because propagation time delays between the inputs and
the outputs of the combinatorial part of the circuit provide
sufficient delay across the feedback loops.
Page  221
 Bistable devices:
– Two stable states:
• Q=0 : the device is reset (reset state)
• Q=1: the device is set (set state)
– A bistable device remains in one of two states indefinitely until directed
by an input signal to change state.
– Two types:
• Latch
• Flip-flop
Page  222
 Latch: transparency property:

– Change state when the input values change
– The new output state is delayed only by the propagation time delays of
the gates between inputs and outputs of the latch.
– Used to implement the memory part of asynchronous circuits.
 Flip-flop: no transparency property
– Has a control (triggering) input, called clock.
– The state change only in response to a transition of a clock pulse at
clock input.
– Used to implement memory part of synchronous circuits
Page  223
SR Latch
 Two inputs: S (set), R (reset)

 Two complementary outputs: Q, Q’
S Q
Current state
S R Q Q+
R Q’ Next state
0 0 0 0
S Q
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
Q' 1 0 1 1
R
1 1 0 -
Indeterminate
1 1 1 -
Q = (R+Q’)’
Page  224
Q’= (S+Q)’
SR Latch S Q
R Q’
S Q
S R Q+
0 0 Q
0 1 0
1 0 1
Q'
1 1 Indeterminate R
Equivalent characteristic table
SR=’00’ => Output no change

A logic ‘1’ at inputs can change outputs’ states
=> active-HIGH latch
Page  225
SR Latch
S Q S Q
R Q’ R Q’
S Q
Q
S
Q' R
R
Q'
active-HIGH SR Latch active-LOW SR Latch
Page  226
SR Latch
 Timing chart (NOR implementation)
S
S
Q
R
R
Q' Q
Q
set reset set reset
Page  227
SR Latch
 Timing chart (NAND implementation)
Q S
S
R
R Q
Q'
Q
set reset set reset
Page  228
SR Latch
R
Q Q Q+ S R
0 0 0 -
S
0 1 1 0
1 0 0 1
1 1 - 0
Circuit showing feedback

Excitation table
Q+ = R’Q + R’S
SR=0 => Q+ = R’Q + R’S + RS = R’Q + S
for active-HIGH SR Latch
Page  229
D Latch
D
D Q S Q
Q’ R Q’
Graphic symbol Implementation using SR Latch
Q Q* D
D Q*
0 0 0
0 0
0 1 1
1 1
1 0 0
1 1 1
Equivalent characteristic table
Excitation table
Page  230
Q* = D
Gated Latches
S Q
E: Enable input control
E
The latch will not change state as long as E=0
R Q’
E=1 SR=10 => Set
E=1 SR=01 => Reset
S
Q ⇒The operation of latch is synchronized
with the E input => E: synchronous input
E
A latch with synchronous input is called
gated latch.
R
Q'
Page  231
Flip-flops
 Latches implement memory part in asynchronous sequential

circuits
 Flip-flops do the same for synchronous circuits. FF has clock
input and changes state synchronously with clock.
 Four common types of flip-flops:

– SR
– D
– JK
– T
Page  232
SR flip-flop
S Q S Q S Q
CLK CLK CLK
R Q R Q R Q
Positive edge-triggered Negative edge-triggered Pulse-triggered

(Master-Slave)
 The triangle called dynamic indicator, indicates that the

device responds only to an input clock transition from LOW
(0) to HIGH (1) => Positive edge-triggered
 Appending a small circle to the CLK input indicates that the
flip-flop responds only to an input clock transition from HIGH
(1) to LOW (0) => Negative edge-triggered
Page  233
SR flip-flop
 The information is entered on the leading edge of

S Q the clock pulse, but the flip-flop does change state
(the output is postponed) until the trailing edge of
CLK
the clock pulse.
R Q’
Pulse-triggered
(Master-Slave)
Difference between Latch and Flip-flop?

• The flip-flop can not change state except on the
triggering edge of clock pulse => synchronous
• Present and next states in a latch are separated
In time by gate delays, they are separated by clock
periods in a flip-flop.
Page  234
SR flip-flop
Current state
Next state
S R Q Q(t+1)
Q Q(t+1) S R
0 0 0 0
S R Q(t+1) 0 0 0 -
0 0 1 1
0 0 Q(t) 0 1 1 0
0 1 0 0
0 1 0 1 0 0 1
0 1 1 0
1 0 1
1 0 0 1 1 1 - 0
1 1 Indeterminate
1 0 1 1
1 1 0 - Reduced characteristic table Excitation table
1 1 1 -
Indeterminate
Characteristic table
(S=1 & R=1) is inhibited

Page  235
Q(t+1) = R’Q(t) + S
Implementation of SR-FF
S Q
CL
Q
R
Implementation of SR-FF by SR-Latch
S S 　 Q
CL Q
SR-latch
R 　 Q
R
Q
Page  236
SR flip-flop
 Timing chart
S
S Q R
CLK CL
R Q
Q
Q
Page  237
D flip-flop
D
D Q S Q
CLK CLK
CLK
Q’ R Q
Positive edge-triggered D flip-flop Implementation using SR flip-flop
 D flip-flop is useful for storing a single bit
Page  238
D flip-flop
Current state
Next state
Q Q(t+1) D
D Q Q(t+1) 0 0 0
0 0 0
0 1 1
D Q(t+1)
0 1 0
0 0 1 0 0
1 0 1
1 1 1 1 1
1 1 1
Characteristic table Excitation table

Reduced characteristic table
Q(t+1) = D
Page  239
JK flip-flop
J Q S Q
CLK CLK
K Q’ R Q
Positive edge-triggered JK flip-flop Implementation using SR flip-flop
 JK = 00 => Q* = Q REMEMBER
 JK = 01 => Q* = 0 RESET
 JK = 10 => Q* = 1 SET
 JK = 11 => Q* = not(Q) INVERT
Page  240
JK flip-flop
Current state
Next state
J K Q Q(t+1)
Q Q(t+1) J K
0 0 0 0
J K Q(t+1) 0 0
0 0 1 1 0 -
0 0 Q(t) 0 1
0 1 0 0 1 -
0 1 0
0 1 1 0 1 0 - 1
1 0 1
1 0 0 1 1 1
1 1 [Q(t)]’ - 0
1 0 1 1
1 1 0 1 Reduced characteristic table Excitation table
1 1 1 0
Characteristic table
Page  241
Q(t+1) = K’Q + JQ’
Master-Slave flip-flop
 A pulse-triggered flip-flop is a bistable device

– states depend on the values of synchronous inputs at the leading edge
of the clock pulse
– those states does not change until the trailling edge of the clock pulse.
Page  242
Master-Slave flip-flop
Master Slave
S S Q S Q Q
C E E
R R Q’ R Q’ Q’
Master latch works when C=1

Slave latch works when C=0
 A pulse-triggered flip-flop consists of two latches, where one acts as a

master and the other acts as a slave => Master-slave flip-flop
Page  243
Edge-Triggered flip-flop
 A edge-triggered flip-flop is a bistable device whose state

depends on the synchronous inputs either at the positive
edge or at the negative edge of a clock pulse.
Page  244
Y1
Q
CLK
Q
Y2
Positive edge-triggered D flip-flop

Page  245
Q
CLK
Q
Positive edge-triggered JK flip-flop

Page  246
Flip-Flop conversions
Each FF can mutually converted

How to implement y-FF by using x-FF
(1) Prepare expanded state table of y-FF
(2) Prepare excitation table of x-FF
(3) Combine (1) and (2)
(4) Calculate logic function for each input of x-ff
circuit
combinatorial
a　 Q
input of y-FF Q 　　
CL x-FF
b Q Q
Page  247
CL
 Example: Implement T-FF using SR-FF
SR-FF T-FF
S R Q Q+ T Q Q+
0 0 0 0 0 0 0
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 1 0 1 1 0
1 0 0 1
1 0 1 1
Expanded state table shows the
1 1 0 -
state
1 1 1 -
transition by the input
Page  248
expanded state table excitation table

SR-FF
S R Q Q+ state 　　　　　 input
0 0 0 0 Q 　　 Q+ 　　 S 　　 R
0 0 1 1 0 0 0 -
0 1 0 0 0 1 1 0
0 1 1 0 1 0 0 1
1 0 0 1 1 1 - 0
1 0 1 1
1 1 0 - Excitation table shows the input value
1 1 1 - corresponding to the state transition
Page  249
excitation table
T-FF
T Q Q+ state 　　　 input
0 0 0 Q 　　 Q+ 　　 T
0 1 1 0 0 0
1 0 1 0 1 1
1 1 0 1 0 1
1 1 0
Page  250
expanded state table of T-FF

T Q Q+
0 0 0
0 1 1
1 0 1
1 1 0 T Q Q+ S R
0 0 0 　 0 -
excitation table of SR-FF
0 1 1 - 0
state 　　　　　 input 1 0 1 1 0
Q 　　 Q+ 　　 S 　　 R 1 1 0 0 1
0 0 0 -
0 1 1 0
1 0 0 1
1
Page  251
1 - 0
T Q Q+ S R Q Q
0 0 0 　 0 - T 0 1 T 0 1
0 1 1 - 0 0 - 0 0 0 -
1 0 1 1 0
1 0 1 1 1 0
1 1 0 0 1
Karnaugh Map of R Karnaugh Map of S
S Q Q R=TQ S=TQ
T CL
Calculate logic function for FF input
R Q Q
Page  252
CL
 Example: Implement D flip-flop using JK FF
D Q Q+
0 0 0
0 1 0
1 0 1
1 1 1
expanded state table of D-FF D Q Q+ J K
excitation table of JK-FF 0 0 0 　 0 -
0 1 0 - 1
state 　　　 input
1 0 1 1 -
Q 　　 Q+ 　　 J K
1 1 1 - 0
0 0 0 -
0 1 1 -
1 0 - 1
1
Page  253
1 - 0
 Example: Implement D flip-flop using JK FF
D Q Q+ J K Q Q
D 0 1 D 0 1
0 0 0 　 0 -
0 1 0 - 1 0 0 - 0 - 1
1 0 1 1 - 1 1 - 1 - 0
1 1 1 - 0
Karnaugh Map of J Karnaugh Map of K
J Q Q
J=D K=D
D CL CL
K Q Q
Page  254
 4.1 Definitions
Page  255
Flip flop excitation equation
 Flip Flop excitation equation express each synchronous input

of each flip-flop as a function of the present state and the
inputs of the circuit.
 These Boolean functions are derived directly from the
combinational part of the circuit.
Page  256
Analysis procedure of sequential circuits
 S1. Find excitation equations, and output equations.

 S2. Establish state table.
 S3. Establish state diagram.
Page  257
Example1: A D flip-flop Moore model circuit
~1PR ~1PR
D1 q1 D2 q2
1D 1Q 1D 1Q
z
1CLK ~1Q 1CLK ~1Q
~1CLR ~1CLR
Cl ock
 Excitation equations:
– D1 = q1q2’ + xq1’ Since output is only a function
– D2 = xq1 of state z=q2’, and not directly
 Output equations: of input, this is Moore model
– z = q2’
Page  258
Example1: A D flip-flop Moore model circuit
q1* = d1 = q1q2’ + xq1’ 0
q2* = d2 = xq1
State table
00
1
q1*q2*
1
q1q2 z
x=0 x=1 0 0
10
00 00 10 1 1
1 1
01 00 10 0
0
10 10 11 1 01 11
0 0
11 00 01 0
1
Page  259 State diagram

Example2: A JK flip-flop Moore model circuit
~1PR ~1PR
x A B
1J 1Q 1J 1Q
1CLK 1CLK
1K ~1Q 1K ~1Q
~1CLR ~1CLR
Cl ock
– JA = x KA = xB’
Since output is only a function
of state z=A+B, and not directly
– JB = KB = x + A’
of input, this is Moore model
 Output equations:
Page  260
– z=A+B
A* = A’JA + AKA= A’x+AxB’

B* = B’JB + BKB = B’(x+A’) + B(x+A’)’
State table 00
0 0
1
A*B* 0
AB z
x=0 x=1 01
1 11
1
0
00 01 11 0 1 1
01 00 10 1 1
10
10 10 01 1 1
11 11 10 1 0
Page  261 State diagram

Page  262
Example3: A D flip-flop Mealy model circuit
x
z
~1PR ~1PR
q1 q2
1D 1Q 1D 1Q
1CLK ~1Q 1CLK ~1Q
~1CLR ~1CLR
Cl ock
Since output is a function of
– d1 = xq1 + xq2
both present input and state
– d2 = xq1’q2’
z=xq1, this is Mealy model
 Output equations:
Page  263
– z = xq1
0/0
q1* = d1 = xq1 + xq2

0/0
q2* = d2 = xq1’q2’ 00 11
1/0
0/0
q* z 0/0 1/1
q
x=0 x=1 x=0 x=1
01 10
00 00 01 0 0 1/0
01 00 10 0 0 1/1
10 00 10 0 1 Notice that:
11 00 10 0 1 2. State 11 is never reached, this example
really only has 3 states.
2. Whenever there is a 0 input, we return to
Page  264
state 00.
 Mealy timing trace:
x 0 1 1 0 1 1 1 1 0
q1 ? 0 0 1 0 0 1 1 1 0
q2 ? 0 1 0 0 1 0 0 0 0
z 0 0 0 0 0 0 1 1 0 0 0
Page  265
Page  266
 4.1 Definitions
Page  267
Design Procedure for Sequential Systems
 S1. From a word description, determine what needs to be stored in

memory, that is, what are the possible states.
 S2. If necessary, code the inputs and outputs in binary.
 S3. Derive a state table or state diagram to describe the behavior
of the system.
 S4. Use state reduction techniques to find a state table that
produces the same input/output behavior, but has fewer states.
 S5. Choose a state assignment, that is, code the states in binary.
 S6. Choose a flip flop type and derive the flip flop input maps or
tables.
 S7. Produce the logic equation and draw a block diagram.
Page  268
Example1: Design sync sequential circuit using JK
 Design a synchronous sequential circuit using JK flip-flop.

The circuit has one input x, one output y. Output is 1 when
receiving a string 0101 in input, otherwhile y=0.
Use Mealy model System

x=0101011.. y=0001010..
1/0 0/0 0/0

A: wait for first 0
B: had 0, wait for 1 0/0
0/0
C: had 01, wait for 0 A B C D
D: had 010, wait for 1 1/0
1/1
1/0
Page  269
Use two state variables q1q2

to encode states in binary
q1
0 1
q2
x 0 A C
S 0 1 1 B D
x
0 1
A B,0 A,0 q1 q2
00 01,0 00,0
B B,0 C,0
01 01,0 10,0
C D,0 A,0
10 11,0 00,0
D B,0 C,1
11 01,0 10,1
State table
Q1Q2 Q1Q2
Page  270
State table after assignment
x q q* J K
0 1
q1q2 0 0 0 -
Application table
00 01,0 00,0 0 1 1 -
1 0 - 1
01 01,0 10,0
1 1 - 0
11 01,0 10,1
x
q1 q2
10 11,0 00,0 0 1
J 1 K1 J2K2 J1K1 J 2 K2
q1*q2*
00 0- 1- 0- 0-
01 0- -0 1- -1
Excitation table
11 -1 -0 -0 -1
10 -0 1- -1 0-
Page  271
x
q1 q2
Minimization for J1 0 1
J 1 K1 J2K2 J 1 K1 J2K2
x 0 1
q1 q2 00 0- 1- 0- 0-
00 0 0
01 0- -0 1- -1
01 0 1 11 -1 -0 -0 -1
10 -0 1- -1 0-
11 - -
10 - - Excitation equations: J1 = xq2
J2 = x K2 = x K 1 = xq 2 + q 2 x
Page  272 Output equation: y = xq1q2

Ex 1: Design sync sequential circuit using JK
&
1 J2 q2 & J1 q1
x y
CLK CLK
=1
K2 q2 K1 q1
CLOCK
Page  273
 Design a synchronous sequential circuit using JK flip-flop.

The circuit has one input x, one output y. Output is 1 when
receiving a string 0111 in input, otherwhile y=0.
Page  274
 Design a synchronous up/down counter using JK with one

input x. If x=0 the circuit counts up from 0 to 3 and repeat, if
x=1 the circuit counts down from 3 downto 0 and repeat.
Page  275

of the system.
tables.
Page  276
S4. State reduction
 State transition diagram may include redundancy. State reduction

technique aims to simplify sequential circuit by reducing redundancy of
the state transition diagram.
 Equivalence:
– two states are equivalent if output sequences are the same when the same
input sequence is given
 Method 1: Procedure to get equivalent states

 Method 2: Reduction of incompletely specified state table
Page  277
State reduction
 Examples:
A
0/0 1/0
B C B C
1/1 1/1 1/1 1/1
0/0 0/0 0/0 0/0
0/0 D 0/0 1/0 E 0/0 0/0 D 0/0 1/0 E 0/0

1/0 1/0 1/0 1/0
F AF
unify A and F
Page  278
A and F have the same output and transition state for the same input
State reduction
 Examples:
B C B C
1/1 0/0
1/1 1/1 0/0
0/0 0/0
0/0 1/1
1/0
0/0 D 0/0 1/0 E 0/0
AF DE 0/0
1/0 1/0 1/0
AF
unify D and E
D and E have the same output and transition state for the same input
Page  279
State reduction
 Examples:
B C BC
0/0 0/0
0/0
1/1 0/0 1/1
1/0
0/0 1/1
1/0
AF DE 0/0
AF DE 0/0 1/0
1/0
unify B and C
Page  280
State reduction
current next state output current next state output

state 0 1 0 1 state 0 1 0 1
A B C 0 0 AF B C 0 0
B D E 0 1 B D E 0 1
C E D 0 1 C E D 0 1
D D F 0 0 D D AF 0 0
E E F 0 0 E E AF 0 0
F B C 0 0

state 0 1 0 1 state 0 1 0 1
AF BC BC 0 0 AF B C 0 0
BC DE DE 0 1 B DE DE 0 1
DE DE AF 0 0 C DE DE 0 1
Page  281 DE DE AF 0 0
State reduction
 Method 1: Procedure to get equivalent states

– (1) Find multiple states that have the same output with the same input,
and treat them as a set of state S1 (s1,s2,…)
– (2) Rewrite state transition table by using the set of state.
– (3) If the next state of the member of the set are different,the set
includes nonequivalent state. Then divide the nonequivalent set and
iterate (2)
Page  282
Example of method 1 (1/4)
 Reduce the state of the state transition diagram
0/0
next state output
current
a state 0 1 0 1
1/0 1/0 a a b 0 0
f b d c 4 1
b 0/0 c a b 0 0
1/0 1/1 0/1 0/1 d f e
0/1 1 1
1/1 e d c 1 1
c e
f e a 1 0
1/1
d 0/1
Page  283
next state output

current
state 0 1 0 1
a a b 0 0
b d c 4 1
c a b 0 0
d f e 1 1
e d c 1 1
f e a 1 0
(b,e) and d are not equivakent
(1) Find a set of state (2) Rewrite next state
hence, divide S2 into S2 and S4
with the same output by using set of state
a : S1,S2
a : S1,S2 S1 equivalent
S1 c : S1,S2
S1 (a,c) c : S1,S2
S2 (b,d,e) S2 b : S4,S1 equivalent
S3 (f) b : S2,S1 e : S4,S1
S2
d : S3,S2
e : S2,S1 S4 d : S3,S2
Page  284
S3 f : S2,S1 S3 f : S2,S1
(2) Rewrite state transition table

current output a : S1,S2
next state S1
state c : S1,S2
0 1 0 1
a a b 0 0 S2 b : S4,S1
b d c 4 1 e : S4,S1
c a b 0 0
d f e S4 d : S3,S2
1 1
e d c 1 1
f e a 1 0 S3 f : S2,S1
current next state output

state 0 1 0 1
S1 S1 S2 0 0
S2 S4 S1 4 1
S4
Page  285
S3 S2 1 1
S3 S2 S1 1 0

Generate state transition diagram state 0 1 0 1
S1 S1 S2 0 0
S2 S4 S1 4 1
0/0 S4 S3 S2 1 1
S3 S2 S1 1 0
a
1/0 1/0 0/0
b 0/0 f
1/1 0/1 0/1
1/1 1
0/1 1/0 1/0
c 1/1 e 0/1 3
2
1/1 0/1
d 0/1 0/1
Page  286
1/1 4
State reduction
 Method 2: Reduction of incompletely specified state table

Incompletely specified: don’t care appears in the next state and output
– 1: Find non compatible pairs
– 2: Find compatible set that doesn’t involve non compatible pairs
– 3: Obtain maximum compatible set
– 4: Calculate minimum closed set
– 5: Generate reduced state transition table
compatible pair: for every input, output are the same

Page  287
Implication table
state input X1X0 input X1X0 b de
00 01 10 11 00 01 10 11
c × ae
a d e b - 0 - 0 -
b e - - a - 1 - 0 d be × de
ad
c a - - e 1 - 0 - e be
bf ae ○ ef
d - b e d - 0 0 -
e a b f - - - - 0 f × de
ae
× × ad
bc
f d c - e 1 - 1 0 a b c d e
a set of not compatible pairs 1:fill in × at incompatible pair

(a,c) (a,f) (b,d) (c,f) (d,f) 2: fill in conditions to be compatible
Page  288
Decompose state set by non compatible pairs

(a,c) (a,f) (b,d) (c,f) (d,f)
(a,b,c,d,e,f)
(a,c)
(a,b,d,e,f) (b,c,d,e,f)
(a,f) (b,d)
(a,b,d,e) (b,d,e,f) (b,c,e,f) (c,d,e,f)
(b,d) (b,d) (c,f) (c,f)
(a,b,e) (a,d,e) (b,e,f) (d,e,f) (b,c,e) (b,e,f) (c,d,e) (d,e,f)
(d,f) remove duplicated node
(d,e) (e,f) remove pair involved to
other node
Maximum compatible set is (a,b,e),(a,d,e),(b,e,f),(b,c,e),(c,d,e)
Page  289
Maximum compatible set Logic function to represent each set involved

C1:(a,b,e) a: C1+C2
C2:(a,d,e) b: C1+C3+C4
C3:(b,e,f) c: C4+C5
C4:(b,c,e) d: C2+C5
C5:(c,d,e) e: C1+C2+C4+C5
f: C3
Minimum closed set is a subset of maximum compatible set that involves all the state
axbxcxdxexf = 1
(C1+C2)(C1+C3+C4)(C4+C5)(C2+C5)(C1+C2+C4+C5)C3
=(C1+C2C3+C2C4)(C2C4+C5) (C1+C2+C4+C5)C3
=(C1C5+C2C3C5+C2C4) (C1+C2+C4+C5)C3
=(C1C5+C2C3C5+C2C4)C3
=C1C3C5+C2C3C5+C2C3C4
hence (C1,C3,C5),(C2,C3,C5),(C2,C3,C4) are candidates for minimum closed set

Page  290
C1:(a,b,e) candidate for minimum closed set:

C2:(a,d,e) (C1,C3,C5),(C2,C3,C5),(C2,C3,C4)
C3:(b,e,f)
C4:(b,c,e) check state transition of each candidate
C5:(c,d,e) by using Implication table
Implication table C1→(d,e)(a,d),(b,e),(b,f),(a,e) →(a,d,e)(b,e,f) →C1,C3

C2 →(b,e),(a,d),(b,e),(b,f),(e,f) →(b,e,f)(a,d) →C3,C2
C3→(a,e),(d,e),(a,d),(b,c) →(a,d,e)(b,c) →C2,C4
b de
C4→(a,e) →(C1|C2)
c × ae C5→(d,e),(e,f) →(C2|C5),C3
d be × de C2,C3,C4 is closed
ad
e be bf ae ○ ef
f × de ae
× × ad
bc
a b c d e
Page  291
C2:(a,d,e),C3:(b,e,f),C4:(b,c,e) are used

state input X1X0 inputX1X0 state input X1X0 input X1X0
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
a d e b - 0 - 0 - C2 C2 C3 C3 C2 0 0 0 0
b e - - a - 1 - 0 C3 C2 C4 C3 C2 1 1 1 0
c a - - e 1 - 0 - C4 C2 C4 C3 C2 1 1 0 0
d - b e d - 0 0 -
e a b f - - - - 0
f d c - e 1 - 1 0
Reduced State Transition Table
Page  292

of the system.
tables.
Page  293
State assignment
 State assignment is to encode the state table into binary

notation, the result is a transition table that combines next-
state table and the output table.
 Better state allocation results in an easy logic function for
input of FF.
 SP (Substitution Property): indicator for good state allocation.
C divide state into blocks so that the next state

a b c d of the same block exists in the same block
C1 C2 state is allocated to distinguish blocks
a b c d
of SP
Page  294
State assignment
next state
current input 　 X
state 0 1 block 1 (q1,q2,q3)
q1 q2 q4 block 2 (q4,q5,q6)
q2 q3 q6
q3 q1 q5 This partition is SP
q4 q5 q2
q5 q6 q1 The first bit is used to
q6 q4 q3 distinguish the blocks.
next state
current state input 　 X
0 1
u 1u2 u 3 u1+2+
u u 3+ u1+u2+u 3+
0 0 0 0 0 1 1 0 0
0 0 1 0 1 0 1 1 0
0 1 0 0 0 0 1 0 1
1 0 0 1 0 1 0 0 1
Page  295
1 0 1 1 1 0 0 0 0
1 1 0 1 0 0 0 1 0
Chapter 5.
Hardware Design Languages
Page  296
Problems
 Problem 1:
Design a synchronous up/down counter using JK with one
input x. If x=0 the circuit counts up from 0 to 3 and repeat, if
x=1 the circuit counts down from 3 downto 0 and repeat.
 Problem 2:
Design a synchronous counter using JK with one input x. The
circuit counts from 0 to 13 then repeat.
 Problem 3:
Page  297
Problems for sequential circuit design
 Textbook:
 Chapter 6: 6.5
– 7a,b,c,d,
– 8a,b,c,d
– 9a,b,c,d
 Chapter 7: 7.6
– 4,5,6,8,9,11,13,15
Page  298

Logic Design

Uploaded by

Logic Design

Uploaded by

Digital Logic Design

Nguyen Thanh Kien

 Author: Nguyen Thanh Kien

 The following materials are used as reference for this slide:

 Introduction to Logic Design, 2nd Ed,, Alan B, Marcovitz, Mc.

1.1. Review of Number Systems

1.1.1 Number Representation

 1.1.1 Number Representation

 Numbers are normally written using a positional number system:

N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m

– Binary: b=2, digits:0,1

N (b ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a− m

N (10 ) = an .b n + an −1.b n −1 + ... + a1.b1 + a0 .b 0 + a−1.b −1 + ... + a− m .b − m

N (10 ) = an an −1an − 2 ...a1a0 .a−1a− 2 ...a−m ai = 0..9

N ( 2 ) = an an −1an −2 ...a1a0 .a−1a− 2 ...a−m ai = 0,1

1011.011(2) = 11 + 0*2-1 + 1*2-2+1*2-3=11 + 0 + 0.25 + 0.125

– MSB – Most Significant Bit

Base b to base 10 conversion

N (10 ) = an .b n + an −1.b n −1 + ... + a1.b1 + a0 .b 0 + a−1.b −1 + ... + a− m .b − m

 Base 10 to base b conversion

 Eg1: 6.625(10) = ?(2)

 Eg2: 20.75(10) = ?(2)

 Group from right to left n-bit groups and replace the

 101011(2) = ?(8) 1010.110(2)=12.6(8)

 Each digit in base 2n is replaced by n bit in base 2.

 37A.B(16)=?(2) = 0011 0111 1010 . 1011(2)

 If both i and j are powers of 2, use base 2 as an intermediate

 Else, use base 10 as an intermediate base:

 1.1.1 Number Representation

 Binary long addition similar to decimal long addition.

Eg: 10101(2) + 11011(2) = 110000 ? (2)

– In 8-bit computer, the result of addition of two binary numbers

 n-bit adder in computer:

1.1.1 Number Representation

 Represent sign and amplitude

Page  31 => need an other representation

 Most left bit is still sign bit

 +10 = 0000 1010

 +10 + (-10) = ? 0000 1010

 Procedure to find binary representation of negative number

 Eg: find representation of -13 in 8-bit signed number

Binary format Unsigned Signed

 To find the magnitude of a negative number:

 Eg: 1001 0110(2) = -106?

 The reason that 2’s complement is so popular is the simplicity

-5 1011 -5 1011 -5 1011

+7 0111 +5 0101 +3 0011

+2 0010 0 0000 -2 1110

⇒Overflow occurs when adding two numbers with the

1.1.1 Number Representation

 Find the 2’s complement of the second operand, then add.

1.1.1 Number Representation

10 1010 0001 0000

11 1011 0001 0001

12 1100 0001 0010

13 1101 0001 0011

14 1110 0001 0100

1.1.1 Number Representation

 American Standard Code for Information Interchange - ASCII

1. Convert the following unsigned numbers:

2. Represent the following signed numbers:

1.1. Review of Number Systems

1.2.1 Definition of Switching Algebra

1.2.1 Definition of Switching Algebra

 Switching algebra is binary:

1.2.1 Definition of Switching Algebra

Basic Properties of Switching Algebra

1. Prove the following equalities:

1.2.1 Definition of Switching Algebra

Manipulation of Algebraic Functions

Manipulation of Algebraic Functions

Manipulation of Algebraic Functions

Manipulation of Algebraic Functions

Manipulation of Algebraic Functions

Manipulation of Algebraic Functions

 Three-variable minterm and Maxterm

1011.011(2) = 11 + 02-1 + 12-2+1*2-3=11 + 0 + 0.25 + 0.125