L2: Combinational Logic Design (Construction and Boolean Algebra)

Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley) and Prof. Gaetano Borriello (University of Washington Department of Computer Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design. 2nd ed. Pentice-Hall/Pearson Education, 2005. J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice Hall/Pearson, 2003.

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Review: Noise Margin

Truth Table
IN OUT IN 0 1
"1" V OH V IH Undefined Region V IL V OL Slope = -1 VOL V VOH V OL IL VIH V(x) V(y) V OH Slope = -1

OUT 1 0

NML= VIL -VOL NMH= VOH -VIH

"0"

Large noise margins protect against various noise sources

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MOS Technology: The NMOS Switch

gate source drain D

N+
P-substrate

N+

VT = 0.5V S

Vs

Switch Model
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OFF

RNMOS
VGS < VT

ON

RNMOS
VGS > VT

NMOS ON when Switch Input is High

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NMOS Device Characteristics

body source gate n+ p+ n+ p n+ polysilicon gate

6
drain

x 10

-4

VGS= 2.5 V

4 (A) 3
D

Resistive

Saturation
VGS= 2.0 V

I 2
gate oxide

inversion layer channel

VGS= 1.5 V VGS= 1.0 V

0.5 1 VDS (V) 1.5 2 2.5

D ID G + VGS VT = 0.5V S
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0 0

MOS is a very non-linear. Switch-resistor model sufficient for first order analysis.
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Introductory Digital Systems Laboratory

PMOS: The Complementary Switch

gate source drain G S VT = -0.5V D

P+
N-substrate

P+

VDD

Switch Model
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OFF

RPMOS
VGS > VT

ON

RPMOS
VGS < VT

PMOS ON when Switch Input is Low

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The CMOS Inverter

Switch Model

VDD
S G D

VDD RPMOS
IN OUT OUT

IN
D G S

RNMOS
IN

Rail-to-rail Swing in CMOS

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Inverter VTC: Load Line Analysis

ID n Vin = 0 Vin = 2.5

VDD
G S

PMOS

Vin = 0.5

Vin = 2

NMOS

Vin = 1

Vin = 1.5 Vin = 1

D IN G S D OUT

Vin = 1.5 Vin = 2 Vin = 2.5

2.5

Vin = 1.5

Vin = 1

Vin = 0.5 Vin = 0 Vout

CMOS gates have: Rail-to-rail swing (0V to VDD) Large noise margins zero static power dissipation
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1.5
out

V
1 0.5 0 0 0.5 1 1.5 2 2.5

(V)

V (V)
in

Introductory Digital Systems Laboratory

Possible Function of Two Inputs

There are 16 possible functions of 2 input variables:
X Y F

X 0 0 1 1

Y 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0
X

16 possible functions (F0F15) 0 0 1 1

Y

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0
X=Y

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1
1

0 X AND Y

X XOR Y X OR Y

NOT Y NOT X

X NOR Y NOT (X OR Y)

X NAND Y NOT (X AND Y)

In general, there are 2 (2^n) functions of n inputs

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Common Logic Gates

Gate
NAND
X Y

Symbol
Z

Truth-Table
X 0 0 1 1 X Y 0 1 0 1 Y 0 1 0 1 Y 0 1 0 1 Z 1 1 1 0 Z 0 0 0 1 Z 1 0 0 0

Expression
Z=XY

AND

X Y

0 0 1 1 X

Z=XY

NOR

X Y

0 0 1 1

Z=X+Y

Y 0 1 0 1

Z 0 1 1 1 9

OR

X Y

0 0 1 1

Z=X+Y

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Exclusive (N)OR Gate

Y 0 1 0 1

Z 0 1 1 0

(X Y)

XOR

X Y

0 1 1

Z=XY+XY X or Y but not both ("inequality", "difference")

Y 0 1 0 1

Z 1 0 0 1

XNOR
(X Y)

X Y

0 0 1 1

Z=XY+XY X and Y the same ("equality")

Widely used in arithmetic structures such as adders and multipliers

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Generic CMOS Recipe

Vdd ...

pullup: make this connection

when we want F(A1,,An) = 1 F(A1,,An)

...

A1 An ...

pulldown: make this connection

when we want F(A1,,An) = 0

Note: CMOS gates result in inverting functions! (easier to build NAND vs. AND)

PUN O

A B

PDN
B

CL

A 0 0 1 1

B PDN PUN 0 0ff 0n 1 0ff 0n 0 0ff 0n 1 0n 0ff

O 1 1 1 0

How do you build a 2-input NOR Gate?

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Theorems of Boolean Algebra (I)

Elementary
1. X + 0 = X 2. X + 1 = 1 3. X + X = X 4. (X) = X 5. X + X = 1 5D. X X = 0 6D. X Y = Y X 7D. (X Y) Z = X (Y Z) 8D. X + (Y Z) = (X + Y) (X + Z) 9D. (X + Y) (X + Y) = X 10D. X (X + Y) = X 11D. (X Y) + Y = X + Y
12

1D. X 1 = X 2D. X 0 = 0 3D. X X = X

Commutativity:
6. X + Y = Y + X

Associativity:
7. (X + Y) + Z = X + (Y + Z)

Distributivity:
8. X (Y + Z) = (X Y) + (X Z)

Uniting:
9. X Y + X Y = X

Absorption:
10. X + X Y = X 11. (X + Y) Y = X Y

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Theorems of Boolean Algebra (II)

Factoring:
12. (X Y) + (X Z) = X (Y + Z) 12D. (X + Y) (X + Z) = X + (Y Z) 13D. (X + Y) (Y + Z) (X + Z) = (X + Y) (X + Z) 14D. (X Y ...) = X + Y + ...

Consensus:
13. (X Y) + (Y Z) + (X Z) = XY+XZ

De Morgan's:
14. (X + Y + ...) = X Y ...

Generalized De Morgan's:
15. f(X1,X2,...,Xn,0,1,+,) = f(X1,X2,...,Xn,1,0,,+)

Duality
Dual of a Boolean expression is derived by replacing by +, + by , 0 by 1, and 1 by 0, and leaving variables unchanged f (X1,X2,...,Xn,0,1,+,) f(X1,X2,...,Xn,1,0,,+)

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Simple Example: One Bit Adder

1-bit binary adder

inputs:

A, B, Carry-in outputs: Sum, Carry-out

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 S Cout 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1

A B Cin

S Cout

Sum-of-Products Canonical Form

S = A B Cin + A B Cin + A B Cin + A B Cin Cout = A B Cin + A B Cin + A B Cin + A B Cin

Product term (or minterm)

ANDed

product of literals input combination for which output

is true Each variable appears exactly once, in true or inverted form (but not both)

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Simplify Boolean Expressions

Cout = A B Cin + A B Cin + A B Cin + A B Cin = A B Cin + A B Cin + A B Cin + A B Cin + A B Cin + A B Cin = (A + A) B Cin + A (B + B) Cin + A B (Cin + Cin) = B Cin + A Cin + A B = (B + A) Cin + A B

S = A B Cin + A B Cin + A B Cin + A B Cin =( A B + A B )Cin + (A B + A B) Cin =(A B) Cin + (A B) Cin = A B Cin

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Sum-of-Products & Product-of-Sum

Product term (or minterm): ANDed product of literals input combination for which output is true A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 minterms A B C A B C A B C A B C A B C A B C A B C A B C m0 m1 m2 m3 m4 m5 m6 m7 F in canonical form: F(A, B, C) = m(1,3,5,6,7) = m1 + m3 + m5 + m6 + m7 F = A B C + A B C+ A B C + A B C + ABC canonical form minimal form F(A, B, C) = A B C + A B C + AB C + ABC + ABC = (A B + A B + AB + AB)C + ABC = ((A + A)(B + B))C + ABC = C + ABC = ABC + C = AB + C

short-hand notation form in terms of 3 variables

Sum term (or maxterm) - ORed sum of literals input combination for which output is false A B C maxterms 0 0 0 A + B + C M0 F in canonical form: 0 0 1 A + B + C M1 F(A, B, C) = M(0,2,4) 0 1 0 A + B + C M2 = M0 M2 M4 0 1 1 A + B + C M3 = (A + B + C) (A + B + C) (A + B + C) 1 0 0 A + B + C M4 canonical form minimal form 1 0 1 A + B+ C M5 F(A, B, C) = (A + B + C) (A + B + C) (A + B + C) 1 1 0 A + B +C M6 = (A + B + C) (A + B + C) 1 1 1 A +B + C M7 (A + B + C) (A + B + C) = (A + C) (B + C) short-hand notation for maxterms of 3 variables
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Mapping Between Forms

1. Minterm to Maxterm conversion: rewrite minterm shorthand using maxterm shorthand replace minterm indices with the indices not already used E.g., F(A,B,C) = m(3,4,5,6,7) = M(0,1,2) 2. Maxterm to Minterm conversion: rewrite maxterm shorthand using minterm shorthand replace maxterm indices with the indices not already used E.g., F(A,B,C) = M(0,1,2) = m(3,4,5,6,7) 3. Minterm expansion of F to Minterm expansion of F': in minterm shorthand form, list the indices not already used in F E.g., F(A,B,C) = m(3,4,5,6,7) = M(0,1,2) 4. F'(A,B,C) = m(0,1,2) = M(3,4,5,6,7)

Minterm expansion of F to Maxterm expansion of F': rewrite in Maxterm form, using the same indices as F E.g., F(A,B,C) = m(3,4,5,6,7) = M(0,1,2) F'(A,B,C) = M(3,4,5,6,7) = m(0,1,2)
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The Uniting Theorem

Key tool to simplification: A (B + B) = A Essence of simplification of two-level logic

Find

two element subsets of the ON-set where only one variable changes its value this single varying variable can be eliminated and a single product term used to represent both elements
F = A B +AB = (A +A)B = B A 0 0 1 1 B 0 1 0 1 F 1 0 1 0 B has the same value in both on-set rows B remains A has a different value in the two rows A is eliminated

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Boolean Cubes

Just another way to represent truth table Visual technique for identifying when the uniting theorem can be applied n input variables = n-dimensional "cube"
XY

1-cube

0 X

01 Y 00 X

11 2-cube 10
1011 0111 WXYZ 1111 1010 1110

011 010

XYZ 111 0011 110 0010

0110 Y 000 X Z 001 101 100 0000 Y Z W X 0100 1000 0001 0101

1001 1101 1100

3-cube
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4-cube
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Mapping Truth Tables onto Boolean Cubes

Uniting theorem
A 0 0 1 1 B 0 1 0 1 F 1 0 1 0 F 01 B 00 A 10 11

Circled group of the on-set is called the

adjacency plane. Each adjacency plane

corresponds to a product term. ON-set = solid nodes OFF-set = empty nodes A varies within face, B does not this face represents the literal B

Three variable example: Binary full-adder carry-out logic

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1 (A+A)BCin
111

AB(Cin+Cin) Cout = BCin+AB+ACin

B 000

C A

101

A(B+B)Cin

The on-set is completely covered by the combination (OR) of the subcubes of lower dimensionality - note that 111 is covered three times

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Higher Dimension Cubes

F(A,B,C) = m(4,5,6,7)
011 010 B C 000 110 001 A 100 101 111

on-set forms a square i.e., a cube of dimension 2 (2-D adjacency plane) represents an expression in one variable i.e., 3 dimensions 2 dimensions A is asserted (true) and unchanged B and C vary This subcube represents the literal A

In a 3-cube (three variables):

0-cube,

i.e., a single node, yields a term in 3 literals 1-cube, i.e., a line of two nodes, yields a term in 2 literals 2-cube, i.e., a plane of four nodes, yields a term in 1 literal 3-cube, i.e., a cube of eight nodes, yields a constant term "1"

In general,
m-subcube

within an n-cube (m < n) yields a term with n m

literals
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Karnaugh Maps

Alternative to truth-tables to help visualize adjacencies

Guide to applying the uniting theorem - On-set elements with only one variable changing value are adjacent unlike in a linear truth-table
B A 0 1
0 1

0 1 0
2 3

1 1 0

A 0 0 1 1

B 0 1 0 1

F 1 0 1 0

Numbering scheme based on Graycode

e.g., 00, 01, 11, 10 (only a single bit changes in code for adjacent map cells)
A B 0 0 0 1 1 2 3 01 AB C 00 0 0 1 1 2 3 B 6 7 4 5 01 11 A 10 C 10 11 1 3 2 5 7 6 B 13 15 14 9 11 10 D 1 AB CD 00 A 00 0 01 4 11 12 10 8

2-variable K-map

3-variable K-map

4-variable K-map
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K-Map Examples
AB Cin 0 1 00 0 0 01 0 1 11 1 1 A 10 0 1
AB C 0 1 00 0 0 01 0 0 B 11 1 1 A 10 1 1

Cout =
AB C 0 1 A 00 1 0 01 0 0 B 11 0 1 10 1 1

F(A,B,C) =
AB C 0 1 A 00 0 1 01 1 1 B 11 1 0 10 0 0

F(A,B,C) = m(0,4,5,7) F=

F' simply replace 1's with 0's and vice versa F'(A,B,C) = m(1,2,3,6) F' =

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Four Variable Karnaugh Map

AB CD 00 01 11 C 10

A 00 1 0 1 1 01 0 1 1 1 B 11 0 0 1 1 10 1 0 D 1 1

F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15) F=C + A BD + B D Find the smallest number of the largest possible subcubes that cover the ON-set

1011 0111 0011 0010 1010 1110 0110 1001 C D 0000 0001 A B 0100 0101 1100 1000

1111

K-map Corner Adjacency Illustrated in the 4-Cube

1101

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K-Map Example: Dont Cares

Don't Don'tCares Carescan canbe betreated treatedas as1's 1'sor or0's 0'sif ifit itis isadvantageous advantageousto todo doso so
AB CD 00 01 11 C 10 0 X B 0 0 A 00 0 1 1 01 0 1 1 11 X X 0 10 0 1 D 0

F(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13) F = A D + B C D w/o don't cares F = C D + A D w/ don't cares By treating this DC as a "1", a 2-cube can be formed rather than one 0-cube
AB CD 00 01 A 00 0 1 1 0 01 0 1 1 X B 11 X X 0 0 10 0 1 D 11 0 0 C 10

In PoS form: F = D (A + C) Equivalent answer as above, but fewer literals

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Hazards

AB Static hazards: Consider this function: C F=A*C+B*C A C B A=B=1 C 1 2 F F 0 1

00 01 11 10 0 0 0 1 1 1 1 0

Implemented with MSI gates: 1 A '00 '00 '00 F C '00 B 2 Glitch

Gate delay

Figure by MIT OpenCourseWare. L2: 6.111 Spring 2006 Introductory Digital Systems Laboratory 26

Fixing Hazards
The glitch is the result of timing differences in parallel data paths. It is associated with the function jumping between groupings or product terms on the K-map. To fix it, cover it up with another grouping or product term!

A C B

AB C 00 01 11 10 0 0
F

0 1

1 1

1 0

1 0

F=A*C+B*C+A*B

Figure by MIT OpenCourseWare.

In general, it is difficult to avoid hazards need a robust design methodology to deal with hazards.
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