DAC0830/DAC0832

8-Bit P Compatible, Double-Buffered D to A Converters

General Description
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, Z80

, and other popular microprocessors. Adeposited

silicon-chromium R-2R resistor ladder network divides the
reference current and provides the circuit with excellent tem-
perature tracking characteristics (0.05% of Full Scale Range
maximum linearity error over temperature). The circuit uses
CMOS current switches and control logic to achieve low
power consumption and low output leakage current errors.
Special circuitry provides TTL logic input voltage level com-
patibility.
Double buffering allows these DACs to output a voltage cor-
responding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number
of DACs.
The DAC0830 series are the 8-bit members of a family of
microprocessor-compatible DACs (MICRO-DAC).
Features
n Double-buffered, single-buffered or flow-through digital
data inputs
n Easy interchange and pin-compatible with 12-bit
DAC1230 series
n Direct interface to all popular microprocessors
n Linearity specified with zero and full scale adjust
only NOT BEST STRAIGHT LINE FIT.
n Works with 10V reference-full 4-quadrant multiplication
n Can be used in the voltage switching mode
n Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
n Operates STAND ALONE (without P) if desired
n Available in 20-pin small-outline or molded chip carrier
package
Key Specifications
n Current settling time: 1 s
n Resolution: 8 bits
n Linearity: 8, 9, or 10 bits (guaranteed over temp.)
n Gain Tempco: 0.0002% FS/C
n Low power dissipation: 20 mW
n Single power supply: 5 to 15 V
DC
Typical Application
BI-FET and MICRO-DAC are trademarks of National Semiconductor Corporation.
Z80

is a registered trademark of Zilog Corporation.

DS005608-1
May 1999
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1999 National Semiconductor Corporation DS005608 www.national.com
Connection Diagrams (Top Views)
Dual-In-Line and
Small-Outline Packages
DS005608-21
Molded Chip Carrier Package
DS005608-22
www.national.com 2
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) 17 V
DC
Voltage at Any Digital Input V
CC
to GND
Voltage at V
REF
Input 25V
Storage Temperature Range 65C to +150C
Package Dissipation
at T
A
=25C (Note 3) 500 mW
DC Voltage Applied to
I
OUT1
or I
OUT2
(Note 4) 100 mV to V
CC
ESD Susceptability (Note 4) 800V
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (plastic) 260C
Dual-In-Line Package (ceramic) 300C
Surface Mount Package
Vapor Phase (60 sec.) 215C
Infrared (15 sec.) 220C
Operating Conditions
Temperature Range T
MIN
T
A
T
MAX
Part numbers with LCN suffix 0C to +70C
Part numbers with LCWM suffix 0C to +70C
Part numbers with LCV suffix 0C to +70C
Part numbers with LCJ suffix 40C to +85C
Part numbers with LJ suffix 55C to +125C
Voltage at Any Digital Input V
CC
to GND
Electrical Characteristics
V
REF
=10.000 V
DC
unless otherwise noted. Boldface limits apply over temperature, T
MIN
T
A
T
MAX
. For all other limits
T
A
=25C.
Parameter Conditions
See
Note
V
CC
= 4.75 V
DC
V
CC
= 15.75 V
DC
V
CC
= 5 V
DC
5%
V
CC
= 12 V
DC
5%
to 15 V
DC
5%
Limit
Units
Typ
(Note 12)
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
CONVERTER CHARACTERISTICS
Resolution 8 8 8 bits
Linearity Error Max Zero and full scale adjusted 4, 8
10VV
REF
+10V
DAC0830LJ & LCJ 0.05 0.05 % FSR
DAC0832LJ & LCJ 0.2 0.2 % FSR
DAC0830LCN, LCWM &
LCV
0.05 0.05 % FSR
DAC0831LCN 0.1 0.1 % FSR
DAC0832LCN, LCWM &
LCV
0.2 0.2 % FSR
Differential Nonlinearity Zero and full scale adjusted 4, 8
Max 10VV
REF
+10V
DAC0830LJ & LCJ 0.1 0.1 % FSR
DAC0832LJ & LCJ 0.4 0.4 % FSR
DAC0830LCN, LCWM &
LCV
0.1 0.1 % FSR
DAC0831LCN 0.2 0.2 % FSR
DAC0832LCN, LCWM &
LCV
0.4 0.4 % FSR
Monotonicity 10VV
REF
LJ & LCJ 4 8 8 bits
+10V LCN, LCWM & LCV 8 8 bits
Gain Error Max Using Internal R
fb
7 0.2 1 1 % FS
10VV
REF
+10V
Gain Error Tempco Max Using internal R
fb
0.0002 0.0006 %
FS/C
Power Supply Rejection All digital inputs latched high
V
CC
=14.5V to 15.5V 0.0002 0.0025 %
11.5V to 12.5V 0.0006 FSR/V
4.5V to 5.5V 0.013 0.015
Reference Max 15 20 20 k
Input Min 15 10 10 k
Output Feedthrough Error V
REF
=20 Vp-p, f=100 kHz
All data inputs latched low
3 mVp-p
www.national.com 3
Electrical Characteristics (Continued)
V
REF
=10.000 V
DC
unless otherwise noted. Boldface limits apply over temperature, T
MIN
T
A
T
MAX
. For all other limits
T
A
=25C.
Parameter Conditions
See
Note
V
CC
= 4.75 V
DC
V
CC
= 15.75 V
DC
V
CC
= 5 V
DC
5%
V
CC
= 12 V
DC
5%
to 15 V
DC
5%
Limit
Units
Typ
(Note 12)
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
CONVERTER CHARACTERISTICS
Output Leakage
Current Max
I
OUT1
All data inputs LJ & LCJ 10 100 100 nA
latched low LCN, LCWM & LCV 50 100
I
OUT2
All data inputs LJ & LCJ 100 100 nA
latched high LCN, LCWM & LCV 50 100
Output I
OUT1
All data inputs 45 pF
Capacitance I
OUT2
latched low 115
I
OUT1
All data inputs 130 pF
I
OUT2
latched high 30
DIGITAL AND DC CHARACTERISTICS
Digital Input Max Logic Low LJ: 4.75V 0.6
Voltages LJ: 15.75V 0.8
LCJ: 4.75V 0.7 V
DC
LCJ: 15.75V 0.8
LCN, LCWM, LCV 0.95 0.8
Min Logic High LJ & LCJ 2.0 2.0 V
DC
LCN, LCWM, LCV 1.9 2.0
Digital Input Max Digital inputs <0.8V
Currents LJ & LCJ 50 200 200 A
LCN, LCWM, LCV 160 200 A
Digital inputs>2.0V
LJ & LCJ 0.1 +10 +10 A
LCN, LCWM, LCV +8 +10
Supply Current Max LJ & LCJ 1.2 3.5 3.5 mA
Drain LCN, LCWM, LCV 1.7 2.0
Electrical Characteristics
V
REF
=10.000 V
DC
unless otherwise noted. Boldface limits apply over temperature, T
MIN
T
A
T
MAX
. For all other limits
T
A
=25C.
Symbol Parameter Conditions
See
Note
V
CC
=15.75 V
DC
V
CC
=12 V
DC
5%
to 15 V
DC
5%
V
CC
=4.75 V
DC
V
CC
=5
V
DC
5%
Limit
Units
Typ
(Note 12)
Tested
Limit
(Note 5)
Design Limit
(Note 6)
Typ
(Note 12)
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
AC CHARACTERISTICS
t
s
Current Setting V
IL
=0V, V
IH
=5V 1.0 1.0 s
Time
t
W
Write and XFER V
IL
=0V, V
IH
=5V 11 100 250 375 600
Pulse Width Min 9 320 320 900 900
t
DS
Data Setup Time V
IL
=0V, V
IH
=5V 9 100 250 375 600
Min 320 320 900 900
t
DH
Data Hold Time V
IL
=0V, V
IH
=5V 9 30 50 ns
Min 30 50
t
CS
Control Setup Time V
IL
=0V, V
IH
=5V 9 110 250 600 900
Min 320 320 1100 1100
t
CH
Control Hold Time V
IL
=0V, V
IH
=5V 9 0 0 10 0 0
Min 0 0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
www.national.com 4
Electrical Characteristics (Continued)
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
,
JA
, and the ambient temperature, T
A
. The maximum
allowable power dissipation at any temperature is P
D
= (T
JMAX
T
A
)/
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
T
JMAX
= 125C (plastic) or 150C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80C/W. For the N pack-
age, this number increases to 100C/W and for the V package this number is 120C/W.
Note 4: For current switching applications, both I
OUT1
and I
OUT2
must go to ground or the Virtual Ground of an operational amplifier. The linearity error is degraded
by approximately V
OS
V
REF
. For example, if V
REF
= 10V then a 1 mV offset, V
OS
, on I
OUT1
or I
OUT2
will introduce an additional 0.01% linearity error.
Note 5: Tested limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Guaranteed at V
REF
=10 V
DC
and V
REF
=1 V
DC
.
Note 8: The unit FSR stands for Full Scale Range. Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a par-
ticular V
REF
value and to indicate the true performance of the part. The Linearity Error specification of the DAC0830 is 0.05% of FSR (MAX). This guarantees that
after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xV
REF
of a straight
line which passes through zero and full scale.
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
Note 10: A 100nA leakage current with R
fb
=20k and V
REF
=10V corresponds to a zero error of (100x10
9
x20x10
3
)x100/10 which is 0.02% of FS.
Note 11: The entire write pulse must occur within the valid data interval for the specified t
W
, t
DS
, t
DH
, and t
S
to apply.
Note 12: Typicals are at 25C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 k resistor.
Switching Waveform
DS005608-2
www.national.com 5
Definition of Package Pinouts
Control Signals (All control signals level actuated)
CS: Chip Select (active low). The CS in combination
with ILE will enable WR
1
.
ILE: Input Latch Enable (active high). The ILE in combi-
nation with CS enables WR
1
.
WR
1
: Write 1. The active low WR
1
is used to load the digi-
tal input data bits (DI) into the input latch. The data
in the input latch is latched when WR
1
is high. To
update the input latchCS and WR
1
must be low
while ILE is high.
WR
2
: Write 2 (active low). This signal, in combination with
XFER, causes the 8-bit data which is available in
the input latch to transfer to the DAC register.
XFER: Transfer control signal (active low). The XFER will
enable WR
2
.
Other Pin Functions
DI
0
-DI
7
: Digital Inputs. DI
0
is the least significant bit (LSB)
and DI
7
is the most significant bit (MSB).
I
OUT1
: DAC Current Output 1. I
OUT1
is a maximum for a
digital code of all 1s in the DAC register, and is
zero for all 0s in DAC register.
I
OUT2
: DAC Current Output 2. I
OUT2
is a constant minus
I
OUT1
, or I
OUT1
+ I
OUT2
= constant (I full scale for
a fixed reference voltage).
R
fb
: Feedback Resistor. The feedback resistor is pro-
vided on the IC chip for use as the shunt feedback
resistor for the external op amp which is used to
provide an output voltage for the DAC. This on-
chip resistor should always be used (not an exter-
nal resistor) since it matches the resistors which
are used in the on-chip R-2R ladder and tracks
these resistors over temperature.
V
REF
: Reference Voltage Input. This input connects an
external precision voltage source to the internal
R-2R ladder. V
REF
can be selected over the range
of +10 to 10V. This is also the analog voltage in-
put for a 4-quadrant multiplying DAC application.
V
CC
: Digital Supply Voltage. This is the power supply
pin for the part. V
CC
can be from +5 to +15V
DC
.
Operation is optimum for +15V
DC
GND: The pin 10 voltage must be at the same ground
potential as I
OUT1
and I
OUT2
for current switching
applications. Any difference of potential (V
OS
pin
10) will result in a linearity change of
For example, if V
REF
= 10V and pin 10 is 9mV offset from
I
OUT1
and I
OUT2
the linearity change will be 0.03%.
Pin 3 can be offset 100mV with no linearity change, but the
logic input threshold will shift.
Linearity Error
Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC0830
has 2
8
or 256 steps and therefore has 8-bit resolution.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting for
zero and full-scale. Linearity error is a parameter intrinsic to
the device and cannot be externally adjusted.
Nationals linearity end point test (a) and the best straight
line test (b,c) used by other suppliers are illustrated above.
The end point test greatly simplifies the adjustment proce-
dure by eliminating the need for multiple iterations of check-
ing the linearity and then adjusting full scale until the linearity
is met. The end point test guarantees that linearity is met
after a single full scale adjust. (One adjustment vs. multiple
iterations of the adjustment.) The end point test uses a
standard zero and F.S. adjustment procedure and is a much
more stringent test for DAC linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within
1
2LSB of the
final output value. Full-scale settling time requires a zero to
full-scale or full-scale to zero output change.
Full Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC0830 series, full scale is V
REF
1LSB.
For V
REF
= 10V and unipolar operation, V
FULL-SCALE
=
10,0000V39mV 9.961V. Full-scale error is adjustable to
zero.
DS005608-23
a) End point test after
zero and fs adj.
DS005608-24
b) Best straight line DS005608-25
c) Shifting fs adj. to pass
best straight line test
www.national.com 6
Definition of Terms (Continued)
Differential Nonlinearity: The difference between any two
consecutive codes in the transfer curve from the theoretical
1 LSB to differential nonlinearity.
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. An 8-bit DAC
which is monotonic to 8 bits simply means that increasing
digital input codes will produce an increasing analog output.
Typical Performance Characteristics
DS005608-4
FIGURE 1. DAC0830 Functional Diagram
Digital Input Threshold
vs. Temperature
DS005608-26
Digital Input Threshold
vs. V
CC
DS005608-27
Gain and Linearity Error
Variation vs. Temperature
DS005608-28
www.national.com 7
Typical Performance Characteristics (Continued)
DAC0830 Series Application Hints
These DACs are the industrys first microprocessor compat-
ible, double-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility from
a digital control point of view. This 20-pin device is also pin
for pin compatible (with one exception) with the DAC1230, a
12-bit MICRO-DAC. In the event that a systems analog out-
put resolution and accuracy must be upgraded, substituting
the DAC1230 can be easily accomplished. By tying address
bit A
0
to the ILE pin, a two-byte P write instruction (double
precision) which automatically increments the address for
the second byte write (starting with A
0
=1) can be used.
This allows either an 8-bit or the 12-bit part to be used with
no hardware or software changes. For the simplest 8-bit ap-
plication, this pin should be tied to V
CC
(also see other uses
in section 1.1).
Analog signal control versatility is provided by a precision
R-2R ladder network which allows full 4-quadrant multiplica-
tion of a wide range bipolar reference voltage by an applied
digital word.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DACs is that the 8-bit
digital input byte is double-buffered. This means that the
data must transfer through two independently controlled 8-bit
latching registers before being applied to the R-2R ladder
network to change the analog output. The addition of a sec-
ond register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more im-
portant, double-buffering allows any number of DACs in a
system to be updated to their new analog output levels si-
multaneously via a common strobe signal.
The timing requirements and logic level convention of the
register control signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit write-only
memory locations that provide an analog output quantity. All
inputs to these DACs meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in
non-microprocessor based systems. To prevent damage to
the chip from static discharge, all unused digital inputs
should be tied to V
CC
or ground. If any of the digital inputs
are inadvertantly left floating, the DAC interprets the pin as a
logic 1.
1.1 Double-Buffered Operation
Updating the analog output of these DACs in a
double-buffered manner is basically a two step or double
write operation. In a microprocessor system two unique sys-
tem addresses must be decoded, one for the input latch con-
trolled by the CS pin and a second for the DAC latch which
is controlled by the XFER line. If more than one DAC is being
driven, Figure 2, the CS line of each DAC would typically be
decoded individually, but all of the converters could share a
common XFER address to allow simultaneous updating of
any number of DACs. The timing for this operation is shown,
Figure 3.
It is important to note that the analog outputs that will change
after a simultaneous transfer are those from the DACs
whose input register had been modified prior to the XFER
command.
Gain and Linearity Error
Variation vs. Supply Voltage
DS005608-29
Write Pulse Width
DS005608-30
Data Hold Time
DS005608-31
www.national.com 8
DAC0830 Series Application Hints (Continued)
The ILE pin is an active high chip select which can be de-
coded from the address bus as a qualifier for the normal CS
signal generated during a write operation. This can be used
to provide a higher degree of decoding unique control sig-
nals for a particular DAC, and thereby create a more efficient
addressing scheme.
Another useful application of the ILE pin of each DAC in a
multiple DAC system is to tie these inputs together and use
this as a control line that can effectively freeze the outputs
of all the DACs at their present value. Pulling this line low
latches the input register and prevents new data from being
written to the DAC. This can be particularly useful in multi-
processing systems to allow a processor other than the one
controlling the DACs to take over control of the data bus and
control lines. If this second system were to use the same ad-
dresses as those decoded for DAC control (but for a different
purpose) the ILE function would prevent the DACs from be-
ing erroneously altered.
In a Stand-Alone system the control signals are generated
by discrete logic. In this case double-buffering can be con-
trolled by simply taking CS and XFER to a logic 0, ILE to a
logic 1 and pulling WR
1
low to load data to the input latch.
Pulling WR
2
low will then update the analog output. A logic
1 on either of these lines will prevent the changing of the
analog output.
DS005608-35
*TIE TO LOGIC 1 IF NOT NEEDED (SEE SEC. 1.1).
FIGURE 2. Controlling Mutiple DACs
DS005608-36
FIGURE 3.
www.national.com 9
DAC0830 Series Application Hints (Continued)
1.2 Single-Buffered Operation
In a microprocessor controlled system where maximum data
throughput to the DAC is of primary concern, or when only
one DAC of several needs to be updated at a time, a
single-buffered configuration can be used. One of the two in-
ternal registers allows the data to flow through and the other
register will serve as the data latch.
Digital signal feedthrough (see Section 1.5) is minimized if
the input register is used as the data latch. Timing for this
mode is shown in Figure 4.
Single-buffering in a stand-alone system is achieved by
strobing WR
1
low to update the DAC with CS, WR
2
and
XFER grounded and ILE tied high.
1.3 Flow-Through Operation
Though primarily designed to provide microprocessor inter-
face compatibility, the MICRO-DACs can easily be config-
ured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in appli-
cations where the DAC is used in a continuous feedback
control loop and is driven by a binary up-down counter, or in
function generation circuits where a ROM is continuously
providing DAC data.
Simply grounding CS, WR
1
, WR
2
, and XFER and tying ILE
high allows both internal registers to follow the applied digital
inputs (flow-through) and directly affect the DAC analog out-
put.
1.4 Control Signal Timing
When interfacing these MICRO-DAC to any microprocessor,
there are two important time relationships that must be con-
sidered to insure proper operation. The first is the minimum
WR strobe pulse width which is specified as 900 ns for all
valid operating conditions of supply voltage and ambient
temperature, but typically a pulse width of only 180ns is ad-
equate if V
CC
=15V
DC
. A second consideration is that the
guaranteed minimum data hold time of 50ns should be met
or erroneous data can be latched. This hold time is defined
as the length of time data must be held valid on the digital in-
puts after a qualified (via CS) WR strobe makes a low to high
transition to latch the applied data.
If the controlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow
memory or peripheral and utilize a technique to extend the
write strobe. A simple extension of the write time, by adding
a wait state, can simultaneously hold the write strobe active
and data valid on the bus to satisfy the minimum WR pulse-
width. If this does not provide a sufficient data hold time at
the end of the write cycle, a negative edge triggered
one-shot can be included between the system write strobe
and the WR pin of the DAC. This is illustrated in Figure 5 for
an exemplary system which provides a 250ns WR strobe
time with a data hold time of less than 10ns.
The proper data set-up time prior to the latching edge (LO to
HI transition) of the WR strobe, is insured if the WR pulse-
width is within spec and the data is valid on the bus for the
duration of the DAC WR strobe.
1.5 Digital Signal Feedthrough
When data is latched in the internal registers, but the digital
inputs are changing state, a narrow spike of current may flow
out of the current output terminals. This spike is caused by
the rapid switching of internal logic gates that are responding
to the input changes.
There are several recommendations to minimize this effect.
When latching data in the DAC, always use the input register
as the latch. Second, reducing the V
CC
supply for the DAC
from +15V to +5V offers a factor of 5 improvement in the
magnitude of the feedthrough, but at the expense of internal
logic switching speed. Finally, increasing C
C
(Figure 8) to a
value consistent with the actual circuit bandwidth require-
ments can provide a substantial damping effect on any out-
put spikes.
DS005608-7
ILE=LOGIC 1; WR2 and XFER GROUNDED
FIGURE 4.
www.national.com 10
DAC0830 Series Application Hints (Continued)
2.0 ANALOG CONSIDERATIONS
The fundamental purpose of any D to A converter is to pro-
vide an accurate analog output quantity which is representa-
tive of the applied digital word. In the case of the DAC0830,
the output, I
OUT1
, is a current directly proportional to the
product of the applied reference voltage and the digital input
word. For application versatility, a second output, I
OUT2
, is
provided as a current directly proportional to the complement
of the digital input. Basically:
where the digital input is the decimal (base 10) equivalent of
the applied 8-bit binary word (0 to 255), V
REF
is the voltage
at pin 8 and 15 k is the nominal value of the internal resis-
tance, R, of the R-2R ladder network (discussed in Section
2.1).
Several factors external to the DAC itself must be consid-
ered to maintain analog accuracy and are covered in subse-
quent sections.
2.1 The Current Switching R-2R Ladder
The analog circuitry, Figure 6, consists of a silicon-chromium
(SiCr or Si-chrome) thin film R-2R ladder which is deposited
on the surface oxide of the monolithic chip. As a result, there
are no parasitic diode problems with the ladder (as there
may be with diffused resistors) so the reference voltage,
V
REF
, can range 10V to +10V even if V
CC
for the device is
5V
DC
.
The digital input code to the DAC simply controls the position
of the SPDT current switches and steers the available ladder
current to either I
OUT1
or I
OUT2
as determined by the logic in-
put level (1 or 0) respectively, as shown in Figure 6. The
MOS switches operate in the current mode with a small volt-
age drop across them and can therefore switch currents of
either polarity. This is the basis for the 4-quadrant multiplying
feature of this DAC.
2.2 Basic Unipolar Output Voltage
To maintain linearity of output current with changes in the ap-
plied digital code, it is important that the voltages at both of
the current output pins be as near ground potential (0V
DC
)
as possible. With V
REF
=+10V every millivolt appearing at ei-
ther I
OUT1
or I
OUT2
will cause a 0.01% linearity error. In most
applications this output current is converted to a voltage by
using an op amp as shown in Figure 7.
The inverting input of the op amp is a virtual ground created
by the feedback from its output through the internal 15 k re-
sistor, R
fb
. All of the output current (determined by the digital
input and the reference voltage) will flow through R
fb
to the
output of the amplifier. Two-quadrant operation can be ob-
tained by reversing the polarity of V
REF
thus causing I
OUT1
to
flow into the DAC and be sourced from the output of the am-
plifier. The output voltage, in either case, is always equal to
I
OUT1
xR
fb
and is the opposite polarity of the reference volt-
age.
The reference can be either a stable DC voltage source or
an AC signal anywhere in the range from 10V to +10V. The
DAC can be thought of as a digitally controlled attenuator:
the output voltage is always less than or equal to the applied
reference voltage. The V
REF
terminal of the device presents
a nominal impedance of 15 k to ground to external circuitry.
Always use the internal R
fb
resistor to create an output volt-
age since this resistor matches (and tracks with tempera-
ture) the value of the resistors used to generate the output
current (I
OUT1
).
DS005608-8
FIGURE 5. Accommodating a High Speed System
www.national.com 11
DAC0830 Series Application Hints (Continued)
2.3 Op Amp Considerations
The op amp used in Figure 7 should have offset voltage null-
ing capability (See Section 2.5).
The selected op amp should have as low a value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage er-
ror which can be significant in low reference voltage applica-
tions. BI-FET op amps are highly recommended for use
with these DACs because of their very low input current.
Transient response and settling time of the op amp are im-
portant in fast data throughput applications. The largest sta-
bility problem is the feedback pole created by the feedback
resistance, R
fb
, and the output capacitance of the DAC. This
appears from the op amp output to the () input and includes
the stray capacitance at this node. Addition of a lead capaci-
tance, C
C
in Figure 8, greatly reduces overshoot and ringing
at the output for a step change in DAC output current.
Finally, the output voltage swing of the amplifier must be
greater than V
REF
to allow reaching the full scale output volt-
age. Depending on the loading on the output of the amplifier
and the available op amp supply voltages (only 12 volts in
many development systems), a reference voltage less than
10 volts may be necessary to obtain the full analog output
voltage range.
2.4 Bipolar Output Voltage with a Fixed Reference
The addition of a second op amp to the previous circuitry can
be used to generate a bipolar output voltage from a fixed ref-
erence voltage. This, in effect, gives sign significance to the
MSB of the digital input word and allows two-quadrant multi-
plication of the reference voltage. The polarity of the refer-
ence can also be reversed to realize full 4-quadrant multipli-
cation: V
REF
xDigital Code=V
OUT
. This circuit is shown
in Figure 9.
This configuration features several improvements over exist-
ing circuits for bipolar outputs with other multiplying DACs.
Only the offset voltage of amplifier 1 has to be nulled to pre-
serve linearity of the DAC. The offset voltage error of the
second op amp (although a constant output voltage error)
has no effect on linearity. It should be nulled only if absolute
output accuracy is required. Finally, the values of the resis-
tors around the second amplifier do not have to match the in-
ternal DAC resistors, they need only to match and tempera-
ture track each other. A thin film 4-resistor network available
from Beckman Instruments, Inc. (part no. 694-3-R10K-D) is
ideally suited for this application. These resistors are
matched to 0.1% and exhibit only 5 ppm/C resistance track-
ing temperature coefficient. Two of the four available 10 k
resistors can be paralleled to form R in Figure 9 and the
other two can be used independently as the resistances la-
beled 2R.
2.5 Zero Adjustment
For accurate conversions, the input offset voltage of the out-
put amplifier must always be nulled. Amplifier offset errors
create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near 0V
DC
as possible.
This is accomplished for the typical DAC op amp connec-
tion (Figure 7) by shorting out R
fb
, the amplifier feedback re-
sistor, and adjusting the V
OS
nulling potentiometer of the op
amp until the output reads zero volts. This is done, of course,
with an applied digital code of all zeros if I
OUT1
is driving the
op amp (all ones for I
OUT2
). The short around R
fb
is then re-
moved and the converter is zero adjusted.
DS005608-37
FIGURE 6.
DS005608-38
FIGURE 7.
www.national.com 12
DAC0830 Series Application Hints (Continued)
2.6 Full-Scale Adjustment
In the case where the matching of R
fb
to the R value of the
R-2R ladder (typically 0.2%) is insufficient for full-scale ac-
curacy in a particular application, the V
REF
voltage can be
adjusted or an external resistor and potentiometer can be
added as shown in Figure 10 to provide a full-scale adjust-
ment.
The temperature coefficients of the resistors used for this ad-
justment are of an important concern. To prevent degrada-
tion of the gain error temperature coefficient by the external
resistors, their temperature coefficients ideally would have to
match that of the internal DAC resistors, which is a highly im-
practical constraint. For the values shown in Figure 10, if the
resistor and the potentiometer each had a temperature coef-
ficient of 100 ppm/C maximum, the overall gain error tem-
perature coefficent would be degraded a maximum of
0.0025%/C for an adjustment pot setting of less than 3% of
R
fb
.
DS005608-39
t
s
OP Amp C
C
(O to Full Scale)
LF356 22 pF 4 s
LF351 22 pF 5 s
LF357* 10 pF 2 s
*2.4 k RESISTOR ADDED FROMINPUT TO GROUND TO
INSURE STABILITY
FIGURE 8.
DS005608-40
Input Code IDEAL V
OUT
MSB LSB +V
REF
V
REF
1 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1
0 0 0 0 0 0 0 0
*THESE RESISTORS ARE AVAILABLE FROM BECKMAN INSTRUMENTS, INC. AS THEIR PART NO. 694-3-R10K-D
FIGURE 9.
www.national.com 13
DAC0830 Series Application Hints
(Continued)
2.7 Using the DAC0830 in a Voltage Switching
Configuration
The R-2R ladder can also be operated as a voltage switch-
ing network. In this mode the ladder is used in an inverted
manner from the standard current switching configuration.
The reference voltage is connected to one of the current out-
put terminals (I
OUT1
for true binary digital control, I
OUT2
is for
complementary binary) and the output voltage is taken from
the normal V
REF
pin. The converter output is now a voltage
in the range from 0V to 255/256 V
REF
as a function of the ap-
plied digital code as shown in Figure 11.
This configuration offers several useful application advan-
tages. Since the output is a voltage, an external op amp is
not necessarily required but the output impedance of the
DAC is fairly high (equal to the specified reference input re-
sistance of 10 k to 20 k) so an op amp may be used for
buffering purposes. Some of the advantages of this mode
are illustrated in Figures 12, 13, 14, 15.
There are two important things to keep in mind when using
this DAC in the voltage switching mode. The applied refer-
ence voltage must be positive since there are internal para-
sitic diodes from ground to the I
OUT1
and I
OUT2
terminals
which would turn on if the applied reference went negative.
There is also a dependence of conversion linearity and gain
error on the voltage difference between V
CC
and the voltage
applied to the normal current output terminals. This is a re-
sult of the voltage drive requirements of the ladder switches.
To ensure that all 8 switches turn on sufficiently (so as not to
add significant resistance to any leg of the ladder and
thereby introduce additional linearity and gain errors) it is
recommended that the applied reference voltage be kept
less than +5V
DC
and V
CC
be at least 9V more positive than
V
REF
. These restrictions ensure less than 0.1% linearity and
gain error change. Figures 16, 17, 18 characterize the ef-
fects of bringing V
REF
and V
CC
closer together as well as
typical temperature performance of this voltage switching
configuration.
DS005608-11
FIGURE 10. Adding Full-Scale Adjustment
DS005608-12
FIGURE 11. Voltage Mode Switching
DS005608-41
Voltage switching mode eliminates output signal inver-
sion and therefore a need for a negative power supply.
Zero code output voltage is limited by the low level output
saturation voltage of the op amp. The 2 k pull-down re-
sistor helps to reduce this voltage.
V
OS
of the op amp has no effect on DAC linearity.
FIGURE 12. Single Supply DAC
www.national.com 14
DAC0830 Series Application Hints (Continued)
DS005608-42
FIGURE 13. Obtaining a Bipolar Output from a Fixed
Reference with a Single Op Amp
DS005608-60
FIGURE 14. Bipolar Output with Increased Output Voltage Swing
www.national.com 15
DAC0830 Series Application Hints (Continued)
DS005608-14
FIGURE 15. Single Supply DAC with Level Shift and Span-
Adjustable Output
Gain and Linearity Error
Variation vs. Supply Voltage
DS005608-32
Note: For these curves, V
REF
is the voltage applied to pin 11 (I
OUT1
) with
pin 12 (I
OUT2
) grounded.
FIGURE 16.
Gain and Linearity Error
Variation vs. Reference Voltage
DS005608-33
FIGURE 17.
www.national.com 16
DAC0830 Series Application Hints
(Continued)
2.8 Miscellaneous Application Hints
These converters are CMOS products and reasonable care
should be exercised in handling them to prevent catastrophic
failures due to static discharge.
Conversion accuracy is only as good as the applied refer-
ence voltage so providing a stable source over time and tem-
perature changes is an important factor to consider.
A good ground is most desirable. A single point ground dis-
tribution technique for analog signals and supply returns
keeps other devices in a system from affecting the output of
the DACs.
During power-up supply voltage sequencing, the 15V (or
12V) supply of the op amp may appear first. This will cause
the output of the op amp to bias near the negative supply po-
tential. No harm is done to the DAC, however, as the on-chip
15 k feedback resistor sufficiently limits the current flow
from I
OUT1
when this lead is internally clamped to one diode
drop below ground.
Careful circuit construction with minimization of lead lengths
around the analog circuitry, is a primary concern. Good high
frequency supply decoupling will aid in preventing inadvert-
ant noise from appearing on the analog output.
Overall noise reduction and reference stability is of particular
concern when using the higher accuracy versions, the
DAC0830 and DAC0831, or their advantages are wasted.
3.0 GENERAL APPLICATION IDEAS
The connections for the control pins of the digital input regis-
ters are purposely omitted. Any of the control formats dis-
cussed in Section 1 of the accompanying text will work with
any of the circuits shown. The method used depends on the
overall system provisions and requirements.
The digital input code is referred to as D and represents the
decimal equivalent value of the 8-bit binary input, for ex-
ample:
Binary Input D
Pin 13 Pin 7 Decimal
MSB LSB Equivalent
1 1 1 1 1 1 1 1 255
1 0 0 0 0 0 0 0 128
0 0 0 1 0 0 0 0 16
0 0 0 0 0 0 1 0 2
0 0 0 0 0 0 0 0 0
Gain and Linearity Error
Variation vs. Temperature
DS005608-34
FIGURE 18.
www.national.com 17
Applications
DAC Controlled Amplifier (Volume Control)
DS005608-43
Capacitance Multiplier
DS005608-44
Variable f
O
, Variable Q
O
, Constant BW Bandpass Filter
DS005608-17
www.national.com 18
Applications (Continued)
DAC Controlled Function Generator
DS005608-18
www.national.com 19
Applications (Continued)
Two Terminal Floating 4 to 20 mA Current Loop Controller
DS005608-19
DAC0830 linearly controls the current flow from the input terminal to the output terminal to be 4 mA (for D=0) to 19.94 mA (for
D=255).
Circuit operates with a terminal voltage differential of 16V to 55V.
P
2
adjusts the magnitude of the output current and P
1
adjusts the zero to full scale range of output current.
Digital inputs can be supplied from a processor using opto isolators on each input or the DAC latches can flow-through (con-
nect control lines to pins 3 and 10 of the DAC) and the input data can be set by SPST toggle switches to ground (pins 3 and
10).
www.national.com 20
Applications (Continued)
Ordering Information
Temperature Range 0C to +70 40C to
+85C
55C to
+125C
Non
0.05%
FSR
DAC0830LCN DAC0830LCM DAC0830LCV DAC0830LCJ DAC0830LJ
Linearity 0.1%
FSR
DAC0831LCN
0.2%
FSR
DAC0832LCN DAC0832LCM DAC0832LCV DAC0832LCJ DAC0832LJ
Package Outline N20AMolded
DIP
M20B Small
Outline
V20A Chip Carrier J20ACeramic DIP
DAC Controlled Exponential Time Response
DS005608-20
Output responds exponentially to input changes and automatically stops when V
OUT
=V
IN
Output time constant is directly proportional to the DAC input code and capacitor C
Input voltage must be positive (See section 2.7)
www.national.com 21
Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number DAC0830LCJ,
DAC0830LJ, DAC0832LJ or DAC0832LCJ
NS Package Number J20A
www.national.com 22
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Small Outline Package (M)
Order Number DAC0830LCM
or DAC0832LCM
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number DAC0830LCN,
or DAC0832LCN
NS Package Number N20A
www.national.com 23
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Tel: 1-800-272-9959
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Email: [email protected]
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Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
www.national.com
Molded Chip Carrier (V)
Order Number DAC0830LCV
or DAC0832LCV
NS Package Number V20A
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.