SPR 2002 EE567 Design of 2-Stage Op Amp: Layout & Simulation Files
SPR 2002 EE567 Design of 2-Stage Op Amp: Layout & Simulation Files
SPR 2002 EE567 Design of 2-Stage Op Amp: Layout & Simulation Files
1.Current Source
2.Sourcing Mirror
3.Sinking Mirror
4.High Output Resistance Mirror
5. Common Source Amp
6. Differential Amp
7. Buffer Source Follower Stage
8. Buffered Differential Amp
9. Two Stage Uncompensated Op Amp
1.
3.
4.
5.
*DC ANALYSIS
*v(VOUT) = 2.6589e+000
*v(VA) = 1.5037e+000
*v(VB) = 3.0405e+000
*v(VIN) = 1.4770e+000
*v(VDD) = 5.0000e+000
*i(VDD) = -4.0538e-004
*i(VIN) = 0.0000e+000
*AC SMALL-SIGNAL MODELS
*
M1
M2
M3
M4
M5
*MODEL
pmos
pmos
nmos
nmos
nmos
*TYPE
PMOS
PMOS
NMOS
NMOS
NMOS
*ID
-2.03e-004 -2.03e-004 -2.03e-004 2.03e-004 2.03e-004
*RD
0.00e+000 0.00e+000 0.00e+000 0.00e+000 0.00e+000
*GM
3.05e-004 2.77e-004 -4.85e-004 4.82e-004 3.88e-004
CSAMP
C/B
50
45
40
Voltage (V)
35
30
25
20
15
10
0
1.0E+001
3.2E+001
1.0E+002
3.2E+002
1.0E+003
3.2E+003
1.0E+004
3.2E+004
1.0E+005
3.2E+005
1.0E+006
3.2E+006
1.0E+007
Frequency (Hz)
6.
3.2E+007
1.0E+008
DC ANALYSIS of BUFFER
v(VOUT) = 1.4798e+000
v(VB) = 3.0405e+000
v(VA) = 1.5037e+000
v(VIN) = 3.2700e+000
v(VDD) = 5.0000e+000
i(VDD) = -4.0499e-004
i(VIN) = 0.0000e+000
y1 =
886.40
y2 =
859.56
dy =
BuffDiffN
-26.85
D/(B-C)
E/(B-C)
60
55
50
45
Voltage (V)
40
35
30
25
20
15
10
1.0E+001
3.2E+001
1.0E+002
3.2E+002
1.0E+003
3.2E+003
1.0E+004
3.2E+004
1.0E+005
Frequency (Hz)
DC ANALYSIS
v(VA) = 1.5062e+000
v(VB) = 3.0452e+000
v(TAIL) = 1.5084e+000
v(VOUT) = 2.3878e+000
v(VOUT2) = 3.2717e+000
v(VIN) = 1.4792e+000
3.2E+005
1.0E+006
3.2E+006
1.0E+007
3.2E+007
1.0E+008
v(VIN2) = 2.7584e+000
v(VIN1) = 2.7584e+000
v(VDD) = 5.0000e+000
i(VDD) = -8.1325e-004
i(VIN1) = 0.0000e+000
i(VIN2) = 0.0000e+000
TOTAL POWER CONSUMPTION = 4.06mW
Uncompensated OP AMP AC ANALYSIS Voltage Gain Mag = 2,870 (69dB)
OA1
vm(VOUT)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.0E+001
3.2E+001
1.0E+002
3.2E+002
1.0E+003
3.2E+003
1.0E+004
3.2E+004
1.0E+005
Frequency (Hz)
3.2E+005
1.0E+006
3.2E+006
1.0E+007
3.2E+007
1.0E+008
OA1
vp(VOUT)
150
100
-50
-100
-150
1.0E+001
3.2E+001
1.0E+002
3.2E+002
1.0E+003
3.2E+003
1.0E+004
3.2E+004
1.0E+005
Frequency (Hz)
Model File
.model nmos nmos
+ Level=2
Ld=0.0u
Tox=225.00E-10
+ Nsub=1.066E+16 Vto=0.622490 Kp=6.326640E-05
+ Gamma=.639243
Phi=0.31
Uo=1215.74
+ Uexp=4.612355E-2 Ucrit=174667 Delta=0.0
+ Vmax=177269
Xj=.9u
Lambda=0.0
+ Nfs=4.55168E+12 Neff=4.68830 Nss=3.00E+10
+ Tpg=1.000
Rsh=60
Cgso=2.89E-10
+ Cgdo=2.89E-10
Cj=3.27E-04 Mj=1.067
+ Cjsw=1.74E-10
Mjsw=0.195
.model pmos pmos
+ Level=2
Ld=.03000u Tox=225.000E-10
+ Nsub=6.575441E+16 Vto=-0.63025 Kp=2.635440E-05
+ Gamma=0.618101 Phi=.541111 Uo=361.941
+ Uexp=8.886957E-02 Ucrit=637449 Delta=0.0
+ Vmax=63253.3
Xj=0.112799u Lambda=0.0
+ Nfs=1.668437E+11 Neff=0.64354 Nss=3.00E+10
+ Tpg=-1.00
Rsh=150
Cgso=3.35E-10
+ Cgdo=3.35E-10
Cj=4.75E-04 Mj=.341
+ Cjsw=2.23E-10
Mjsw=0.307
10. Two Stage Compensated Op Amp
Layout for a 2pF capacitor
3.2E+005
1.0E+006
3.2E+006
1.0E+007
3.2E+007
1.0E+008
TSPICE Netlist
C1 CAP2 1 C=2.0628646p
* C1 PLUS MINUS (-27.5 -51.5 62.5 100)
* Total Nodes: 2
* Total Elements: 1
* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
.END
Compensated Op Amp Layout (showing Compensation Capacitor)
Magnitude and Phase Open Loop Responses Pre and Post Compensation
Compensation Capacitor =10pf
With Closed Loop Gain of 10, PM =48degrees
(Top trace = magnitude response, bottom trace = phase response)
Open Loop bandwidth after compensation = 95K
COMPOA
D/F
3 .0
H/K
2 .5
2 .0
1 .5
1 .0
0 .5
0 .0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
COMPOA
v p (VOUT)
v p (VOUT)
15 0
10 0
50
-5 0
-1 0 0
-1 5 0
10
100
1k
10k
100k
Frequency (Hz)
Model File
.model nmos nmos
+ Level=2
Ld=0.0u
Tox=225.00E-10
+ Nsub=1.066E+16 Vto=0.622490 Kp=6.326640E-05
+ Gamma=.639243
Phi=0.31
Uo=1215.74
+ Uexp=4.612355E-2 Ucrit=174667 Delta=0.0
+ Vmax=177269
Xj=.9u
Lambda=0.0
+ Nfs=4.55168E+12 Neff=4.68830 Nss=3.00E+10
+ Tpg=1.000
Rsh=60
Cgso=2.89E-10
+ Cgdo=2.89E-10
Cj=3.27E-04 Mj=1.067
+ Cjsw=1.74E-10
Mjsw=0.195
.model pmos pmos
+ Level=2
Ld=.03000u Tox=225.000E-10
+ Nsub=6.575441E+16 Vto=-0.63025 Kp=2.635440E-05
+ Gamma=0.618101 Phi=.541111 Uo=361.941
+ Uexp=8.886957E-02 Ucrit=637449 Delta=0.0
+ Vmax=63253.3
Xj=0.112799u Lambda=0.0
+ Nfs=1.668437E+11 Neff=0.64354 Nss=3.00E+10
+ Tpg=-1.00
Rsh=150
Cgso=3.35E-10
+ Cgdo=3.35E-10
Cj=4.75E-04 Mj=.341
+ Cjsw=2.23E-10
Mjsw=0.307
1M
10M
100M
Schematic
Layout
Layout
Am pere (uA)
-140
-145
-150
-155
2.5
3.0
3.5
Voltage (V)
4.0
Schematic
Plot transfer characteristic for amplifying device M3 to determine VGS for IDS=144.6uA
Sweep VIN from 0.5 to 0.8 volt. Set VOUT=3V
Netlist File for Driver M3 device Transfer Characteristic
VOUT VOUT GND 3
VIN VIN GND 1
.dc VIN .5 .8 .0005
.print dc id(M3)
M3 GND VIN VOUT GND NMOS L=2.4u W=558.9u AD=6.53913n PD=1.1412m AS=5.70078n
PS=1.1382m
* M3 DRAIN GATE SOURCE BULK (140.5 -73.5 1072 -69.5)
.END
DC Transfer Characteristic Results
*GM=1.78mA/V at VDS=3V VGS=0.731V
DC Transfer Characteristic Plot:
x1 = 533.59m
x2 = 732.48m
dx =
198.90m
y1 =
-206.88u
y2 =
-146.62u
AMPTFHRO
dy =
60.26u
id(M3)
-42.35u
Ampere (uA)
-50
-100
-150
550
600
650
700
750
Voltage (mV)
-135
Ampere (uA)
-140
-145
-150
-155
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
Voltage (V)
3.5
Layout
NETLIST File
VIN VIN GND 0.7312 AC 0.01 0
.ac dec 5 10 100MEG
.print ac v(VOUT) v(VIN)
VDD VDD GND 5
M1 VOUT VB VDD VDD PMOS L=3.6u W=28.8u AD=216p PD=72.6u AS=190.08p PS=70.8u
* M1 DRAIN GATE SOURCE BULK (161.5 67.5 209.5 73.5)
M2 VB VB VDD VDD PMOS L=1.2u W=9.6u AD=51.84p PD=30u AS=40.32p PS=27.6u
* M2 DRAIN GATE SOURCE BULK (56 66 72 68)
M3 GND VIN VOUT GND NMOS L=2.4u W=558.9u AD=6.53913n PD=1.1412m AS=5.70078n
PS=1.1382m
* M3 DRAIN GATE SOURCE BULK (140.5 -73.5 1072 -69.5)
M4 VA VB VB GND NMOS L=1.2u W=9.6u AD=83.52p PD=36.6u AS=51.84p PS=30u
* M4 DRAIN GATE SOURCE BULK (57.5 -50 73.5 -48)
M5 GND VA VA GND NMOS L=1.2u W=9.6u AD=83.52p PD=36.6u AS=51.84p PS=30u
* M5 DRAIN GATE SOURCE BULK (57.5 -89.5 73.5 -87.5)
.END
Frequency Domain Analysis Results
Theoretic Av (calc) = - GM3 X (RDS1//RDS3) = - 1.78mA/V X ( 125K//250K)
= - 1.78mA/V X 83.33K = 147.5
Actual Av (Simulated) =150
CSAMP144
C/B
150
Voltage (V)
100
50
0
1.0E+001
3.2E+001
1.0E+002
3.2E+002
1.0E+003
3.2E+003
1.0E+004
3.2E+004
1.0E+005
Frequency (Hz)
3.2E+005
1.0E+006
3.2E+006
1.0E+007
3.2E+007
1.0E+008