TDA8920B: 1. General Description

TDA8920B
2 × 100 W class-D power amplifier

Rev. 02 — 07 November 2005 Product data sheet
1. General description
The TDA8920B is a high efficiency class-D audio power amplifier with very low
dissipation. The typical output power is 2 × 100 W.
The device is available in the HSOP24 power package and in the DBS23P through-hole
power package. The amplifier operates over a wide supply voltage range from
±12.5 V to ±30 V (±32 V non operating) and consumes a very low quiescent current.
2. Features
■ Zero dead time switching
■ Advanced current protection: output current limiting
■ Smooth start-up: no pop noise due to DC offset
■ High efficiency
■ Operating supply voltage from ±12.5 V to ±30 V
■ Low quiescent current
■ Usable as a stereo Single-Ended (SE) amplifier or as a mono amplifier in Bridge-Tied
Load (BTL)
■ Fixed gain of 30 dB in Single-Ended (SE) and 36 dB in Bridge-Tied Load (BTL)
■ High output power
■ High supply voltage ripple rejection
■ Internal switching frequency can be overruled by an external clock
■ Full short-circuit proof across load and to supply lines
■ Thermally protected
3. Applications
■ Television sets
■ Home-sound sets
■ Multimedia systems
■ All mains fed audio systems
■ Car audio (boosters)
Philips Semiconductors TDA8920B
4. Quick reference data

Table 1: Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
General; VP = ±27 V
VP supply voltage ±12.5 ±27 ±30 V
Iq(tot) total quiescent no load; no filter; no RC-snubber - 50 65 mA
supply current network connected
Stereo single-ended configuration
Po output power RL = 3 Ω; THD = 10 %; VP = ±27 V - 110 - W
RL = 4 Ω; THD = 10 %; VP = ±27 V - 86 - W
Mono bridge-tied load configuration
Po output power RL = 6 Ω; THD = 10 %; VP = ±27 V - 210 - W
5. Ordering information
Table 2: Ordering information
Type number Package
Name Description Version
TDA8920BTH HSOP24 plastic, heatsink small outline package; 24 leads; low SOT566-3
stand-off height
TDA8920BJ DBS23P plastic DIL-bent-SIL power package; 23 leads (straight SOT411-1
lead length 3.2 mm)
TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 07 November 2005 2 of 34

6. Block diagram
VDDA2 VDDA1 STABI PROT VDDP2 VDDP1
3 (20) 10 (4) 18 (12) 13 (7) 23 (16) 14 (8)

15 (9)
BOOT1
9 (3) RELEASE1
IN1M DRIVER
INPUT PWM
SWITCH1 HIGH
8 (2) STAGE MODULATOR CONTROL 16 (10)
IN1P AND OUT1
ENABLE1 HANDSHAKE
DRIVER
mute
11 (5) LOW
SGND1
STABI
VSSP1
7 (1)
OSC
TEMPERATURE SENSOR TDA8920BTH
6 (23) OSCILLATOR MANAGER (TDA8920BJ) VDDP2
CURRENT PROTECTION
MODE MODE
VOLTAGE PROTECTION
22 (15)
BOOT2
2 (19)
SGND2
mute ENABLE2 DRIVER
CONTROL HIGH
5 (22) SWITCH2 21 (14)
AND OUT2
IN2P
INPUT PWM HANDSHAKE
RELEASE2 DRIVER
4 (21) STAGE MODULATOR
IN2M LOW
1 (18) 12 (6) 24 (17) 19 (-) 17 (11) 20 (13) coa023

VSSA2 VSSA1 VSSD n.c. VSSP1 VSSP2
Pin numbers in parenthesis refer to the TDA8920BJ.

Fig 1. Block diagram

7. Pinning information
7.1 Pinning
OSC 1
IN1P 2
IN1M 3
VDDA1 4
SGND1 5
VSSA1 6
VSSD 24 1 VSSA2
PROT 7
VDDP2 23 2 SGND2
VDDP1 8
BOOT2 22 3 VDDA2
BOOT1 9
OUT2 21 4 IN2M
OUT1 10
VSSP2 20 5 IN2P
VSSP1 11
n.c. 19 6 MODE
TDA8920BTH STABI 12 TDA8920BJ
STABI 18 7 OSC
VSSP2 13
VSSP1 17 8 IN1P
OUT2 14
OUT1 16 9 IN1M
BOOT2 15
BOOT1 15 10 VDDA1
VDDP2 16
VDDP1 14 11 SGND1
VSSD 17
PROT 13 12 VSSA1
VSSA2 18
SGND2 19
001aab217
VDDA2 20
IN2M 21
IN2P 22
MODE 23
001aab218
Fig 2. Pin configuration TDA8920BTH Fig 3. Pin configuration TDA8920BJ
7.2 Pin description

Table 3: Pin description
Symbol Pin Description
TDA8920BTH TDA8920BJ
VSSA2 1 18 negative analog supply voltage for channel 2
SGND2 2 19 signal ground for channel 2
VDDA2 3 20 positive analog supply voltage for channel 2
IN2M 4 21 negative audio input for channel 2
IN2P 5 22 positive audio input for channel 2
MODE 6 23 mode selection input: Standby, Mute or Operating mode
OSC 7 1 oscillator frequency adjustment or tracking input
IN1P 8 2 positive audio input for channel 1
IN1M 9 3 negative audio input for channel 1
VDDA1 10 4 positive analog supply voltage for channel 1

Table 3: Pin description …continued

Symbol Pin Description
TDA8920BTH TDA8920BJ
SGND1 11 5 signal ground for channel 1
VSSA1 12 6 negative analog supply voltage for channel 1
PROT 13 7 decoupling capacitor for protection (OCP)
VDDP1 14 8 positive power supply voltage for channel 1
BOOT1 15 9 bootstrap capacitor for channel 1
OUT1 16 10 PWM output from channel 1
VSSP1 17 11 negative power supply voltage for channel 1
STABI 18 12 decoupling of internal stabilizer for logic supply
n.c. 19 - not connected
VSSP2 20 13 negative power supply voltage for channel 2
OUT2 21 14 PWM output from channel 2
BOOT2 22 15 bootstrap capacitor for channel 2
VDDP2 23 16 positive power supply voltage for channel 2
VSSD 24 17 negative digital supply voltage
8. Functional description
8.1 General
The TDA8920B is a two channel audio power amplifier using class-D technology.
The audio input signal is converted into a digital pulse width modulated signal via an
analog input stage and Pulse Width Modulation (PWM) modulator. To enable the output
power transistors to be driven, this digital PWM signal is applied to a control and
handshake block and driver circuits for both the high side and low side. In this way a level
shift is performed from the low power digital PWM signal (at logic levels) to a high power
PWM signal which switches between the main supply lines.
A 2nd-order low-pass filter converts the PWM signal to an analog audio signal across the
loudspeakers.
The TDA8920B one-chip class-D amplifier contains high power D-MOS switches, drivers,
timing and handshaking between the power switches and some control logic. For
protection a temperature sensor and a maximum current detector are built-in.
The two audio channels of the TDA8920B contain two PWM modulators, two analog
feedback loops and two differential input stages. It also contains circuits common to both
channels such as the oscillator, all reference sources, the mode functionality and a digital
timing manager.
The TDA8920B contains two independent amplifier channels with high output power, high
efficiency, low distortion and a low quiescent current. The amplifier channels can be
connected in the following configurations:
• Mono Bridge-Tied Load (BTL) amplifier

• Stereo Single-Ended (SE) amplifiers

The amplifier system can be switched to one of three operating modes by pin MODE:
• Standby mode; with a very low supply current

• Mute mode; the amplifiers are operational; but the audio signal at the output is
suppressed by disabling the VI-converter input stages
• Operating mode; the amplifiers are fully operational with output signal
To ensure pop noise-free start-up, the DC output offset voltage is applied gradually to the
output at a level between Mute mode and Operating mode levels. The bias current setting
of the VI converters is related to the voltage on the MODE pin; in Mute mode the bias
current setting of the VI converters is zero (VI converters disabled) and in Operating mode
the bias current is at maximum. The time constant required to apply the DC output offset
voltage gradually between Mute and Operating mode levels can be generated via an
RC-network on the MODE pin. An example of a switching circuit for driving pin MODE is
illustrated in Figure 4. If the capacitor C is left out of the application the voltage on the
MODE pin will be applied with a much smaller time-constant, which might result in audible
pop noises during start-up (depending on DC output offset voltage and loudspeaker
used).
In order to fully charge the coupling capacitors at the inputs, the amplifier will remain
automatically in the Mute mode before switching to the Operating mode. A complete
overview of the start-up timing is given in Figure 5.
+5 V
standby/
mute
MODE pin
R
C
mute/on
SGND
001aab172
Fig 4. Example of mode selection circuit

audio output
modulated PWM
Vmode
50 %
duty cycle
operating
> 4.2 V
mute
2.2 V < Vmode < 3 V
standby
0 V (SGND)
100 ms > 350 ms time
50 ms
audio output
modulated PWM
Vmode
50 %
duty cycle
operating
> 4.2 V
mute
2.2 V < Vmode < 3 V
standby
0 V (SGND)
100 ms > 350 ms time
50 ms
coa024
Upper diagram: When switching from standby to mute, there is a delay of 100 ms before the
output starts switching. The audio signal is available after Vmode has been set to operating, but
not earlier than 150 ms after switching to mute. For pop noise-free start-up it is recommended
that the time constant applied to the MODE pin is at least 350 ms for the transition between
mute and operating.
Lower diagram: When switching directly from standby to operating, there is a first delay of
100 ms before the outputs starts switching. The audio signal is available after a second delay
of 50 ms. For pop noise-free start-up it is recommended that the time constant applied to the
MODE pin is at least 500 ms for the transition between standby and operating.
Fig 5. Timing on mode selection input

8.2 Pulse width modulation frequency

The output signal of the amplifier is a PWM signal with a carrier frequency of
approximately 317 kHz. Using a 2nd-order LC demodulation filter in the application results
in an analog audio signal across the loudspeaker. This switching frequency is fixed by an
external resistor ROSC connected between pin OSC and VSSA. An optimal setting for the
carrier frequency is between 300 kHz and 350 kHz.
Using an external resistor of 30 kΩ on the OSC pin, the carrier frequency is set to
317 kHz.
If two or more class-D amplifiers are used in the same audio application, it is advisable to
have all devices operating at the same switching frequency by using an external clock
circuit.
8.3 Protections
The following protections are included in TDA8920B:
• OverTemperature Protection (OTP)

• OverCurrent Protection (OCP)
• Window Protection (WP)
• Supply voltage protections:
– UnderVoltage Protection (UVP)
– OverVoltage Protection (OVP)
– UnBalance Protection (UBP)
The reaction of the device to the different fault conditions differs per protection.
8.3.1 OverTemperature Protection (OTP)

If the junction temperature Tj > 150 °C, then the power stage will shut-down immediately.
The power stage will start switching again if the temperature drops to approximately
130 °C, thus there is a hysteresis of approximately 20 °C.
8.3.2 OverCurrent Protection (OCP)

When the loudspeaker terminals are short-circuited or if one of the demodulated outputs
of the amplifier is short-circuited to one of the supply lines, this will be detected by the
OverCurrent Protection (OCP). If the output current exceeds the maximum output current
of 8 A, this current will be limited by the amplifier to 8 A while the amplifier outputs remain
switching (the amplifier is NOT shut-down completely).
The amplifier can distinguish between an impedance drop of the loudspeaker and a
low-ohmic short across the load. In the TDA8920B this impedance threshold (Zth)
depends on the supply voltage used.
When a short is made across the load causing the impedance to drop below the threshold
level (< Zth) then the amplifier is switched off completely and after a time of 100 ms it will
try to restart again. If the short circuit condition is still present after this time this cycle will
be repeated. The average dissipation will be low because of this low duty cycle.

In case of an impedance drop (e.g. due to dynamic behavior of the loudspeaker) the same
protection will be activated; the maximum output current is again limited to 8 A, but the
amplifier will NOT switch-off completely (thus preventing audio holes from occurring).
Result will be a clipping output signal without any artefacts.
See also Section 13.6 for more information on this maximum output current limiting
feature.
8.3.3 Window Protection (WP)

During the start-up sequence, when pin MODE is switched from standby to mute, the
conditions at the output terminals of the power stage are checked. In the event of a
short-circuit at one of the output terminals to VDD or VSS the start-up procedure is
interrupted and the system waits for open-circuit outputs. Because the test is done before
enabling the power stages, no large currents will flow in the event of a short-circuit. This
system is called Window Protection (WP) and protects for short-circuits at both sides of
the output filter to both supply lines. When there is a short-circuit from the power PWM
output of the power stage to one of the supply lines (before the demodulation filter) it will
also be detected by the start-up safety test. Practical use of this test feature can be found
in detection of short-circuits on the printed-circuit board.
Remark: This test is operational during (every) start-up sequence at a transition between
Standby and Mute mode. However when the amplifier is completely shut-down due to
activation of the OverCurrent Protection (OCP) because a short to one of the supply lines
occurred, then during restart (after 100 ms) the window protection will be activated. As a
result the amplifier will not start-up until the short to the supply line is removed.

8.3.4 Supply voltage protections

If the supply voltage drops below ±12.5 V, the UnderVoltage Protection (UVP) circuit is
activated and the system will shut-down correctly. If the internal clock is used, this
switch-off will be silent and without pop noise. When the supply voltage rises above the
threshold level, the system is restarted again after 100 ms. If the supply voltage exceeds
±33 V the OverVoltage Protection (OVP) circuit is activated and the power stages will
shut-down. It is re-enabled as soon as the supply voltage drops below the threshold level.
So in this case no timer of 100 ms is started.
An additional UnBalance Protection (UBP) circuit compares the positive analog (VDDA)
and the negative analog (VSSA) supply voltages and is triggered if the voltage difference
between them exceeds a certain level. This level depends on the sum of both supply
voltages. An expression for the unbalanced threshold level is as follows:
Vth(ub) ≈ 0.15 × (VDDA + VSSA).
When the supply voltage difference drops below the threshold level, the system is
restarted again after 100 ms.
Example: With a symmetrical supply of ±30 V, the protection circuit will be triggered if the
unbalance exceeds approximately 9 V; see also Section 13.7.
In Table 4 an overview is given of all protections and the effect on the output signal.
Table 4: Overview of TDA8920B protections

Protection name Complete shut-down Restart directly Restart every 100 ms
OTP Y Y [1] N [1]
OCP N [2] Y [2] N [2]
WP Y [3] Y N
UVP Y N Y
OVP Y Y N
UBP Y N Y
[1] Hysteresis of 20 °C will influence restart timing depending on heatsink size.

[2] Only complete shut-down of amplifier if short-circuit impedance is below threshold of 1 Ω. In all other cases
current limiting: resulting in clipping output signal.
[3] Fault condition detected during (every) transition between standby-to-mute and during restart after
activation of OCP (short to one of the supply lines).

8.4 Differential audio inputs

For a high common mode rejection ratio and a maximum of flexibility in the application, the
audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of
the channels can be inverted, so that a load can be connected between the two output
filters. In this case the system operates as a mono BTL amplifier and with the same
loudspeaker impedance an approximately four times higher output power can be
obtained.
The input configuration for a mono BTL application is illustrated in Figure 6.
In the stereo single-ended configuration it is also recommended to connect the two

differential inputs in anti-phase. This has advantages for the current handling of the power
supply at low signal frequencies.
OUT1
IN1P
IN1M
Vin SGND
IN2P
IN2M OUT2
power stage
mbl466
Fig 6. Input configuration for mono BTL application
9. Limiting values
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VP supply voltage
operating - ±30 V
non operating [1] - ±32 V
IORM repetitive peak current in maximum output [2] 8 - A
output pin current limiting
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −40 +85 °C
Tj junction temperature - 150 °C
[1] Overvoltage protection might be activated.

[2] Current limiting concept. See also Section 13.6.

10. Thermal characteristics

Table 6: Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient [1]
TDA8920BTH in free air 35 K/W

TDA8920BJ in free air 35 K/W
Rth(j-c) thermal resistance from junction to case [1]
TDA8920BTH 1.3 K/W

TDA8920BJ 1.3 K/W
[1] See also Section 13.5.
11. Static characteristics

Table 7: Static characteristics
VP = ±27 V; fosc = 317 kHz; Tamb = 25 °C; unless otherwise specified.
Supply
VP supply voltage [1] ±12.5 ±27 ±30 V
Iq(tot) total quiescent supply current no load, no filter; no - 50 65 mA
RC-snubber network
connected
Istb standby supply current - 150 500 µA
Mode select input; pin MODE
VI input voltage [2] 0 - 6 V
II input current VI = 5.5 V - 100 300 µA
Vstb input voltage for Standby mode [2] [3] 0 - 0.8 V
Vmute input voltage for Mute mode [2] [3] 2.2 - 3.0 V
Von input voltage for Operating mode [2] [3] 4.2 - 6 V
Audio inputs; pins IN1M, IN1P, IN2P and IN2M
VI DC input voltage [2] - 0 - V
Amplifier outputs; pins OUT1 and OUT2
VOO(SE)(mute) mute SE output offset voltage - - 15 mV
VOO(SE)(on) operating SE output offset voltage [4] - - 150 mV
VOO(BTL)(mute) mute BTL output offset voltage - - 21 mV
VOO(BTL)(on) operating BTL output offset voltage [4] - - 210 mV
Stabilizer output; pin STABI
Vo(stab) stabilizer output voltage mute and operating; 11 12.5 15 V
with respect to VSSP1

Table 7: Static characteristics …continued

VP = ±27 V; fosc = 317 kHz; Tamb = 25 °C; unless otherwise specified.
Temperature protection
Tprot temperature protection activation - 150 - °C
Thys hysteresis of temperature protection - 20 - °C
[1] The circuit is DC adjusted at VP = ±12.5 V to ±30 V.

[2] With respect to SGND (0 V).
[3] The transition between Standby and Mute mode has hysteresis, while the slope of the transition between Mute and Operating mode is
determined by the time-constant of the RC-network on the MODE pin; see Figure 7.
[4] DC output offset voltage is applied to the output during the transition between Mute and Operating mode in a gradual way. The slope of
the dV/dt caused by any DC output offset is determined by the time-constant of the RC-network on the MODE pin.
slope is directly related to the time-constant

of the RC-network on the MODE pin
VO (V)
Voo(on)
STBY MUTE ON
Voo(mute)
0 0.8 2.2 3.0 4.2 5.5

VMODE (V)
coa021
Fig 7. Behavior of mode selection pin MODE
12. Dynamic characteristics
12.1 Switching characteristics

Table 8: Switching characteristics
VDD = ±27 V; Tamb = 25 °C; unless otherwise specified.
Internal oscillator
fosc typical internal oscillator frequency ROSC = 30.0 kΩ 290 317 344 kHz
fosc(int) internal oscillator frequency range 210 - 600 kHz
External oscillator or frequency tracking
VOSC high-level voltage on pin OSC SGND + 4.5 SGND + 5 SGND + 6 V
VOSC(trip) trip level for tracking on pin OSC - SGND + 2.5 - V
ftrack frequency range for tracking 210 - 600 kHz

12.2 Stereo and dual SE application

Table 9: Stereo and dual SE application characteristics
VP = ±27 V; RL = 4 Ω; fi = 1 kHz; fosc = 317 kHz; RsL < 0.1 Ω [1]; Tamb = 25 °C; unless otherwise specified.
Po output power RL = 3 Ω; VP = ±27 V [2]
THD = 0.5 % - 87 - W
THD = 10 % - 110 - W
RL = 4 Ω; VP = ±27 V [2]
THD = 0.5 % - 69 - W
THD = 10 % - 86 - W
RL = 6 Ω; VP = ±27 V [2]
THD = 0.5 % - 48 - W
THD = 10 % - 60 - W
RL = 8 Ω; VP = ±27 V [2]
THD = 0.5 % - 36 - W
THD = 10 % - 45 - W
THD total harmonic distortion Po = 1 W [3]
fi = 1 kHz - 0.02 0.05 %

fi = 6 kHz - 0.03 - %
Gv(cl) closed loop voltage gain 29 30 31 dB
SVRR supply voltage ripple rejection operating [4]
fi = 100 Hz - 55 - dB
fi = 1 kHz 40 50 - dB
mute; fi = 100 Hz [4] - 55 - dB
standby; fi = 100 Hz [4] - 80 - dB
Zi input impedance 45 68 - kΩ
Vn(o) noise output voltage operating
Rs = 0 Ω [5] - 210 - µV
mute [6] - 160 - µV
αcs channel separation [7] - 70 - dB
∆Gv channel unbalance - - 1 dB
Vo(mute) output signal in mute [8] - 100 - µV
CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) - 75 - dB
[1] RsL is the series resistance of inductor of low-pass LC filter in the application.
[2] Output power is measured indirectly; based on RDSon measurement. See also Section 13.3.
[3] Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, using AES17 20 kHz brickwall filter. Maximum limit is
guaranteed but may not be 100 % tested.
[4] Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω.
[5] B = 22 Hz to 20 kHz, using AES17 20 kHz brickwall filter.
[6] B = 22 Hz to 22 kHz, using AES17 20 kHz brickwall filter; independent of Rs.
[7] Po = 1 W; Rs = 0 Ω; fi = 1 kHz.
[8] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.

12.3 Mono BTL application

Table 10: Mono BTL application characteristics
VP = ±27 V; RL = 8 Ω; fi = 1 kHz; fosc = 317 kHz; RsL < 0.1 Ω [1]; Tamb = 25 °C; unless otherwise specified.
Po output power RL = 6 Ω; VP = ±27 V [2]
THD = 0.5 % - 174 - W

THD = 10 % - 210 - W
RL = 8 Ω; VP = ±27 V [2]
THD = 0.5 % - 138 - W

THD = 10 % - 173 - W
THD total harmonic distortion Po = 1 W [3]
fi = 1 kHz - 0.02 0.05 %

fi = 6 kHz - 0.03 - %
Gv(cl) closed loop voltage gain 35 36 37 dB
SVRR supply voltage ripple rejection operating [4]
fi = 100 Hz - 80 - dB
fi = 1 kHz 70 80 - dB
mute; fi = 100 Hz [4] - 80 - dB
standby; fi = 100 Hz [4] - 80 - dB
Zi input impedance 22 34 - kΩ
Vn(o) noise output voltage operating
Rs = 0 Ω [5] - 300 - µV
mute [6] - 220 - µV
Vo(mute) output signal in mute [7] - 200 - µV
CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) - 75 - dB
[1] RsL is the series resistance of inductor of low-pass LC filter in the application.
[2] Output power is measured indirectly; based on RDSon measurement. See also Section 13.3.
[3] Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, using an AES17 20 kHz brickwall filter. Maximum limit is
guaranteed but may not be 100 % tested.
[4] Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω.
[5] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall filter.
[6] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall filter; independent of Rs.
[7] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.
13. Application information
13.1 BTL application

When using the power amplifier in a mono BTL application the inputs of both channels
must be connected in parallel and the phase of one of the inputs must be inverted (see
Figure 6). In principle the loudspeaker can be connected between the outputs of the two
single-ended demodulation filters.

13.2 MODE pin

For pop noise-free start-up an RC time-constant must be applied on the MODE pin. The
bias-current setting of the VI-converter input is directly related to the voltage on the MODE
pin. In turn the bias-current setting of the VI converters is directly related to the DC output
offset voltage. Thus a slow dV/dt on the MODE pin results in a slow dV/dt for the DC
output offset voltage, resulting in pop noise-free start-up. A time-constant of 500 ms is
sufficient to guarantee pop noise-free start-up (see also Figure 4, 5 and 7).
13.3 Output power estimation

The achievable output powers in several applications (SE and BTL) can be estimated
using the following expressions:
SE:
RL 2
-------------------- × V P × ( 1 – t min × f osc )
R L + 0.4
P o ( 1% ) = ----------------------------------------------------------------------------------------- (1)
2 × RL
Maximum current (internally limited to 8 A):
V P × ( 1 – t min × f osc )
I o ( peak ) = ------------------------------------------------------ (2)
R L + 0.4
BTL:
RL 2
-------------------- × 2V P × ( 1 – t min × f osc )
R L + 0.8
P o ( 1% ) = --------------------------------------------------------------------------------------------- (3)
2 × RL
Maximum current (internally limited to 8 A):
2V P × ( 1 – t min × f osc )
I o ( peak ) = --------------------------------------------------------- (4)
R L + 0.8
Variables:
RL = load impedance
fosc = oscillator frequency
tmin = minimum pulse width (typically 150 ns)
VP = single-sided supply voltage (so, if supply is ±30 V symmetrical, then VP = 30 V)
Po(1%) = output power just at clipping
Po(10%) = output power at THD = 10 %
Po(10%) = 1.24 × Po(1%).
13.4 External clock

When using an external clock the following accuracy of the duty cycle of the external clock
has to be taken into account: 47.5 % < δ < 52.5 %.

If two or more class-D amplifiers are used in the same audio application, it is strongly
recommended that all devices run at the same switching frequency. This can be realized
by connecting all OSC pins together and feed them from an external central oscillator.
Using an external oscillator it is necessary to force pin OSC to a DC-level above SGND for
switching from the internal to an external oscillator. In this case the internal oscillator is
disabled and the PWM modulator will be switched on the external frequency. The
frequency range of the external oscillator must be in the range as specified in the
switching characteristics; see Section 12.1.
In an application circuit:
• Internal oscillator: ROSC connected between pin OSC and VSSA

• External oscillator: connect the oscillator signal between pins OSC and SGND; ROSC
and COSC removed
13.5 Heatsink requirements

In some applications it may be necessary to connect an external heatsink to the
TDA8920B. Limiting factor is the 150 °C maximum junction temperature Tj(max) which
cannot be exceeded. The expression below shows the relationship between the maximum
allowable power dissipation and the total thermal resistance from junction to ambient:
T j ( max ) – T amb
R th ( j – a ) = -----------------------------------
- (5)
P diss
Pdiss is determined by the efficiency (η) of the TDA8920B. The efficiency measured in the
TDA8920B as a function of output power is given in Figure 21. The power dissipation can
be derived as a function of output power (see Figure 20).
The derating curves (given for several values of Rth(j-a)) are illustrated in Figure 8.
A maximum junction temperature Tj = 150 °C is taken into account. From Figure 8 the
maximum allowable power dissipation for a given heatsink size can be derived or the
required heatsink size can be determined at a required dissipation level.

mbl469
30
Pdiss
(W) (1)
20
(2)
10
(3)
(4)
(5)
0
0 20 40 60 80 100
Tamb (°C)
(1) Rth(j-a) = 5 K/W.

(2) Rth(j-a) = 10 K/W.
(3) Rth(j-a) = 15 K/W.
(4) Rth(j-a) = 20 K/W.
(5) Rth(j-a) = 35 K/W.
Fig 8. Derating curves for power dissipation as a function of maximum ambient
temperature
13.6 Output current limiting

To guarantee the robustness of the class-D amplifier the maximum output current which
can be delivered by the output stage is limited. An advanced OverCurrent Protection
(OCP) is included for each output power switch.
When the current flowing through any of the power switches exceeds the defined internal
threshold of 8 A (e.g. in case of a short-circuit to the supply lines or a short-circuit across
the load) the maximum output current of the amplifier will be regulated to 8 A.
The TDA8920B amplifier can distinguish between a low-ohmic short circuit condition and
other overcurrent conditions like dynamic impedance drops of the loudspeakers used. The
impedance threshold (Zth) depends on the supply voltage used.
Depending on the impedance of the short circuit the amplifier will react as follows:
1. Short-circuit impedance > Zth:

the maximum output current of the amplifier is regulated to 8 A, but the amplifier will
not shut-down its PWM outputs. Effectively this results in a clipping output signal
across the load (behavior is very similar to voltage clipping).
2. Short-circuit impedance < Zth:
the amplifier will limit the maximum output current to 8 A and at the same time the
capacitor on the PROT pin is discharged. When the voltage across this capacitor
drops below an internal threshold voltage the amplifier will shut-down completely and
an internal timer will be started.

A typical value for the capacitor on the PROT pin is 220 pF. After a fixed time of
100 ms the amplifier is switched on again. If the requested output current is still too
high the amplifier will switch-off again. Thus the amplifier will try to switch to the
Operating mode every 100 ms. The average dissipation will be low in this situation
because of this low duty cycle. If the overcurrent condition is removed the amplifier will
remain in Operating mode once restarted.
In this way the TDA8920B amplifier is fully robust against short circuit conditions while at
the same time so-called audio holes as a result of loudspeaker impedance drops are
eliminated.
13.7 Pumping effects

In a typical stereo half-bridge SE application the TDA8920B class-D amplifier is supplied
by a symmetrical voltage (e.g VDD = +27 V and VSS = −27 V). When the amplifier is used
in a SE configuration, a so-called ‘pumping effect’ can occur. During one switching
interval, energy is taken from one supply (e.g. VDD), while a part of that energy is
delivered back to the other supply line (e.g. VSS) and visa versa. When the voltage supply
source cannot sink energy, the voltage across the output capacitors of that voltage supply
source will increase: the supply voltage is pumped to higher levels. The voltage increase
caused by the pumping effect depends on:
• Speaker impedance
• Supply voltage
• Audio signal frequency
• Value of decoupling capacitors on supply lines
• Source and sink currents of other channels
The pumping effect should not cause a malfunction of either the audio amplifier and/or the
voltage supply source. For instance, this malfunction can be caused by triggering of the
undervoltage or overvoltage protection or unbalance protection of the amplifier.
Best remedy for pumping effects is to use the TDA8920B in a mono full-bridge application
or in case of stereo half-bridge application adapt the power supply (e.g. increase supply
decoupling capacitors).

13.8 Application schematic

Notes for the application schematic:
• A solid ground plane around the switching amplifier is necessary to prevent emission
• 100 nF capacitors must be placed as close as possible to the power supply pins of the
TDA8920BTH
• The internal heat spreader of the TDA8920BTH is internally connected to VSS
• The external heatsink must be connected to the ground plane
• Use a thermal conductive electrically non-conductive Sil-Pad between the backside of
the TDA8920BTH and a small external heatsink
• The differential inputs enable the best system level audio performance with
unbalanced signal sources. In case of hum due to floating inputs, connect the
shielding or source ground to the amplifier ground. Jumpers J1 and J2 are open on
set level and are closed on the stand-alone demo board
• Minimum total required capacitance per power supply line is 3300 µF

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Product data sheet
TDA8920B_2
Philips Semiconductors
R2 VDDP
VDDA
10 Ω
L1 BEAD R1
VDDP 5.6 kΩ
R3
CON1 C1 C2 C3
+25 V VDD 100 nF 47 µF/35 V 470 µF/35 V 5.6 kΩ
1 DZ1 R4
GND 2 5V6 5.6 kΩ
3 C4
−25 V VSS C7 C5 C6 S1 S2
100 nF 47 µF/35 V 470 µF/35 V 100 µF/10 V
ON/OFF OPERATE/MUTE
VSSP
L2 BEAD
R5 VSSA VDDP VSSP
VSSA
10 Ω C8
VDDA VSSA C9 R6 47 µF/

100 nF 30 kΩ 63 V SINGLE ENDED
OUTPUT FILTER VALUES
C12 C13 C14 C15 C16 VDDP VSSP
FB GND FB GND LS1/LS2 L3/L4 C22/C31
Rev. 02 — 07 November 2005
100 nF 100 nF 100 nF 100 nF 100 nF 2Ω 10 µH 1 µF

C10 C11
4Ω 22 µH 680 nF
MODE
VDDA1
VDDP1
220 pF 220 pF
VSSA1
VSSP1
6Ω 33 µH
OSC
470 nF
C17 8Ω 47 µH 330 nF
1 nF R7
IN1 R8 C18
IN1P 10 12 7 6 14 17
8 10 Ω
OUT1 L3 OUT1P
5.6 kΩ 470 nF C19 16 LS1
220 pF
R10 C20 OUT1M
IN1M R9
9 BOOT1 C21 22 Ω
5.6 kΩ 470 nF SGND1 15
C23 11 15 nF
1 nF U1 C22 C24
FB GND 100
C25
TDA8920BTH FB nF
SGND2
1 nF 2 BOOT2 C27 GND
R11 C26
IN2P 22
5 15 nF

5.6 kΩ 470 nF C28 OUT2 L4 OUT2M
220 pF 21 LS2
IN2 R12 C29
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
IN2M OUT2P
4 R13 R14
C30 5.6 kΩ 470 nF 10 Ω 22 Ω
1 nF 3 1 13 19 24 18 23 20
C31 C32
VDDA2
VSSA2
PROT
n.c.
VSSD
STABI
VDDP2
VSSP2
100
TDA8920B
C40 C41 nF
220 pF 220 pF FB
C34 C35 C33 C37 C38 C39 GND
FB GND FB GND
220 pF
C36
100 nF 100 nF 100 nF 100 nF 100 nF
100 nF 001aab224
VDDA VSSA VSSA VSSP VDDP VSSP VDDP VSSP

21 of 34
Fig 9. TDA8920BTH application schematic

13.9 Curves measured in reference design
001aab225 001aab226
102 102
(THD + N)/S (THD + N)/S
(%) (%)
10 10
1 1
(1)
(1)
10−1 (2) 10−1

(2)
(3)
10−2 10−2 (3)
10−3 10−3
10−2 10−1 1 10 102 103 10−2 10−1 1 10 102
Po (W) Po (W)
VP = ±27 V; 2 × 3 Ω SE configuration. VP = ±27 V; 2 × 4 Ω SE configuration.

(1) f = 6 kHz. (1) f = 6 kHz.
(2) f = 1 kHz. (2) f = 1 kHz.
(3) f = 100 Hz. (3) f = 100 Hz.
Fig 10. (THD + N)/S as a function of output power; SE Fig 11. (THD + N)/S as a function of output power; SE
configuration with 2 × 3 Ω load configuration with 2 × 4 Ω load
001aab227 001aab228
102 102
(%) (%)
10 10
1 1
(1)
10−1 (1) 10−1
(2)
(2)
10−2 10−2
(3)
(3)
10−3 10−3
10−2 10−1 1 10 102 103 10−2 10−1 1 10 102 103
Po (W) Po (W)
VP = ±27 V; 1 × 6 Ω BTL configuration. VP = ±27 V; 1 × 8 Ω BTL configuration.

(1) f = 6 kHz. (1) f = 6 kHz.
(2) f = 1 kHz. (2) f = 1 kHz.
(3) f = 100 Hz. (3) f = 100 Hz.
Fig 12. (THD + N)/S as a function of output power; BTL Fig 13. (THD + N)/S as a function of output power; BTL

001aab229 001aab230
102 102
(%) (%)
10 10
1 1
10−1 10−1
(1)
(1)
10−2 (2) 10−2 (2)
10−3 10−3
10 102 103 104 105 10 102 103 104 105
f (Hz) f (Hz)

(1) Pout = 1 W. (1) Pout = 1 W.
(2) Pout = 10 W. (2) Pout = 10 W.
Fig 14. (THD + N)/S as a function of frequency; SE Fig 15. (THD + N)/S as a function of frequency; SE
001aab231 001aab232
102 102
(%) (%)
10 10
1 1
10−1 10−1
(1) (1)
10−2 10−2
(2) (2)
10−3 10−3
10 102 103 104 105 10 102 103 104 105
f (Hz) f (Hz)
VP = ±27 V; 1 × 6 Ω BTL configuration. VP = ±27 V; 1 × 8 Ω BTL configuration.

(1) Pout = 1 W. (1) Pout = 1 W.
(2) Pout = 10 W. (2) Pout = 10 W.
Fig 16. (THD + N)/S as a function of frequency; BTL Fig 17. (THD + N)/S as a function of frequency; BTL

001aab233 001aab234
0 0
αcs αcs
(dB) (dB)
−20 −20
−40 −40
−60 −60
(1)
(1)
−80 (2) −80 (2)
−100 −100
10 102 103 104 105 10 102 103 104 105
f (Hz) f (Hz)

(1) Pout = 10 W. (1) Pout = 10 W.
(2) Pout = 1 W. (2) Pout = 1 W.
Fig 18. Channel separation as a function of frequency; Fig 19. Channel separation as a function of frequency;
SE configuration with 2 × 3 Ω load SE configuration with 2 × 4 Ω load
001aab235 001aab236
32 100
(3)
(2) (1)
η
Pdiss
(%)
(W) (4) (3)
80
24
(1)
60
(4)
16
(2)
40
8
20
0 0
10−2 10−1 1 10 102 103 0 80 160 240
Po (W) Po (W)
VP = ±27 V; f = 1 kHz. VP = ±27 V; f = 1 kHz.

(1) 2 × 3 Ω SE configuration. (1) 2 × 3 Ω SE configuration.
(3) 1 × 6 Ω BTL configuration. (3) 1 × 6 Ω BTL configuration.
Fig 20. Power dissipation as a function of total output Fig 21. Efficiency as a function of total output power
power

001aab237 001aab238
200 240
Po
(1)
(W) (1) Po
160 (W)
(2)
(2)
160
120
(3)
(3)
80 (4)
(4)
80
40
0 0
10 15 20 25 30 35 10 15 20 25 30 35
VP (V) VP (V)
f = 1 kHz. f = 1 kHz.
Fig 22. Output power as a function of supply voltage; Fig 23. Output power as a function of supply voltage;
THD + N = 0.5 % THD + N = 10 %
001aab239 001aab240
45 45
G G
(dB) (dB)
40 40
(1)
35 (1) 35
(2)
(2)
(3)
30 30
(3)
(4)
(4)
25 25
20 20
10 102 103 104 105 10 102 103 104 105
f (Hz) f (Hz)
Vi = 100 mV; Rs = 5.6 kΩ; Ci = 330 pF; VP = ±27 V. Vi = 100 mV; Rs = 0 Ω; Ci = 330 pF; VP = ±27 V.
Fig 24. Gain as a function of frequency; Rs = 5.6 kΩ and Fig 25. Gain as a function of frequency; Rs = 0 Ω and
Ci = 330 pF Ci = 330 pF

001aab241 001aab242
0 10
Vo
SVRR
(V)
(dB) 1
−20
10−1
−40
10−2
(1)
10−3
−60
(2)
10−4
−80
10−5
−100 10−6
10 102 103 104 105 0 2 4 6
f (Hz) Vmode (V)
VP = ±27 V; Vripple = 2 V (p-p). Vi = 100 mV; f = 1 kHz.

(1) Both supply lines rippled.
(2) One supply line rippled.
Fig 26. SVRR as a function of frequency Fig 27. Output voltage as a function of mode voltage
001aab243
120
S/N
(dB)
(1)
80
(2)
40
0
10−2 10−1 1 10 102 103
Po (W)
VP = ±27 V; Rs = 5.6 kΩ; 20 kHz AES17 filter.

(1) 2 × 3 Ω SE configuration and 1 × 6 Ω BTL configuration.
(2) 2 × 4 Ω SE configuration and 1 × 8 Ω BTL configuration.
Fig 28. S/N ratio as a function of output power
14. Test information
14.1 Quality information

The General Quality Specification for Integrated Circuits, SNW-FQ-611 is applicable.

15. Package outline
HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3
E A
D
x X
y E2
HE v M A
D1
D2
1 12
pin 1 index
A2 A
E1 (A3)
A4
θ
Lp
detail X
24 13
Z w M
e bp
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A2 A3 A4(1) bp c D(2) D1 D2 E(2) E1 E2 e HE Lp Q v w x y Z θ
max.
3.5 +0.08 0.53 0.32 16.0 13.0 1.1 11.1 6.2 2.9 14.5 1.1 1.7 2.7 8°
mm 3.5 0.35 1 0.25 0.25 0.03 0.07
3.2 −0.04 0.40 0.23 15.8 12.6 0.9 10.9 5.8 2.5 13.9 0.8 1.5 2.2 0°
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
03-02-18
SOT566-3
03-07-23
Fig 29. Package outline SOT566-3 (HSOP24)


DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
non-concave
x Dh
Eh
view B: mounting base side
A2
d A5
β A4
B E2
j
E
E1
L2
L1 L3
L Q c v M
1 23
e1 m e2
Z w M
bp
e
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A 2 A4 A5 bp c D (1) d D h E (1) e e1 e2 Eh E1 E2 j L L1 L2 L3 m Q v w x β Z (1)
4.6 1.15 1.65 0.75 0.55 30.4 28.0 12.2 6 10.15 6.2 1.85 3.6 14 10.7 2.4 2.1 1.43
mm 12 2.54 1.27 5.08 4.3 0.6 0.25 0.03 45°
4.3 0.85 1.35 0.60 0.35 29.9 27.5 11.8 9.85 5.8 1.65 2.8 13 9.9 1.6 1.8 0.78
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
98-02-20
SOT411-1
02-04-24
Fig 30. Package outline SOT411-1 (DBS23P)


16. Soldering
16.1 Introduction
This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering is often
preferred when through-hole and surface mount components are mixed on one
printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it
is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing.
16.2 Through-hole mount packages
16.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
16.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
16.3 Surface mount packages
16.3.1 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste
material. The top-surface temperature of the packages should preferably be kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
16.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically

developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
16.3.3 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.

16.4 Package related soldering information

Table 11: Suitability of IC packages for wave, reflow and dipping soldering methods
Mounting Package [1] Soldering method
Wave Reflow [2] Dipping
Through-hole mount CPGA, HCPGA suitable − −
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable [3] − suitable
Through-hole-surface PMFP [4] not suitable not suitable −
mount
Surface mount BGA, HTSSON..T [5], LBGA, not suitable suitable −
LFBGA, SQFP, SSOP..T [5],
TFBGA, VFBGA, XSON
DHVQFN, HBCC, HBGA, HLQFP, not suitable [6] suitable −
HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN,
HVSON, SMS
PLCC [7], SO, SOJ suitable suitable −
LQFP, QFP, TQFP not recommended [7] [8] suitable −
SSOP, TSSOP, VSO, VSSOP not recommended [9] suitable −
CWQCCN..L [10], WQCCN..L [10] not suitable not suitable −
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips
Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with
respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of
the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
[4] Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed
through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C
measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate
between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the
heatsink surface.
[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint
must incorporate solder thieves downstream and at the side corners.
[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for
packages with a pitch (e) equal to or smaller than 0.65 mm.
[9] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely
not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil.
However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate
soldering profile can be provided on request.

17. Revision history

Table 12: Revision history
Document ID Release date Data sheet status Change notice Doc. number Supersedes
TDA8920B_2 20051107 Product data sheet - - TDA8920B_1
Modifications: • In Section 9 “Limiting values” the maximum value for the supply voltage is given for both
operating and non operating conditions (see Table 5)
TDA8920B_1 20041001 Preliminary data sheet - 9397 750 13356 -

18. Data sheet status
Level Data sheet status [1] Product status [2] [3] Definition
I Objective data Development This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
19. Definitions customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is Right to make changes — Philips Semiconductors reserves the right to
extracted from a full data sheet with the same type number and title. For make changes in the products - including circuits, standard cells, and/or
detailed information see the relevant data sheet or data handbook. software - described or contained herein in order to improve design and/or
Limiting values definition — Limiting values given are in accordance with performance. When the product is in full production (status ‘Production’),
the Absolute Maximum Rating System (IEC 60134). Stress above one or relevant changes will be communicated via a Customer Product/Process
more of the limiting values may cause permanent damage to the device. Change Notification (CPCN). Philips Semiconductors assumes no
These are stress ratings only and operation of the device at these or at any responsibility or liability for the use of any of these products, conveys no
other conditions above those given in the Characteristics sections of the license or title under any patent, copyright, or mask work right to these
specification is not implied. Exposure to limiting values for extended periods products, and makes no representations or warranties that these products are
may affect device reliability. free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
21. Trademarks
Notice — All referenced brands, product names, service names and
20. Disclaimers trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
22. Contact information

For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: [email protected]

23. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 16.3.2 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 30
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 16.3.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 30
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 16.4 Package related soldering information . . . . . . 31
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32
5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 18 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 33
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 22 Contact information . . . . . . . . . . . . . . . . . . . . 33
8 Functional description . . . . . . . . . . . . . . . . . . . 5
8.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8.2 Pulse width modulation frequency . . . . . . . . . . 8
8.3 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
8.3.1 OverTemperature Protection (OTP) . . . . . . . . . 8
8.3.2 OverCurrent Protection (OCP) . . . . . . . . . . . . . 8
8.3.3 Window Protection (WP). . . . . . . . . . . . . . . . . . 9
8.3.4 Supply voltage protections . . . . . . . . . . . . . . . 10
8.4 Differential audio inputs . . . . . . . . . . . . . . . . . 11
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
10 Thermal characteristics. . . . . . . . . . . . . . . . . . 12
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 12
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 13
12.1 Switching characteristics . . . . . . . . . . . . . . . . 13
12.2 Stereo and dual SE application . . . . . . . . . . . 14
12.3 Mono BTL application . . . . . . . . . . . . . . . . . . . 15
13 Application information. . . . . . . . . . . . . . . . . . 15
13.1 BTL application . . . . . . . . . . . . . . . . . . . . . . . . 15
13.2 MODE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
13.3 Output power estimation. . . . . . . . . . . . . . . . . 16
13.4 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16
13.5 Heatsink requirements . . . . . . . . . . . . . . . . . . 17
13.6 Output current limiting. . . . . . . . . . . . . . . . . . . 18
13.7 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 19
13.8 Application schematic . . . . . . . . . . . . . . . . . . . 20
13.9 Curves measured in reference design . . . . . . 22
14 Test information . . . . . . . . . . . . . . . . . . . . . . . . 26
14.1 Quality information . . . . . . . . . . . . . . . . . . . . . 26
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 27
16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 29
16.2 Through-hole mount packages . . . . . . . . . . . . 29
16.2.1 Soldering by dipping or by solder wave . . . . . 29
16.2.2 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 29
16.3 Surface mount packages . . . . . . . . . . . . . . . . 29
16.3.1 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 29
© Koninklijke Philips Electronics N.V. 2005

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 07 November 2005
Document number: TDA8920B_2
Published in The Netherlands

TDA8920B: 1. General Description

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TDA8920B: 1. General Description

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TDA8920B

2 × 100 W class-D power amplifier

4. Quick reference data

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 2 of 34

VDDA2 VDDA1 STABI PROT VDDP2 VDDP1

3 (20) 10 (4) 18 (12) 13 (7) 23 (16) 14 (8)

1 (18) 12 (6) 24 (17) 19 (-) 17 (11) 20 (13) coa023

Pin numbers in parenthesis refer to the TDA8920BJ.

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 3 of 34

Fig 2. Pin configuration TDA8920BTH Fig 3. Pin configuration TDA8920BJ

7.2 Pin description

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 4 of 34

Table 3: Pin description …continued

• Mono Bridge-Tied Load (BTL) amplifier

Product data sheet Rev. 02 — 07 November 2005 5 of 34

• Standby mode; with a very low supply current

Fig 4. Example of mode selection circuit

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 6 of 34

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 7 of 34

8.2 Pulse width modulation frequency

• OverTemperature Protection (OTP)

8.3.1 OverTemperature Protection (OTP)

8.3.2 OverCurrent Protection (OCP)

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 8 of 34

8.3.3 Window Protection (WP)

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 9 of 34

8.3.4 Supply voltage protections

Table 4: Overview of TDA8920B protections

[1] Hysteresis of 20 °C will influence restart timing depending on heatsink size.

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 10 of 34

8.4 Differential audio inputs

The input configuration for a mono BTL application is illustrated in Figure 6.

In the stereo single-ended configuration it is also recommended to connect the two

Fig 6. Input configuration for mono BTL application

[1] Overvoltage protection might be activated.

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 11 of 34

10. Thermal characteristics

TDA8920BTH in free air 35 K/W

TDA8920BTH 1.3 K/W

[1] See also Section 13.5.

11. Static characteristics

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 12 of 34

Table 7: Static characteristics …continued

[1] The circuit is DC adjusted at VP = ±12.5 V to ±30 V.

slope is directly related to the time-constant

0 0.8 2.2 3.0 4.2 5.5

Fig 7. Behavior of mode selection pin MODE

12. Dynamic characteristics

12.1 Switching characteristics

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 13 of 34

12.2 Stereo and dual SE application

fi = 1 kHz - 0.02 0.05 %

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 14 of 34

12.3 Mono BTL application

THD = 0.5 % - 174 - W

THD = 0.5 % - 138 - W

fi = 1 kHz - 0.02 0.05 %

13. Application information

13.1 BTL application

TDA8920B_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet Rev. 02 — 07 November 2005 15 of 34

13.2 MODE pin

13.3 Output power estimation

Maximum current (internally limited to 8 A):