Scribd
Upload
144 views14 pages

Constraints - Analysis - Fixes

Uploaded by

Rony Mathews
The document discusses timing analysis constraints and fundamentals. It covers setup time, hold time, clock latency, skew, and how timing is analyzed from input to output through logic and registers in a chip. It also discusses exceptions like false paths and multi-cycle paths. The stages of timing analysis from synthesis to signoff are outlined. Finally fixes for setup and hold violations like upsizing, downsizing and delay cell addition are mentioned.

Copyright:

Attribution Non-Commercial (BY-NC)

Available Formats

Download as PPT, PDF, TXT or read online on Scribd
Download as ppt, pdf, or txt
144 views14 pages

Constraints - Analysis - Fixes

Uploaded by

Rony Mathews
The document discusses timing analysis constraints and fundamentals. It covers setup time, hold time, clock latency, skew, and how timing is analyzed from input to output through logic and registers in a chip. It also discusses exceptions like false paths and multi-cycle paths. The stages of timing analysis from synthesis to signoff are outlined. Finally fixes for setup and hold violations like upsizing, downsizing and delay cell addition are mentioned.

Copyright:

Attribution Non-Commercial (BY-NC)

Available Formats

Download as PPT, PDF, TXT or read online on Scribd
Download as ppt, pdf, or txt
Download as ppt, pdf, or txt
You are on page 1/ 14

STA

•Constraints
•Analysis
•Fixes
Constraints
• Optimization constraints
– Area
– Power
– Drive strength
– Load
• Timing Constraints
– Frequency
– Fixed margins
Fundamentals
• Setup Time – setup the data before the
active clock edge

CLK

DATA

tsetup
Contd..
• Hold Time – hold the data after the active
clock edge

CLK

DATA

thold
Digital: Timing break-up in the chip
• Input to FF
• FF to FF
• FF to output
• Input to output
Contd..
• Important terms:
– Setup time
– Hold time
– Clock latency
– Skew
• Proper data capture at subsequent edges
– Setup check at next edge
– Hold check at the same edge
Contd..
• FF to FF timing components
Combo

D Q D Q
CK-> Q
setup

FF1 FF2

CK-> Q Combo setup

Period
Contd..
• Input to FF timing
– Input delay

Chip IO boundary

External Delay (part of


combinational delay)
Contd..
• FF to output timing

Chip IO boundary
External Delay (part of
combinational delay)
Contd..
• Input to output timing

Combinational logic:
timing path not broken
Exceptions
• False paths

Clock domain1 Clock domain2

– Clock domains 1 and 2 are asynchronous: STA tool


cannot determine the relationship
– Types
• Functional
• Timing
Contd..
• Multi-Cycle paths
Skipped
edge

Capture
Launch

MCP = 2
Analysis
• Stages
– Synthesis  Margins are abstract
– Pre-layout  Abstract
– CTS  Clock latency included
– P&R  Parasitics included
– Signoff  Noise included
Fixes
• Setup
– Upsizing
– Logic simplification
– Pipelining
– Register retiming
– Useful skew
• Hold
– Downsizing
– Delay cell addition

You might also like