Intel Core i7 Processor Family for the LGA-2011 Socket

Preliminary Datasheet, Volume 1

Supporting Desktop Intel Core i7-3960X Extreme Edition Processor for the LGA-2011 Socket Supporting Desktop Intel Core i7-39xxK and i7-38xx Processor Series for the LGA-2011 Socket This is volume 1 of 2.

November 2011

Reference Number:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information including details on which processors support HT Technology, see http://www.intel.com/products/ht/hyperthreading_more.htm. Enhanced Intel SpeedStep Technology - See the Processor Spec Finder or contact your Intel representative for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Intel Virtualization Technology requires a computer system with an enabled Intel processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/technology/turboboost/. Intel Active Management Technology requires the platform to have an Intel AMT-enabled chipset, network hardware and software, connection with a power source and a network connection. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel, Enhanced Intel SpeedStep Technology, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright 2011, Intel Corporation. All rights reserved.

Datasheet, Volume 1

Table of Contents
1 Introduction .............................................................................................................. 9 1.1 Processor Feature Details ................................................................................... 10 1.1.1 Supported Technologies .......................................................................... 10 1.2 Interfaces ........................................................................................................ 11 1.2.1 System Memory Support ......................................................................... 11 1.2.2 PCI Express* ......................................................................................... 11 1.2.3 Direct Media Interface Gen 2 (DMI2)......................................................... 13 1.2.4 Platform Environment Control Interface (PECI) ........................................... 13 1.3 Power Management Support ............................................................................... 13 1.3.1 Processor Package and Core States........................................................... 13 1.3.2 System States Support ........................................................................... 13 1.3.3 Memory Controller.................................................................................. 13 1.3.4 PCI Express* ......................................................................................... 13 1.4 Thermal Management Support ............................................................................ 14 1.5 Package Summary............................................................................................. 14 1.6 Terminology ..................................................................................................... 14 1.7 Related Documents ........................................................................................... 17 Interfaces................................................................................................................ 19 2.1 System Memory Interface .................................................................................. 19 2.1.1 System Memory Technology Support ........................................................ 19 2.1.2 System Memory Timing Support............................................................... 19 2.2 PCI Express* Interface....................................................................................... 19 2.2.1 PCI Express* Architecture ....................................................................... 19 2.2.1.1 Transaction Layer ..................................................................... 20 2.2.1.2 Data Link Layer ........................................................................ 20 2.2.1.3 Physical Layer .......................................................................... 21 2.2.2 PCI Express* Configuration Mechanism ..................................................... 21 2.3 DMI2/PCI Express* Interface .............................................................................. 21 2.3.1 DMI2 Error Flow ..................................................................................... 21 2.3.2 DMI2 Link Down..................................................................................... 22 2.4 Platform Environment Control Interface (PECI) ...................................................... 22 Technologies ........................................................................................................... 23 3.1 Intel Virtualization Technology (Intel VT) ......................................................... 23 3.1.1 Intel VT-x Objectives ............................................................................ 23 3.1.2 Intel VT-x Features .............................................................................. 24 3.1.3 Intel VT-d Objectives ............................................................................ 24 3.1.3.1 Intel VT-d Features Supported.................................................. 25 3.1.3.2 Intel VT-d Processor Feature Additions ...................................... 25 3.1.4 Intel Virtualization Technology Processor Extensions ................................. 25 3.2 Security Technologies ........................................................................................ 26 3.2.1 AES Instructions .................................................................................... 26 3.2.2 Execute Disable Bit................................................................................. 26 3.3 Intel Hyper-Threading Technology ..................................................................... 26 3.4 Intel Turbo Boost Technology ........................................................................... 27 3.4.1 Intel Turbo Boost Operating Frequency ................................................... 27 3.5 Enhanced Intel SpeedStep Technology............................................................. 27 3.6 Intel Advanced Vector Extensions (Intel AVX) ................................................... 28 Power Management ................................................................................................. 29 4.1 ACPI States Supported....................................................................................... 29 4.1.1 System States ....................................................................................... 29 4.1.2 Processor Package and Core States........................................................... 29

Datasheet, Volume 1

4.2

4.3

4.4 5 6

4.1.3 Integrated Memory Controller States .........................................................31 4.1.4 DMI2/PCI Express* Link States.................................................................31 4.1.5 G, S, and C State Combinations................................................................32 Processor Core/Package Power Management .........................................................32 4.2.1 Enhanced Intel SpeedStep Technology ..................................................32 4.2.2 Low-Power Idle States.............................................................................33 4.2.3 Requesting Low-Power Idle States ............................................................34 4.2.4 Core C-states .........................................................................................34 4.2.4.1 Core C0 State ...........................................................................35 4.2.4.2 Core C1/C1E State ....................................................................35 4.2.4.3 Core C3 State ...........................................................................35 4.2.4.4 Core C6 State ...........................................................................35 4.2.4.5 Core C7 State ..........................................................................35 4.2.4.6 C-State Auto-Demotion .............................................................35 4.2.5 Package C-States ...................................................................................36 4.2.5.1 Package C0 ..............................................................................37 4.2.5.2 Package C1/C1E........................................................................37 4.2.5.3 Package C2 State ......................................................................38 4.2.5.4 Package C3 State ......................................................................38 4.2.5.5 Package C6 State ......................................................................38 4.2.6 Package C-State Power Specifications........................................................39 System Memory Power Management ....................................................................39 4.3.1 CKE Power-Down ....................................................................................39 4.3.2 Self Refresh ...........................................................................................40 4.3.2.1 Self Refresh Entry .....................................................................40 4.3.2.2 Self Refresh Exit .......................................................................40 4.3.2.3 DLL and PLL Shutdown...............................................................40 4.3.3 DRAM I/O Power Management ..................................................................40 DMI2/PCI Express* Power Management ................................................................40

Thermal Management Specifications ........................................................................41 Signal Descriptions ..................................................................................................43 6.1 System Memory Interface ...................................................................................43 6.2 PCI Express* Based Interface Signals ...................................................................44 6.3 DMI2/PCI Express* Port 0 Signals ........................................................................46 6.4 PECI Signal .......................................................................................................46 6.5 System Reference Clock Signals ..........................................................................46 6.6 JTAG and TAP Signals.........................................................................................46 6.7 Serial VID Interface (SVID) Signals ......................................................................47 6.8 Processor Asynchronous Sideband and Miscellaneous Signals...................................48 6.9 Processor Power and Ground Supplies ..................................................................50 Electrical Specifications ...........................................................................................51 7.1 Processor Signaling ............................................................................................51 7.1.1 System Memory Interface Signal Groups....................................................51 7.1.2 PCI Express* 3.0 Signals .........................................................................51 7.1.3 DMI2/PCI Express* Signals ......................................................................51 7.1.4 Platform Environmental Control Interface (PECI) .........................................51 7.1.4.1 Input Device Hysteresis .............................................................52 7.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) .........................52 7.1.5.1 PLL Power Supply ......................................................................52 7.1.6 JTAG and Test Access Port (TAP) Signals....................................................53 7.1.7 Processor Sideband Signals ......................................................................53 7.1.8 Power, Ground and Sense Signals .............................................................53 7.1.8.1 Power and Ground Lands............................................................53 7.1.8.2 Decoupling Guidelines ................................................................54 7.1.8.3 Voltage Identification (VID) ........................................................54 7.1.9 Reserved or Unused Signals .....................................................................58

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7.2 7.3 7.4 7.5

Signal Group Summary ...................................................................................... 58 Power-On Configuration (POC) Options................................................................. 61 Absolute Maximum and Minimum Ratings ............................................................. 62 7.4.1 Storage Conditions Specifications ............................................................. 62 DC Specifications .............................................................................................. 63 7.5.1 Voltage and Current Specifications............................................................ 63 7.5.2 Die Voltage Validation ............................................................................. 65 7.5.2.1 VCC Overshoot Specifications ...................................................... 65 7.5.3 Signal DC Specifications .......................................................................... 66 7.5.3.1 PCI Express* DC Specifications ................................................... 71 7.5.3.2 DMI2/PCI Express* DC Specifications .......................................... 71 7.5.3.3 Reset and Miscellaneous Signal DC Specifications .......................... 71

8 9

Processor Land Listing............................................................................................. 73 Package Mechanical Specifications ........................................................................ 121

Figures
1-1 1-2 2-1 2-2 4-1 4-2 4-3 7-1 7-2 7-3 Processor Platform Block Diagram Example........................................................... 10 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) .................. 12 PCI Express* Layering Diagram........................................................................... 20 Packet Flow through the Layers........................................................................... 20 Idle Power Management Breakdown of the Processor Cores..................................... 33 Thread and Core C-State Entry and Exit .............................................................. 33 Package C-State Entry and Exit ........................................................................... 37 Input Device Hysteresis ..................................................................................... 52 VR Power-State Transitions................................................................................. 56 VCC Overshoot Example Waveform...................................................................... 65

Tables
1-1 1-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 Terminology ..................................................................................................... 14 Reference Documents ........................................................................................ 17 System States .................................................................................................. 29 Package C-State Support.................................................................................... 30 Core C-State Support......................................................................................... 30 System Memory Power States ............................................................................. 31 DMI2/PCI Express* Link States ........................................................................... 31 G, S, and C State Combinations .......................................................................... 32 P_LVLx to MWAIT Conversion ............................................................................. 34 Coordination of Core Power States at the Package Level ......................................... 37 Package C-State Power Specifications .................................................................. 39 Memory Channel DDR0, DDR1, DDR2, DDR3......................................................... 43 Memory Channel Miscellaneous ........................................................................... 44 PCI Express* Port 1 Signals ................................................................................ 44 PCI Express* Port 2 Signals ................................................................................ 45 PCI Express* Port 3 Signals ................................................................................ 45 PCI Express* Miscellaneous Signals ..................................................................... 46 DMI2 to Port 0 Signals ....................................................................................... 46 PECI Signals ..................................................................................................... 46 System Reference Clock (BCLK{0/1}) Signals ....................................................... 46

Datasheet, Volume 1

6-10 6-11 6-12 6-13 6-14 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 8-1 8-2

JTAG and TAP Signals.........................................................................................46 SVID Signals .....................................................................................................47 Processor Asynchronous Sideband Signals.............................................................48 Miscellaneous Signals .........................................................................................49 Power and Ground Signals ..................................................................................50 Power and Ground Lands ....................................................................................53 SVID Address Usage ..........................................................................................56 Voltage Identification Definition ...........................................................................57 Signal Description Buffer Types ...........................................................................58 Signal Groups ...................................................................................................59 Signals with On-Die Termination ..........................................................................61 Power-On Configuration Option Lands...................................................................61 Processor Absolute Minimum and Maximum Ratings ...............................................62 Voltage Specification ..........................................................................................63 Current (Icc_Max and Icc_TDC) Specification.........................................................64 VCC Overshoot Specifications ..............................................................................65 DDR3 Signal DC Specifications.............................................................................66 PECI DC Specifications .......................................................................................67 System Reference Clock (BCLK{0/1}) DC Specifications..........................................68 SMBus DC Specifications.....................................................................................68 JTAG and TAP Signals DC Specifications ................................................................69 Serial VID Interface (SVID) DC Specifications ........................................................69 Processor Asynchronous Sideband DC Specifications...............................................70 Miscellaneous Signals DC Specifications ................................................................71 Land Name .......................................................................................................74 Land Number ....................................................................................................97

Datasheet, Volume 1

Revision History

Revision Number 001 Initial Release

Description

Revision Date November 2011

Datasheet, Volume 1

Datasheet, Volume 1

Introduction

Introduction
The Intel Core i7 processor family for the LGA-2011 socket is the next generation of 64-bit, multi-core desktop processor built on 32-nanometer process technology. Based on the low-power/high performance Intel Core i7 processor microarchitecture, the processor is designed for a two-chip platform as opposed to the traditional three-chip platforms (processor, MCH, and ICH). The two-chip platform consists of a processor and the Platform Controller Hub (PCH) and enables higher performance, easier validation, and improved x-y footprint. Refer to Figure 1-1 for a block diagram of the processor platform. The processor features up to 40 lanes of PCI Express* 3.0 links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* 2.0 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and 48 bits of virtual address space. Included in this family of processors is an integrated memory controller (IMC) and integrated I/O (IIO) (such as PCI Express* and DMI2) on a single silicon die. This single die solution is known as a monolithic processor. This document is Volume 1 of the datasheet for the Intel Core i7 processor family for the LGA-2011 socket. The complete datasheet consists of two volumes. This document provides DC electrical specifications, land and signal definitions, interface functional descriptions, power management descriptions, and additional feature information pertinent to the implementation and operation of the processor on its platform. Volume 2 provides register information. Refer to Section 1.7, Related Documents for access to Volume 2.

Note: Note: Note: Note:

Throughout this document, the Intel Core i7 processor family for the LGA-2011 socket may be referred to as processor. Throughout this document, the Desktop Intel Core i7-39xxK processor series for the LGA-2011 socket refers to the i7-3930K. Throughout this document, the Desktop Intel Core i7-38xx processor series for the LGA-2011 socket refers to the i7-3820. Throughout this document, the Intel X79 Chipset Platform Controller Hub may be referred to as PCH.

Datasheet, Volume 1

Introduction

Figure 1-1.

Processor Platform Block Diagram Example

DDR3

DDR3

DDR3

ethernet

SATA
x1 x4

Processor PCH
DMI2 SCU Uplink

PCIe PCIe

B I O S

Note: if SCU Uplink is used, the x8 PCIe device shown is limited to x4.

PCIe

x16

PCIe

x8

1.1

Processor Feature Details

Up to 6 Execution Cores Each core supports two threads (Intel Hyper-Threading Technology) for up to 12 threads A 32-KB instruction and 32-KB data first-level cache (L1) for each core A 256-KB shared instruction/data mid-level (L2) cache for each core Up to 15 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores

1.1.1

Supported Technologies
Intel Virtualization Technology (Intel VT) Intel Virtualization Technology for Directed I/O (Intel VT-d) Intel Virtualization Technology Intel Core i7 processor family for the LGA-2011 socket Extensions Intel 64 Architecture Intel Streaming SIMD Extensions 4.1 (Intel SSE4.1) Intel Streaming SIMD Extensions 4.2 (Intel SSE4.2) Intel Advanced Vector Extensions (Intel AVX) Intel Hyper-Threading Technology Execute Disable Bit Intel Turbo Boost Technology Enhanced Intel SpeedStep Technology

10

PCIe x16

DDR3

. . .

Datasheet, Volume 1

Introduction

1.2
1.2.1

Interfaces
System Memory Support
The processor supports 4 DDR3 channels with 1 unbuffered DIMM per channel Unbuffered DDR3 DIMMs supported Data burst length of eight cycles for all memory organization modes Memory DDR3 data transfer rates of 1066, 1333, and 1600 MT/s DDR3 UDIMM standard I/O Voltage of 1.5 V 1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices: UDIMMs x8, x16 Up to 2 ranks supported per memory channel, 1 or 2 ranks per DIMM Open with adaptive idle page close timer or closed page policy Command launch modes of 1n/2n Improved Thermal Throttling with dynamic CLTT Memory thermal monitoring support for DIMM temperature using two memory signals, MEM_HOT

1.2.2

PCI Express*
The PCI Express* port(s) are fully-compliant to the PCI Express* Base Specification, Revision 3.0 (PCIe 3.0) Support for PCI Express* 3.0 (8.0 GT/s), PCI Express 2.0 (5.0 GT/s), and PCI Express* (2.5 GT/s) Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express devices at PCI Express 3.0 speeds that are configurable for up to 10 independent ports. Negotiating down to narrower widths is supported, see Figure 1-2 x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1 x8 port (Port 1) may negotiate down to x4, x2, or x1 x4 port (Port 0) may negotiate down to x2, or x1 When negotiating down to narrower widths, there are caveats as to how lane reversal is supported Address Translation Services (ATS) 1.0 support Hierarchical PCI-compliant configuration mechanism for downstream devices Traditional PCI style traffic (asynchronous snooped, PCI ordering) PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space. PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory mapped fashion.

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Introduction

Supports receiving and decoding 64 bits of address from PCI Express* Memory transactions received from PCI Express* that go above the top of physical address space (when Intel VT-d is enabled, the check would be against the translated HPA (Host Physical Address) address) are reported as errors by the processor. Outbound access to PCI Express* will always have address bits 63 to 46 cleared Re-issues Configuration cycles that have been previously completed with the Configuration Retry status Power Management Event (PME) functions Message Signaled Interrupt (MSI and MSI-X) messages Degraded Mode support and Lane Reversal support Static lane numbering reversal and polarity inversion support Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)

Port 0 DMI

Port 1 (IOU2) PCIe

Port 2 (IOU0) PCIe

Port 3 (IOU1) PCIe

Transaction

Transaction

Transaction

Transaction

Link Physical
03

Link Physical
03 47 03

Link Physical
47 811 12..15 03

Link Physical
47 811 12..15

X4 DMI

X4

X4

X4
Port 2a

X4
Port 2b

X4
Port 2c

X4
Port 2d

X4

X4

X4

X4
Port 3d

Port 1a Port 1b

Port 3a Port 3b Port 3c

X8
Port 1a

X8
Port 2a

X8
Port 2c

X8
Port 3a

X8
Port 3c

X16
Port 2a

X16
Port 3a

12

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Introduction

1.2.3

Direct Media Interface Gen 2 (DMI2)

Serves as the chip-to-chip interface to the PCH The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2 Operates at PCIe2 or PCIe1 speeds Transparent to software Processor and peer-to-peer writes and reads with 64-bit address support APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined End of Interrupt broadcast message when initiated by the processor. System Management Interrupt (SMI), SCI, and SERR error indication Static lane numbering reversal support Supports DMI2 virtual channels VC0, VC1, VCm, and VCp

1.2.4

Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master (the PCH). Refer to the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, Related Documents) for additional details on PECI services available in the processor. Supports operation at up to 2 Mbps data transfers Link layer improvements to support additional services and higher efficiency over PECI 2.0 generation Services include processor thermal and estimated power information, control functions for power limiting, P-state and T-state control, and access for Machine Check Architecture registers and PCI configuration space (both within the processor package and downstream devices) Single domain (Domain 0) is supported

1.3
1.3.1

Power Management Support

Processor Package and Core States
ACPI C-states as implemented by the following processor C-states Package: PC0, PC1/PC1E, PC2, PC3, PC6 (Package C7 is not supported) Core: CC0, CC1, CC1E, CC3, CC6, CC7 Enhanced Intel SpeedStep Technology

1.3.2

System States Support

S0, S1, S3, S4, S5

1.3.3

Memory Controller
Multiple CKE power down modes Multiple self-refresh modes Memory thermal monitoring using MEM_HOT_C01_N and MEM_HOT_C23_N Signals

1.3.4

PCI Express*
L0s and L1 ASPM power management capability

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Introduction

1.4

Thermal Management Support

Adaptive Thermal Monitor THERMTRIP_N and PROCHOT_N signal support On-Demand mode clock modulation Open Loop Thermal Throttling and Hybrid OLTT/CLTT support for system memory Fan speed control with DTS Two integrated SMBus masters for accessing thermal data from DIMMs New Memory Thermal Throttling features using MEM_HOT signals

1.5

Package Summary
The processor socket type is noted as LGA2011. The processor package is a 52.5 x 45 mm FC-LGA package (LGA2011). Refer to the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, Related Documents) for the package mechanical specifications.

1.6
Table 1-1.

Terminology
Terminology (Sheet 1 of 3)
Term ASPM Cbo DDR3 DMA DMI DMI2 DTS ECC Enhanced Intel SpeedStep Technology Active State Power Management Cache and Core Box. It is a term used for internal logic providing ring interface to LLC and Core. Third generation Double Data Rate SDRAM memory technology that is the successor to DDR2 SDRAM Direct Memory Access Direct Media Interface Direct Media Interface Gen 2 Digital Thermal Sensor Error Correction Code Allows the operating system to reduce power consumption when performance is not needed. The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in nonexecutable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel 64 and IA-32 Architectures Software Developer's Manuals for more detailed information. Refers to the normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical, and thermal, are satisfied. A Memory Controller that is integrated in the processor die. An I/O controller that is integrated in the processor die. 64-bit memory extensions to the IA-32 architecture. Further details on Intel 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/. Intel Turbo Boost Technology is a way to automatically run the processor core faster than the marked frequency if the part is operating under power, temperature, and current specifications limits of the Thermal Design Power (TDP). This results in increased performance of both single and multi-threaded applications. Description

Execute Disable Bit

Functional Operation Integrated Memory Controller (IMC) Integrated I/O Controller (IIO) Intel 64 Technology

Intel Turbo Boost Technology

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Introduction

Table 1-1.

Terminology (Sheet 2 of 3)
Term Description Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware assist, under system software (Virtual Machine Manager or OS) control, for enabling I/O device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d. A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. Any timing variation of a transition edge or edges from the defined Unit Interval (UI). I/O Virtualization The 2011-land FC-LGA package mates with the system board through this surface mount, 2011-contact socket. Last Level Cache Management Engine Non-Critical to Function: NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. Intels 32-nm processor design, follow-on to the 32-nm 2nd Generation Intel Core processor family desktop design. Platform Controller Hub. The next generation chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features. Power Control Unit. The third generation PCI Express* specification that operates at twice the speed of PCI Express* 2.0 (8 Gb/s); however, PCI Express* 3.0 is completely backward compatible with PCI Express* 1.0 and 2.0. PCI Express* Platform Environment Control Interface The 64-bit, single-core or multi-core component (package) The term processor core refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache. All DC and AC timing and signal integrity specifications are measured at the processor die (pads), unless otherwise noted. Uncore Power Manager A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DDR3 DIMM. System Control Interrupt. Used in ACPI protocol. Intel Streaming SIMD Extensions (Intel SSE) A processor Stock Keeping Unit (SKU) to be installed in the platform. Electrical, power and thermal specifications for these SKUs are based on specific use condition assumptions. System Management Bus. A two-wire interface through which simple system and power management related devices can communicate with the rest of the system. It is based on the principals of the operation of the I2C* two-wire serial bus from Philips Semiconductor. A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to free air (that is, unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. Thermal Averaging Constant Thermal Design Power Thermal Sensor on DIMM Unbuffered Dual In-line Module

Intel Virtualization Technology (Intel VT)

Intel

VT-d

Integrated Heat Spreader (IHS) Jitter IOV LGA2011 Socket LLC ME NCTF Intel Core i7 processor family for the LGA-2011 socket PCH PCU PCI Express* 3.0 PCIe* PECI Processor Processor Core PCU Rank SCI SSE SKU SMBus

Storage Conditions

TAC TDP TSOD UDIMM

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Introduction

Table 1-1.

Terminology (Sheet 3 of 3)
Term Description Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t1, t2, tn,...., tk then the UI at instance n is defined as: UI n = t n t n 1 Processor core power supply Processor ground Power supply for the processor system memory interface. VCCD is the generic term for VCCD_01, VCCD_23. Refers to a Link or Port with one Physical Lane Refers to a Link or Port with four Physical Lanes Refers to a Link or Port with eight Physical Lanes Refers to a Link or Port with sixteen Physical Lanes

Unit Interval

VCC VSS VCCD_01, VCCD_23 x1 x4 x8 x16

1.7
Table 1-2.

Related Documents
Refer to the following documents for additional information. Reference Documents
Document Advanced Configuration and Power Interface Specification 3.0 PCI Local Bus Specification 3.0 PCI Express* Base Specification 3.0 System Management Bus (SMBus) Specification DDR3 SDRAM Specification Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide Intel 64 and IA-32 Architectures Optimization Reference Manual Intel Virtualization Technology Specification for Directed I/O Architecture Specification Document Number/ Location http://www.acpi.info http://www.pcisig.com/ specifications http://www.pcisig.com http://smbus.org/ http://www.jedec.org http://www.intel.com/p roducts/processor/man uals/index.htm

http://download.intel.co m/technology/computin g/vptech/Intel(r)_VT_fo r_Direct_IO.pdf

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2
2.1
2.1.1

Interfaces
This chapter describes the functional behaviors supported by the processor.

System Memory Interface

System Memory Technology Support
The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels and supports 1 unbuffered DIMM per channel.

2.1.2

System Memory Timing Support

The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface: tCL = CAS Latency tRCD = Activate Command to READ or WRITE Command delay tRP = PRECHARGE Command Period CWL = CAS Write Latency Command Signal modes = 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and memory configuration.

2.2

PCI Express* Interface

This section describes the PCI Express 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express 3.0.

2.2.1

PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification. The PCI Express architecture is specified in three layers Transaction Layer, Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries. Refer to Figure 2-1 for the PCI Express Layering Diagram.

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Figure 2-1.

PCI Express* Layering Diagram

Transaction Data Link Physical

Logical Sub-Block

Transaction Data Link Physical

Logical Sub-Block

Electrical Sub-Block

Electrical Sub-Block

RX

TX

RX

TX

PCI Express uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Figure 2-2. Packet Flow through the Layers
Framing Sequence Number Header Date ECRC LCRC Framing

Transaction Layer Data Link Layer Physical Layer

2.2.1.1

Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs.

2.2.1.2

Data Link Layer

The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer include link management, error detection, and error correction.

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The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP sequence number, and submits them to Physical Layer for transmission across the Link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing. On detection of TLP error(s), this layer is responsible for requesting retransmission of TLPs until information is correctly received, or the Link is determined to have failed. The Data Link Layer also generates and consumes packets which are used for Link management functions.

2.2.1.3

Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching circuitry. It also includes logical functions related to interface initialization and maintenance. The Physical Layer exchanges data with the Data Link Layer in an implementation-specific format, and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device.

2.2.2

PCI Express* Configuration Mechanism

The PCI Express link is mapped through a PCI-to-PCI bridge structure. PCI Express extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express configuration space is divided into a PCI-compatible region (which consists of the first 256 bytes of a logical device's configuration space) and an extended PCI Express region (which consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section. The PCI Express Host Bridge is required to translate the memory-mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express* Base Specification for details of both the PCI-compatible and PCI Express Enhanced configuration mechanisms and transaction rules.

2.3

DMI2/PCI Express* Interface

Direct Media Interface 2 (DMI2) connects the processor to the Platform Controller Hub (PCH). DMI2 is similar to a four-lane PCI Express supporting a speed of 5 GT/s per lane. Refer to Section 6.3, DMI2/PCI Express* Port 0 Signals for additional details.

Note:

Only DMI2 x4 configuration is supported.

2.3.1

DMI2 Error Flow

DMI2 can only generate SERR in response to errors; never SCI, SMI, MSI, PCI INT, or GPE. Any DMI2 related SERR activity is associated with Device 0.

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2.3.2

DMI2 Link Down

The DMI2 link going down is a fatal, unrecoverable error. If the DMI2 data link goes to data link down, after the link was up, then the DMI2 link hangs the system by not allowing the link to retrain to prevent data corruption. This is controlled by the PCH. Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal. No completions from downstream, non-posted transactions are returned upstream over the DMI2 link after a link down event.

2.4

Platform Environment Control Interface (PECI)

The Platform Environment Control Interface (PECI) uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. The physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic 0 or logic 1. PECI also includes variable data transfer rate established with every message. In this way, it is highly flexible even though underlying logic is simple. The interface design was optimized for interfacing to Intel processor and chipset components in both single processor and multiple processor environments. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information. Refer to the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, Related Documents) for additional details regarding PECI and for a list of supported PECI commands.

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3.1

Technologies
Intel Virtualization Technology (Intel VT)
Intel Virtualization Technology (Intel VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets. Intel Virtualization Technology (Intel VT) for Intel 64 and IA-32 Intel Architecture (Intel VT-x) adds hardware support in the processor to improve the virtualization performance and robustness. Intel VT-x specifications and functional descriptions are included in the Intel 64 and IA-32 Architectures Software Developers Manual, Volume 3B and is available at http://www.intel.com/ products/processor/manuals/index.htm Intel Virtualization Technology (Intel VT) for Directed I/O (Intel VT-d) adds processor and uncore hardware implementations to support and improve I/O virtualization performance and robustness. The Intel VT-d specification and other Intel VT documents can be referenced at http://www.intel.com/technology/virtualization/index.htm

3.1.1

Intel VT-x Objectives

Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable virtualized platform. By using Intel VT-x, a VMM is: Robust: VMMs no longer need to use para-virtualization or binary translation. This means that they will be able to run off-the-shelf operating systems and applications without any special steps. Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors. More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient. This improves reliability and availability and reduces the potential for software conflicts. More secure: The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system.

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3.1.2

Intel VT-x Features

The processor core supports the following Intel VT-x features: Extended Page Tables (EPT) hardware assisted page table virtualization eliminates VM exits from guest OS to the VMM for shadow page-table maintenance Virtual Processor IDs (VPID) Ability to assign a VM ID to tag processor core hardware structures (such as, TLBs) This avoids flushes on VM transitions to give a lower-cost VM transition time and an overall reduction in virtualization overhead. Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM. The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service (QoS) guarantees Descriptor-Table Exiting Descriptor-table exiting allows a VMM to protect a guest OS from internal (malicious software based) attack by preventing relocation of key system data structures like IDT (interrupt descriptor table), GDT (global descriptor table), LDT (local descriptor table), and TSS (task segment selector). A VMM using this feature can intercept (by a VM exit) attempts to relocate these data structures and prevent them from being tampered by malicious software.

3.1.3

Intel VT-d Objectives

The key Intel VT-d objectives are abstraction and robustness. Hardware abstraction has two key benefits. First is partitioning hardware into configurable isolated environments called domains to which a subset of host physical memory is allocated. Second is greater flexibility in modifying hardware capability without direct operating system interference. Virtualization allows for the creation of one or more partitions on a single system. This could be multiple partitions in the same operating system, or there can be multiple operating system instances running on the same system. The VT-d architecture provides the flexibility to support multiple usage models and in turn complement Intel VT-x capability. This offers benefits such as system consolidation, legacy migration, activity partitioning, or security. The second objective is robustness. VT-d enables protected access to I/O devices from a given virtual machine so that it does not interfere with a different virtual machine on the same platform. Any errors or permission violation are trapped and hence the system is more robust.

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3.1.3.1

Intel VT-d Features Supported

The processor supports the following Intel VT-d features: Root entry, context entry, and default context Support for 4-K page sizes only Support for register-based fault recording only (for single entry only) and support for MSI interrupts for faults Support for fault collapsing based on Requester ID Support for both leaf and non-leaf caching Support for boot protection of default page table Support for non-caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads upon IOTLB invalidation Support for page-selective IOTLB invalidation Support for ARI (Alternative Requester ID a PCI SIG ECR for increasing the function number count in a PCIe device) to support IOV devices

3.1.3.2

Intel VT-d Processor Feature Additions

The following are new features supported in Intel VT-d on the processor: Improved invalidation architecture End point caching support (Address Translation Services) Interrupt remapping 2M/1G/512G super page support

3.1.4

Intel Virtualization Technology Processor Extensions

The processor supports the following Intel VT Intel Core i7 processor family for the LGA-2011 socket Extensions features: Large Intel VT-d Pages Adds 2 MB and 1 GB page sizes to Intel VT-d implementations Matches current support for Extended Page Tables (EPT) Ability to share CPU's EPT page-table (with super-pages) with Intel VT-d Benefits: Less memory foot-print for I/O page-tables when using super-pages Potential for improved performance Due to shorter page-walks, allows hardware optimization for IOTLB Transition latency reductions expected to improve virtualization performance without the need for VMM enabling. This reduces the VMM overheads further and increase virtualization performance.

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3.2
3.2.1

Security Technologies
AES Instructions
These instructions enable fast and secure data encryption and decryption using the Advanced Encryption Standard (AES), which is defined by FIPS Publication number 197. Since AES is the dominant block cipher, and it is deployed in various protocols, the new instructions will be valuable for a wide range of applications. The architecture consists of six instructions that offer full hardware support for AES. Four instructions support the AES encryption and decryption, and the other two instructions support the AES key expansion. Together, they offer a significant increase in performance compared to pure software implementations. The AES instructions have the flexibility to support all three standard AES key lengths, all standard modes of operation, and even some nonstandard or future variants. Beyond improving performance, the AES instructions provide important security benefits. Since the instructions run in data-independent time and do not use lookup tables, they help in eliminating the major timing and cache-based attacks that threaten table-based software implementations of AES. In addition, these instructions make AES simple to implement, with reduced code size. This helps reducing the risk of inadvertent introduction of security flaws, such as difficult-to-detect side channel leaks.

3.2.2

Execute Disable Bit

Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system: Allows the processor to classify areas in memory by where application code can execute and where it cannot. When a malicious worm attempts to insert code in the buffer, the processor disables code execution, preventing damage and worm propagation.

3.3

Intel Hyper-Threading Technology

The processor supports Intel Hyper-Threading Technology (Intel HT Technology) that allows an execution core to function as two logical processors. While some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled using the BIOS and requires operating system support. For more information on Intel Hyper-Threading Technology, see http://www.intel.com/ technology/platform-technology/hyper-threading/.

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3.4

Intel Turbo Boost Technology

Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power, temperature, and current limits. The result is increased performance in multithreaded and single threaded workloads. It should be enabled in the BIOS for the processor to operate with maximum performance.

3.4.1

Intel Turbo Boost Operating Frequency

The processors rated frequency assumes that all execution cores are running an application at the thermal design power (TDP). However, under typical operation, not all cores are active. Therefore, most applications are consuming less than the TDP at the rated frequency. To take advantage of the available TDP headroom, the active cores can increase their operating frequency. To determine the highest performance frequency amongst active cores, the processor takes the following into consideration: The number of cores operating in the C0 state. The estimated current consumption. The estimated power consumption. The temperature. Any of these factors can affect the maximum frequency for a given workload. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit.

Note:

Intel Turbo Boost Technology is only active if the operating system is requesting the P0 state. For more information on P-states and C-states, refer to Chapter 4, "Power Management".

3.5

Enhanced Intel SpeedStep Technology

The processor supports Enhanced Intel SpeedStep Technology (EIST) as an advanced means of enabling very high performance while also meeting the power-conservation needs of the platform. Enhanced Intel SpeedStep Technology builds upon that architecture using design strategies that include the following: Separation between Voltage and Frequency Changes. By stepping voltage up and down in small increments separately from frequency changes, the processor can reduce periods of system unavailability (which occur during frequency change). Thus, the system can transition between voltage and frequency states more often, providing improved power/performance balance. Clock Partitioning and Recovery. The bus clock continues running during state transition, even when the core clock and Phase-Locked Loop are stopped, which allows logic to remain active. The core clock can also restart more quickly under Enhanced Intel SpeedStep Technology. For additional information on Enhanced Intel SpeedStep Technology, see Section 4.2.1.

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3.6

Intel Advanced Vector Extensions (Intel AVX)

Intel Advanced Vector Extensions (Intel AVX) is a new 256-bit vector SIMD extension of Intel Architecture. The introduction of Intel AVX starts with the 2nd Generation Intel Core Processor Family Desktop. Intel AVX accelerates the trend of parallel computation in general purpose applications like image, video, and audio processing, engineering applications such as 3D modeling and analysis, scientific simulation, and financial analysts. Intel AVX is a comprehensive ISA extension of the Intel 64 Architecture. The main elements of Intel AVX are: Support for wider vector data (up to 256-bit) for floating-point computation Efficient instruction encoding scheme that supports 3 operand syntax and headroom for future extensions Flexibility in programming environment, ranging from branch handling to relaxed memory alignment requirements New data manipulation and arithmetic compute primitives, including broadcast, permute, fused-multiply-add, etc The key advantages of Intel AVX are: Performance Intel AVX can accelerate application performance using data parallelism and scalable hardware infrastructure across existing and new application domains: 256-bit vector data sets can be processed up to twice the throughput of 128-bit data sets Application performance can scale up with number of hardware threads and number of cores Power Efficiency Intel AVX is extremely power efficient. Incremental power is insignificant when the instructions are unused or scarcely used. Combined with the high performance that it can deliver, applications that lend themselves heavily to using Intel AVX can be much more energy efficient and realize a higher performance-per-watt. Extensibility Intel AVX has built-in extensibility for the future vector extensions: OS context management for vector-widths beyond 256 bits is streamlined Efficient instruction encoding allows unlimited functional enhancements: Vector width support beyond 256 bits 256-bit Vector Integer processing Additional computational and/or data manipulation primitives. Compatibility Intel AVX is backward compatible with previous ISA extensions including Intel SSE4: Existing Intel SSE applications/library can: Run unmodified and benefit from processor enhancements Recompile existing Intel SSE intrinsic using compilers that generate Intel AVX code Inter-operate with library ported to Intel AVX Applications compiled with Intel AVX can inter-operate with existing Intel SSE libraries

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Power Management
This chapter provides information on the following power management topics: ACPI States System States Processor Core/Package States Integrated Memory Controller (IMC) and System Memory States Direct Media Interface Gen 2 (DMI2)/PCI Express* Link States

4.1
4.1.1
Table 4-1.

ACPI States Supported

The ACPI states supported by the processor are described in this section.

System States
System States
State G0/S0 G1/S3-Cold G1/S4 G2/S5 G3 Full On Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). Suspend-to-Disk (STD). All power lost (except wakeup on PCH). Soft off. All power lost (except wakeup on PCH). Total reboot. Mechanical off. All power removed from system. Description

4.1.2

Processor Package and Core States

Table 4-2 lists the package C-state support as: the shallowest core C-state that allows entry into the package C-state the additional factors that will restrict the state from going any deeper the actions taken with respect to the Ring Vcc, PLL state, and LLC.

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Table 4-3 lists the processor core C-states support. Table 4-2. Package C-State Support
Package C-State PC0 Active Core States CC0 N/A PC2 Snoopable Idle CC3CC7 PC3 Light Retention at least one Core in C3 PCIe/PCH and Remote Socket Snoops PCIe/PCH and Remote Socket Accesses Interrupt response time requirement DMI Sidebands Configuration Constraints Core C-state Snoop Response Time Interrupt Response Time Non Snoop Response Time LLC ways open Snoop Response Time Non Snoop Response Time Interrupt Response Time Limiting Factors Retention and PLL-Off No LLC Fully Flushed No Notes1 2

VccMin Freq = MinFreq PLL = ON

No

Vcc = retention PLL = OFF

No

2,3,4

PC6 Deeper Retention

CC6CC7

Vcc = retention PLL = OFF

No

2,3,4

Notes: 1. Package C7 is not supported. 2. All package states are defined to be "E" states such that they always exit back into the LFM point upon execution resume. 3. The mapping of actions for PC3, and PC6 are suggestions microcode will dynamically determine which actions should be taken based on the desired exit latency parameters. 4. CC3/CC6 will all use a voltage below the VccMin operational point. The exact voltage selected will be a function of the snoop and interrupt response time requirements made by the devices (PCIe* and DMI) and the operating system.

Table 4-3.

Core C-State Support

Core C-State CC0 CC1 CC1E CC3 CC6 CC7 Global Clock Running Stopped Stopped Stopped Stopped Stopped PLL On On On On On Off L1/L2 Cache Coherent Coherent Coherent Flushed to LLC Flushed to LLC Flushed to LLC Core VCC Active Active Request LFM Request Retention Power Gate Power Gate Context Maintained Maintained Maintained Maintained Flushed to LLC Flushed to LLC

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4.1.3
Table 4-4.

Integrated Memory Controller States

System Memory Power States
State Power Up/Normal Operation Description CKE asserted. Active Mode, highest power consumption. Opportunistic, per rank control after idle time: Active Power Down (APD) (default mode) CKE de-asserted. Power savings in this mode, relative to active idle state is about 55% of the memory power. Exiting this mode takes 35 DCLK cycles. Pre-charge Power Down Fast Exit (PPDF) CKE de-asserted. DLL-On. Also known as Fast CKE. Power savings in this mode, relative to active idle state, is about 60% of the memory power. Exiting this mode takes 35 DCLK cycles. Pre-charge Power Down Slow Exit (PPDS) CKE de-asserted. DLL-Off. Also known as Slow CKE. Power savings in this mode, relative to active idle state, is about 87% of the memory power. Exiting this mode takes 35 DCLK cycles until the first command is allowed and 16 cycles until first data is allowed. Register CKE Power Down IBT-ON mode: Both CKEs are de-asserted, the Input Buffer Terminators (IBTs) are left on. IBT-OFF mode: Both CKEs are de-asserted, the Input Buffer Terminators (IBTs) are turned off. CKE de-asserted. In this mode, no transactions are executed and the system memory consumes the minimum possible power. Self refresh modes apply to all memory channels for the processor. IO-MDLL Off: Option that sets the IO master DLL off when self refresh occurs. PLL Off: Option that sets the PLL off when self refresh occurs. In addition, the register component found on registered DIMMs (RDIMMs) is complemented with the following power down states: Self Refresh Clock Stopped Power Down with IBT-On Clock Stopped Power Down with IBT-Off

CKE Power Down

Self-Refresh

4.1.4
Table 4-5.

DMI2/PCI Express* Link States

DMI2/PCI Express* Link States
State L0 L11 Notes: 1. L1 is only supported when the DMI2/PCI Express port is operating as a PCI Express port. Full on Active transfer state. Lowest Active State Power Management (ASPM) - Longer exit latency. Description

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4.1.5
Table 4-6.

G, S, and C State Combinations

G, S, and C State Combinations
Global (G) State G0 G0 G0 G0 G1 G1 G2 G3 Sleep (S) State S0 S0 S0 S0 S3 S4 S5 NA Processor Core (C) State C0 C1/C1E C3 C6/C7 Power off Power off Power off Power off Processor State Full On Auto-Halt Deep Sleep Deep Power Down System Clocks On On On On Off, except RTC Off, except RTC Off, except RTC Power off Full On Auto-Halt Deep Sleep Deep Power Down Suspend to RAM Suspend to Disk Soft Off Hard off Description

4.2

Processor Core/Package Power Management

While executing code, Enhanced Intel SpeedStep Technology optimizes the processors frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-states have longer entry and exit latencies.

4.2.1

Enhanced Intel SpeedStep Technology

The following are the key features of Enhanced Intel SpeedStep Technology: Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on temperature, leakage, power delivery loadline, and dynamic capacitance. If the target frequency is higher than the current frequency, VCC is ramped up to an optimized voltage. This voltage is signaled by the SVID Bus to the voltage regulator. Once the voltage is established, the PLL locks on to the target frequency. If the target frequency is lower than the current frequency, the PLL locks to the target frequency, then transitions to a lower voltage by signaling the target voltage on the SVID Bus. All active processor cores share the same frequency and voltage. In a multicore processor, the highest frequency P-state requested amongst all active cores is selected. Software-requested transitions are accepted at any time. The processor has a new capability from the previous processor generation, it can preempt the previous transition and complete the new request without waiting for this request to complete. The processor controls voltage ramp rates internally to ensure glitch-free transitions. Because there is low transition latency between P-states, a significant number of transitions per-second are possible.

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4.2.2

Low-Power Idle States

When the processor is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-states. However, higher C-states have longer exit and entry latencies. Resolution of C-states occur at the thread, processor core, and processor package level. Thread level C-states are available if Hyper-Threading Technology is enabled. Entry and exit of the C-States at the thread and core level are shown in Figure 4-2.

Figure 4-1.

Idle Power Management Breakdown of the Processor Cores

T h re a d 0

T h re a d 1

T h re a d 0

T h re a d 1

C o r e 0 S ta te

C o r e N S ta te

P r o c e s s o r P a c k a g e S t a te

Figure 4-2.

Thread and Core C-State Entry and Exit

C0
MWAIT(C1), HLT MWAIT(C1), HLT (C1E Enabled) MWAIT(C7), P_LVL4 I/O Read

MWAIT(C3), P_LVL2 I/O Read

MWAIT(C6), P_LVL3 I/O Read

C1

C1E

C3

C6

C7

While individual threads can request low power C-states, power saving actions only take place once the core C-state is resolved. Core C-states are automatically resolved by the processor. For thread and core C-states, a transition to and from C0 is required before entering any other C-state.

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4.2.3

Requesting Low-Power Idle States

If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1 state or higher. The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx. This method of requesting C-states provides legacy support for operating systems that initiate C-state transitions using I/O reads. For legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS.

Note:

The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as shown in Table 4-7. P_LVLx to MWAIT Conversion
P_LVLx P_LVL2 P_LVL3 P_LVL4 MWAIT(Cx) MWAIT(C3) MWAIT(C6) MWAIT(C7) C6. No sub-states allowed. C7. No sub-states allowed. Notes

Table 4-7.

The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any P_LVLx reads outside of this range do not cause an I/O redirection to MWAIT(Cx) like request. They fall through like a normal I/O instruction. Note: When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O redirections enable the MWAIT 'break on EFLAGS.IF feature that triggers a wakeup on an interrupt, even if interrupts are masked by EFLAGS.IF.

4.2.4

Core C-states
The following are general rules for all core C-states, unless specified otherwise: A core C-State is determined by the lowest numerical thread state (such as, Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See Table 4-6. A core transitions to C0 state when: an interrupt occurs. there is an access to the monitored address if the state was entered using an MWAIT instruction. For core C1/C1E, and core C3, an interrupt directed toward a single thread wakes only that thread. However, since both threads are no longer at the same core Cstate, the core resolves to C0. An interrupt only wakes the target thread for both C3 and C6 states. Any interrupt coming into the processor package may wake any core.

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4.2.4.1

Core C0 State
The normal operating state of a core where code is being executed.

4.2.4.2

Core C1/C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel 64 and IA-32 Architecture Software Developers Manual, Volume 3A/3B: System Programmers Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see Section 4.2.5.2, Package C1/C1E.

4.2.4.3

Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while maintaining its architectural state. All core clocks are stopped at this point. Because the cores caches are flushed, the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory.

4.2.4.4

Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts. During exit, the core is powered on and its architectural state is restored. In addition to flushing core caches core architecture state is saved to the uncore. Once the core state save is completed, core voltage is reduced to zero.

4.2.4.5

Core C7 State
Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to the P_BLK or by an MWAIT(C7) instruction. Core C7 and core C7 substate are the same as Core C6. The processor does not support LLC flush under any condition.

4.2.4.6

C-State Auto-Demotion
In general, deeper C-states such as C6 or C7 have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. To increase residency in deeper C-states, the processor supports C-state auto-demotion. There are two C-State auto-demotion options: C6/C7 to C3 C7/C6/C3 To C1 The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 is based on each cores immediate residency history. Upon each core C6/C7 request, the core C-state is demoted to C3 or C1 until a sufficient amount of residency has been established. At that point, a core is allowed to go into C3/C6 or C7. Each option can be run concurrently or individually.

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This feature is disabled by default. BIOS must enable it in the PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by this register.

4.2.5

Package C-States
The processor supports C0, C1/C1E, C2, C3, and C6 power states. The following is a summary of the general rules for package C-state entry. These apply to all package C-states unless specified otherwise: A package C-state request is determined by the lowest numerical core C-state amongst all cores. A package C-state is automatically resolved by the processor depending on the core idle power states and the status of the platform components. Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C-state. The platform may allow additional power savings to be realized in the processor. For package C-states, the processor is not required to enter C0 before entering any other C-state. The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following: If a core break event is received, the target core is activated and the break event message is forwarded to the target core. If the break event is not masked, the target core enters the core C0 state and the processor enters package C0. If the break event is masked, the processor attempts to re-enter its previous package state. If the break event was due to a memory access or snoop request. But the platform did not request to keep the processor in a higher package Cstate, the package returns to its previous C-state. And the platform requests a higher power C-state, the memory access or snoop request is serviced and the package remains in the higher power C-state. The package C-states fall into two categories uncoordinated and coordinated. C0/C1/ C1E are uncoordinated, while C2/C3/C6 are coordinated. Starting with the 2nd Generation Intel Core Processor Family Desktop, package Cstates are based on exit latency requirements which are accumulated from the PCIe* devices, PCH, and software sources. The level of power savings that can be achieved is a function of the exit latency requirement from the platform. As a result, there is no fixed relationship between the coordinated C-state of a package, and the power savings that will be obtained from the state. Coordinated package C-states offer a range of power savings which is a function of the ensured exit latency requirement from the platform. There is also a concept of Execution Allowed (EA) when EA status is 0, the cores in a socket are in C3 or a deeper state, a socket initiates a request to enter a coordinated package C-state. The coordination is across all sockets and the PCH. Table 4-8 shows an example of a dual-core processor package C-state resolution. Figure 4-3 summarizes package C-state transitions with package C2 as the interim between PC0 and PC1 prior to PC3 and PC6.

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Table 4-8.

Coordination of Core Power States at the Package Level

Package C-State Core 1 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C3 C0 C11 C3 C3 C6 C0 C11 C3 C6

C0 C1 C3 C6 Notes:

Core 0

1. If enabled, the package C-state will be C1E if all actives cores have resolved a core C1 state or higher.

Figure 4-3.

Package C-State Entry and Exit

4.2.5.1

Package C0
The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0.

4.2.5.2

Package C1/C1E
No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. Autonomous power reduction actions that are based on idle timers can trigger depending on the activity in the system. The package enters the C1 low power state when: At least one core is in the C1 state The other cores are in a C1 or lower power state

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The package enters the C1E state when: All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint All cores are in a power state lower that C1/C1E but the package low power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is enabled in IA32_MISC_ENABLES No notification to the system occurs upon entry to C1/C1E.

4.2.5.3

Package C2 State
The Package C2 state is an intermediate state that represents the point at which the system level coordination is in progress. The package cannot reach this state unless all cores are in at least C3. The package will remain in C2 when: it is awaiting for a coordinated response the coordinated exit latency requirements are too stringent for the package to take any power saving actions If the exit latency requirements are high enough, the package will transition to C3 or C6 depending on the state of the cores.

4.2.5.4

Package C3 State
A processor enters the package C3 low power state when: At least one core is in the C3 state The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform L3 shared cache retains context and becomes inaccessible in this state Additional power savings actions, as allowed by the exit latency requirements, include putting PCIe* links in L1, the uncore is not available, further voltage reduction can be taken In package C3, the ring will be off and as a result no accesses to the LLC are possible. The content of the LLC is preserved

4.2.5.5

Package C6 State
A processor enters the package C6 low power state when: At least one core is in the C6 state The other cores are in a C6 or lower power state, and the processor has been granted permission by the platform L3 shared cache retains context and becomes inaccessible in this state Additional power savings actions, as allowed by the exit latency requirements, include putting PCIe* links in L1, the uncore is not available, further voltage reduction can be taken In package C6 state, all cores have saved their architectural state and have had their core voltages reduced to zero volts. The LLC retains context, but no accesses can be made to the LLC in this state, the cores must break out to the internal state package C2 for snoops to occur.

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4.2.6

Package C-State Power Specifications

Table 4-9 lists the processor package C-state power specifications for various processor SKUs. The C-state power specification is based on post-silicon validation results. The processor case temperature is assumed at 50 C for all C-states.

Table 4-9.

Package C-State Power Specifications

TDP SKUs 6-Core C1E (W) C3 (W) C6 (W)

130 W (6-core)
4-Core

53

35

21

130 W (4-core)

53

28

16

4.3

System Memory Power Management

The DDR3 power states can be summarized as the following: Normal operation (highest power consumption) CKE Power-Down: Opportunistic, per rank control after idle time. There may be different levels. Active Power-Down Precharge Power-Down with Fast Exit Precharge power Down with Slow Exit Self Refresh: In this mode no transaction is executed. The DDR consumes the minimum possible power.

4.3.1

CKE Power-Down
The CKE input land is used to enter and exit different power-down modes. The memory controller has a configurable activity timeout for each rank. When no reads are present to a given rank for the configured interval, the memory controller will transition the rank to power-down mode. The memory controller transitions the DRAM to power-down by de-asserting CKE and driving a NOP command. The memory controller will tri-state all DDR interface lands except CKE (de-asserted) and ODT while in power-down. The memory controller will transition the DRAM out of power-down state by synchronously asserting CKE and driving a NOP command. When CKE is off, the internal DDR clock is disabled and the DDR power is significantly reduced. The DDR defines three levels of power-down: Active power-down: This mode is entered if there are open pages when CKE is deasserted. In this mode the open pages are retained. Existing this mode is 35 DCLK cycles. Precharge power-down fast exit: This mode is entered if all banks in DDR are precharged when de-asserting CKE. Existing this mode is 35 DCLK cycles. The difference from the active power-down mode is that when waking up, all pagebuffers are empty. Precharge power-down slow exit: In this mode the data-in DLLs on DDR are off. Existing this mode is 35 DCLK cycles until the first command is allowed, but about 16 cycles until first data is allowed.

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4.3.2

Self Refresh
The Uncore Power Manager (PCU) may request the memory controller to place the DRAMs in self refresh state. Self refresh per channel is supported. The BIOS can put the channel in self refresh if software remaps memory to use a subset of all channels. Also processor channels can enter self refresh autonomously without PCU instruction when the package is in a package C0 state.

4.3.2.1

Self Refresh Entry

Self refresh entrance can be either disabled or triggered by an idle counter. Idle counter always clears with any access to the memory controller and remains clear as long as the memory controller is not drained. As soon as the memory controller is drained, the counter starts counting, and when it reaches the idle-count, the memory controller will place the DRAMs in self refresh state. Power may be removed from the memory controller core at this point, but the VCCD supply (1.5 V) to the DDR I/O must be maintained.

4.3.2.2

Self Refresh Exit

Self refresh exit can be either a message from an external unit (PCU in most cases, but also possibly from any message-channel master) or as reaction for an incoming transaction. The proper actions on self refresh exit are: CK is enabled, and four CK cycles driven When proper skew between Address/Command and CK are established, assert CKE Issue NOPs for tXSRD cycles Issue ZQCL to each rank The global scheduler will be enabled to issue commands

4.3.2.3

DLL and PLL Shutdown

Self refresh, according to configuration, may be a trigger for master DLL shut-down and PLL shut-down. The master DLL shut-down is issued by the memory controller after the DRAMs have entered self refresh. The PLL shut-down and wake-up is issued by the PCU. The memory controller gets a signal from PLL indicating that the memory controller can start working again.

4.3.3

DRAM I/O Power Management

Unused signals are tristated to save power. This includes all signals associated with an unused memory channel. The I/O buffer for an unused signal should be tristated (output driver disabled), the input receiver (differential sense-amp) should be disabled. The input path must be gated to prevent spurious results due to noise on the unused signals (typically handled automatically when input receiver is disabled).

4.4

DMI2/PCI Express* Power Management

Active State Power Management (ASPM) support using the L1 state.

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Thermal Management Specifications

For thermal specifications and design guidelines, refer to the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, Related Documents).

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Signal Descriptions
This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category.

6.1
Table 6-1.

System Memory Interface

Memory Channel DDR0, DDR1, DDR2, DDR3
Signal Name Description Bank Address. Defines the bank which is the destination for the current Activate, Read, Write, or Precharge command. Column Address Strobe. Clock Enable. Differential clocks to the DIMM. All command and control signals are valid on the rising edge of clock. Chip Select. Each signal selects one rank as the target of the command and address. Data Bus. DDR3 Data bits. Data strobes. Differential pair, Data Strobe. Differential strobes latch data for each DRAM. Driven with edges in center of data, receive edges are aligned with data edges. Check bits. An error correction code is driven along with data on these lines for DIMMs that support that capability. Note: ECC DIMMs are not supported on the processor; thus, these signals are not used. Memory Address. Selects the Row address for Reads and writes, and the column address for activates. Also used to set values for DRAM configuration registers. On Die Termination. Enables DRAM on die termination during Data Write or Data Read transactions. Row Address Strobe. Write Enable.

DDR{0/1/2/3}_BA[2:0] DDR{0/1/2/3}_CAS_N DDR{0/1/2/3}_CKE[3:0] DDR{0/1/2/3}_CLK_DN[3:0] DDR{0/1/2/3}_CLK_DP[3:0] DDR{0/1/2/3}_CS_N[1:0] DDR{0/1/2/3}_CS_N[5:4] DDR{0/1/2/3}_DQ[63:00] DDR{0/1/2/3}_DQS_DP[08:00] DDR{0/1/2/3}_DQS_DN[08:00] DDR{0/1/2/3}_ECC[7:0]

DDR{0/1/2/3}_MA[15:00] DDR{0/1/2/3}_ODT[3:0] DDR{0/1/2/3}_RAS_N DDR{0/1/2/3}_WE_N

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Table 6-2.

Memory Channel Miscellaneous

Signal Name Description System memory reset: Reset signal from processor to DRAM devices on the DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while DDR_RESET_C23_N is used for memory channels 2 and 3. SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs. DDR_SCL_C01 is used for memory channels 0 and 1 while DDR_SCL_C23 is used for memory channels 2 and 3. SMBus data for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs. DDR_SDA_C1 is used for memory channels 0 and 1 while DDR_SDA_C23 is used for memory channels 2 and 3. Voltage reference for system memory reads. DDR_VREFDQRX_C01 is used for memory channels 0 and 1 while DDR_VREFDQRX_C23 is used for memory channels 2 and 3. Voltage reference for system memory writes. DDR_VREFDQTX_C01 is used for memory channels 0 and 1 while DDR_VREFDQTX_C23 is used for memory channels 2 and 3. Note: Future implementation option, not included in first silicon. System memory impedance compensation. Impedance compensation must be terminated on the system board using a precision resistor. Power good input signal used to indicate that the VCCD power supply is stable for memory channels 0 & 1 and channels 2 & 3.

DDR_RESET_C01_N DDR_RESET_C23_N DDR_SCL_C01 DDR_SCL_C23 DDR_SDA_C01 DDR_SDA_C23 DDR_VREFDQRX_C01 DDR_VREFDQRX_C23 DDR_VREFDQTX_C01 DDR_VREFDQTX_C23 DDR{01/ 23}_RCOMP[2:0] DRAM_PWR_OK_C01 DRAM_PWR_OK_C23

6.2
Note: Table 6-3.

PCI Express* Based Interface Signals

PCI Express* Ports 1, 2, and 3 Signals are receive and transmit differential pairs. PCI Express* Port 1 Signals
Signal Name Description PCIe Receive Data Input

PE1A_RX_DN[3:0] PE1A_RX_DP[3:0] PE1B_RX_DN[7:4] PE1B_RX_DP[7:4] PE1A_TX_DN[3:0] PE1A_TX_DP[3:0] PE1B_TX_DN[7:4] PE1B_TX_DP[7:4]

PCIe Receive Data Input

PCIe Transmit Data Output

PCIe Transmit Data Output

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Table 6-4.

PCI Express* Port 2 Signals

Signal Name Description PCIe Receive Data Input

PE2A_RX_DN[3:0] PE2A_RX_DP[3:0] PE2B_RX_DN[7:4] PE2B_RX_DP[7:4] PE2C_RX_DN[11:8] PE2C_RX_DP[11:8] PE2D_RX_DN[15:12] PE2D_RX_DP[15:12] PE2A_TX_DN[3:0] PE2A_TX_DP[3:0] PE2B_TX_DN[7:4] PE2B_TX_DP[7:4] PE2C_TX_DN[11:8] PE2C_TX_DP[11:8] PE2D_TX_DN[15:12] PE2D_TX_DP[15:12]

PCIe Receive Data Input

PCIe Receive Data Input

PCIe Receive Data Input

PCIe Transmit Data Output

PCIe Transmit Data Output

PCIe Transmit Data Output

PCIe Transmit Data Output

Table 6-5.

PCI Express* Port 3 Signals

Signal Name Description PCIe Receive Data Input

PE3A_RX_DN[3:0] PE3A_RX_DP[3:0] PE3B_RX_DN[7:4] PE3B_RX_DP[7:4] PE3C_RX_DN[11:8] PE3C_RX_DP[11:8] PE3D_RX_DN[15:12] PE3D_RX_DP[15:12] PE3A_TX_DN[3:0] PE3A_TX_DP[3:0] PE3B_TX_DN[7:4] PE3B_TX_DP[7:4] PE3C_TX_DN[11:8] PE3C_TX_DP[11:8] PE3D_TX_DN[15:12] PE3D_TX_DP[15:12]

PCIe Receive Data Input

PCIe Receive Data Input

PCIe Receive Data Input

PCIe Transmit Data Output

PCIe Transmit Data Output

PCIe Transmit Data Output

PCIe Transmit Data Output

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Table 6-6.

PCI Express* Miscellaneous Signals

Signal Name Description This input is used to control PCI Express* bias currents. A 50 ohm 1% tolerance resistor must be connected from this land to VSS by the platform. PE_RBIAS is required to be connected as if the link is being used even when PCIe* is not used. Provides dedicated bias resistor sensing to minimize the voltage drop caused by packaging and platform effects. PE_RBIAS_SENSE is required to be connected as if the link is being used even when PCIe* is not used. PCI Express* voltage reference used to measure the actual output voltage and comparing it to the assumed voltage. A 0.01 uF capacitor must be connected from this land to VSS.

PE_RBIAS

PE_RBIAS_SENSE

PE_VREF_CAP

6.3
Table 6-7.

DMI2/PCI Express* Port 0 Signals

DMI2 to Port 0 Signals
Signal Name DMI_RX_DN[3:0] DMI_RX_DP[3:0] DMI_TX_DP[3:0] DMI_TX_DN[3:0] DMI2 Transmit Data Output DMI2 Receive Data Input Description

6.4
Table 6-8.

PECI Signal
PECI Signals
Signal Name Description PECI (Platform Environment Control Interface) is the serial sideband interface to the processor and is used primarily for thermal, power and error management.

PECI

6.5
Table 6-9.

System Reference Clock Signals

System Reference Clock (BCLK{0/1}) Signals
Signal Name Description Reference Clock Differential input. These pins provide the PLL reference clock differential input into the processor.

BCLK{0/1}_D[N/P]

6.6

JTAG and TAP Signals

Table 6-10. JTAG and TAP Signals (Sheet 1 of 2)

Signal Name Description Breakpoint and Performance Monitor Signals: I/O signals from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. These are 100 MHz signals.

BPM_N[7:0]

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Table 6-10. JTAG and TAP Signals (Sheet 2 of 2)

Signal Name Description External Alignment of Reset, used to bring the processor up into a deterministic state. This signal is pulled up on the die; refer to Table 7-6 for details. Probe Mode Ready is a processor output used by debug tools to determine processor debug readiness. Probe Mode Request is used by debug tools to request debug operation of the processor. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must be driven low during power on Reset.

EAR_N PRDY_N PREQ_N TCK TDI TDO TMS TRST_N

6.7

Serial VID Interface (SVID) Signals

Table 6-11. SVID Signals

Signal Name Description Serial VID alert. Serial VID clock. Serial VID data out.

SVIDALERT_N SVIDCLK SVIDDATA

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6.8

Processor Asynchronous Sideband and Miscellaneous Signals

Table 6-12. Processor Asynchronous Sideband Signals (Sheet 1 of 2)

Signal Name Description Input which allows the platform to enable or disable built-in self test (BIST) on the processor. This signal is pulled up on the die; refer to Table 7-6 for details. Indicates that the system has experienced a fatal or catastrophic error and cannot continue to operate. The processor will assert CAT_ERR_N for nonrecoverable machine check errors and other internal unrecoverable errors. It is expected that every processor in the system will wire-OR CAT_ERR_N for all processors. Since this is an I/O land, external agents are allowed to assert this land, which will cause the processor to take a machine check exception. This signal is sampled after PWRGOOD assertion. On the processor, CAT_ERR_N is used for signaling the following types of errors: Legacy MCERRs, CAT_ERR_N is asserted for 16 BCLKs. Legacy IERRs, CAT_ERR_N remains asserted until warm or cold reset.

BIST_ENABLE

CAT_ERR_N

CPU_ONLY_RESET

Resets all the processors on the platform without resetting the DMI2 links. Error status signals for integrated I/O (IIO) unit: 0 = Hardware correctable error (no operating system or firmware action necessary)

ERROR_N[2:0]

1 = Non-fatal error (operating system or firmware action required to contain and recover) 2 = Fatal error (system reset likely required to recover) Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two modes of operation input and output mode.

MEM_HOT_C01_N MEM_HOT_C23_N

Input mode is externally asserted and is used to detect external events such as VR_HOT# from the memory voltage regulator and causes the processor to throttle the appropriate memory channels. Output mode is asserted by the processor known as level mode. In level mode, the output indicates that a particular branch of memory subsystem is hot. MEM_HOT_C01_N is used for memory channels 0 & 1 while MEM_HOT_C23_N is used for memory channels 2 & 3.

PMSYNC

Power Management Sync. A sideband signal to communicate power management status from the Platform Controller Hub (PCH) to the processor. PROCHOT_N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal can also be driven to the processor to activate the Thermal Control Circuit. This signal is sampled after PWRGOOD assertion. If PROCHOT_N is asserted at the deassertion of RESET_N, the processor will tristate its outputs. Power Good is a processor input. The processor requires this signal to be a clean indication that BCLK, VTTA/VTTD, VSA, VCCPLL, VCCD_01 and VCCD_23 supplies are stable and within their specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. PWRGOOD transitions from inactive to active when all supplies except VCC are stable. VCC has a VBOOT of zero volts and is not included in PWRGOOD indication in this phase. However, for the active to inactive transition, if any processor power supply (VCC, VTTA/VTTD, VSA, VCCD, or VCCPLL) is about to fail or is out of regulation, the PWRGOOD is to be negated. The signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. Note: VCC has a Vboot setting of 0.0 V and is not included in the PWRGOOD indication and VSA has a Vboot setting of 0.9 V.

PROCHOT_N

PWRGOOD

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Table 6-12. Processor Asynchronous Sideband Signals (Sheet 2 of 2)

Signal Name Description Asserting the RESET_N signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. Some PLL and error states are not effected by reset and only PWRGOOD forces them to a known state. Test[4:0] must be individually connected to an appropriate power source or ground through a resistor for proper processor operation. Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical overtemperature conditions: One, the processor junction temperature has reached a level beyond which permanent silicon damage may occur and Two, the system memory interface has exceeded a critical temperature limit set by BIOS. Measurement of the processor junction temperature is accomplished through multiple internal thermal sensors that are monitored by the Digital Thermal Sensor (DTS). Simultaneously, the Power Control Unit (PCU) monitors external memory temperatures using the dedicated SMBus interface to the DIMMs.

RESET_N TEST[4:0]

THERMTRIP_N

If any of the DIMMs exceed the BIOS defined limits, the PCU will signal THERMTRIP_N to prevent damage to the DIMMs. Once activated, the processor will stop all execution and shut down all PLLs. To further protect the processor, its core voltage (VCC), VTTA, VTTD, VSA, VCCPLL, VCCD supplies must be removed following the assertion of THERMTRIP_N. Once activated, THERMTRIP_N remains latched until RESET_N is asserted. While the assertion of the RESET_N signal may de-assert THERMTRIP_N, if the processor's junction temperature remains at or above the trip level, THERMTRIP_N will again be asserted after RESET_N is de-asserted. This signal can also be asserted if the system memory interface has exceeded a critical temperature limit set by BIOS. This signal is sampled after PWRGOOD assertion.

Table 6-13. Miscellaneous Signals

Signal Name Description These configuration straps are used to inform the processor that a nonstandard value for BCLK is going to is been applied at reset. A "11" encoding on these inputs will inform the processor to run at DEFAULT BCLK = 100 MHz. These signals have internal pull-up to VTT. The encoding is as follows: BCLK_SELECT[1:0] BCLK_SELECT1 BCLK_SELECT0 X 1 1 0 0 CORE_VREF_CAP CORE_RBIAS CORE_RBIAS_SENSE X 1 0 1 0 BCLK Selected 100 MHz (default) 100 MHz 125 MHz Reserved Reserved

A capacitor must be connected from this land. This input is used to control bias currents. Provides dedicated bias resistor sensing to minimize the voltage drop caused by packaging and platform effects. This output can be used by the platform to determine if the installed processor is a Intel Core i7 processor family for the LGA-2011 socket or a future processor planned for the platforms. There is no connection to the processor silicon for this signal. This signal is also used by the VCCPLL and VTT rails to switch their output voltage to support future processors. RESERVED. All signals that are RSVD must be left unconnected on the board. Refer to Section 7.1.9 for details. SKTOCC_N (Socket occupied) is used to indicate that a processor is present. This is pulled to ground on the processor package; there is no connection to the processor silicon for this signal. TESTHI_XX signal must be pulled up on the board.

PROC_SEL_N

RSVD SKTOCC_N TESTHI_BH48 TESTHI_BF48 TESTHI_AT50

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6.9

Processor Power and Ground Supplies

Table 6-14. Power and Ground Signals

Signal Name Description Variable power supply for the processor cores, lowest level caches (LLC), ring interface, and home agent. It is provided by a VR12 compliant regulator. The output voltage of this supply is selected by the processor using the serial voltage ID (SVID) bus. Note: VCC has a Vboot setting of 0.0 V and is not included in the PWRGOOD indication.

VCC

VCC_SENSE VSS_VCC_SENSE VSA_SENSE VSS_VSA_SENSE VTTD_SENSE VSS_VTTD_SENSE

VCC_SENSE and VSS_VCC_SENSE provide an isolated, low impedance connection to the processor core power and ground. These signals must be connected to the voltage regulator feedback circuit, which insures the output voltage (that is, processor voltage) remains within specification. VSA_SENSE and VSS_VSA_SENSE provide an isolated, low impedance connection to the processor system agent (VSA) power plane. These signals must be connected to the voltage regulator feedback circuit, which insures the output voltage (that is, processor voltage) remains within specification. VTTD_SENSE and VSS_VTTD_SENSE provide an isolated, low impedance connection to the processor I/O power plane. These signals must be connected to the voltage regulator feedback circuit, which insures the output voltage (that is, processor voltage) remains within specification. Power supply for the processor system memory interface. Provided by two VR12 compliant regulators or two non-VR12 voltage regulators (simple switching VRs for example). VCCD_01 and VCCD_23 are used for memory channels 0, 1 & 2, 3 respectively. VCCD_01 and VCCD_23 will also be referred to as VCCD. VCCD is generic for VCCD_01, VCCD_23. Note: The processor must be provided VCCD_01 and VCCD_23 for proper operation, even in configurations where no memory is populated. A VR12.0 controller is recommended, but not required.

VCCD_01 and VCCD_23

VCCPLL

Fixed power supply (1.8 V) for the processor phased lock loop (PLL). Variable power supply for the processor system agent units. These include logic (non-I/O) for the integrated I/O controller, the integrated memory controller (iMC), and the Power Control Unit (PCU). The output voltage of this supply is selected by the processor, using the serial voltage ID (SVID) bus. Note: VSA has a Vboot setting of 0.9 V.

VSA

VSS VTTA VTTD

Processor ground node. Combined fixed analog and digital power supply for I/O sections of Direct Media Interface Gen 2 (DMI2) interface and PCI Express* interface. Will also be referred to as VTT.

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7.1

Electrical Specifications
Processor Signaling
The processor includes 2011 lands that use various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups. These include DDR3 (Reference Clock, Command, Control, and Data), PCI Express*, DMI2, Platform Environmental Control Interface (PECI), System Reference Clock, SMBus, JTAG and Test Access Port (TAP), SVID Interface, Processor Asynchronous Sideband, Miscellaneous, and Power/Other signals. Refer to Table 7-5 for details. Intel strongly recommends performing analog simulations of all interfaces. Refer to Section 1.7, Related Documents for signal integrity model availability.

7.1.1

System Memory Interface Signal Groups

The system memory interface uses DDR3 technology that consists of numerous signal groups. These groups include Reference Clocks, Command Signals, Control Signals, and Data Signals. Each group consists of numerous signals that may use various signaling technologies. Refer to Table 7-5 for further details. Throughout this chapter, the system memory interface maybe referred to as DDR3.

7.1.2

PCI Express* 3.0 Signals

The PCI Express Signal Group consists of PCI Express* ports 1, 2, and 3, and PCI Express miscellaneous signals. Refer to Table 7-5 for further details.

7.1.3

DMI2/PCI Express* Signals

The Direct Media Interface (DMI2) Gen 2 sends and receives packets and/or commands to the PCH. The DMI2 is an extension of the standard PCI Express Specification. The DMI2/PCI Express Signals consist of DMI2 receive and transmit input/output signals and a control signal. Refer to Table 7-5 for further details.

7.1.4

Platform Environmental Control Interface (PECI)

PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature. Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read processor temperature, perform processor manageability functions, and manage processor interface tuning and diagnostics. Refer to Section 2.4, Platform Environment Control Interface (PECI) for processor specific implementation details for PECI. Refer to the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, Related Documents) for additional details regarding PECI and for a list of supported PECI commands. The PECI interface operates at a nominal voltage set by VTTD. The set of DC electrical specifications shown in Table 7-13 is used with devices normally operating from a VTTD interface supply.

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7.1.4.1

Input Device Hysteresis

The PECI client and host input buffers must use a Schmitt-triggered input design for improved noise immunity. Refer to Figure 7-1 and Table 7-13.

Figure 7-1.

Input Device Hysteresis

VTTD Maximum VP Minimum VP Minimum Hysteresis Maximum VN Minimum VN PECI Ground PECI Low Range Valid Input Signal Range PECI High Range

7.1.5

System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)

The processor core, processor uncore, PCI Express*, and DDR3 memory interface frequencies are generated from BCLK{0/1}_DP and BCLK{0/1}_DN signals. The processor maximum core frequency and DDR memory frequency are set during manufacturing. It is possible to override the processor core frequency setting using software. This permits operation at lower core frequencies than the factory set maximum core frequency. The processor core frequency is configured during reset by using values stored within the device during manufacturing. The stored value sets the lowest core multiplier at which the particular processor can operate. If higher speeds are desired, the appropriate ratio can be configured using the IA32_PERF_CTL MSR (MSR 199h); Bits 15:0. Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP, BCLK{0/1}_DN inputs are provided in Table 7-14.

7.1.5.1

PLL Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to Table 7-9 and Table 7-10 for DC specifications.

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7.1.6

JTAG and Test Access Port (TAP) Signals

Due to the voltage levels supported by other components in the JTAG and Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Two copies of each signal may be required with each driving a different voltage level.

7.1.7

Processor Sideband Signals

The processor includes asynchronous sideband signals that provide asynchronous input, output or I/O signals between the processor and the platform or Platform Controller Hub. Details can be found in Table 7-5. All processor Asynchronous Sideband signals are required to be asserted/deasserted for a defined number of BCLKs in order for the processor to recognize the proper signal state. These are outlined in Table 7-18 (DC specifications).

7.1.8

Power, Ground and Sense Signals

Processors also include various other signals including power/ground and sense points. Details can be found in Table 7-5.

7.1.8.1

Power and Ground Lands

All VCC, VCCPLL, VSA, VCCD, VTTA, and VTTD lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane. For clean on-chip power distribution, processors include lands for all required voltage supplies. These are listed in Table 7-1

Table 7-1.

Power and Ground Lands

Power and Ground Lands VCC Comments Each VCC land must be supplied with the voltage determined by the SVID Bus signals. Table 7-3 defines the voltage level associated with each core SVID pattern. Note: VCC has a VBOOT setting of 0.0 V. Each VCCPLL land is connected to a 1.80 V supply, power the Phase Lock Loop (PLL) clock generation circuitry. An on-die PLL filter solution is implemented within the processor. Each VCCD land is connected to a 1.50 V supply to provide power to the processor DDR3 interface. These supplies also power the DDR3 memory subsystem. VCCD may be controlled by the SVID Bus using a VR12 controller and or a non-VR12 regulator may be used. VCCD is the generic term for VCCD_01, VCCD_23. VTTA lands must be supplied by a fixed 1.05 V supply. VTTD lands must be supplied by a fixed 1.05 V supply. Each VSA land must be supplied with the voltage determined by the SVID Bus signals, typically set at 0.85 V. VSA has a VBOOT setting of 0.9 V. Ground

VCCPLL VCCD_01 VCCD_23 VTTA VTTD VSA VSS

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7.1.8.2

Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Large electrolytic bulk capacitors (CBULK), help maintain the output voltage during current transients; for example, coming out of an idle condition. Care must be taken in the baseboard design to ensure that the voltages provided to the processor remains within the specifications listed in Table 7-9. Failure to do so can result in timing violations or reduced lifetime of the processor.

7.1.8.3

Voltage Identification (VID)

The Voltage Identification (VID) specification for the VCC, VSA, and optionally the VCCD voltage are defined by the VR12/IMVP7 Pulse Width Modulation (PWM) Specification. The reference voltage or the VID setting is set using the SVID communication bus between the processor and the voltage regulator controller chip. The VID setting is the nominal voltage to be delivered to the processor VCC, VSA, and the VCCD lands. Table 7-3 specifies the reference voltage level corresponding to the VID value transmitted over serial VID. The VID codes will change due to temperature and/or current load changes to minimize the power and to maximize the performance of the part. The specifications are set so that a voltage regulator can operate with all supported frequencies. Individual processor VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings. The processor uses voltage identification signals to support automatic selection of VCC, VSA, and if desired the VCCD power supply voltages. If the processor socket is empty (SKTOCC_N high), or a not supported response is received from the SVID bus, then the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself or not power on. Vout MAX register (30h) is programmed by the processor to set the maximum supported VID code and if the programmed VID code is higher than the VID supported by the VR, then VR will respond with a not supported acknowledgement.

7.1.8.3.1

SVID Commands The processor provides the ability to operate while transitioning to a new VID and its associated processor core voltage. This is represented by a DC shift in the loadline. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target voltage. Transitions above the maximum specified VID are not supported. The processor supports the following VR commands: SetVID_fast (20 mV/s for VCC, 10m V/s for VCC/VSA/VCCD), SetVID_slow (5m V/s for VCC, 2.5 mV/s for VCC/VSA/VCCD), and Slew Rate Decay (downward voltage only and its a function of the output capacitances time constant) commands. Table 7-3 and Table 7-17 includes SVID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 7-8. The VR used must be capable of regulating its output to the value defined by the new VID. Power source characteristics must be ensured to be stable whenever the supply to the voltage regulator is stable.

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7.1.8.3.2

SetVID Fast Command The SetVID-fast command contains the target VID in the payload byte. The range of voltage is defined in the VID table. The VR should ramp to the new VID setting with a fast slew rate as defined in the slew rate data register; typically 10 to 20 mV/us depending on platform, voltage rail, and the amount of decoupling capacitance. The SetVID-fast command is preemptive, the VR interrupts its current processes and moves to the new VID. The SetVID-fast command operates on 1 VR address at a time. This command is used in the processor for package C6 fast exit and entry.

7.1.8.3.3

SetVID Slow The SetVID-slow command contains the target VID in the payload byte. The range of voltage is defined in the VID table. The VR should ramp to the new VID setting with a slow slew rate as defined in the slow slew rate data register. The SetVID_Slow is 1/4 slower than the SetVID_fast slew rate. The SetVID-slow command is preemptive, the VR interrupts its current processes and moves to the new VID. This is the instruction used for normal P-state voltage change. This command is used in the processor for the Intel Enhanced SpeedStep Technology transitions.

7.1.8.3.4

SetVID Decay The SetVID-Decay command is the slowest of the DVID transitions. It is only used for VID down transitions. The VR does not control the slew rate, the output voltage declines with the output load current only. The SetVID-Decay command is preemptive; that is, the VR interrupts its current processes and moves to the new VID.

7.1.8.3.5

SVID Power State Functions SetPS The processor has three power state functions and these will be set seamlessly using the SVID bus using the SetPS command. Based on the power state command, the SetPS commands sends information to VR controller to configure the VR to improve efficiency, especially at light loads. For example, typical power states are: PS(00h): Represents full power or active mode PS(01h): Represents a light load 5 A to 20 A PS(02h): Represents a very light load <5 A The VR may change its configuration to meet the processors power needs with greater efficiency. For example, it may reduce the number of active phases, transition from CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode, reduce the switching frequency or pulse skip, or change to asynchronous regulation. For example, typical power states are 00h = run in normal mode; a command of 01h = shed phases mode, and an 02h = pulse skip. The VR may reduce the number of active phases from PS(00h) to PS(01h) or PS(02h) for example. There are multiple VR design schemes that can be used to maintain a greater efficiency in these different power states, please work with your VR controller suppliers for optimizations. The SetPS command sends a byte that is encoded as to what power state the VR should transition to.

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If a power state is not supported by the controller, the slave should acknowledge with command rejected (11b) If the VR is in a low power state and receives a SetVID command moving the VID up, then the VR exits the low power state to normal mode (PS0) to move the voltage up as fast as possible. The processor must re-issue low power state (PS1, PS2, or PS3) command if it is in a low current condition at the new higher voltage. See Figure 7-2 for VR power state transitions. Figure 7-2. VR Power-State Transitions

PS0

PS1

PS2

PS3

7.1.8.3.6

SVID Voltage Rail Addressing The processor addresses 4 different voltage rail control segments within VR12 (VCC, VCCD_01, VCCD_23, and VSA). The SVID data packet contains a 4-bit addressing code.

Table 7-2.

SVID Address Usage

PWM Address (HEX) 00 01 02 03 04 05 Processor Vcc Vsa VCCD_01 +1 not used VCCD_23 +1 not used

Notes: 1. Check with VR vendors for determining the physical address assignment method for their controllers. 2. VR addressing is assigned on a per voltage rail basis. 3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase count. 4. For future platform flexibility, the VR controller should include an address offset, as shown with +1 not used.

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Table 7-3.
HEX 00 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 Vcc 0.00000 0.50000 0.50500 0.51000 0.51500 0.52000 0.52500 0.53000 0.53500 0.54000 0.54500 0.55000 0.55500 0.56000 0.56500 0.57000 0.57500 0.58000 0.58500 0.59000 0.59500 0.60000 0.60500 0.61000 0.61500 0.62000 0.62500 0.63000 0.63500 0.64000 0.64500 0.65000 0.65500 0.66000 0.66500

Voltage Identification Definition

HEX 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 Vcc & Vsa 0.67000 0.67500 0.68000 0.68500 0.69000 0.69500 0.70000 0.70500 0.71000 0.71500 0.72000 0.72500 0.73000 0.73500 0.74000 0.74500 0.75000 0.75500 0.76000 0.76500 0.77000 0.77500 0.78000 0.78500 0.79000 0.79500 0.80000 0.80500 0.81000 0.81500 0.82000 0.82500 0.83000 0.83500 0.84000 HEX 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A Vcc & Vsa 0.84500 0.85000 0.85500 0.86000 0.86500 0.87000 0.87500 0.88000 0.88500 0.89000 0.89500 0.90000 0.90500 0.91000 0.91500 0.92000 0.92500 0.93000 0.93500 0.94000 0.94500 0.95000 0.95500 0.96000 0.96500 0.97000 0.97500 0.98000 0.98500 0.99000 0.99500 1.00000 1.00500 1.01000 1.01500 HEX 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD Vcc & Vsa 1.02000 1.02500 1.03000 1.03500 1.04000 1.04500 1.05000 1.05500 1.06000 1.06500 1.07000 1.07500 1.08000 1.08500 1.09000 1.09500 1.10000 1.10500 1.11000 1.11500 1.12000 1.12500 1.13000 1.13500 1.14000 1.14500 1.15000 1.15500 1.16000 1.16500 1.17000 1.17500 1.18000 1.18500 1.19000 HEX BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 Vcc & Vsa 1.19500 1.20000 1.20500 1.21000 1.21500 1.22000 1.22500 1.23000 1.23500 1.24000 1.24500 1.25000 1.25500 1.26000 1.26500 1.27000 1.27500 1.28000 1.28500 1.29000 1.29500 1.30000 1.30500 1.31000 1.31500 1.32000 1.32500 1.33000 1.33500 1.34000 1.34500 1.35000 1.35500 1.36000 1.36500 HEX E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Vcc 1.37000 1.37500 1.38000 1.38500 1.39000 1.39500 1.40000 1.40500 1.41000 1.41500 1.42000 1.42500 1.43000 1.43500 1.44000 1.44500 1.45000 1.45500 1.46000 1.46500 1.47000 1.47500 1.48000 1.48500 1.49000 1.49500 1.50000 1.50500 1.51000 1.51500 1.52000

Notes: 1. 00h = Off State 2. VID Range HEX 0132 are not used by the processor. 3. For VID Ranges supported, see Table 7-9 4. VCCD is a fixed voltage of 1.5 V.

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7.1.9

Reserved or Unused Signals

All Reserved (RSVD) signals must not be connected. Connection of these signals to VCC, VTTA, VTTD, VCCD, VCCPLL, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 8, "Processor Land Listing," for a land listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may interfere with some Test Access Port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability.

7.2

Signal Group Summary

Signals are grouped by buffer type and similar characteristics as listed in Table 7-4. The buffer type indicates which signaling technology and specifications apply to the signals.

Table 7-4.

Signal Description Buffer Types

Signal Analog Asynchronous1 CMOS DDR3 DMI2 Open Drain CMOS PCI Express* Reference SSTL Notes: 1. Qualifier for a buffer type. Description Analog reference or output. May be used as a threshold voltage or for buffer compensation Signal has no timing relationship with any system reference clock. CMOS buffers: 1.05 V or 1.5 V tolerant DDR3 buffers: 1.5 V tolerant Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express* 2.0 and 1.0 Signaling Environment AC Specifications. Open Drain CMOS (ODCMOS) buffers: 1.05 V tolerant PCI Express* interface signals. These signals are compatible with PCI Express 3.0 Signalling Environment AC Specifications and are AC coupled. The buffers are not 3.3-V tolerant. Refer to the PCIe specification. Voltage reference signal. Source Series Terminated Logic. (JEDEC SSTL_15)

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Table 7-5.

Signal Groups (Sheet 1 of 3)

Differential/Single Ended DDR3 Reference Clocks2 Differential SSTL Output DDR{0/1/2/3}_CLK_D[N/P][3:0] Buffer Type Signals1

DDR3 Command Signals2 DDR{0/1/2/3}_BA[2:0] DDR{0/1/2/3}_CAS_N DDR{0/1/2/3}_MA[15:00] DDR{0/1/2/3}_MA_PAR DDR{0/1/2/3}_RAS_N DDR{0/1/2/3}_WE_N DDR_RESET_C{01/23}_N

Single ended

SSTL Output

CMOS1.5v Output DDR3 Control Signals2

CMOS1.5v Output Single ended Reference Output Reference Input DDR3 Data Signals2 Differential Single ended SSTL Input/Output SSTL Input/Output

DDR{0/1/2/3}_CS_N[1:0] DDR{0/1/2/3}_CS_N[5:4] DDR{0/1/2/3}_ODT[3:0] DDR{0/1/2/3}_CKE[3:0] DDR_VREFDQTX_C{01/23} DDR_VREFDQRX_C{01/23} DDR{01/23}_RCOMP[2:0]

DDR{0/1/2/3}_DQS_D[N/P][08:00] DDR{0/1/2/3}_DQ[63:00] DDR{01/2/3}_ECC[7:0]3

DDR3 Miscellaneous Signals2 Single ended CMOS1.5v Input DRAM_PWR_OK_C{01/23}

PCI Express* Port 1, 2, & 3 Signals PE1A_RX_D[N/P][3:0] PE1B_RX_D[N/P][7:4] PE2A_RX_D[N/P][3:0] PE2B_RX_D[N/P][7:4] PE2C_RX_D[N/P][11:8] PE2D_RX_D[N/P][15:12] PE3A_RX_D[N/P][3:0] PE3B_RX_D[N/P][7:4] PE3C_RX_D[N/P][11:8] PE3D_RX_D[N/P][15:12] PE1A_TX_D[N/P][3:0] PE1B_TX_D[N/P][7:4] PE2A_TX_D[N/P][3:0] PE2B_TX_D[N/P][7:4] PE2C_TX_D[N/P][11:8] PE2D_TX_D[N/P][15:12] PE3A_TX_D[N/P][3:0] PE3B_TX_D[N/P][7:4] PE3C_TX_D[N/P][11:8] PE3D_TX_D[N/P][15:12]

Differential

PCI Express* Input

Differential

PCI Express* Output

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Table 7-5.

Signal Groups (Sheet 2 of 3)

Differential/Single Ended Buffer Type Signals1

PCI Express* Miscellaneous Signals Analog Input Single ended Reference Input/Output PE_RBIAS_SENSE PE_RBIAS PE_VREF_CAP

DMI2/PCI Express* Signals Differential DMI2 Input DMI2 Output DMI_RX_D[N/P][3:0] DMI_TX_D[N/P][3:0]

Platform Environmental Control Interface (PECI) Single ended PECI PECI

System Reference Clock (BCLK{0/1}) Differential SMBus Single ended JTAG & TAP Signals CMOS1.05v Input CMOS1.05v Input/Output Single ended Open Drain CMOS Input/Output CMOS1.05v Output Open Drain CMOS Output Serial VID Interface (SVID) Signals CMOS1.05v Input Single ended Open Drain CMOS Input/Output Open Drain CMOS Output Processor Asynchronous Sideband Signals CMOS1.05v Input PWRGOOD PMSYNC RESET_N CAT_ERR_N CPU_ONLY_RESET MEM_HOT_C{01/23}_N PROCHOT_N THERMTRIP_N SVIDALERT_N SVIDDATA SVIDCLK TCK, TDI, TMS, TRST_N PREQ_N BPM_N[7:0] EAR_N PRDY_N TDO Open Drain CMOS Input/Output DDR_SCL_C{01/23} DDR_SDA_C{01/23} CMOS1.05v Input BCLK{0/1}_D[N/P]

Single ended

Open Drain CMOS Input/Output Open Drain CMOS Output

Miscellaneous Signals Single ended N/A CMOS1.05v Input Output Analog Input Analog Input/Output BIST_ENABLE BCLK_SELECT[1:0] PROC_SEL_N SKTOCC_N CORE_RBIAS_SENSE CORE_RBIAS

Single ended

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Table 7-5.

Signal Groups (Sheet 3 of 3)

Differential/Single Ended Power/Other Signals Power / Ground VCC, VTTA, VTTD, VCCD_01, VCCD_23,VCCPLL, VSA and VSS VCC_SENSE VSS_VCC_SENSE VSS_VTTD_SENSE VTTD_SENSE VSA_SENSE VSS_VSA_SENSE Buffer Type Signals1

Sense Points

Notes: 1. 2. 3. Refer to Chapter 6, "Signal Descriptions," for signal description details. DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channel 1, DDR3 Channel 2, and DDR3 Channel 3. ECC DIMMs are not supported on the processor; thus, these signals are not used.

Table 7-6.

Signals with On-Die Termination

Signal Name BCLK_SELECT[1:0] BIST_ENABLE EAR_N Pull Up /Pull Down Pull up Pull Up Pull Up Rail VTT VTT VTT Value 2K 2K 2K Units Ohm Ohm Ohm 1 Notes

Notes: 1. Refer to Table 7-16 for details on the RON (Buffer on Resistance) value for this signal.

7.3

Power-On Configuration (POC) Options

Several configuration options can be configured by hardware. The processor samples its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these options, please refer to Table 7-7. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset transition of the latching signal (RESET_N or PWRGOOD).

Table 7-7.

Power-On Configuration Option Lands

Configuration Option BCLK input select Execute BIST (Built-In Self Test) Power-up Sequence Halt for ITP configuration Notes: 1. BIST_ENABLE is sampled at RESET_N de-assertion. 2. This signal is sampled at PWRGOOD assertion. Land Name BCLK_SELECT[1:0] BIST_ENABLE EAR_N 1 2 Notes

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7.4

Absolute Maximum and Minimum Ratings

Table 7-8 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits (but within the absolute maximum and minimum ratings) the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. Although the processor contains protective circuitry to resist damage from ElectroStatic Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields.

Table 7-8.

Processor Absolute Minimum and Maximum Ratings

Symbol VCC VCCPLL VCCD VSA VTTA VTTD Parameter Processor core voltage with respect to Vss Processor PLL voltage with respect to Vss Processor IO supply voltage for DDR3 with respect to Vss Processor SA voltage with respect to Vss Processor analog IO voltage with respect to Vss Min -0.3 -0.3 -0.3 -0.3 -0.3 Max 1.4 2.0 1.85 1.4 1.4 Unit V V V V V Notes 1 1 1 1 1

Notes: 1. For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must be satisfied.

7.4.1

Storage Conditions Specifications

Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored in a Moisture Barrier Bag. The storage condition specifications are included in the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, Related Documents).

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7.5

DC Specifications
DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting the thermal specifications as specified in the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, Related Documents), clock frequency, and input voltages. Care should be taken to read all notes associated with each specification.

7.5.1
Table 7-9.

Voltage and Current Specifications

Voltage Specification
Parameter VCC VID Range VCC Loadline Slope VCC Tolerance Band VCC Ripple PLL Voltage I/O Voltage for DDR3 Voltage Plane VCC VCC Vcc VCCPLL VCCD VTT VSA VSA 0.955*VCCPLL_TYP 0.95*VCCD_TYP 0.957*VTT_TYP 0.6 Min 0.6 0.8 15 5 1.8 1.5 1.05 0.965 1.045*VCCPLL_TYP 1.05*VCCD_TYP 1.043*VTT_TYP 1.20 Typ Max 1.35 Unit V m mV mV V V V V Notes1 2, 3, 18 3, 4, 7, 8, 12, 17 3, 4, 7, 8, 12, 17 3, 4, 7, 8, 12, 17 10, 11 11, 14, 15 3, 5, 9, 11 2, 3, 13, 18 3, 6, 16, 18

Symbol VCCVID VCCLL VCCTOB VCCRipple VCCPLL VCCD (VCCD_01, VCCD_23) VTT (VTTA,
VTTD)

VTT Uncore Voltage VSA VID Range VSA Tolerance Band (DC+AC+Ripple+Gro und Noise)

VSA_VID VSATOB

64

mV

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on pre-silicon characterization and will be updated as further data becomes available. 2. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different settings. 3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. 4. The VCC voltage specification requirements are measured across the remote sense pin pairs (VCC_SENSE and VSS_VCC_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe. 5. The VTTA, and VTTD voltage specification requirements are measured across the remote sense pin pairs (VTTD_SENSE and VSS_VTTD_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe. 6. The VSA voltage specification requirements are measured across the remote sense pin pairs (VSA_SENSE and VSS_VSA_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe. 7. The processor should not be subjected to any static VCC level that exceeds the VCC_MAX associated with any particular current. Failure to adhere to this specification can shorten processor lifetime. 8. Minimum VCC and maximum ICC are specified at the maximum processor temperature. Refer to the Thermal Mechanical Specification and Design Guide (see Section 1.7, Related Documents) for thermal specifications. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The processor is capable of drawing ICC_MAX for up to 10 ms.

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9. 10. 11. 12. 13. 14. 15.

16. 17. 18.

The processor should not be subjected to any static VTTA, VTTD level that exceeds the VTT_MAX associated with any particular current. Failure to adhere to this specification can shorten processor lifetime. Baseboard bandwidth is limited to 20 MHz. DC + AC + Ripple specification. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands. VSA_VID does not have a loadline, the output voltage is expected to be the VID value. VCCD tolerance at processor pins. Tolerance for VR at remote sense is 3.3%*VCCD. The VCCPLL, VCCD01, VCCD23 voltage specification requirements are measured across vias on the platform. Choose VCCPLL, VCCD01, or VCCD23 vias close to the socket and measure with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe. DC + AC + Ripple + Ground Noise specification. VCC has a Vboot setting of 0.0 V and is not included in the PWRGOOD indication. VSA has a Vboot setting of 0.9 V.

Table 7-10. Current (Icc_Max and Icc_TDC) Specification

Symbol ICC_MAX ICC_MAX ITT_MAX ISA_MAX Max. Processor Current: (TDP - 130W) VCC VTTA/VTTD VSA VCCD_01 VCCD_23 VCCPLL 150 24 24 4 4 2 165 24 24 4 4 2 A A A A A A Parameter Voltage Plane 4-Core Max 6-Core Max Unit Notes1

ICCD_01_MAX ICCD_23_MAX ICCPLL_MAX ICC_TDC ICC_TDC ITT_TDC ISA_TDC Thermal Design Current: (TDP - 130 W)

4, 5

ICCD_01_TDC ICCD_23_TDC ICCPLL_TDC ICCD_S3 DDR3 System Memory Interface Supply Current in Standby State

VCC VTTA/VTTD VSA VCCD_01 VCCD_23 VCCPLL VCCD_01 VCCD_23

115 20 20 3 3 2 TBD

135 20 20 3 3 2 TBD

A A A A A A A

2, 5

3, 4

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on pre-silicon characterization and will be updated as further data becomes available. 2. ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used for the voltage regulator thermal assessment. The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion. 3. Specification is at TCASE = 50 C. Characterized by design (not tested). 4. ICCD_01_MAX and ICCD_23_MAX refers only to the processors current draw and does not account for the current consumption by the memory devices. 5. Minimum VCC and maximum ICC are specified at the maximum processor temperature. Refer to the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, Related Documents) for thermal specifications. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The processor is capable of drawing ICC_MAX for up to 10 ms.

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7.5.2

Die Voltage Validation

Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 7-11 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.

7.5.2.1

VCC Overshoot Specifications

The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_VCC_SENSE lands.

Table 7-11. VCC Overshoot Specifications

Symbol VOS_MAX TOS_MAX Parameter Magnitude of VCC overshoot above VID Time duration of VCC overshoot above VccMAX value at the new lighter load Min Max 65 25 Units mV ms Figure 7-3 7-3 Notes

Figure 7-3.

VCC Overshoot Example Waveform

VID + VOS_MAX

VOS_MAX

Voltage [V]

VccMAX (I1) TOS_MAX

10

15

20

25

Time [us]

Notes: 1. VOS is the measured overshoot voltage. 2. TOS_MAX is the measured time duration above VccMAX(I1). 3. Istep: Load Release Current Step, for example, I2 to I1, where I2 > I1. 4. VccMAX(I1) = VID - I1*RLL + 15 mV

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7.5.3

Signal DC Specifications
DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature (TCASE specified in the processor Thermal Mechanical Specification and Design Guide; see Section 1.7, Related Documents), clock frequency, and input voltages. Care should be taken to read all notes associated with each specification.

Table 7-12. DDR3 Signal DC Specifications

Symbol IIL Data Signals VIL VIH RON Data ODT Input Low Voltage Input High Voltage DDR3 Data Buffer On Resistance On-Die Termination for Data Signals 0.57*VCCD 21 45 90 31 55 110 0.43*VCCD V V 2, 3 2, 4, 5 6 8 Parameter Input Leakage Current Min -500 Typ Max +500 Units uA Notes1 10

Reference Clock Signals, Command, and Data Signals VOL VOH Output Low Voltage Output High Voltage (VCCD/ 2)* (RON /(RON+RVTT_TERM)) VCCD ((VCCD/ 2)* (RON/(RON+RVTT_TERM)) V V 2, 7 2, 5, 7

Reference Clock Signal RON Command Signals RON RON VOL_CMOS1.5v VOH_CMOS1.5v IIL_CMOS1.5v Control Signals RON DDR01_RCOMP[0] DDR01_RCOMP[1] DDR01_RCOMP[2] DDR23_RCOMP[0] DDR23_RCOMP[1] DDR23_RCOMP[2] DDR3 Control Buffer On Resistance COMP Resistance COMP Resistance COMP Resistance COMP Resistance COMP Resistance COMP Resistance 21 128.7 25.839 198 128.7 25.839 198 130 26.1 200 130 26.1 200 31 131.3 26.361 202 131.3 26.361 202 6 9, 12 9, 12 9, 12 9, 12 9, 12 9, 12 DDR3 Command Buffer On Resistance DDR3 Reset Buffer On Resistance Output Low Voltage, Signals DDR_RESET_ C{01/23}_N Output High Voltage, Signals DDR_RESET_ C{01/23}_N Input Leakage Current 16 25 0.9*VCCD -100 24 75 0.2*VCCD +100 V V uA 6 6 1, 2 1, 2 1, 2 DDR3 Clock Buffer On Resistance 21 31 6

Miscellaneous Signals VIL VIH Input Low Voltage DRAM_PWR_OK_C{01/23} Input High Voltage DRAM_PWR_OK_C{01/23} 0.55*VCCD +0.2 0.55*VCCD 0.2 V V 2, 3, 11, 13 2, 4, 5, 11, 13

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The voltage rail VCCD will be set to 1.50 V nominal. 3. VIL is the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 4. VIH is the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VCCD.

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6. 7. 8. 9. 10. 11. 12. 13.

This is the pull-down driver resistance. Reset drive does not have a termination. RVTT_TERM is the termination on the DIMM and not controlled by the processor. Refer to the applicable DIMM datasheet. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs. COMP resistance must be provided on the system board with 1% resistors. Input leakage current is specified for all DDR3 signals. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55+ 300 mV and -200 mV and the edge must be monotonic. The DDR01/23_RCOMP error tolerance is 5% from the compensated value. DRAM_PWR_OK_C{01/23}: Data Scrambling should be enabled for production environments. Disabling Data scrambling can be used for debug and testing purposes only. Running systems with Data Scrambling off will make the configuration out of specification. For details, refer to Volume 2 of the Datasheet.

Table 7-13. PECI DC Specifications

Symbol VIn VHysteresis VN VP ISOURCE ILeak+ ILeakCBus VNoise Definition and Conditions Input Voltage Range Hysteresis Negative-edge threshold voltage Positive-edge threshold voltage High level output source VOH = 0.75 * VTT High impedance state leakage to VTTD (Vleak = VOL) High impedance leakage to GND (Vleak = VOH) Bus capacitance per node Signal noise immunity above 300 MHz Min -0.150 0.100 * VTTD 0.275 * VTTD 0.550 * VTTD -6.0 N/A N/A N/A 0.100 * VTTD Max VTTD 0.500 * VTTD 0.725 * VTTD 50 25 10 N/A Units V V V V mA A A pF Vp-p 3 3 4,5 7-1 7-1 2 2 Figure Notes1

Notes: 1. VTTD supplies the PECI interface. PECI behavior does not affect VTTD min/max specification 2. It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and consequently, be able to drive its output within safe limits (-0.150 V to 0.275*VTTD for the low level and 0.725*VTTD to VTTD+0.150 V for the high level). 3. The leakage specification applies to powered devices on the PECI bus. 4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes. 5. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently limit the maximum bit rate at which the interface can operate.

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Table 7-14. System Reference Clock (BCLK{0/1}) DC Specifications

Symbol VBCLK_diff_ih VBCLK_diff_il Vcross (abs) Vcross(rel) Parameter Differential Input High Voltage Differential Input Low Voltage Absolute Crossing Point Relative Crossing Point Signal Differential Differential Single Ended Single Ended Single Ended Single Ended N/A N/A Min 0.150 0.250 0.250 + 0.5*(VHavg - 0.700) N/A Vcross - 0.1 0.9 Max N/A -0.150 0.550 0.550 + 0.5*(VHavg - 0.700) 0.140 Vcross + 0.1 1.50 1.1

Unit
V V V V V V A pF

Figure

Notes1

2, 4, 7 3, 4, 5 6

Vcross
VTH IIL Cpad

Range of Crossing Points Threshold Voltage Input Leakage Current Pad Capacitance

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP. 3. VHavg is the statistical average of the VH measured by the oscilloscope. 4. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 5. VHavg can be measured directly using Vtop on Agilent* and High on Tektronix oscilloscopes. 6. VCROSS is defined as the total variation of all crossing voltages as defined in Note 3. 7. The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP. 8. For Vin between 0 and Vih.

Table 7-15. SMBus DC Specifications

Symbol VIL VIH VOL VOH RON IL Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Buffer On Resistance Leakage Current, Signals DDR_SCL_C{1/23}, DDR_SDA_C{1/23} Parameter Min 0.7*VTT -100 Max 0.3*VTT 0.2*VTT VTT(max) 14 +100 Units V V V V A Notes

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Table 7-16. JTAG and TAP Signals DC Specifications

Symbol VIL VIH VOL VOH RON IIL IIL Input Low Voltage Input High Voltage Output Low Voltage (RTEST = 500 ohm) Output High Voltage (RTEST = 500 ohm) Buffer On Resistance Signals BPM[7:0], TDO, EAR_N Input Leakage Current, Signals PREQ_N, TCK, TDI, TMS, TRST_N Input Leakage Current, Signals BPM_N[7:0], TDO, EAR_N (RTEST = 50 ohm) Output Current, Signal PRDY_N (RTEST = 500 ohm) Input Edge Rate Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK, TDI, TMS, TRST_N Notes: 1. These are measured between VIL and VIH. Parameter Min 0.7*VTT 0.88*VTT -50 Max 0.3*VTT 0.12*VTT 14 +50 Units V V V V A Notes

+900

IO

-1.50

+1.50

mA

0.05

V/ns

Table 7-17. Serial VID Interface (SVID) DC Specifications

Symbol VTT VIL VIH VOH RON IIL IIL Parameter CPU I/O Voltage Input Low Voltage SVIDDATA, SVIDALERT_N Input High Voltage SVIDDATA, SVIDALERT_N Output High Voltage SVIDCLK, SVIDDATA Buffer On Resistance SVIDCLK, SVIDDATA Input Leakage Current, Signals SVIDCLK, SVIDDATA Input Leakage Current, Signal SVIDALERT_N Min VTT - 3% 0.7*VTT -500 Typ 1.05 Max VTT + 3% 0.3*VTT VTT(max) 14 +900 +500 Units V V V V A A 1 1 1 2 3 3 Notes

Notes: 1. VTT refers to instantaneous VTT. 2. Measured at 0.31*VTT 3. Vin between 0 V and VTT

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Table 7-18. Processor Asynchronous Sideband DC Specifications

Symbol Parameter Input Edge Rate Signals: CAT_ERR_N, MEM_HOT_C{01/23}_N, PMSYNC, PROCHOT_N, PWRGOOD, RESET_N CMOS1.05 V Signals VIL_CMOS1.05v VIH_CMOS1.05v VIL_MAX VIH_MIN VOL_CMOS1.05v VOH_CMOS1.05v IIL_CMOS1.05v IO_CMOS1.05v ANM_Rise ANM_Fall Input Low Voltage Input High Voltage Input Low Voltage Signal PWRGOOD Input High Voltage Signal PWRGOOD Output Low Voltage Output High Voltage Input Leakage Current Output Current (RTEST = 500 ohm) Non-Monotonicity Amplitude, Rising Edge Signal PWRGOOD Non-Monotonicity Amplitude, Falling Edge Signal PWRGOOD 0.7*VTT 0.640 0.88*VTT -50 -1.50 0.320 0.12*VTT +50 +1.50 0.135 0.165 0.3*VTT V V V V V V A mA V V 1,2 1,2 1,2,4 1,2,4 1,2 1,2 1,2 1,2 4 4 Min Max Units Notes

0.05

V/ns

Open Drain CMOS (ODCMOS) Signals VIL_ODCMOS VIH_ODCMOS VOH_ODCMOS IOL IOL Input Low Voltage Input High Voltage Output High Voltage, Signals CAT_ERR_N, ERROR_N[2:0], THERMTRIP_N, PROCHOT_N, CPU_ONLY_RESET Output Leakage Current, Signal: MEM_HOT_C{01/23}_N Output Leakage Current (RTEST = 50 ohm) Buffer On Resistance, Signals: CAT_ERR_N, CPU_ONLY_RESET, ERROR_N[2:0], MEM_HOT_C{01/23}_N, PROCHOT_N, THERMTRIP_N 0.7*VTT 0.3*VTT VTT(max) +100 +900 V V V 1,2 1,2 1,2

-100

A A

3 3

RON

14

1,2

Note: 1. This table applies to the miscellaneous signals specified in Table 7-5. 2. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 3. For Vin between 0 and VOH. 4. PWRGOOD Non Monotonicity duration (TNM) time is maximum 1.3 ns. 5. These are measured between VIL and VIH and the edge must be monotonic.

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Table 7-19. Miscellaneous Signals DC Specifications

Symbol PROC_SEL_N Signal VO_ABS_MAX IO SKTOCC_N Signal VO_ABS_MAX IOMAX Output Absolute Max Voltage Output Max Current 3.30 3.50 1 V mA Output Absolute Max Voltage Output Current 1.10 1.80 0 V A 1 1 Parameter Min Typical Max Units Notes

Notes: 1. 10 k pull-up and 4 k pull-down to a voltage divider from +3.3 V.

7.5.3.1

PCI Express* DC Specifications

The DC specifications for the PCI Express* are available in the PCI Express* Base Specification 3.0. This document will provide only the processor exceptions to the PCI Express* Base Specification 3.0.

7.5.3.2

DMI2/PCI Express* DC Specifications

The DC specifications for the DMI2/PCI Express* are available in the PCI Express Base Specification 2.0 and 1.0. This document will provide only the processor exceptions to the PCI Express Base Specification 2.0 and 1.0.

7.5.3.3

Reset and Miscellaneous Signal DC Specifications

For a power-on Reset, RESET_N must stay active for at least 3.5 milliseconds after VCC and BCLK have reached their proper specifications. RESET_N must not be kept asserted for more than 100 ms while PWRGOOD is asserted. RESET_N must be held asserted for at least 3.5 milliseconds before it is deasserted again. RESET_N must be held asserted before PWRGOOD is asserted. This signal does not have on-die termination and must be terminated on the system board.

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Processor Land Listing

This chapter provides sorted land list. Table 8-1 is a listing of all processor lands ordered alphabetically by land name. Table 8-2 is a listing of all processor lands ordered by land number.

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Table 8-1.
Land Name

Land Name (Sheet 1 of 45)

Land No. BD48 AJ55 CM44 CN43 BA45 AW45 AT48 AR43 AT44 AU43 AV44 BB44 AW43 BA43 AY44 CC51 CE53 CC53 CU51 AN43 CB18 AE27 CY42 U43 CW41 R43 BY16 J1 CN41 P42 CM28 CN27 CM20 CL29 CL19 CM18 CH20 CP18 CF24 CE23 CE21 CF22 CH24 CG23 CG21 ODCMOS CMOS1.5v CMOS1.5v ODCMOS ODCMOS ODCMOS ODCMOS DC DC DC DC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Buffer Type Direction CMOS CMOS CMOS CMOS CMOS CMOS CMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS Analog Analog I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O O O I/O I/O I/O I/O I I O O O O O O O O O O O O O O O O O

Table 8-1.
Land Name

Land Name (Sheet 2 of 45)

Land No. CH22 CN25 CH26 CG27 CF26 CC7 CD8 CK8 CL9 BY6 CA7 CJ7 CL7 CB2 CB4 CH4 CJ5 CA1 CA3 CG3 CG5 CK12 CM12 CK16 CM16 CG13 CL11 CJ15 CL15 BY10 BY12 CB12 CD12 BW9 CA9 CH10 CF10 CE31 CC31 CE35 CC35 CD30 CB30 CD34 CB34 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

BCLK_SELECT[0] BCLK_SELECT[1] BCLK0_DN BCLK0_DP BCLK1_DN BCLK1_DP BIST_ENABLE BPM_N[0] BPM_N[1] BPM_N[2] BPM_N[3] BPM_N[4] BPM_N[5] BPM_N[6] BPM_N[7] CAT_ERR_N CORE_RBIAS CORE_RBIAS_SENSE CORE_VREF_CAP CPU_ONLY_RESET DDR_RESET_C01_N DDR_RESET_C23_N DDR_SCL_C01 DDR_SCL_C23 DDR_SDA_C01 DDR_SDA_C23 DDR_VREFDQRX_C01 DDR_VREFDQRX_C23 DDR_VREFDQTX_C01 DDR_VREFDQTX_C23 DDR0_BA[0] DDR0_BA[1] DDR0_BA[2] DDR0_CAS_N DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CLK_DN[0] DDR0_CLK_DN[1] DDR0_CLK_DN[2] DDR0_CLK_DN[3] DDR0_CLK_DP[0] DDR0_CLK_DP[1] DDR0_CLK_DP[2]

DDR0_CLK_DP[3] DDR0_CS_N[0] DDR0_CS_N[1] DDR0_CS_N[4] DDR0_CS_N[5] DDR0_DQ[00] DDR0_DQ[01] DDR0_DQ[02] DDR0_DQ[03] DDR0_DQ[04] DDR0_DQ[05] DDR0_DQ[06] DDR0_DQ[07] DDR0_DQ[08] DDR0_DQ[09] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31] DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39]

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Table 8-1.
Land Name

Land Name (Sheet 3 of 45)

Land No. CL31 CJ31 CL35 CJ35 CK30 CH30 CK34 CH34 CB38 CD38 CE41 CD42 CC37 CE37 CC41 CB42 CH38 CK38 CH42 CK42 CJ37 CL37 CJ41 CL41 CG7 CE3 CH14 CD10 CE33 CL33 CB40 CH40 CE17 CH8 CF4 CK14 CE11 CC33 CJ33 CD40 CK40 CC17 CE15 CC15 CH18 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Table 8-1.
Land Name

Land Name (Sheet 4 of 45)

Land No. CF18 CB14 CD14 CG17 CK18 CL25 CR25 CG25 CK24 CM24 CL23 CN23 CM22 CK22 CN21 CK26 CL21 CK20 CG29 CG19 CN19 CE25 CE27 CH28 CF28 CE29 CN29 CA17 CC19 CB20 DB26 DC25 DF18 CY30 CT20 CU19 CY18 DA17 CV20 CV22 CY24 DA21 CY20 CY22 CV24 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Analog Analog Analog SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O I I I O O O O O O O O O O O O O O O

DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47] DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63] DDR0_DQS_DN[00] DDR0_DQS_DN[01] DDR0_DQS_DN[02] DDR0_DQS_DN[03] DDR0_DQS_DN[04] DDR0_DQS_DN[05] DDR0_DQS_DN[06] DDR0_DQS_DN[07] DDR0_DQS_DN[08] DDR0_DQS_DP[00] DDR0_DQS_DP[01] DDR0_DQS_DP[02] DDR0_DQS_DP[03] DDR0_DQS_DP[04] DDR0_DQS_DP[05] DDR0_DQS_DP[06] DDR0_DQS_DP[07] DDR0_DQS_DP[08] DDR0_ECC[0] DDR0_ECC[1] DDR0_ECC[2]

DDR0_ECC[3] DDR0_ECC[4] DDR0_ECC[5] DDR0_ECC[6] DDR0_ECC[7] DDR0_MA[00] DDR0_MA[01] DDR0_MA[02] DDR0_MA[03] DDR0_MA[04] DDR0_MA[05] DDR0_MA[06] DDR0_MA[07] DDR0_MA[08] DDR0_MA[09] DDR0_MA[10] DDR0_MA[11] DDR0_MA[12] DDR0_MA[13] DDR0_MA[14] DDR0_MA[15] DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3] DDR0_RAS_N DDR0_WE_N DDR01_RCOMP[0] DDR01_RCOMP[1] DDR01_RCOMP[2] DDR1_BA[0] DDR1_BA[1] DDR1_BA[2] DDR1_CAS_N DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CLK_DN[0] DDR1_CLK_DN[1] DDR1_CLK_DN[2] DDR1_CLK_DN[3] DDR1_CLK_DP[0] DDR1_CLK_DP[1] DDR1_CLK_DP[2]

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Table 8-1.
Land Name

Land Name (Sheet 5 of 45)

Land No. DC21 DB24 CU23 CU25 CT24 CP4 CP2 CV4 CY4 CM4 CL3 CV2 CW3 DA7 DC7 DC11 DE11 CY6 DB6 DB10 DF10 CR7 CU7 CT10 CP10 CP6 CT6 CW9 CV10 CR13 CU13 CR17 CU17 CT12 CV12 CT16 CV16 CT30 CP30 CT34 CP34 CU29 CR29 CU33 CR33 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Table 8-1.
Land Name

Land Name (Sheet 6 of 45)

Land No. DA33 DD32 DC35 DA35 DA31 CY32 DF34 DE35 CR37 CU37 CR41 CU41 CT36 CV36 CT40 CV40 DE37 DF38 DD40 DB40 DA37 DC37 DA39 DF40 CT4 DC9 CV8 CR15 CT32 CY34 CR39 DE39 DE15 CR3 DE9 CU9 CU15 CP32 DB34 CU39 DC39 DC15 DE13 DF14 DD16 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

DDR1_CLK_DP[3] DDR1_CS_N[0] DDR1_CS_N[1] DDR1_CS_N[4] DDR1_CS_N[5] DDR1_DQ[00] DDR1_DQ[01] DDR1_DQ[02] DDR1_DQ[03] DDR1_DQ[04] DDR1_DQ[05] DDR1_DQ[06] DDR1_DQ[07] DDR1_DQ[08] DDR1_DQ[09] DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15] DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31] DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39]

DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] DDR1_DQS_DN[00] DDR1_DQS_DN[01] DDR1_DQS_DN[02] DDR1_DQS_DN[03] DDR1_DQS_DN[04] DDR1_DQS_DN[05] DDR1_DQS_DN[06] DDR1_DQS_DN[07] DDR1_DQS_DN[08] DDR1_DQS_DP[00] DDR1_DQS_DP[01] DDR1_DQS_DP[02] DDR1_DQS_DP[03] DDR1_DQS_DP[04] DDR1_DQS_DP[05] DDR1_DQS_DP[06] DDR1_DQS_DP[07] DDR1_DQS_DP[08] DDR1_ECC[0] DDR1_ECC[1] DDR1_ECC[2]

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Table 8-1.
Land Name

Land Name (Sheet 7 of 45)

Land No. DB16 DA13 DC13 DA15 DF16 DC23 DE23 DF24 DA23 DB22 DF22 DE21 DF20 DB20 DA19 DF26 DE19 DC19 DB30 DB18 DC17 CT22 DA25 CY26 CV26 DB28 CV28 R17 L17 P24 T16 AA25 T26 U27 AD24 Y24 Y22 W21 W23 AB24 AB22 AA21 AA23 AB20 AE19 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O

Table 8-1.
Land Name

Land Name (Sheet 8 of 45)

Land No. AA19 P18 T40 V40 P36 T36 R41 U41 R37 U37 AE41 AD40 AA37 AC37 AC41 AA41 AF38 AE37 U33 R33 W29 U29 T34 P34 V30 T30 AC35 AE35 AE33 AF32 AA35 W35 AB32 AD32 AC13 AE13 AG11 AF10 AD14 AA13 AB10 AD10 V6 Y6 AF8 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

DDR1_ECC[3] DDR1_ECC[4] DDR1_ECC[5] DDR1_ECC[6] DDR1_ECC[7] DDR1_MA[00] DDR1_MA[01] DDR1_MA[02] DDR1_MA[03] DDR1_MA[04] DDR1_MA[05] DDR1_MA[06] DDR1_MA[07] DDR1_MA[08] DDR1_MA[09] DDR1_MA[10] DDR1_MA[11] DDR1_MA[12] DDR1_MA[13] DDR1_MA[14] DDR1_MA[15] DDR1_ODT[0] DDR1_ODT[1] DDR1_ODT[2] DDR1_ODT[3] DDR1_RAS_N DDR1_WE_N DDR2_BA[0] DDR2_BA[1] DDR2_BA[2] DDR2_CAS_N DDR2_CKE[0] DDR2_CKE[1] DDR2_CKE[2] DDR2_CKE[3] DDR2_CLK_DN[0] DDR2_CLK_DN[1] DDR2_CLK_DN[2] DDR2_CLK_DN[3] DDR2_CLK_DP[0] DDR2_CLK_DP[1] DDR2_CLK_DP[2] DDR2_CLK_DP[3] DDR2_CS_N[0] DDR2_CS_N[1]

DDR2_CS_N[4] DDR2_CS_N[5] DDR2_DQ[00] DDR2_DQ[01] DDR2_DQ[02] DDR2_DQ[03] DDR2_DQ[04] DDR2_DQ[05] DDR2_DQ[06] DDR2_DQ[07] DDR2_DQ[08] DDR2_DQ[09] DDR2_DQ[10] DDR2_DQ[11] DDR2_DQ[12] DDR2_DQ[13] DDR2_DQ[14] DDR2_DQ[15] DDR2_DQ[16] DDR2_DQ[17] DDR2_DQ[18] DDR2_DQ[19] DDR2_DQ[20] DDR2_DQ[21] DDR2_DQ[22] DDR2_DQ[23] DDR2_DQ[24] DDR2_DQ[25] DDR2_DQ[26] DDR2_DQ[27] DDR2_DQ[28] DDR2_DQ[29] DDR2_DQ[30] DDR2_DQ[31] DDR2_DQ[32] DDR2_DQ[33] DDR2_DQ[34] DDR2_DQ[35] DDR2_DQ[36] DDR2_DQ[37] DDR2_DQ[38] DDR2_DQ[39] DDR2_DQ[40] DDR2_DQ[41] DDR2_DQ[42]

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Table 8-1.
Land Name

Land Name (Sheet 9 of 45)

Land No. AG7 U7 W7 AD8 AE7 R13 U13 T10 V10 T14 V14 R9 U9 W3 Y4 AF4 AE5 U3 V4 AF2 AE3 T38 AD38 W31 AA33 AC11 AB8 U11 AC3 AB28 V38 AB38 U31 AC33 AE11 AC7 W11 AB4 AC27 AF30 AF28 Y26 AB26 AB30 AD30 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Table 8-1.
Land Name

Land Name (Sheet 10 of 45)

Land No. W27 AA27 AB18 R19 U19 T20 P20 U21 R21 P22 T22 R23 T18 U23 T24 R15 W25 U25 Y20 W19 AD18 Y18 U17 P16 U15 AC15 Y14 A17 E19 B24 B14 K24 M24 J25 N25 J23 J21 M20 K22 L23 L21 K20 M22 G19 J19 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Analog Analog Analog SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O O O O O O O O O O O O O O O O O O O O O O O I I I O O O O O O O O O O O O O O O O O O

DDR2_DQ[43] DDR2_DQ[44] DDR2_DQ[45] DDR2_DQ[46] DDR2_DQ[47] DDR2_DQ[48] DDR2_DQ[49] DDR2_DQ[50] DDR2_DQ[51] DDR2_DQ[52] DDR2_DQ[53] DDR2_DQ[54] DDR2_DQ[55] DDR2_DQ[56] DDR2_DQ[57] DDR2_DQ[58] DDR2_DQ[59] DDR2_DQ[60] DDR2_DQ[61] DDR2_DQ[62] DDR2_DQ[63] DDR2_DQS_DN[00] DDR2_DQS_DN[01] DDR2_DQS_DN[02] DDR2_DQS_DN[03] DDR2_DQS_DN[04] DDR2_DQS_DN[05] DDR2_DQS_DN[06] DDR2_DQS_DN[07] DDR2_DQS_DN[08] DDR2_DQS_DP[00] DDR2_DQS_DP[01] DDR2_DQS_DP[02] DDR2_DQS_DP[03] DDR2_DQS_DP[04] DDR2_DQS_DP[05] DDR2_DQS_DP[06] DDR2_DQS_DP[07] DDR2_DQS_DP[08] DDR2_ECC[0] DDR2_ECC[1] DDR2_ECC[2] DDR2_ECC[3] DDR2_ECC[4] DDR2_ECC[5]

DDR2_ECC[6] DDR2_ECC[7] DDR2_MA[00] DDR2_MA[01] DDR2_MA[02] DDR2_MA[03] DDR2_MA[04] DDR2_MA[05] DDR2_MA[06] DDR2_MA[07] DDR2_MA[08] DDR2_MA[09] DDR2_MA[10] DDR2_MA[11] DDR2_MA[12] DDR2_MA[13] DDR2_MA[14] DDR2_MA[15] DDR2_ODT[0] DDR2_ODT[1] DDR2_ODT[2] DDR2_ODT[3] DDR2_RAS_N DDR2_WE_N DDR23_RCOMP[0] DDR23_RCOMP[1] DDR23_RCOMP[2] DDR3_BA[0] DDR3_BA[1] DDR3_BA[2] DDR3_CAS_N DDR3_CKE[0] DDR3_CKE[1] DDR3_CKE[2] DDR3_CKE[3] DDR3_CLK_DN[0] DDR3_CLK_DN[1] DDR3_CLK_DN[2] DDR3_CLK_DN[3] DDR3_CLK_DP[0] DDR3_CLK_DP[1] DDR3_CLK_DP[2] DDR3_CLK_DP[3] DDR3_CS_N[0] DDR3_CS_N[1]

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Table 8-1.
Land Name

Land Name (Sheet 11 of 45)

Land No. K18 G17 B40 A39 C37 E37 F40 D40 F38 A37 N39 L39 L35 J35 M40 K40 K36 H36 A35 F34 D32 F32 E35 C35 A33 B32 M32 L31 M28 L27 L33 K32 N27 M26 D12 A11 C9 E9 F12 B12 F10 A9 J13 L13 J9 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Table 8-1.
Land Name

Land Name (Sheet 12 of 45)

Land No. L9 K14 M14 K10 M10 E7 F6 N7 P6 C7 D6 L7 M6 G3 H2 N3 P4 F4 H4 L1 M2 B38 L37 G33 P28 B10 L11 J7 L3 G27 D38 J37 E33 N29 D10 N11 K6 M4 E27 G29 J29 E25 C25 F30 H30 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

DDR3_CS_N[4] DDR3_CS_N[5] DDR3_DQ[00] DDR3_DQ[01] DDR3_DQ[02] DDR3_DQ[03] DDR3_DQ[04] DDR3_DQ[05] DDR3_DQ[06] DDR3_DQ[07] DDR3_DQ[08] DDR3_DQ[09] DDR3_DQ[10] DDR3_DQ[11] DDR3_DQ[12] DDR3_DQ[13] DDR3_DQ[14] DDR3_DQ[15] DDR3_DQ[16] DDR3_DQ[17] DDR3_DQ[18] DDR3_DQ[19] DDR3_DQ[20] DDR3_DQ[21] DDR3_DQ[22] DDR3_DQ[23] DDR3_DQ[24] DDR3_DQ[25] DDR3_DQ[26] DDR3_DQ[27] DDR3_DQ[28] DDR3_DQ[29] DDR3_DQ[30] DDR3_DQ[31] DDR3_DQ[32] DDR3_DQ[33] DDR3_DQ[34] DDR3_DQ[35] DDR3_DQ[36] DDR3_DQ[37] DDR3_DQ[38] DDR3_DQ[39] DDR3_DQ[40] DDR3_DQ[41] DDR3_DQ[42]

DDR3_DQ[43] DDR3_DQ[44] DDR3_DQ[45] DDR3_DQ[46] DDR3_DQ[47] DDR3_DQ[48] DDR3_DQ[49] DDR3_DQ[50] DDR3_DQ[51] DDR3_DQ[52] DDR3_DQ[53] DDR3_DQ[54] DDR3_DQ[55] DDR3_DQ[56] DDR3_DQ[57] DDR3_DQ[58] DDR3_DQ[59] DDR3_DQ[60] DDR3_DQ[61] DDR3_DQ[62] DDR3_DQ[63] DDR3_DQS_DN[00] DDR3_DQS_DN[01] DDR3_DQS_DN[02] DDR3_DQS_DN[03] DDR3_DQS_DN[04] DDR3_DQS_DN[05] DDR3_DQS_DN[06] DDR3_DQS_DN[07] DDR3_DQS_DN[08] DDR3_DQS_DP[00] DDR3_DQS_DP[01] DDR3_DQS_DP[02] DDR3_DQS_DP[03] DDR3_DQS_DP[04] DDR3_DQS_DP[05] DDR3_DQS_DP[06] DDR3_DQS_DP[07] DDR3_DQS_DP[08] DDR3_ECC[0] DDR3_ECC[1] DDR3_ECC[2] DDR3_ECC[3] DDR3_ECC[4] DDR3_ECC[5]

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Table 8-1.
Land Name

Land Name (Sheet 13 of 45)

Land No. F26 H26 A19 E21 F20 B20 D20 A21 F22 B22 D22 G23 D18 A23 E23 A13 D24 F24 L19 F18 E17 J17 B16 A15 E47 D48 E49 D50 C47 B48 C49 B50 D42 E43 D44 E45 B42 C43 B44 C45 CW17 L15 CH56 CB22 E13 Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX CMOS1.5v CMOS1.5v ODCMOS ODCMOS ODCMOS I/O I/O O O O O O O O O O O O O O O O O O O O O O O I I I I I I I I O O O O O O O O I I I/O I/O I/O

Table 8-1.
Land Name PE_RBIAS

Land Name (Sheet 14 of 45)

Land No. AH52 AF52 AJ43 E51 F52 F54 G55 C51 D52 D54 E55 K42 L43 K44 L45 H42 J43 H44 J45 L53 M54 L57 M56 J53 K54 J57 K56 K46 L47 K48 L49 H46 J47 H48 J49 N55 V54 V56 W55 L55 T54 T56 U55 AR49 AP50 Buffer Type Direction PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 I/O I I/O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O O

DDR3_ECC[6] DDR3_ECC[7] DDR3_MA[00] DDR3_MA[01] DDR3_MA[02] DDR3_MA[03] DDR3_MA[04] DDR3_MA[05] DDR3_MA[06] DDR3_MA[07] DDR3_MA[08] DDR3_MA[09] DDR3_MA[10] DDR3_MA[11] DDR3_MA[12] DDR3_MA[13] DDR3_MA[14] DDR3_MA[15] DDR3_ODT[0] DDR3_ODT[1] DDR3_ODT[2] DDR3_ODT[3] DDR3_RAS_N DDR3_WE_N DMI_RX_DN[0] DMI_RX_DN[1] DMI_RX_DN[2] DMI_RX_DN[3] DMI_RX_DP[0] DMI_RX_DP[1] DMI_RX_DP[2] DMI_RX_DP[3] DMI_TX_DN[0] DMI_TX_DN[1] DMI_TX_DN[2] DMI_TX_DN[3] DMI_TX_DP[0] DMI_TX_DP[1] DMI_TX_DP[2] DMI_TX_DP[3] DRAM_PWR_OK_C01 DRAM_PWR_OK_C23 EAR_N MEM_HOT_C01_N MEM_HOT_C23_N

PE_RBIAS_SENSE PE_VREF_CAP PE1A_RX_DN[0] PE1A_RX_DN[1] PE1A_RX_DN[2] PE1A_RX_DN[3] PE1A_RX_DP[0] PE1A_RX_DP[1] PE1A_RX_DP[2] PE1A_RX_DP[3] PE1A_TX_DN[0] PE1A_TX_DN[1] PE1A_TX_DN[2] PE1A_TX_DN[3] PE1A_TX_DP[0] PE1A_TX_DP[1] PE1A_TX_DP[2] PE1A_TX_DP[3] PE1B_RX_DN[4] PE1B_RX_DN[5] PE1B_RX_DN[6] PE1B_RX_DN[7] PE1B_RX_DP[4] PE1B_RX_DP[5] PE1B_RX_DP[6] PE1B_RX_DP[7] PE1B_TX_DN[4] PE1B_TX_DN[5] PE1B_TX_DN[6] PE1B_TX_DN[7] PE1B_TX_DP[4] PE1B_TX_DP[5] PE1B_TX_DP[6] PE1B_TX_DP[7] PE2A_RX_DN[0] PE2A_RX_DN[1] PE2A_RX_DN[2] PE2A_RX_DN[3] PE2A_RX_DP[0] PE2A_RX_DP[1] PE2A_RX_DP[2] PE2A_RX_DP[3] PE2A_TX_DN[0] PE2A_TX_DN[1]

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Table 8-1.
Land Name

Land Name (Sheet 15 of 45)

Land No. AR51 AP52 AN49 AM50 AN51 AM52 AD54 AD56 AE55 AF58 AB54 AB56 AC55 AE57 AJ53 AK54 AR53 AT54 AG53 AH54 AN53 AP54 AL57 AU57 AK56 AM58 AJ57 AR57 AH56 AK58 BB54 BA51 AY52 BA53 AY54 AW51 AV52 AW53 AV58 AT56 BA57 BB56 AT58 AP56 AY58 Buffer Type Direction PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I

Table 8-1.
Land Name

Land Name (Sheet 16 of 45)

Land No. AY56 AY50 BA49 AY48 BA47 AV50 AW49 AV48 AW47 AH44 AJ45 AH46 AC49 AF44 AG45 AF46 AA49 K50 L51 U47 T48 H50 J51 R47 P48 AB50 AB52 AC53 AC51 Y50 Y52 AA53 AA51 T52 U51 T50 U49 P52 R51 P50 R49 AH50 AJ49 AH48 AJ51 Buffer Type Direction PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I

PE2A_TX_DN[2] PE2A_TX_DN[3] PE2A_TX_DP[0] PE2A_TX_DP[1] PE2A_TX_DP[2] PE2A_TX_DP[3] PE2B_RX_DN[4] PE2B_RX_DN[5] PE2B_RX_DN[6] PE2B_RX_DN[7] PE2B_RX_DP[4] PE2B_RX_DP[5] PE2B_RX_DP[6] PE2B_RX_DP[7] PE2B_TX_DN[4] PE2B_TX_DN[5] PE2B_TX_DN[6] PE2B_TX_DN[7] PE2B_TX_DP[4] PE2B_TX_DP[5] PE2B_TX_DP[6] PE2B_TX_DP[7] PE2C_RX_DN[10] PE2C_RX_DN[11] PE2C_RX_DN[8] PE2C_RX_DN[9] PE2C_RX_DP[10] PE2C_RX_DP[11] PE2C_RX_DP[8] PE2C_RX_DP[9] PE2C_TX_DN[10] PE2C_TX_DN[11] PE2C_TX_DN[8] PE2C_TX_DN[9] PE2C_TX_DP[10] PE2C_TX_DP[11] PE2C_TX_DP[8] PE2C_TX_DP[9] PE2D_RX_DN[12] PE2D_RX_DN[13] PE2D_RX_DN[14] PE2D_RX_DN[15] PE2D_RX_DP[12] PE2D_RX_DP[13] PE2D_RX_DP[14]

PE2D_RX_DP[15] PE2D_TX_DN[12] PE2D_TX_DN[13] PE2D_TX_DN[14] PE2D_TX_DN[15] PE2D_TX_DP[12] PE2D_TX_DP[13] PE2D_TX_DP[14] PE2D_TX_DP[15] PE3A_RX_DN[0] PE3A_RX_DN[1] PE3A_RX_DN[2] PE3A_RX_DN[3] PE3A_RX_DP[0] PE3A_RX_DP[1] PE3A_RX_DP[2] PE3A_RX_DP[3] PE3A_TX_DN[0] PE3A_TX_DN[1] PE3A_TX_DN[2] PE3A_TX_DN[3] PE3A_TX_DP[0] PE3A_TX_DP[1] PE3A_TX_DP[2] PE3A_TX_DP[3] PE3B_RX_DN[4] PE3B_RX_DN[5] PE3B_RX_DN[6] PE3B_RX_DN[7] PE3B_RX_DP[4] PE3B_RX_DP[5] PE3B_RX_DP[6] PE3B_RX_DP[7] PE3B_TX_DN[4] PE3B_TX_DN[5] PE3B_TX_DN[6] PE3B_TX_DN[7] PE3B_TX_DP[4] PE3B_TX_DP[5] PE3B_TX_DP[6] PE3B_TX_DP[7] PE3C_RX_DN[10] PE3C_RX_DN[11] PE3C_RX_DN[8] PE3C_RX_DN[9]

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Table 8-1.
Land Name

Land Name (Sheet 17 of 45)

Land No. AF50 AG49 AF48 AG51 U45 AB46 T46 AC47 R45 Y46 P46 AA47 AJ47 AR47 AP46 AR45 AG47 AN47 AM46 AN45 AC45 AB44 AA43 P44 AA45 Y44 AC43 T44 BJ47 K52 R53 U53 AH42 BD52 BJ53 CK44 AK52 A53 AA15 AA17 AA7 AB12 AB16 AB34 AB40 ODCMOS CMOS CMOS Buffer Type Direction PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PECI CMOS CMOS CMOS I I I I O O O O O O O O I I I I I I I I O O O O O O O O I/O I O I/O O I/O I I

Table 8-1.
Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Land Name (Sheet 18 of 45)

Land No. AB48 AC29 AC39 AC5 AD12 AD16 AD20 AD22 AD28 AD4 AE21 AE23 AE25 AL47 AL55 AM44 AP48 AR55 AU55 AV46 AY46 B18 B34 B46 BC47 BC51 BD44 BD46 BD50 BD58 BE43 BE45 BE47 BE53 BE55 BE57 BF46 BF50 BF52 BF54 BF56 BF58 BG43 BG45 BG49 Buffer Type Direction

PE3C_RX_DP[10] PE3C_RX_DP[11] PE3C_RX_DP[8] PE3C_RX_DP[9] PE3C_TX_DN[10] PE3C_TX_DN[11] PE3C_TX_DN[8] PE3C_TX_DN[9] PE3C_TX_DP[10] PE3C_TX_DP[11] PE3C_TX_DP[8] PE3C_TX_DP[9] PE3D_RX_DN[12] PE3D_RX_DN[13] PE3D_RX_DN[14] PE3D_RX_DN[15] PE3D_RX_DP[12] PE3D_RX_DP[13] PE3D_RX_DP[14] PE3D_RX_DP[15] PE3D_TX_DN[12] PE3D_TX_DN[13] PE3D_TX_DN[14] PE3D_TX_DN[15] PE3D_TX_DP[12] PE3D_TX_DP[13] PE3D_TX_DP[14] PE3D_TX_DP[15] PECI PMSYNC PRDY_N PREQ_N PROC_SEL_N PROCHOT_N PWRGOOD RESET_N RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

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Table 8-1.
Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Land Name (Sheet 19 of 45)

Land No. BG51 BG53 BG55 BG57 BH44 BH46 BH50 BH52 BH54 BH56 BJ43 BJ45 BJ49 BJ51 BK44 BK58 BL43 BL45 BL53 BL55 BL57 BM44 BM46 BM48 BM50 BM52 BM54 BM56 BM58 BN47 BN49 BN51 BN53 BN55 BN57 BP44 BP46 BP48 BP50 BP52 BP54 BP56 BR43 BR47 BR49 Buffer Type Direction

Table 8-1.
Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Land Name (Sheet 20 of 45)

Land No. BR51 BT44 BT58 BU43 BU53 BU55 BU57 BV46 BV48 BV50 BV52 BV54 BV56 BV58 BW45 BW47 BW49 BW51 BW53 BW55 BW57 BY46 BY48 BY50 BY52 BY54 BY56 C53 CA45 CA47 CA49 CA51 CB10 CB24 CB26 CB28 CB32 CB54 CC11 CC21 CC23 CC25 CC27 CC39 CC5 Buffer Type Direction

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Table 8-1.
Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Land Name (Sheet 21 of 45)

Land No. CC55 CD16 CD32 CD4 CD44 CD46 CD48 CD50 CD52 CD54 CD56 CE19 CE39 CE43 CE45 CE47 CE49 CE51 CE55 CE7 CF16 CF20 CF44 CF46 CF48 CF50 CF52 CF54 CF56 CF8 CG11 CG45 CG47 CG49 CG51 CH32 CJ13 CJ39 CJ53 CJ55 CK28 CK32 CK46 CK48 CK50 Buffer Type Direction

Table 8-1.
Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Land Name (Sheet 22 of 45)

Land No. CK52 CK54 CK56 CL13 CL27 CL39 CL45 CL47 CL49 CL51 CL53 CL55 CM26 CM46 CM48 CM50 CM52 CM54 CM56 CN45 CN47 CN49 CN51 CP14 CP38 CP54 CP58 CP8 CR1 CR19 CR21 CR23 CR27 CR31 CR53 CR55 CR57 CT14 CT18 CT2 CT26 CT38 CT44 CT46 CT48 Buffer Type Direction

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Table 8-1.
Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Land Name (Sheet 23 of 45)

Land No. CT50 CT52 CT56 CT58 CT8 CU21 CU27 CU31 CU43 CU45 CU47 CU49 CU53 CU55 CU57 CV44 CV46 CV48 CV50 CV52 CV56 CW43 CW45 CW47 CW49 CY14 CY28 CY38 CY46 CY48 CY54 CY56 CY58 D14 D16 D34 D46 D56 DA27 DA29 DA53 DA55 DA57 DB14 DB38 Buffer Type Direction

Table 8-1.
Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Land Name (Sheet 24 of 45)

Land No. DB42 DB44 DB46 DB48 DB50 DB52 DB54 DB56 DB8 DC33 DC43 DC45 DC47 DC49 DC51 DC53 DC55 DD42 DD44 DD46 DD48 DD50 DD52 DD54 DD8 DE25 DE33 DE43 DE45 DE47 DE49 DE51 DE55 E11 E15 E39 E53 E57 F14 F16 F28 F46 F56 F58 G11 Buffer Type Direction

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Table 8-1.
Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SKTOCC_N

Land Name (Sheet 25 of 45)

Land No. G15 G21 G39 G7 H28 H56 H58 H6 J15 J3 K12 K16 K38 K4 K58 M12 M16 M18 M30 M38 M48 N31 R25 R27 T12 T32 U39 V12 V32 V52 W15 W17 W39 Y16 Y34 Y48 Y8 BU49 CR43 CB44 BR45 BY44 BW43 CA43 DB4 CMOS ODCMOS ODCMOS CMOS CMOS ODCMOS O I O I/O I I O O Buffer Type Direction

Table 8-1.
Land Name TEST1 TEST2 TEST3 TEST4

Land Name (Sheet 26 of 45)

Land No. CW1 F2 D4 BA55 AT50 BF48 BH48 BL47 BV44 CT54 AG19 AG25 AG27 AG29 AG31 AG33 AG35 AG37 AG39 AG41 AL1 AL11 AL13 AL15 AL17 AL3 AL5 AL7 AL9 AM10 AM12 AM14 AM16 AM2 AM4 AM6 AM8 AN1 AN11 AN13 AN15 AN17 AN3 AN5 AN7 CMOS Open Drain Open Drain ODCMOS CMOS CMOS PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Buffer Type Direction O O O I I I/O I/O O I I

TESTHI_AT50 TESTHI_BF48 TESTHI_BH48 THERMTRIP_N TMS TRST_N VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SVIDALERT_N SVIDCLK SVIDDATA TCK TDI TDO TEST0

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Table 8-1.
Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Land Name (Sheet 27 of 45)

Land No. AN9 AP10 AP12 AP14 AP16 AP2 AP4 AP6 AP8 AU1 AU11 AU13 AU15 AU17 AU3 AU5 AU7 AU9 AV10 AV12 AV14 AV16 AV2 AV4 AV6 AV8 AW1 AW11 AW13 AW15 AW17 AW3 AW5 AW7 AW9 AY10 AY12 AY14 AY16 AY2 AY4 AY6 AY8 BA1 BA11 Buffer Type Direction PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

Table 8-1.
Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Land Name (Sheet 28 of 45)

Land No. BA13 BA15 BA17 BA3 BA5 BA7 BA9 BB10 BB12 BB14 BB16 BB2 BB4 BB6 BB8 BE1 BE11 BE13 BE15 BE17 BE3 BE5 BE7 BE9 BF10 BF12 BF14 BF16 BF2 BF4 BF6 BF8 BG1 BG11 BG13 BG15 BG17 BG3 BG5 BG7 BG9 BH10 BH12 BH14 BH16 Buffer Type Direction PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

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Table 8-1.
Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Land Name (Sheet 29 of 45)

Land No. BH2 BH4 BH6 BH8 BJ1 BJ11 BJ13 BJ15 BJ17 BJ3 BJ5 BJ7 BJ9 BK10 BK12 BK14 BK16 BK2 BK4 BK6 BK8 BN1 BN11 BN13 BN15 BN17 BN3 BN5 BN7 BN9 BP10 BP12 BP14 BP16 BP2 BP4 BP6 BP8 BR1 BR11 BR13 BR15 BR17 BR3 BR5 Buffer Type Direction PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

Table 8-1.
Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_SENSE VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01

Land Name (Sheet 30 of 45)

Land No. BR7 BR9 BT10 BT12 BT14 BT16 BT2 BT4 BT6 BT8 BU1 BU11 BU13 BU15 BU17 BU3 BU5 BU7 BU9 BV10 BV12 BV14 BV16 BV2 BV4 BV6 BV8 BY18 BY26 BY28 BY30 BY32 BY34 BY36 BY38 BY40 CA25 CA29 BW3 CD20 CD22 CD24 CD26 CD28 CJ19 PWR PWR PWR PWR PWR PWR Buffer Type Direction PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR O

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Table 8-1.
Land Name VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23

Land Name (Sheet 31 of 45)

Land No. CJ21 CJ23 CJ25 CJ27 CP20 CP22 CP24 CP26 CP28 CW19 CW21 CW23 CW25 CW27 DD18 DD20 DD22 DD24 DD26 AC17 AC19 AC21 AC23 AC25 C15 C17 C19 C21 C23 G13 H16 H18 H20 H22 H24 N15 N17 N19 N21 N23 V16 V18 V20 V22 V24 Buffer Type Direction PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

Table 8-1.
Land Name VCCPLL VCCPLL VCCPLL VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA_SENSE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 32 of 45)

Land No. BY14 CA13 CA15 AE15 AE17 AF18 AG15 AG17 AH10 AH12 AH14 AH16 AH2 AH4 AH6 AH8 AJ1 AJ11 AJ13 AJ3 AJ5 AJ7 AJ9 B54 G43 G49 N45 N51 AG13 A41 A43 A45 A47 A49 A5 A51 A7 AA11 AA29 AA3 AA31 AA39 AA5 AA55 AA9 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Buffer Type Direction PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR O

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Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 33 of 45)

Land No. AB14 AB36 AB42 AB6 AC31 AC9 AD26 AD34 AD36 AD42 AD44 AD46 AD48 AD50 AD52 AD6 AE29 AE31 AE39 AE43 AE47 AE49 AE51 AE9 AF12 AF16 AF20 AF26 AF34 AF36 AF40 AF42 AF54 AF56 AF6 AG1 AG3 AG43 AG5 AG55 AG57 AG9 AH58 AJ15 AJ17 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 34 of 45)

Land No. AK10 AK12 AK14 AK16 AK2 AK4 AK42 AK44 AK46 AK48 AK50 AK6 AK8 AL43 AL45 AL49 AL51 AL53 AM56 AN55 AN57 AP42 AP44 AP58 AR1 AR11 AR13 AR15 AR17 AR3 AR5 AR7 AR9 AT10 AT12 AT14 AT16 AT2 AT4 AT46 AT52 AT6 AT8 AU45 AU47 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 35 of 45)

Land No. AU49 AU51 AV42 AV54 AV56 AW55 AW57 B36 B52 B6 B8 BB42 BB46 BB48 BB50 BB52 BB58 BC1 BC11 BC13 BC15 BC17 BC3 BC43 BC45 BC49 BC5 BC53 BC55 BC57 BC7 BC9 BD10 BD12 BD14 BD16 BD2 BD4 BD54 BD56 BD6 BD8 BE49 BE51 BF42 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 36 of 45)

Land No. BF44 BG47 BH58 BJ55 BJ57 BK42 BK46 BK48 BK50 BK52 BK54 BL1 BL11 BL13 BL15 BL17 BL3 BL49 BL5 BL7 BL9 BM10 BM12 BM14 BM16 BM2 BM4 BM6 BM8 BN43 BN45 BP58 BR53 BR57 BT46 BT48 BT50 BT52 BT54 BT56 BU45 BU51 BW1 BW11 BW13 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 37 of 45)

Land No. BW15 BW17 BW5 BW7 BY24 BY4 BY42 BY58 BY8 C11 C13 C3 C33 C39 C41 C5 C55 CA11 CA19 CA27 CA31 CA33 CA35 CA37 CA39 CA41 CA5 CA55 CA57 CB16 CB36 CB46 CB48 CB50 CB52 CB56 CB6 CB8 CC13 CC29 CC3 CC43 CC47 CC49 CC9 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 38 of 45)

Land No. CD18 CD36 CD6 CE13 CE5 CE9 CF12 CF14 CF30 CF32 CF34 CF36 CF38 CF40 CF42 CF6 CG15 CG31 CG33 CG35 CG37 CG39 CG41 CG43 CG53 CG9 CH12 CH16 CH36 CH44 CH46 CH48 CH50 CH52 CH54 CH6 CJ11 CJ17 CJ29 CJ3 CJ43 CJ45 CJ47 CJ51 CJ9 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 39 of 45)

Land No. CK10 CK36 CK4 CK6 CL17 CL43 CL5 CM10 CM14 CM30 CM32 CM34 CM36 CM38 CM40 CM42 CM6 CM8 CN11 CN13 CN15 CN17 CN3 CN31 CN33 CN35 CN37 CN39 CN5 CN53 CN55 CN57 CN7 CN9 CP12 CP16 CP36 CP40 CP42 CP44 CP46 CP48 CP50 CP52 CP56 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 40 of 45)

Land No. CR11 CR35 CR47 CR49 CR5 CR9 CT28 CT42 CU1 CU11 CU3 CU35 CU5 CV14 CV18 CV30 CV32 CV34 CV38 CV42 CV54 CV58 CV6 CW11 CW13 CW15 CW29 CW31 CW33 CW35 CW37 CW39 CW5 CW51 CW53 CW55 CW57 CW7 CY10 CY12 CY16 CY2 CY36 CY40 CY44 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 41 of 45)

Land No. CY50 CY52 CY8 D2 D26 D36 D8 DA11 DA3 DA41 DA43 DA45 DA47 DA5 DA51 DA9 DB12 DB2 DB32 DB36 DB58 DC3 DC41 DC5 DD10 DD12 DD14 DD34 DD36 DD38 DD6 DE17 DE41 DE53 DE7 DF12 DF36 DF42 DF44 DF46 DF48 DF50 DF52 DF8 E1 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 42 of 45)

Land No. E29 E3 E31 E41 E5 F36 F42 F44 F48 F50 F8 G1 G25 G31 G35 G37 G41 G45 G47 G5 G51 G53 G57 G9 H10 H12 H14 H32 H34 H38 H40 H52 H54 H8 J11 J27 J31 J33 J39 J41 J5 J55 K2 K26 K28 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 43 of 45)

Land No. K30 K34 K8 L25 L29 L41 L5 M34 M36 M42 M44 M46 M50 M52 M8 N13 N33 N35 N37 N41 N43 N47 N49 N5 N53 N9 P10 P12 P14 P26 P30 P32 P38 P40 P54 P56 P8 R11 R29 R3 R31 R35 R39 R5 R55 Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Table 8-1.
Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Land Name (Sheet 44 of 45)

Land No. R7 T28 T4 T42 T6 T8 U35 U5 V26 V28 V34 V36 V42 V44 V46 V48 V50 V8 W13 W33 W37 W41 W43 W45 W47 W5 W51 W53 W9 Y10 Y12 Y28 Y30 Y32 Y36 Y38 Y40 Y42 Y56 BY2 AF14 BT42 AE45 AE53 AM48 PWR PWR PWR Buffer Type Direction GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND O O O

VSS_VCC_SENSE VSS_VSA_SENSE VSS_VTTD_SENSE VTTA VTTA VTTA

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Table 8-1.
Land Name VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD

Land Name (Sheet 45 of 45)

Land No. AM54 AU53 CA53 CC45 CG55 CJ49 CR45 CR51 DA49 W49 Y54 AF22 AF24 AG21 AG23 AM42 AT42 AY42 BD42 BH42 BK56 BL51 BM42 BR55 BU47 BV42 BY20 BY22 CA21 CA23 BP42 Buffer Type Direction PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR O

VTTD_SENSE

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Table 8-2.
Land No. A11 A13 A15 A17 A19 A21 A23 A33 A35 A37 A39 A41 A43 A45 A47 A49 A5 A51 A53 A7 A9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AA27 AA29 AA3 AA31 AA33 AA35 AA37 AA39 AA41 AA43 AA45 AA47 AA49 AA5 AA51 AA53

Land Number (Sheet 1 of 45)

Land Name DDR3_DQ[33] DDR3_MA[13] DDR3_WE_N DDR3_BA[0] DDR3_MA[00] DDR3_MA[05] DDR3_MA[11] DDR3_DQ[22] DDR3_DQ[16] DDR3_DQ[07] DDR3_DQ[01] VSS VSS VSS VSS VSS VSS VSS RSVD VSS DDR3_DQ[39] VSS DDR2_DQ[37] RSVD RSVD DDR2_CS_N[4] DDR2_CLK_DP[2] DDR2_CLK_DP[3] DDR2_CKE[0] DDR2_ECC[7] VSS VSS VSS SSTL SSTL SSTL SSTL SSTL GND GND GND SSTL SSTL SSTL GND SSTL PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 PCIEX3 I I I/O O O O I I/O I/O I/O O O O O I/O GND SSTL GND SSTL I/O I/O Buffer Type Direction SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND GND GND GND GND I/O O O O O O O I/O I/O I/O I/O

Table 8-2.
Land No. AA55 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AB26 AB28 AB30 AB32 AB34 AB36 AB38 AB4 AB40 AB42 AB44 AB46 AB48 AB50 AB52 AB54 AB56 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AC25 AC27 AC29 AC3 AC31 AC33 AC35 AC37

Land Number (Sheet 2 of 45)

Land Name VSS RSVD VSS DDR2_DQ[38] RSVD VSS RSVD DDR2_MA[00] DDR2_CS_N[0] DDR2_CLK_DP[1] DDR2_CLK_DP[0] DDR2_ECC[3] SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL O O O O I/O I/O I/O I/O GND GND SSTL I/O Buffer Type Direction GND

DDR2_DQS_DN[08] DDR2_ECC[4] DDR2_DQ[30] RSVD VSS DDR2_DQS_DP[01] DDR2_DQS_DP[07] RSVD VSS PE3D_TX_DN[13] PE3C_TX_DN[11] RSVD PE3B_RX_DN[4] PE3B_RX_DN[5] PE2B_RX_DP[4] PE2B_RX_DP[5] VSS DDR2_DQS_DN[05] DDR2_DQS_DN[04] DDR2_DQ[32] DDR23_RCOMP[1] VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 DDR2_DQS_DP[08] RSVD DDR2_DQS_DN[07] VSS DDR2_DQS_DP[03] DDR2_DQ[24] DDR2_DQ[11]

GND SSTL SSTL I/O I/O

GND PCIEX3 PCIEX3 O O

PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND SSTL SSTL SSTL Analog PWR PWR PWR PWR PWR SSTL

I I I I

I/O I/O I/O I

DDR2_DQS_DN[03] DDR2_DQ[28] DDR2_DQ[10] VSS DDR2_DQ[13] PE3D_TX_DN[14] PE3D_TX_DP[12] PE3C_TX_DP[9] PE3A_RX_DP[3] VSS PE3B_RX_DP[7] PE3B_RX_DP[6]

I/O

SSTL GND SSTL SSTL SSTL

I/O

I/O I/O I/O

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Table 8-2.
Land No. AC39 AC41 AC43 AC45 AC47 AC49 AC5 AC51 AC53 AC55 AC7 AC9 AD10 AD12 AD14 AD16 AD18 AD20 AD22 AD24 AD26 AD28 AD30 AD32 AD34 AD36 AD38 AD4 AD40 AD42 AD44 AD46 AD48 AD50 AD52 AD54 AD56 AD6 AD8 AE11 AE13 AE15 AE17 AE19 AE21

Land Number (Sheet 3 of 45)

Land Name RSVD DDR2_DQ[12] PE3D_TX_DP[14] PE3D_TX_DN[12] PE3C_TX_DN[9] PE3A_RX_DN[3] RSVD PE3B_RX_DN[7] PE3B_RX_DN[6] PE2B_RX_DP[6] PCIEX3 PCIEX3 PCIEX3 SSTL GND SSTL I/O I I I I/O SSTL PCIEX3 PCIEX3 PCIEX3 PCIEX3 I/O O O O I Buffer Type Direction

Table 8-2.
Land No. AE23 AE25 AE27 AE29 AE3 AE31 AE33 AE35 AE37 AE39 AE41 AE43 AE45 AE47

Land Number (Sheet 4 of 45)

Land Name RSVD RSVD Buffer Type Direction

DDR_RESET_C23_N VSS DDR2_DQ[63] VSS DDR2_DQ[26] DDR2_DQ[25] DDR2_DQ[15] VSS DDR2_DQ[08] VSS VTTA VSS VSS DDR2_DQ[59] VSS VTTA PE2B_RX_DN[6] PE2B_RX_DP[7] DDR2_DQ[47] VSS DDR2_DQ[35] VSS VSS_VSA_SENSE VSS VSA DDR2_DQ[62] VSS VTTD VTTD VSS DDR2_ECC[1] DDR2_ECC[0] DDR2_DQ[27] VSS VSS DDR2_DQ[14] DDR2_DQ[58] VSS VSS PE3A_RX_DP[0] PE3A_RX_DP[2] PE3C_RX_DP[8] PE3C_RX_DP[10]

CMOS1.5v GND SSTL GND SSTL SSTL SSTL GND SSTL GND PWR GND GND SSTL GND PWR PCIEX3 PCIEX3 SSTL GND SSTL GND

I/O

I/O I/O I/O

DDR2_DQS_DP[05] VSS DDR2_DQ[39] RSVD DDR2_DQ[36] RSVD DDR2_ODT[2] RSVD RSVD DDR2_CKE[3] VSS RSVD DDR2_ECC[5] DDR2_DQ[31] VSS VSS DDR2_DQS_DN[01] RSVD DDR2_DQ[09] VSS VSS VSS VSS VSS VSS PE2B_RX_DN[4] PE2B_RX_DN[5] VSS DDR2_DQ[46] DDR2_DQS_DP[04] DDR2_DQ[33] VSA VSA DDR2_CS_N[1] RSVD

I/O

SSTL

I/O

AE49 AE5

I/O

SSTL

AE51 AE53 AE55

I I I/O

SSTL GND

AE57 AE7 AE9

SSTL SSTL GND GND SSTL

I/O I/O

AF10 AF12 AF14 AF16

I/O

O GND PWR SSTL GND PWR PWR GND SSTL SSTL SSTL GND GND SSTL SSTL GND GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 I I I I I/O I/O I/O I/O I/O I/O

I/O

AF18 AF2

SSTL GND GND GND GND GND GND PCIEX3 PCIEX3 GND SSTL SSTL SSTL PWR PWR SSTL

I/O

AF20 AF22 AF24 AF26 AF28 AF30 AF32

I I

AF34 AF36 AF38

I/O I/O I/O

AF4 AF40 AF42 AF44 AF46

AF48 AF50

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Table 8-2.
Land No. AF52 AF54 AF56 AF58 AF6 AF8 AG1 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AG25 AG27 AG29 AG3 AG31 AG33 AG35 AG37 AG39 AG41 AG43 AG45 AG47 AG49 AG5 AG51 AG53 AG55 AG57 AG7 AG9 AH10 AH12 AH14 AH16 AH2 AH4 AH42 AH44 AH46 AH48

Land Number (Sheet 5 of 45)

Land Name PE_RBIAS_SENSE VSS VSS PE2B_RX_DN[7] VSS DDR2_DQ[42] VSS DDR2_DQ[34] VSA_SENSE VSA VSA VCC VTTD VTTD VCC VCC VCC VSS VCC VCC VCC VCC VCC VCC VSS PE3A_RX_DP[1] PE3D_RX_DP[12] PE3C_RX_DP[11] VSS PE3C_RX_DP[9] PE2B_TX_DP[4] VSS VSS DDR2_DQ[43] VSS VSA VSA VSA VSA VSA VSA PROC_SEL_N PE3A_RX_DN[0] PE3A_RX_DN[2] PE3C_RX_DN[8] PCIEX3 PCIEX3 PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR GND PWR PWR PWR PWR PWR PWR GND PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 PCIEX3 GND GND SSTL GND PWR PWR PWR PWR PWR PWR O I I I I/O I O I I I Buffer Type Direction PCIEX3 GND GND PCIEX3 GND SSTL GND SSTL I/O O I/O I I

Table 8-2.
Land No. AH50 AH52 AH54 AH56 AH58 AH6 AH8 AJ1 AJ11 AJ13 AJ15 AJ17 AJ3 AJ43 AJ45 AJ47 AJ49 AJ5 AJ51 AJ53 AJ55 AJ57 AJ7 AJ9 AK10 AK12 AK14 AK16 AK2 AK4 AK42 AK44 AK46 AK48 AK50 AK52 AK54 AK56 AK58 AK6 AK8 AL1 AL11 AL13 AL15

Land Number (Sheet 6 of 45)

Land Name PE3C_RX_DN[10] PE_RBIAS PE2B_TX_DP[5] PE2C_RX_DP[8] VSS VSA VSA VSA VSA VSA VSS VSS VSA PE_VREF_CAP PE3A_RX_DN[1] PE3D_RX_DN[12] PE3C_RX_DN[11] VSA PE3C_RX_DN[9] PE2B_TX_DN[4] BCLK_SELECT[1] PE2C_RX_DP[10] VSA VSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSVD PE2B_TX_DN[5] PE2C_RX_DN[8] PE2C_RX_DP[9] VSS VSS VCC VCC VCC VCC PCIEX3 PCIEX3 PCIEX3 GND GND PWR PWR PWR PWR O I I Buffer Type Direction PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND PWR PWR PWR PWR PWR GND GND PWR PCIEX3 PCIEX3 PCIEX3 PCIEX3 PWR PCIEX3 PCIEX3 CMOS PCIEX3 PWR PWR GND GND GND GND GND GND GND GND GND GND GND I O I I I/O I I I I I/O O I

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Table 8-2.
Land No. AL17 AL3 AL43 AL45 AL47 AL49 AL5 AL51 AL53 AL55 AL57 AL7 AL9 AM10 AM12 AM14 AM16 AM2 AM4 AM42 AM44 AM46 AM48 AM50 AM52 AM54 AM56 AM58 AM6 AM8 AN1 AN11 AN13 AN15 AN17 AN3 AN43 AN45 AN47 AN49 AN5 AN51 AN53 AN55 AN57

Land Number (Sheet 7 of 45)

Land Name VCC VCC VSS VSS RSVD VSS VCC VSS VSS RSVD PE2C_RX_DN[10] VCC VCC VCC VCC VCC VCC VCC VCC VTTD RSVD PE3D_RX_DP[14] VTTA PE2A_TX_DP[1] PE2A_TX_DP[3] VTTA VSS PE2C_RX_DN[9] VCC VCC VCC VCC VCC VCC VCC VCC CPU_ONLY_RESET PE3D_RX_DP[15] PE3D_RX_DP[13] PE2A_TX_DP[0] VCC PE2A_TX_DP[2] PE2B_TX_DP[6] VSS VSS PCIEX3 PWR PCIEX3 PCIEX3 PWR GND PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR ODCMOS PCIEX3 PCIEX3 PCIEX3 PWR PCIEX3 PCIEX3 GND GND O O I/O I I O I O O I PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR PWR I GND PWR GND GND Buffer Type Direction PWR PWR GND GND

Table 8-2.
Land No. AN7 AN9 AP10 AP12 AP14 AP16 AP2 AP4 AP42 AP44 AP46 AP48 AP50 AP52 AP54 AP56 AP58 AP6 AP8 AR1 AR11 AR13 AR15 AR17 AR3 AR43 AR45 AR47 AR49 AR5 AR51 AR53 AR55 AR57 AR7 AR9 AT10 AT12 AT14 AT16 AT2 AT4 AT42 AT44 AT46

Land Number (Sheet 8 of 45)

Land Name VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS PE3D_RX_DN[14] RSVD PE2A_TX_DN[1] PE2A_TX_DN[3] PE2B_TX_DP[7] PE2D_RX_DP[13] VSS VCC VCC VSS VSS VSS VSS VSS VSS BPM_N[0] PE3D_RX_DN[15] PE3D_RX_DN[13] PE2A_TX_DN[0] VSS PE2A_TX_DN[2] PE2B_TX_DN[6] RSVD PE2C_RX_DP[11] VSS VSS VSS VSS VSS VSS VSS VSS VTTD BPM_N[1] VSS PCIEX3 GND GND GND GND GND GND GND GND PWR ODCMOS GND I/O I PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND PWR PWR GND GND GND GND GND GND ODCMOS PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 PCIEX3 O O I/O I I O O O O I Buffer Type Direction PWR PWR PWR PWR PWR PWR PWR PWR GND GND PCIEX3 I

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Table 8-2.
Land No. AT48 AT50 AT52 AT54 AT56 AT58 AT6 AT8 AU1 AU11 AU13 AU15 AU17 AU3 AU43 AU45 AU47 AU49 AU5 AU51 AU53 AU55 AU57 AU7 AU9 AV10 AV12 AV14 AV16 AV2 AV4 AV42 AV44 AV46 AV48 AV50 AV52 AV54 AV56 AV58 AV6 AV8 AW1 AW11 AW13

Land Number (Sheet 9 of 45)

Land Name BIST_ENABLE TESTHI_AT50 VSS PE2B_TX_DN[7] PE2D_RX_DN[13] PE2D_RX_DP[12] VSS VSS VCC VCC VCC VCC VCC VCC BPM_N[2] VSS VSS VSS VCC VSS VTTA RSVD PE2C_RX_DN[11] VCC VCC VCC VCC VCC VCC VCC VCC VSS BPM_N[3] RSVD PE2D_TX_DP[14] PE2D_TX_DP[12] PE2C_TX_DP[8] VSS VSS PE2D_RX_DN[12] VCC VCC VCC VCC VCC PCIEX3 PCIEX3 PCIEX3 GND GND PCIEX3 PWR PWR PWR PWR PWR I O O O PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR GND ODCMOS I/O I Buffer Type Direction CMOS CMOS GND PCIEX3 PCIEX3 PCIEX3 GND GND PWR PWR PWR PWR PWR PWR ODCMOS GND GND GND PWR GND PWR I/O O I I I I

Table 8-2.
Land No. AW15 AW17 AW3 AW43 AW45 AW47 AW49 AW5 AW51 AW53 AW55 AW57 AW7 AW9 AY10 AY12 AY14 AY16 AY2 AY4 AY42 AY44 AY46 AY48 AY50 AY52 AY54 AY56 AY58 AY6 AY8 B10 B12 B14 B16 B18 B20 B22 B24 B32 B34 B36 B38 B40 B42

Land Number (Sheet 10 of 45)

Land Name VCC VCC VCC BPM_N[5] BCLK1_DP PE2D_TX_DP[15] PE2D_TX_DP[13] VCC PE2C_TX_DP[11] PE2C_TX_DP[9] VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VTTD BPM_N[7] RSVD PE2D_TX_DN[14] PE2D_TX_DN[12] PE2C_TX_DN[8] PE2C_TX_DP[10] PE2D_RX_DP[15] PE2D_RX_DP[14] VCC VCC PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PWR PWR SSTL SSTL SSTL SSTL I/O I/O O O O O O O I I Buffer Type Direction PWR PWR PWR ODCMOS CMOS PCIEX3 PCIEX3 PWR PCIEX3 PCIEX3 GND GND PWR PWR PWR PWR PWR PWR PWR PWR PWR ODCMOS I/O O O I/O I O O

DDR3_DQS_DN[04] DDR3_DQ[37] DDR3_CAS_N DDR3_RAS_N RSVD DDR3_MA[03] DDR3_MA[07] DDR3_BA[2] DDR3_DQ[23] RSVD VSS DDR3_DQS_DN[00] DDR3_DQ[00] DMI_TX_DP[0]

SSTL SSTL SSTL SSTL

O O O I/O

GND SSTL SSTL PCIEX I/O I/O O

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Table 8-2.
Land No. B44 B46 B48 B50 B52 B54 B6 B8 BA1 BA11 BA13 BA15 BA17 BA3 BA43 BA45 BA47 BA49 BA5 BA51 BA53 BA55 BA57 BA7 BA9 BB10 BB12 BB14 BB16 BB2 BB4 BB42 BB44 BB46 BB48 BB50 BB52 BB54 BB56 BB58 BB6 BB8 BC1 BC11 BC13

Land Number (Sheet 11 of 45)

Land Name DMI_TX_DP[2] RSVD DMI_RX_DP[1] DMI_RX_DP[3] VSS VSA VSS VSS VCC VCC VCC VCC VCC VCC BPM_N[6] BCLK1_DN PE2D_TX_DN[15] PE2D_TX_DN[13] VCC PE2C_TX_DN[11] PE2C_TX_DN[9] TEST4 PE2D_RX_DN[14] VCC VCC VCC VCC VCC VCC VCC VCC VSS BPM_N[4] VSS VSS VSS VSS PE2C_TX_DN[10] PE2D_RX_DN[15] VSS VCC VCC VSS VSS VSS PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR GND ODCMOS GND GND GND GND PCIEX3 PCIEX3 GND PWR PWR GND GND GND O I I/O PCIEX PCIEX GND PWR GND GND PWR PWR PWR PWR PWR PWR ODCMOS CMOS PCIEX3 PCIEX3 PWR PCIEX3 PCIEX3 O O I I I/O I O O I I Buffer Type Direction PCIEX O

Table 8-2.
Land No. BC15 BC17 BC3 BC43 BC45 BC47 BC49 BC5 BC51 BC53 BC55 BC57 BC7 BC9 BD10 BD12 BD14 BD16 BD2 BD4 BD42 BD44 BD46 BD48 BD50 BD52 BD54 BD56 BD58 BD6 BD8 BE1 BE11 BE13 BE15 BE17 BE3 BE43 BE45 BE47 BE49 BE5 BE51 BE53 BE55

Land Number (Sheet 12 of 45)

Land Name VSS VSS VSS VSS VSS RSVD VSS VSS RSVD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTTD RSVD RSVD BCLK_SELECT[0] RSVD PROCHOT_N VSS VSS RSVD VSS VSS VCC VCC VCC VCC VCC VCC RSVD RSVD RSVD VSS VCC VSS RSVD RSVD GND PWR GND GND GND PWR PWR PWR PWR PWR PWR ODCMOS GND GND I/O CMOS I GND GND GND GND GND GND GND GND GND GND GND PWR GND GND Buffer Type Direction GND GND GND GND GND

102

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Table 8-2.
Land No. BE57 BE7 BE9 BF10 BF12 BF14 BF16 BF2 BF4 BF42 BF44 BF46 BF48 BF50 BF52 BF54 BF56 BF58 BF6 BF8 BG1 BG11 BG13 BG15 BG17 BG3 BG43 BG45 BG47 BG49 BG5 BG51 BG53 BG55 BG57 BG7 BG9 BH10 BH12 BH14 BH16 BH2 BH4 BH42 BH44

Land Number (Sheet 13 of 45)

Land Name RSVD VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS RSVD TESTHI_BF48 RSVD RSVD RSVD RSVD RSVD VCC VCC VCC VCC VCC VCC VCC VCC RSVD RSVD VSS RSVD VCC RSVD RSVD RSVD RSVD VCC VCC VCC VCC VCC VCC VCC VCC VTTD RSVD PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR GND PWR PWR PWR PWR PWR PWR PWR PWR Open Drain I/O PWR PWR PWR PWR PWR PWR PWR PWR GND GND Buffer Type Direction

Table 8-2.
Land No. BH46 BH48 BH50 BH52 BH54 BH56 BH58 BH6 BH8 BJ1 BJ11 BJ13 BJ15 BJ17 BJ3 BJ43 BJ45 BJ47 BJ49 BJ5 BJ51 BJ53 BJ55 BJ57 BJ7 BJ9 BK10 BK12 BK14 BK16 BK2 BK4 BK42 BK44 BK46 BK48 BK50 BK52 BK54 BK56 BK58 BK6 BK8 BL1 BL11

Land Number (Sheet 14 of 45)

Land Name RSVD TESTHI_BH48 RSVD RSVD RSVD RSVD VSS VCC VCC VCC VCC VCC VCC VCC VCC RSVD RSVD PECI RSVD VCC RSVD PWRGOOD VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS RSVD VSS VSS VSS VSS VSS VTTD RSVD VCC VCC VSS VSS PWR PWR GND GND GND GND GND GND GND PWR CMOS GND GND PWR PWR PWR PWR PWR PWR PWR PWR GND I PWR PECI I/O GND PWR PWR PWR PWR PWR PWR PWR PWR Open Drain I/O Buffer Type Direction

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Table 8-2.
Land No. BL13 BL15 BL17 BL3 BL43 BL45 BL47 BL49 BL5 BL51 BL53 BL55 BL57 BL7 BL9 BM10 BM12 BM14 BM16 BM2 BM4 BM42 BM44 BM46 BM48 BM50 BM52 BM54 BM56 BM58 BM6 BM8 BN1 BN11 BN13 BN15 BN17 BN3 BN43 BN45 BN47 BN49 BN5 BN51 BN53

Land Number (Sheet 15 of 45)

Land Name VSS VSS VSS VSS RSVD RSVD THERMTRIP_N VSS VSS VTTD RSVD RSVD RSVD VSS VSS VSS VSS VSS VSS VSS VSS VTTD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSS VSS VCC VCC VCC VCC VCC VCC VSS VSS RSVD RSVD VCC RSVD RSVD PWR GND GND PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND GND GND GND GND PWR ODCMOS GND GND PWR O Buffer Type Direction GND GND GND GND

Table 8-2.
Land No. BN55 BN57 BN7 BN9 BP10 BP12 BP14 BP16 BP2 BP4 BP42 BP44 BP46 BP48 BP50 BP52 BP54 BP56 BP58 BP6 BP8 BR1 BR11 BR13 BR15 BR17 BR3 BR43 BR45 BR47 BR49 BR5 BR51 BR53 BR55 BR57 BR7 BR9 BT10 BT12 BT14 BT16 BT2 BT4 BT42

Land Number (Sheet 16 of 45)

Land Name RSVD RSVD VCC VCC VCC VCC VCC VCC VCC VCC VTTD_SENSE RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSS VCC VCC VCC VCC VCC VCC VCC VCC RSVD SVIDDATA RSVD RSVD VCC RSVD VSS VTTD VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS_VTTD_SENSE GND PWR GND PWR PWR PWR PWR PWR PWR PWR PWR O PWR ODCMOS I/O GND PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR O Buffer Type Direction

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Table 8-2.
Land No. BT44 BT46 BT48 BT50 BT52 BT54 BT56 BT58 BT6 BT8 BU1 BU11 BU13 BU15 BU17 BU3 BU43 BU45 BU47 BU49 BU5 BU51 BU53 BU55 BU57 BU7 BU9 BV10 BV12 BV14 BV16 BV2 BV4 BV42 BV44 BV46 BV48 BV50 BV52 BV54 BV56 BV58 BV6 BV8 BW1

Land Number (Sheet 17 of 45)

Land Name RSVD VSS VSS VSS VSS VSS VSS RSVD VCC VCC VCC VCC VCC VCC VCC VCC RSVD VSS VTTD SKTOCC_N VCC VSS RSVD RSVD RSVD VCC VCC VCC VCC VCC VCC VCC VCC VTTD TMS RSVD RSVD RSVD RSVD RSVD RSVD RSVD VCC VCC VSS PWR PWR GND PWR PWR PWR PWR PWR PWR PWR PWR PWR CMOS I PWR GND GND PWR O PWR PWR PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND Buffer Type Direction

Table 8-2.
Land No. BW11 BW13 BW15 BW17 BW3 BW43 BW45 BW47 BW49 BW5 BW51 BW53 BW55 BW57 BW7 BW9 BY10 BY12 BY14 BY16 BY18 BY2 BY20 BY22 BY24 BY26 BY28 BY30 BY32 BY34 BY36 BY38 BY4 BY40 BY42 BY44 BY46 BY48 BY50 BY52 BY54 BY56 BY58 BY6 BY8

Land Number (Sheet 18 of 45)

Land Name VSS VSS VSS VSS VCC_SENSE TDI RSVD RSVD RSVD VSS RSVD RSVD RSVD RSVD VSS DDR0_DQ[28] DDR0_DQ[24] DDR0_DQ[25] VCCPLL GND SSTL SSTL SSTL PWR DC PWR O PWR PWR GND PWR PWR PWR PWR PWR PWR PWR GND PWR GND CMOS I I I/O I/O I/O GND CMOS Buffer Type Direction GND GND GND GND O I

DDR_VREFDQRX_C01 VCC VSS_VCC_SENSE VTTD VTTD VSS VCC VCC VCC VCC VCC VCC VCC VSS VCC VSS TCK RSVD RSVD RSVD RSVD RSVD RSVD VSS DDR0_DQ[04] VSS

GND SSTL GND I/O

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Table 8-2.
Land No. C11 C13 C15 C17 C19 C21 C23 C25 C3 C33 C35 C37 C39 C41 C43 C45 C47 C49 C5 C51 C53 C55 C7 C9 CA1 CA11 CA13 CA15 CA17 CA19 CA21 CA23 CA25 CA27 CA29 CA3 CA31 CA33 CA35 CA37 CA39 CA41 CA43 CA45 CA47

Land Number (Sheet 19 of 45)

Land Name VSS VSS VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 DDR3_ECC[3] VSS VSS DDR3_DQ[21] DDR3_DQ[02] VSS VSS DMI_TX_DP[1] DMI_TX_DP[3] DMI_RX_DP[0] DMI_RX_DP[2] VSS PE1A_RX_DP[0] RSVD VSS DDR3_DQ[52] DDR3_DQ[34] DDR0_DQ[12] VSS VCCPLL VCCPLL DDR01_RCOMP[0] VSS VTTD VTTD VCC VSS VCC DDR0_DQ[13] VSS VSS VSS VSS VSS VSS TDO RSVD RSVD GND SSTL SSTL SSTL GND PWR PWR Analog GND PWR PWR PWR GND PWR SSTL GND GND GND GND GND GND ODCMOS O I/O I I/O I/O I/O Buffer Type Direction GND GND PWR PWR PWR PWR PWR SSTL GND GND SSTL SSTL GND GND PCIEX PCIEX PCIEX PCIEX GND PCIEX3 I O O I I I/O I/O I/O

Table 8-2.
Land No. CA49 CA5 CA51 CA53 CA55 CA57 CA7 CA9 CB10 CB12 CB14 CB16 CB18 CB2 CB20 CB22 CB24 CB26 CB28 CB30 CB32 CB34 CB36 CB38 CB4 CB40 CB42 CB44 CB46 CB48 CB50 CB52 CB54 CB56 CB6 CB8 CC11 CC13 CC15 CC17 CC19 CC21 CC23 CC25 CC27

Land Number (Sheet 20 of 45)

Land Name RSVD VSS RSVD VTTA VSS VSS DDR0_DQ[05] DDR0_DQ[29] RSVD DDR0_DQ[26] DDR0_ECC[4] VSS SSTL SSTL GND CMOS1.5v SSTL Analog ODCMOS O I/O I I/O I/O I/O PWR GND GND SSTL SSTL I/O I/O GND Buffer Type Direction

DDR_RESET_C01_N DDR0_DQ[08] DDR01_RCOMP[2] MEM_HOT_C01_N RSVD RSVD RSVD DDR0_DQ[37] RSVD DDR0_DQ[39] VSS DDR0_DQ[48] DDR0_DQ[09] DDR0_DQS_DN[06] DDR0_DQ[55] SVIDCLK VSS VSS VSS VSS RSVD VSS VSS VSS RSVD VSS DDR0_ECC[1] DDR0_DQS_DP[08] DDR01_RCOMP[1] RSVD RSVD RSVD RSVD

SSTL

I/O

SSTL GND SSTL SSTL SSTL SSTL ODCMOS GND GND GND GND

I/O

I/O I/O I/O I/O O

GND GND GND

GND SSTL SSTL Analog I/O I/O I

106

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Table 8-2.
Land No. CC29 CC3 CC31 CC33 CC35 CC37 CC39 CC41 CC43 CC45 CC47 CC49 CC5 CC51 CC53 CC55 CC7 CC9 CD10 CD12 CD14 CD16 CD18 CD20 CD22 CD24 CD26 CD28 CD30 CD32 CD34 CD36 CD38 CD4 CD40 CD42 CD44 CD46 CD48 CD50 CD52 CD54 CD56 CD6 CD8

Land Number (Sheet 21 of 45)

Land Name VSS VSS DDR0_DQ[33] Buffer Type Direction GND GND SSTL SSTL SSTL SSTL I/O I/O I/O I/O

Table 8-2.
Land No. CE11 CE13 CE15 CE17 CE19 CE21 CE23

Land Number (Sheet 22 of 45)

Land Name Buffer Type Direction SSTL GND SSTL SSTL I/O I/O I/O

DDR0_DQS_DP[03] VSS DDR0_ECC[0] DDR0_DQS_DN[08] RSVD DDR0_CLK_DN[2] DDR0_CLK_DN[1] DDR0_ODT[0] DDR0_ODT[1] DDR0_RAS_N DDR0_DQS_DN[01] DDR0_DQ[32] DDR0_DQS_DN[04] DDR0_DQ[34] DDR0_DQ[53] RSVD DDR0_DQ[50] RSVD RSVD RSVD RSVD VSS RSVD CORE_RBIAS RSVD RSVD VSS DDR0_DQ[31] VSS VSS RSVD DDR0_ECC[3] RSVD DDR0_CLK_DN[3] DDR0_CLK_DN[0] DDR0_CS_N[5] DDR0_ODT[3] VSS VSS VSS VSS VSS DDR0_DQS_DP[01] VSS VSS

DDR0_DQS_DP[04] DDR0_DQ[35] DDR0_DQ[52] RSVD DDR0_DQ[54] VSS VTTA VSS VSS RSVD CAT_ERR_N CORE_RBIAS_SENSE RSVD DDR0_DQ[00] VSS DDR0_DQS_DN[03] DDR0_DQ[27] DDR0_ECC[5] RSVD VSS VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 DDR0_DQ[36] RSVD DDR0_DQ[38] VSS DDR0_DQ[49] RSVD DDR0_DQS_DP[06] DDR0_DQ[51] RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSS DDR0_DQ[01]

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

O O O O O I/O I/O I/O I/O I/O

SSTL GND PWR GND GND

I/O

CE25 CE27 CE29 CE3 CE31 CE33

ODCMOS Analog

I/O I

CE35 CE37 CE39

SSTL GND SSTL SSTL SSTL

I/O

CE41 CE43

SSTL

I/O

I/O I/O I/O

CE45 CE47 CE49 CE5

GND

GND PWR PWR PWR PWR PWR SSTL I/O

CE51 CE53 CE55 CE7 CE9 CF10 CF12 CF14

Analog

I/O

GND SSTL GND GND I/O

SSTL GND SSTL

I/O

CF16 CF18

SSTL

I/O

I/O

CF20 CF22

SSTL SSTL SSTL SSTL GND GND GND GND GND SSTL GND GND

O O O O

SSTL SSTL

I/O I/O

CF24 CF26 CF28 CF30 CF32 CF34 CF36 CF38 CF4

I/O

GND SSTL I/O

CF40 CF42

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Table 8-2.
Land No. CF44 CF46 CF48 CF50 CF52 CF54 CF56 CF6 CF8 CG11 CG13 CG15 CG17 CG19 CG21 CG23 CG25 CG27 CG29 CG3 CG31 CG33 CG35 CG37 CG39 CG41 CG43 CG45 CG47 CG49 CG5 CG51 CG53 CG55 CG7 CG9 CH10 CH12 CH14 CH16 CH18 CH20 CH22 CH24 CH26

Land Number (Sheet 23 of 45)

Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSS RSVD RSVD DDR0_DQ[20] VSS DDR0_ECC[6] DDR0_MA[14] DDR0_CLK_DP[2] DDR0_CLK_DP[1] DDR0_MA[02] DDR0_CS_N[4] DDR0_MA[13] DDR0_DQ[14] VSS VSS VSS VSS VSS VSS VSS RSVD RSVD RSVD DDR0_DQ[15] RSVD VSS VTTA GND PWR SSTL GND SSTL GND SSTL GND SSTL SSTL SSTL SSTL SSTL I/O O O O O I/O I/O I/O SSTL I/O SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND GND GND GND GND I/O O O O O O O I/O I/O GND Buffer Type Direction

Table 8-2.
Land No. CH28 CH30 CH32 CH34 CH36 CH38 CH4 CH40 CH42 CH44 CH46 CH48 CH50 CH52 CH54 CH56 CH6 CH8 CJ11 CJ13 CJ15 CJ17 CJ19 CJ21 CJ23 CJ25 CJ27 CJ29 CJ3 CJ31 CJ33 CJ35 CJ37 CJ39 CJ41 CJ43 CJ45 CJ47 CJ49 CJ5 CJ51 CJ53 CJ55 CJ7 CJ9

Land Number (Sheet 24 of 45)

Land Name DDR0_ODT[2] DDR0_DQ[45] RSVD DDR0_DQ[47] VSS DDR0_DQ[56] DDR0_DQ[10] SSTL GND SSTL SSTL SSTL SSTL GND GND GND GND GND GND ODCMOS GND SSTL GND I/O I/O I/O I/O I/O I/O I/O Buffer Type Direction SSTL SSTL O I/O

DDR0_DQS_DN[07] DDR0_DQ[58] VSS VSS VSS VSS VSS VSS EAR_N VSS DDR0_DQS_DP[00] VSS RSVD DDR0_DQ[22] VSS VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VSS VSS DDR0_DQ[41] DDR0_DQS_DP[05] DDR0_DQ[43] DDR0_DQ[60] RSVD DDR0_DQ[62] VSS VSS VSS VTTA DDR0_DQ[11] VSS RSVD RSVD DDR0_DQ[06] VSS

SSTL GND PWR PWR PWR PWR PWR GND GND SSTL SSTL SSTL SSTL

I/O

I/O I/O I/O I/O

DDR0_DQS_DN[00] VSS DDR0_DQ[30] VSS DDR0_DQS_DN[02] VSS DDR0_ECC[2] DDR0_CKE[2] DDR0_CLK_DP[3] DDR0_CLK_DP[0] DDR0_CS_N[1]

SSTL GND GND GND PWR SSTL GND

I/O

I/O

SSTL GND

I/O

108

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Table 8-2.
Land No. CK10 CK12 CK14 CK16 CK18 CK20 CK22 CK24 CK26 CK28 CK30 CK32 CK34 CK36 CK38 CK4 CK40 CK42 CK44 CK46 CK48 CK50 CK52 CK54 CK56 CK6 CK8 CL11 CL13 CL15 CL17 CL19 CL21 CL23 CL25 CL27 CL29 CL3 CL31 CL33 CL35 CL37 CL39 CL41 CL43

Land Number (Sheet 25 of 45)

Land Name VSS DDR0_DQ[16] Buffer Type Direction GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O I/O I/O O O O O

Table 8-2.
Land No. CL45 CL47 CL49 CL5 CL51 CL53 CL55 CL7 CL9 CM10

Land Number (Sheet 26 of 45)

Land Name RSVD RSVD RSVD VSS RSVD RSVD RSVD DDR0_DQ[07] DDR0_DQ[03] VSS DDR0_DQ[17] VSS DDR0_DQ[19] DDR0_CKE[1] DDR0_BA[2] DDR0_MA[07] DDR0_MA[04] RSVD DDR0_BA[0] VSS VSS VSS VSS VSS DDR1_DQ[04] VSS VSS BCLK0_DN RSVD RSVD RSVD RSVD RSVD RSVD VSS VSS VSS VSS VSS VSS DDR0_MA[15] DDR0_MA[09] DDR0_MA[06] DDR0_CS_N[0] DDR0_BA[1] GND GND GND GND GND GND SSTL SSTL SSTL SSTL SSTL O O O O O SSTL GND GND GND GND GND SSTL GND GND CMOS I I/O O SSTL SSTL GND SSTL GND SSTL SSTL SSTL SSTL SSTL I/O O O O O I/O I/O I/O GND Buffer Type Direction

DDR0_DQS_DP[02] DDR0_DQ[18] DDR0_ECC[7] DDR0_MA[12] DDR0_MA[08] DDR0_MA[03] DDR0_MA[10] RSVD DDR0_DQ[44] RSVD DDR0_DQ[46] VSS DDR0_DQ[57] VSS DDR0_DQS_DP[07] DDR0_DQ[59] RESET_N RSVD RSVD RSVD RSVD RSVD RSVD VSS DDR0_DQ[02] DDR0_DQ[21] RSVD DDR0_DQ[23] VSS DDR0_CKE[0] DDR0_MA[11] DDR0_MA[05] DDR0_MA[00] RSVD DDR0_CAS_N DDR1_DQ[05] DDR0_DQ[40] DDR0_DQS_DN[05] DDR0_DQ[42] DDR0_DQ[61] RSVD DDR0_DQ[63] VSS

SSTL

I/O

CM12 CM14

SSTL GND SSTL GND SSTL SSTL CMOS

I/O

CM16 CM18

I/O

CM20 CM22

I/O I/O I

CM24 CM26 CM28 CM30 CM32 CM34 CM36 CM38 CM4

GND SSTL SSTL I/O I/O

CM40 CM42 CM44 CM46

SSTL GND SSTL SSTL SSTL SSTL

I/O

CM48 CM50

O O O O

CM52 CM54 CM56 CM6 CM8

SSTL SSTL SSTL SSTL SSTL SSTL

O I/O I/O I/O I/O I/O

CN11 CN13 CN15 CN17 CN19 CN21 CN23

SSTL GND

I/O

CN25 CN27

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Table 8-2.
Land No. CN29 CN3 CN31 CN33 CN35 CN37 CN39 CN41 CN43 CN45 CN47 CN49 CN5 CN51 CN53 CN55 CN57 CN7 CN9 CP10 CP12 CP14 CP16 CP18 CP2 CP20 CP22 CP24 CP26 CP28 CP30 CP32 CP34 CP36 CP38 CP4 CP40 CP42 CP44 CP46 CP48 CP50 CP52 CP54 CP56

Land Number (Sheet 27 of 45)

Land Name DDR0_WE_N VSS VSS VSS VSS VSS VSS Buffer Type Direction SSTL GND GND GND GND GND GND DC CMOS O I O

Table 8-2.
Land No. CP58 CP6 CP8 CR1 CR11 CR13 CR15 CR17 CR19 CR21 CR23 CR25

Land Number (Sheet 28 of 45)

Land Name RSVD DDR1_DQ[20] RSVD RSVD VSS DDR1_DQ[24] GND SSTL SSTL SSTL I/O I/O I/O SSTL I/O Buffer Type Direction

DDR1_DQS_DN[03] DDR1_DQ[26] RSVD RSVD RSVD DDR0_MA[01] RSVD DDR1_DQ[37] DDR1_DQS_DP[00] RSVD DDR1_DQ[39] VSS DDR1_DQ[48] DDR1_DQS_DN[06] DDR1_DQ[50] SVIDALERT_N VTTA VSS VSS VSS VTTA RSVD RSVD RSVD DDR1_DQ[16] VSS DDR1_DQ[18] DDR1_DQ[28] RSVD DDR1_DQ[30] RSVD RSVD DDR1_CKE[0] DDR1_ODT[0] DDR1_CS_N[5] RSVD VSS DDR1_DQ[32] DDR1_DQS_DN[04]

DDR_VREFDQTX_C01 BCLK0_DP RSVD RSVD RSVD VSS RSVD VSS VSS VSS VSS VSS DDR1_DQ[19] VSS RSVD VSS DDR0_CKE[3] DDR1_DQ[01] VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 DDR1_DQ[33] DDR1_DQS_DP[04] DDR1_DQ[35] VSS RSVD DDR1_DQ[00] VSS VSS VSS VSS VSS VSS VSS RSVD VSS

SSTL

GND

CR27 CR29

SSTL SSTL

I/O I/O

GND GND GND GND GND SSTL GND I/O

CR3 CR31 CR33 CR35 CR37 CR39 CR41 CR43

SSTL GND SSTL SSTL SSTL CMOS PWR GND GND GND PWR

I/O

I/O I/O I/O I

GND SSTL SSTL PWR PWR PWR PWR PWR SSTL SSTL SSTL GND I/O I/O I/O O I/O

CR45 CR47 CR49 CR5 CR51 CR53 CR55 CR57 CR7 CR9 CT10 CT12 CT14

SSTL GND SSTL SSTL

I/O

I/O I/O

SSTL GND GND GND GND GND GND GND

I/O

CT16 CT18 CT2 CT20 CT22 CT24 CT26 CT28 CT30

SSTL

I/O

SSTL SSTL SSTL

O O O

GND SSTL SSTL I/O I/O

GND

CT32

110

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Table 8-2.
Land No. CT34 CT36 CT38 CT4 CT40 CT42 CT44 CT46 CT48 CT50 CT52 CT54 CT56 CT58 CT6 CT8 CU1 CU11 CU13 CU15 CU17 CU19 CU21 CU23 CU25 CU27 CU29 CU3 CU31 CU33 CU35 CU37 CU39 CU41 CU43 CU45 CU47 CU49 CU5 CU51 CU53 CU55 CU57 CU7 CU9

Land Number (Sheet 29 of 45)

Land Name DDR1_DQ[34] DDR1_DQ[52] RSVD Buffer Type Direction SSTL SSTL I/O I/O

Table 8-2.
Land No. CV10 CV12 CV14

Land Number (Sheet 30 of 45)

Land Name DDR1_DQ[23] DDR1_DQ[29] VSS DDR1_DQ[31] VSS DDR1_DQ[06] DDR1_CLK_DN[0] DDR1_CLK_DN[1] DDR1_CLK_DP[2] DDR1_ODT[3] DDR1_WE_N VSS VSS VSS DDR1_DQ[53] VSS DDR1_DQ[02] DDR1_DQ[55] VSS RSVD RSVD RSVD RSVD RSVD VSS RSVD VSS VSS GND GND SSTL I/O O GND GND GND CMOS1.5v PWR PWR PWR PWR PWR GND SSTL GND GND GND GND I/O I GND Buffer Type Direction SSTL SSTL GND SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND SSTL GND SSTL SSTL GND I/O I/O I/O I/O O O O O O I/O I/O I/O

DDR1_DQS_DN[00] DDR1_DQ[54] VSS RSVD RSVD RSVD RSVD RSVD TRST_N RSVD RSVD DDR1_DQ[21] RSVD VSS VSS DDR1_DQ[25] DDR1_DQS_DP[03] DDR1_DQ[27] DDR1_CKE[1] RSVD DDR1_CS_N[1] DDR1_CS_N[4] RSVD DDR1_DQ[36] VSS RSVD DDR1_DQ[38] VSS DDR1_DQ[49] DDR1_DQS_DP[06] DDR1_DQ[51] RSVD RSVD RSVD RSVD VSS CORE_VREF_CAP RSVD RSVD RSVD DDR1_DQ[17] DDR1_DQS_DP[02]

SSTL SSTL GND

I/O I/O

CV16 CV18 CV2 CV20 CV22 CV24 CV26 CV28

CMOS

CV30 CV32 CV34

SSTL

I/O

CV36 CV38

GND GND SSTL SSTL SSTL SSTL I/O I/O I/O O

CV4 CV40 CV42 CV44 CV46 CV48 CV50

SSTL SSTL

O O

CV52 CV54 CV56

SSTL GND

I/O

CV58 CV6 CV8

DDR1_DQS_DN[02] TEST1 VSS VSS VSS DRAM_PWR_OK_C01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VSS DDR1_DQ[07] VSS VSS VSS VSS

SSTL GND SSTL SSTL SSTL

I/O

CW1 CW11

I/O I/O I/O

CW13 CW15 CW17 CW19 CW21 CW23 CW25

GND I/O

CW27 CW29 CW3 CW31 CW33

SSTL SSTL

I/O I/O

CW35 CW37

Datasheet, Volume 1

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Table 8-2.
Land No. CW39 CW41 CW43 CW45 CW47 CW49 CW5 CW51 CW53 CW55 CW57 CW7 CW9 CY10 CY12 CY14 CY16 CY18 CY2 CY20 CY22 CY24 CY26 CY28 CY30 CY32 CY34 CY36 CY38 CY4 CY40 CY42 CY44 CY46 CY48 CY50 CY52 CY54 CY56 CY58 CY6 CY8 D10 D12 D14

Land Number (Sheet 31 of 45)

Land Name VSS DDR_SDA_C01 RSVD RSVD RSVD RSVD VSS VSS VSS VSS VSS VSS DDR1_DQ[22] VSS VSS RSVD VSS DDR1_CKE[2] VSS DDR1_CLK_DP[0] DDR1_CLK_DP[1] DDR1_CLK_DN[2] DDR1_ODT[2] RSVD DDR1_CAS_N DDR1_DQ[45] SSTL SSTL SSTL GND O I/O I/O GND SSTL GND SSTL SSTL SSTL SSTL O O O O O GND GND GND GND GND GND SSTL GND GND I/O Buffer Type Direction GND ODCMOS I/O

Table 8-2.
Land No. D16 D18 D2 D20 D22 D24 D26 D32 D34 D36 D38 D4 D40 D42 D44 D46 D48 D50 D52 D54 D56 D6 D8 DA11 DA13 DA15 DA17 DA19 DA21

Land Number (Sheet 32 of 45)

Land Name RSVD DDR3_MA[10] VSS DDR3_MA[04] DDR3_MA[08] DDR3_MA[14] VSS DDR3_DQ[18] RSVD VSS GND SSTL I/O O SSTL PCIEX PCIEX I/O O O SSTL GND SSTL SSTL SSTL GND SSTL I/O O O O O Buffer Type Direction

DDR3_DQS_DP[00] TEST3 DDR3_DQ[05] DMI_TX_DN[0] DMI_TX_DN[2] RSVD DMI_RX_DN[1] DMI_RX_DN[3] PE1A_RX_DP[1] PE1A_RX_DP[2] RSVD DDR3_DQ[53] VSS VSS DDR1_ECC[4] DDR1_ECC[6] DDR1_CKE[3] DDR1_MA[09] DDR1_CLK_DN[3] DDR1_MA[03] DDR1_ODT[1] RSVD RSVD VSS DDR1_DQ[44] DDR1_DQ[40] DDR1_DQ[43] DDR1_DQ[60] DDR1_DQ[62] VSS VSS VSS VSS VTTA VSS

PCIEX PCIEX PCIEX3 PCIEX3

I I I I

SSTL GND GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O

I/O I/O O O O O O

DDR1_DQS_DN[05] VSS RSVD DDR1_DQ[03] VSS DDR_SCL_C01 VSS RSVD RSVD VSS VSS RSVD RSVD RSVD DDR1_DQ[12] VSS DDR3_DQS_DP[04] DDR3_DQ[32] RSVD

SSTL GND ODCMOS GND

I/O

DA23 DA25

I/O

DA27 DA29 DA3 DA31

GND SSTL SSTL SSTL SSTL SSTL GND GND GND GND PWR GND I/O I/O I/O I/O I/O

GND GND

DA33 DA35 DA37 DA39 DA41

SSTL GND SSTL SSTL

I/O

DA43 DA45

I/O I/O

DA47 DA49 DA5

112

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Table 8-2.
Land No. DA51 DA53 DA55 DA57 DA7 DA9 DB10 DB12 DB14 DB16 DB18 DB2 DB20 DB22 DB24 DB26 DB28 DB30 DB32 DB34 DB36 DB38 DB4 DB40 DB42 DB44 DB46 DB48 DB50 DB52 DB54 DB56 DB58 DB6 DB8 DC11 DC13 DC15 DC17 DC19 DC21 DC23 DC25 DC3 DC33

Land Number (Sheet 33 of 45)

Land Name VSS RSVD RSVD RSVD DDR1_DQ[08] VSS DDR1_DQ[14] VSS RSVD DDR1_ECC[3] DDR1_MA[14] VSS DDR1_MA[08] DDR1_MA[04] DDR1_CS_N[0] DDR1_BA[0] DDR1_RAS_N DDR1_MA[13] VSS SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL GND I/O O O O O O O I/O O SSTL GND SSTL GND I/O I/O Buffer Type Direction GND

Table 8-2.
Land No. DC35 DC37 DC39 DC41 DC43 DC45 DC47 DC49 DC5 DC51 DC53 DC55 DC7 DC9 DD10 DD12 DD14 DD16 DD18 DD20 DD22 DD24

Land Number (Sheet 34 of 45)

Land Name DDR1_DQ[42] DDR1_DQ[61] Buffer Type Direction SSTL SSTL SSTL GND I/O I/O I/O

DDR1_DQS_DP[07] VSS RSVD RSVD RSVD RSVD VSS RSVD RSVD RSVD DDR1_DQ[09] DDR1_DQS_DN[01] VSS VSS VSS DDR1_ECC[2] VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 DDR1_DQ[41] VSS VSS VSS DDR1_DQ[58] RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSS RSVD DDR1_DQ[11] DDR1_ECC[0] DDR1_DQS_DN[08] VSS DDR1_MA[11] DDR1_MA[06] DDR1_MA[01] RSVD

GND

SSTL SSTL GND GND GND SSTL PWR PWR PWR PWR PWR SSTL GND GND GND SSTL

I/O I/O

I/O

DDR1_DQS_DP[05] VSS RSVD TEST0 DDR1_DQ[59] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSS DDR1_DQ[13] RSVD DDR1_DQ[10] DDR1_ECC[5] DDR1_DQS_DP[08] DDR1_MA[15] DDR1_MA[12] DDR1_CLK_DP[3] DDR1_MA[00] DDR1_BA[1] VSS RSVD

O SSTL I/O

DD26 DD32 DD34 DD36 DD38 DD40 DD42 DD44 DD46 DD48

I/O

I/O

GND SSTL I/O

DD50 DD52 DD54

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND

I/O I/O I/O O O O O O

DD6 DD8 DE11 DE13 DE15 DE17 DE19 DE21 DE23 DE25

GND

SSTL SSTL SSTL GND SSTL SSTL SSTL

I/O I/O I/O

O O O

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113

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Table 8-2.
Land No. DE33 DE35 DE37 DE39 DE41 DE43 DE45 DE47 DE49 DE51 DE53 DE55 DE7 DE9 DF10 DF12 DF14 DF16 DF18 DF20 DF22 DF24 DF26 DF34 DF36 DF38 DF40 DF42 DF44 DF46 DF48 DF50 DF52 DF8 E1 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29

Land Number (Sheet 35 of 45)

Land Name RSVD DDR1_DQ[47] DDR1_DQ[56] SSTL SSTL SSTL GND I/O I/O I/O Buffer Type Direction

Table 8-2.
Land No. E3 E31 E33 E35 E37 E39 E41 E43 E45 E47

Land Number (Sheet 36 of 45)

Land Name VSS VSS Buffer Type Direction GND GND SSTL SSTL SSTL I/O I/O I/O

DDR3_DQS_DP[02] DDR3_DQ[20] DDR3_DQ[03] RSVD VSS DMI_TX_DN[1] DMI_TX_DN[3] DMI_RX_DN[0] DMI_RX_DN[2] VSS PE1A_RX_DN[0] RSVD PE1A_RX_DP[3] RSVD DDR3_DQ[48] DDR3_DQ[35] DDR3_DQ[38] DDR3_DQ[36] RSVD RSVD DDR3_ODT[1] TEST2 DDR3_MA[02] DDR3_MA[06] DDR3_MA[15] DDR3_ECC[6] RSVD DDR3_ECC[4] DDR3_DQ[19] DDR3_DQ[17] VSS DDR3_DQ[06] DDR3_DQ[60] DDR3_DQ[04] VSS VSS RSVD VSS VSS PE1A_RX_DN[1] PE1A_RX_DN[2] RSVD RSVD

DDR1_DQS_DN[07] VSS RSVD RSVD RSVD RSVD RSVD VSS RSVD VSS DDR1_DQS_DP[01] DDR1_DQ[15] VSS DDR1_ECC[1] DDR1_ECC[7] DDR1_BA[2] DDR1_MA[07] DDR1_MA[05] DDR1_MA[02] DDR1_MA[10] DDR1_DQ[46] VSS DDR1_DQ[57] DDR1_DQ[63] VSS VSS VSS VSS VSS VSS VSS VSS RSVD MEM_HOT_C23_N RSVD DDR3_ODT[2] DDR3_BA[1] DDR3_MA[01] DDR3_MA[12] DDR3_ECC[2] DDR3_DQS_DP[08] VSS

GND PCIEX PCIEX PCIEX PCIEX GND PCIEX3 I O O I I

GND

E49 E5

GND SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL GND GND GND GND GND GND GND GND I/O I/O I/O I/O O O O O O I/O I/O I/O

E51 E53 E55 E57 E7 E9 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F28 F30 F32 F34 F36 F38 F4 F40

PCIEX3

SSTL SSTL SSTL SSTL

I/O I/O I/O I/O

SSTL

O O

SSTL SSTL SSTL SSTL

O O O I/O

SSTL SSTL SSTL GND SSTL SSTL SSTL GND GND

I/O I/O I/O

I/O I/O I/O

ODCMOS

I/O

F42 F44

SSTL SSTL SSTL SSTL SSTL SSTL GND

O O O O I/O I/O

F46 F48 F50 F52 F54 F56 F58

GND GND PCIEX3 PCIEX3 I I

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Table 8-2.
Land No. F6 F8 G1 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G3 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G5 G51 G53 G55 G57 G7 G9 H10 H12 H14 H16 H18 H2 H20 H22 H24 H26 H28 H30 H32 H34

Land Number (Sheet 37 of 45)

Land Name DDR3_DQ[49] VSS VSS RSVD VCCD_23 RSVD DDR3_CS_N[5] DDR3_CS_N[0] RSVD DDR3_MA[09] VSS SSTL GND SSTL SSTL SSTL GND SSTL GND GND I/O I/O I/O I/O O SSTL SSTL O O PWR Buffer Type Direction SSTL GND GND I/O

Table 8-2.
Land No. H36 H38 H4 H40 H42 H44 H46 H48 H50 H52 H54 H56 H58 H6 H8 J1 J11 J13 J15

Land Number (Sheet 38 of 45)

Land Name DDR3_DQ[15] VSS DDR3_DQ[61] VSS PE1A_TX_DP[0] PE1A_TX_DP[2] PE1B_TX_DP[4] PE1B_TX_DP[6] PE3A_TX_DP[0] VSS VSS RSVD RSVD RSVD VSS GND DC GND SSTL I/O I Buffer Type Direction SSTL GND SSTL GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND GND O O O O O I/O I/O

DDR3_DQS_DN[08] DDR3_ECC[0] DDR3_DQ[56] VSS DDR3_DQS_DN[02] VSS VSS RSVD VSS VSA VSS VSS VSA VSS VSS VSS PE1A_RX_DN[3] VSS RSVD VSS VSS VSS VSS VCCD_23 VCCD_23 DDR3_DQ[57] VCCD_23 VCCD_23 VCCD_23 DDR3_ECC[7] RSVD DDR3_ECC[5] VSS VSS

DDR_VREFDQRX_C23 VSS DDR3_DQ[40] RSVD DDR3_ODT[3] DDR3_CS_N[1] DDR3_CLK_DN[1] DDR3_CLK_DN[0] DDR3_CKE[2] VSS DDR3_ECC[1] RSVD VSS VSS DDR3_DQ[11] DDR3_DQS_DP[01] VSS VSS PE1A_TX_DP[1] PE1A_TX_DP[3] PE1B_TX_DP[5] PE1B_TX_DP[7] VSS PE3A_TX_DP[1] PE1B_RX_DP[4] VSS PE1B_RX_DP[6] DDR3_DQS_DN[06] DDR3_DQ[42] DDR3_DQ[46]

GND PWR GND GND PWR GND GND GND PCIEX3 GND I

J17 J19 J21 J23 J25 J27 J29 J3 J31 J33 J35

SSTL SSTL SSTL SSTL SSTL GND SSTL

O O O O O

I/O

GND GND SSTL SSTL GND GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 PCIEX3 GND PCIEX3 SSTL SSTL SSTL I I/O I/O I/O O I O O O O I/O I/O

GND GND GND GND PWR PWR SSTL PWR PWR PWR SSTL I/O I/O

J37 J39 J41 J43 J45 J47 J49 J5 J51 J53 J55 J57

SSTL GND GND

I/O

J7 J9 K10

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Table 8-2.
Land No. K12 K14 K16 K18 K2 K20 K22 K24 K26 K28 K30 K32 K34 K36 K38 K4 K40 K42 K44 K46 K48 K50 K52 K54 K56 K58 K6 K8 L1 L11 L13 L15 L17 L19 L21 L23 L25 L27 L29 L3 L31 L33 L35 L37 L39

Land Number (Sheet 39 of 45)

Land Name RSVD DDR3_DQ[44] RSVD DDR3_CS_N[4] VSS DDR3_CLK_DP[2] DDR3_CLK_DN[3] DDR3_CKE[0] VSS VSS VSS DDR3_DQ[29] VSS DDR3_DQ[14] RSVD RSVD DDR3_DQ[13] PE1A_TX_DN[0] PE1A_TX_DN[2] PE1B_TX_DN[4] PE1B_TX_DN[6] PE3A_TX_DN[0] PMSYNC PE1B_RX_DP[5] PE1B_RX_DP[7] RSVD SSTL PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 CMOS PCIEX3 PCIEX3 I/O O O O O O I I I SSTL GND SSTL SSTL SSTL GND GND GND SSTL GND SSTL I/O I/O O O O O SSTL I/O Buffer Type Direction

Table 8-2.
Land No. L41 L43 L45 L47 L49 L5 L51 L53 L55 L57 L7 L9 M10 M12 M14 M16 M18 M2 M20 M22 M24 M26 M28 M30 M32 M34

Land Number (Sheet 40 of 45)

Land Name VSS PE1A_TX_DN[1] PE1A_TX_DN[3] PE1B_TX_DN[5] PE1B_TX_DN[7] VSS PE3A_TX_DN[1] PE1B_RX_DN[4] PE2A_RX_DP[0] PE1B_RX_DN[6] DDR3_DQ[54] DDR3_DQ[43] DDR3_DQ[47] RSVD DDR3_DQ[45] RSVD RSVD DDR3_DQ[63] DDR3_CLK_DN[2] DDR3_CLK_DP[3] DDR3_CKE[1] DDR3_DQ[31] DDR3_DQ[26] RSVD DDR3_DQ[24] VSS VSS RSVD SSTL GND GND I/O SSTL SSTL SSTL SSTL SSTL SSTL I/O O O O I/O I/O SSTL I/O Buffer Type Direction GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 SSTL SSTL SSTL O I I I I/O I/O I/O O O O O

DDR3_DQS_DP[06] VSS DDR3_DQ[62] DDR3_DQS_DN[05] DDR3_DQ[41] DRAM_PWR_OK_C23 DDR2_BA[1] DDR3_ODT[0] DDR3_CLK_DP[1] DDR3_CLK_DP[0] VSS DDR3_DQ[27] VSS DDR3_DQS_DN[07] DDR3_DQ[25] DDR3_DQ[28] DDR3_DQ[10] DDR3_DQS_DN[01] DDR3_DQ[09]

SSTL GND SSTL SSTL SSTL CMOS1.5v SSTL SSTL SSTL SSTL GND SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL

I/O

M36 M38

I/O I/O I/O I O O O O

M4 M40 M42 M44 M46 M48 M50 M52 M54

DDR3_DQS_DP[07] DDR3_DQ[12] VSS VSS VSS RSVD VSS VSS PE1B_RX_DN[5] PE1B_RX_DN[7] DDR3_DQ[55] VSS DDR3_DQS_DP[05] VSS VCCD_23 VCCD_23 VCCD_23

SSTL SSTL GND GND GND

I/O I/O

GND GND PCIEX3 PCIEX3 SSTL GND SSTL GND PWR PWR PWR I/O I I I/O

I/O

M56 M6

I/O I/O I/O I/O I/O I/O

M8 N11 N13 N15 N17 N19

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Table 8-2.
Land No. N21 N23 N25 N27 N29 N3 N31 N33 N35 N37 N39 N41 N43 N45 N47 N49 N5 N51 N53 N55 N7 N9 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38 P4 P40 P42 P44 P46 P48 P50 P52

Land Number (Sheet 41 of 45)

Land Name VCCD_23 VCCD_23 DDR3_CKE[3] DDR3_DQ[30] Buffer Type Direction PWR PWR SSTL SSTL SSTL SSTL O I/O I/O I/O

Table 8-2.
Land No. P54 P56 P6 P8 R11 R13 R15

Land Number (Sheet 42 of 45)

Land Name VSS VSS DDR3_DQ[51] VSS VSS DDR2_DQ[48] DDR2_MA[13] DDR2_BA[0] DDR2_MA[01] DDR2_MA[06] DDR2_MA[09] RSVD RSVD VSS VSS VSS DDR2_DQ[17] VSS DDR2_DQ[06] VSS DDR2_DQ[04] DDR_SDA_C23 PE3C_TX_DP[10] PE3A_TX_DP[2] PE3B_TX_DP[7] VSS PE3B_TX_DP[5] PRDY_N VSS VSS DDR2_DQ[54] DDR2_DQ[50] RSVD DDR2_DQ[52] DDR2_CAS_N DDR2_MA[10] DDR2_MA[03] DDR2_MA[08] DDR2_MA[12] DDR2_CKE[1] VSS DDR2_DQ[23] RSVD DDR2_DQ[20] DDR2_DQ[03] SSTL SSTL I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL I/O I/O O O O O O O GND GND GND SSTL GND SSTL GND SSTL ODCMOS PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 CMOS GND GND SSTL SSTL I/O I/O O O I/O I/O O O O I/O I/O Buffer Type Direction GND GND SSTL GND GND SSTL SSTL SSTL SSTL SSTL SSTL I/O O O O O O I/O

DDR3_DQS_DP[03] DDR3_DQ[58] RSVD VSS VSS VSS DDR3_DQ[08] VSS VSS VSA VSS VSS VSS VSA VSS PE2A_RX_DN[0] DDR3_DQ[50] VSS VSS VSS VSS DDR2_WE_N DDR2_CS_N[5] DDR2_MA[04] DDR2_MA[07] DDR2_BA[2] VSS DDR3_DQS_DN[03] VSS VSS DDR2_DQ[21] DDR2_DQ[02] VSS DDR3_DQ[59] VSS DDR_VREFDQTX_C23 PE3D_TX_DN[15] PE3C_TX_DP[8] PE3A_TX_DP[3] PE3B_TX_DP[6] PE3B_TX_DP[4]

GND GND GND SSTL GND GND PWR GND GND GND PWR GND PCIEX3 SSTL GND GND GND GND SSTL SSTL SSTL SSTL SSTL GND SSTL GND GND SSTL SSTL GND SSTL GND DC PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 O O O O O O I/O I/O I/O I/O O O O O O I I/O I/O

R17 R19 R21 R23 R25 R27 R29 R3 R31 R33 R35 R37 R39 R41 R43 R45 R47 R49 R5 R51 R53 R55 R7 R9 T10 T12 T14 T16 T18 T20 T22 T24 T26 T28 T30 T32 T34 T36

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Table 8-2.
Land No. T38 T4 T40 T42 T44 T46 T48 T50 T52 T54 T56 T6 T8 U11 U13 U15 U17 U19 U21 U23 U25 U27 U29 U3 U31 U33 U35 U37 U39 U41 U43 U45 U47 U49 U5 U51 U53 U55 U7 U9 V10 V12 V14 V16 V18

Land Number (Sheet 43 of 45)

Land Name Buffer Type Direction SSTL GND SSTL GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND GND SSTL SSTL Analog SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL I/O I/O I/O I O O O O O O I/O I/O I/O I/O O O O O O I I I/O I/O

Table 8-2.
Land No. V20 V22 V24 V26 V28 V30 V32 V34 V36 V38 V4 V40 V42 V44 V46 V48 V50 V52 V54 V56 V6 V8 W11 W13 W15 W17 W19 W21 W23

Land Number (Sheet 44 of 45)

Land Name VCCD_23 VCCD_23 VCCD_23 VSS VSS DDR2_DQ[22] RSVD VSS VSS GND GND SSTL SSTL SSTL GND GND GND GND GND I/O I/O I/O Buffer Type Direction PWR PWR PWR GND GND SSTL I/O

DDR2_DQS_DN[00] VSS DDR2_DQ[00] VSS PE3D_TX_DP[15] PE3C_TX_DN[8] PE3A_TX_DN[3] PE3B_TX_DN[6] PE3B_TX_DN[4] PE2A_RX_DP[1] PE2A_RX_DP[2] VSS VSS DDR2_DQS_DN[06] DDR2_DQ[49] DDR23_RCOMP[0] DDR2_RAS_N DDR2_MA[02] DDR2_MA[05] DDR2_MA[11] DDR2_MA[15] DDR2_CKE[2] DDR2_DQ[19] DDR2_DQ[60] DDR2_DQS_DP[02] DDR2_DQ[16] VSS DDR2_DQ[07] RSVD DDR2_DQ[05] DDR_SCL_C23 PE3C_TX_DN[10] PE3A_TX_DN[2] PE3B_TX_DN[7] VSS PE3B_TX_DN[5] PREQ_N PE2A_RX_DP[3] DDR2_DQ[44] DDR2_DQ[55] DDR2_DQ[51] RSVD DDR2_DQ[53] VCCD_23 VCCD_23

DDR2_DQS_DP[00] DDR2_DQ[61] DDR2_DQ[01] VSS VSS VSS VSS VSS RSVD PE2A_RX_DN[1] PE2A_RX_DN[2] DDR2_DQ[40] VSS DDR2_DQS_DP[06] VSS RSVD RSVD DDR2_ODT[1] DDR2_CLK_DN[2] DDR2_CLK_DN[3] DDR2_MA[14] DDR2_ECC[6] DDR2_DQ[18] DDR2_DQ[56] DDR2_DQS_DN[02] VSS DDR2_DQ[29] VSS RSVD VSS VSS VSS VSS VTTA VSS VSS

PCIEX3 PCIEX3 SSTL GND SSTL GND

I I I/O

I/O

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL GND

O O O O I/O I/O I/O I/O

SSTL ODCMOS PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 CMOS PCIEX3 SSTL SSTL SSTL

I/O I/O O O O

W25 W27 W29 W3 W31 W33

O I/O I I/O I/O I/O

W35 W37 W39 W41 W43 W45 W47

I/O

GND GND GND GND PWR GND GND

SSTL PWR PWR

I/O

W49 W5 W51

118

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Processor Land Listing

Table 8-2.
Land No. W53 W55 W7 W9 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y24 Y26 Y28 Y30 Y32 Y34 Y36 Y38 Y4 Y40 Y42 Y44 Y46 Y48 Y50 Y52 Y54 Y56 Y6 Y8

Land Number (Sheet 45 of 45)

Land Name VSS PE2A_RX_DN[3] DDR2_DQ[45] VSS VSS VSS DDR23_RCOMP[2] RSVD DDR2_ODT[3] DDR2_ODT[0] DDR2_CLK_DN[1] DDR2_CLK_DN[0] DDR2_ECC[2] VSS VSS VSS RSVD VSS VSS DDR2_DQ[57] VSS VSS PE3D_TX_DP[13] PE3C_TX_DP[11] RSVD PE3B_RX_DP[4] PE3B_RX_DP[5] VTTA VSS DDR2_DQ[41] RSVD PCIEX3 PCIEX3 PWR GND SSTL I/O I I GND GND SSTL GND GND PCIEX3 PCIEX3 O O I/O SSTL SSTL SSTL SSTL SSTL GND GND GND O O O O I/O Buffer Type Direction GND PCIEX3 SSTL GND GND GND Analog I I I/O

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Package Mechanical Specifications

Package Mechanical Specifications

For mechanical specifications and design guidelines refer to the Intel Core i7 Processor Family for the LGA-2011 Socket Thermal Mechanical Specification and Design Guide.

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Package Mechanical Specifications

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