Mentor Paper 52590 BGA Fanout Breakout
Mentor Paper 52590 BGA Fanout Breakout
Mentor Paper 52590 BGA Fanout Breakout
Charles Pfeil
Charles Pfeil
8/26/2008
Very large BGAs, over 1500 pins, present a unique challenge for routing on a printed circuit board. Often just routing out of the BGA is the primary contributor to the number of layers required for routing. This book presents a number of studies and solutions for addressing these challenges.
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expressed or implied. This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. Contractor is: Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777 Telephone: 503.685.7000 Toll-Free Telephone: 800.592.2210 Website: www.mentor.com SupportNet: www.mentor.com/supportnet Contact the author: [email protected] TRADEMARKS: The trademarks, logos and service marks (Marks) used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. A current list of Mentor Graphics trademarks may be viewed at: www.mentor.com/terms_conditions/trademarks.cfm
Acknowledgments
I gratefully acknowledge those who contributed material, ideas, and review during the production of this book. My colleagues at Mentor Graphics who provided review, discussion and feedback on various aspects of the content: Happy Holden Steve Kaufer Chuck Ferry Kendall Hiles Mentor Graphics SDD customers who took the time to meet with me and discuss the issues: Vern Wnek and Kevin Seaman, Broadcom Aydin Cokoyoglu, Alcatel-Lucent Shaun Olsen, Intel Kathy Brady, Raytheon Larry Paul and Andy Green, Qualcomm The software and package design team at Xilinx who provide feedback on my research with the Virtex-4 and Virtex-5 devices. The Marcom team at Mentor Graphics who provided review and produced the finished copy: Leslie Van Grove Mark Forbes
Table of Contents
Preface Second Edition ....................................................................... v Chapter One - Introduction ...................................................................1 Expedition PCB ............................................................................... 2 Figures ............................................................................................ 2 Definitions ...................................................................................... 2 Via Types ........................................................................................ 6 Stackup Types................................................................................. 6 The Problem ................................................................................. 12 Solutions ....................................................................................... 15 Chapter Two - BGA Packages .............................................................. 17 High Pin Counts ............................................................................ 17 Impact on Routing, Performance and Cost .................................. 20 Off-Matrix Ball Pads ..................................................................... 22 0.8mm Pin-Pitch ........................................................................... 23 The Near Future ........................................................................... 24 Chapter Three - HDI Layer Stackups .................................................... 25 Fabrication Vendors ..................................................................... 25 Dependencies ............................................................................... 26 Overview of Stackup Types .......................................................... 27 HDI Stackup Details ...................................................................... 31 Via Models.................................................................................... 36 Plane Layer Assignments.............................................................. 39 Layer Count .................................................................................. 42 Design Rules ................................................................................. 43 Fanout Patterns ............................................................................ 43 Signal Integrity ............................................................................. 44 Recommended HDI Stackups ....................................................... 44 Secondary HDI Stackups............................................................... 48 Any-Layer-Via Stackups ................................................................ 52 Summary ...................................................................................... 53
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Chapter Four - Fanout Patterns ...........................................................55 Theoretical Breakout Methods ....................................................56 Signal Integrity Concerns..............................................................60 Minimizing the Variables ..............................................................61 Fanout Pattern Goals and Approach ............................................64 Through-Vias ................................................................................65 Drilled Blind and Buried-vias ........................................................78 HDI Micro-Vias..............................................................................89 Summary ......................................................................................94 Chapter Five - Layer Biased Breakouts ................................................95 Board Description .........................................................................95 General Assessment of Original Board.........................................95 Recommendations and Solutions ................................................96 Using Layer Biased Breakouts ......................................................97 Fanouts for Micro-Via Layers .....................................................101 Route Results..............................................................................119 Summary ....................................................................................120 Chapter Six - 0.8mm Pin-Pitch BGA Tests .......................................... 121 Test Scenario ..............................................................................121 Test 1: Through-Vias...................................................................124 Test 2: Micro-Vias and Through-Vias .........................................134 Test 3: Any-Layer-Vias ................................................................149 Summary ....................................................................................163 Chapter Seven - Software for Generating BGA Fanouts ..................... 165 Method .......................................................................................166 Regions .......................................................................................167 Adding Blind and Through-Vias ..................................................168 Adding Buried Vias .....................................................................170 Additional Example ....................................................................173 Conclusion ........................................................................................ 175 About the Author .............................................................................. 177
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BGA Breakouts and Routing over the last 18 months and have come from extensive evaluation of various BGA packages and real PCB designs.
Expedition PCB
All the figures showing PCB design graphics are screen captures from Mentor Graphics ExpeditionTM PCB. The cover image was created using the prototype Expedition PCB 3D Viewer. The fanouts were created using the existing fanout and copy trace routines, and the escape traces were mostly added using prototype automatic routing software. These capabilities and more related to BGA breakouts and routing are available in the 2007.3 release of Mentors Expedition PCB and Board Station XE suite of tools.
Figures
There are more than a hundred figures in this book showing details about BGA breakouts. I encourage you to study them with the intent of finding techniques and tricks that will help you route these challenging devices. With all the variables involved in routing of large BGAs, my specific examples may not map directly to your experiences; however, you should be able to discover principles that can, at a minimum, give you some new ideas that will enable greater route density, a reduction in layer count and help bring your products to market faster.
Definitions
These definitions are in the context of BGA breakouts and routing. Breakout - The combination of fanouts and escape traces, which allow routing out of the BGA pin array to the perimeter of the device prior to general routing of the PCB. See figures 1-1 and 1-2.
BGA Break kouts and Rou uting Fanout Pattern When adding fanou to the BGA enabling rou n uts A, uting on the inner layer the pattern may vary considerably depending on th layer rs, n he stackup, vi model, and pin density. The pattern m range from simple ia T may m quadrant-m matrix to a set of complex alternating arrangements. Using the a appropriat fanout patt te tern will make a significant difference on the success e of breakou and routing of the BGA. ut g
Figure 1-4: Shifte fanouts wit more space for escape traces ed th e 4
Figure 1-5: Multiple fanout patterns using blind, buried and through vias
Via Types
Through-Via A via that extends from the top to the bottom of the board. Through-vias are usually mechanically drilled and require an aspect ratio of 10/1 (length to hole diameter) for acceptable yields often an aspect ratio of 8/1 is defined as the goal. It is usually larger than any other type of via, and as such, restricts routing space compared to smaller via types. Blind-Via A via that begins on an outer layer and ends on an inner layer. Usually it will span 2-3 layers; however, there are no layer span restrictions except for those imposed by keeping the aspect ratio below 1/1 (length to hole diameter). The term is used to describe vias that extend from an outer layer to an inner layer in a sequentially laminated stackup (simply called blind-vias) and an HDI buildup stackup (called blind micro-vias). Buried-Via This type of via starts and ends on an inner layer. The buried-via is used in combination with blind-vias in a sequentially laminated stackup, and micro-vias in an HDI buildup stackup. Micro-Via This via has a hole diameter less than or equal to 0.15mm (6th). Generally it is laser drilled. Micro-vias may be a blind-via or buried-via and are used in HDI stackups. Any Layer-Via These are short micro-vias that individually span only a pair of layers and are stacked together to result in a span between any two layers.
Stackup Types
There many different stackups using different via spans, via types, layer counts, and materials. Most stackups in production fall into these categories: laminated with through-vias, laminated with blind and buried6
Chapter One Introduction vias, and HDI buildup with micro-vias. The most common stackups are discussed in terms of route density, cost, signal integrity, and power integrity in Chapter 3, Layer Stackups.
Figure 1-7: Laminated with blind and buried-vias Red = Blind-via, Orange = Buried-via
HDI Buildup with Micro-Vias There are many variations of HDI of which here are a few:
BGA Breakouts and Routing NSEW Breakout North, South, East, and West routing of the escape traces. This means the escape traces are routed in all four directions on the same layer.
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Chapter One Introduction Layer Bia ased Breakout The escape traces are ro t e outed in the direction of the layer bias as oppos to NSEW routing. Escap traces are a routed in sed r pe also ording to the l layer bias. the direction of the connection acco
The Problem
The increasing pin-count and decreasing pin pitch of BGAs amplify already difficult design problems. Maintaining signal integrity at high performance levels and reducing fabrication costs are arguably the two most important requirements. Unfortunately, these requirements are conflicting. Reducing crosstalk is generally accomplished by increasing the space between conductors which can increase layer count, plus routing dense BGA packages require smaller design rules and more layers. Smaller features and increasing layers contribute significantly to board cost. This is nothing new; yet further miniaturization of BGA packages will make it even more difficult to maintain performance and cost goals. Many PCB designers who are designing with large pin-count BGAs (over 1500 pins) claim that the breakout of the device is the greatest contributor to increased number of PCB layers. An effective breakout solution will provide the foundation for layer reduction. I use the phrase BGA breakout to describe the method of applying a fanout solution and routing escape traces from those fanouts to the perimeter of the device prior to general routing of the PCB. Why have breakouts? Why not just route the device without breakouts? The answer is simple. If the BGA device has too many pins in a dense array, the only way to minimize the number of layers is to utilize all the available space inside the component area with a pattern of fanouts and breakout traces. Routing such a device without an effective pattern will certainly waste space and require more layers.
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Figure 1-12: BGA breakout - 1760 Pins, 1mm pitch, fanout vias, and traces on multiple layers Not all BGAs present a routing challenge. Low pin-count devices (less than 800 pins), even with a pin-pitch of less than 0.8 mm, do not present a significant breakout problem and are usually routed without a breakout method. This means the pins are generally accessible and can be routed with a reasonable number of layers. The high pin-count devices (over 1500 pins) with a pin-pitch of 1mm or less require a strategy for getting the traces out of the array. Without a breakout strategy, the layer count will be excessive thus affecting the fabrication cost and reliability of the PCB. 13
Additional factors complicate the breakout process. To attain the performance and cost goals, these items must be defined and managed properly and in concert with each other. Layer Stackup Via Models Design Rules Signal Integrity Power Integrity
Layer Stackup - Early in the design process, the layer stackup will be defined. If the board has large and dense BGAs, High Density Interconnect (HDI) with a laminated core and buildup layers may be required. There are many different options using various materials and processes. Cost and reliability are usually the primary factors in determining the stackup and you will have to balance the tradeoff between layer count and fabrication processes to reach your goals. Via Models - Within the context of any given layer stackup, you have many options regarding via models. The decision on which type of via to use (thru, laminated blind and buried or HDI micro vias) will likely be driven by the density of the board and the BGA packages. There are also options regarding vias inside pads and stacking that affect cost. In addition to this, board fabricators tend to focus on a limited set of processes thereby limiting your choice of vendors, depending on the technology you desire. From the design point of view, choosing the appropriate via models directly impacts the route-ability of the board. Design Rules - PCB fabricators continue to find methods that allow for further miniaturization and increased reliability. The design rules have to balance the tradeoffs between cost, signal integrity, and route-ability. Signal Integrity - Although the fabricators continue to improve their processes and produce reliable boards with smaller and features and clearances, maintaining signal integrity at high performance levels usually 14
Chapter One Introduction requires greater spacing between critical nets, especially to manage crosstalk effects at higher speeds. This conflict is exasperated with high pincount and dense BGAs. Choosing appropriate layer stackups and via models will not only improve route-ability but signal integrity as well. Power Integrity - Managing power distribution effectively for large pincount BGAs is a challenge and is significantly impacted by the layer stackup. There are methods that can minimize the number decoupling capacitors required, thereby increasing the space available for signal routing.
Solutions
Because of the high number of variables with any PCB design, it is not possible to have a single BGA breakout solution for all situations. It is possible however, to develop solutions within reasonable sets of variables. This book offers principles for breakouts that may be applied as appropriate within the constraints of your own designs. It is my hope that in addition to finding useful ideas and methods herein, your imagination will be stirred to discover unique solutions.
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Figure 2-1: TI GTM (N2377) BGA with 2377 pins at 1mm pitch You can immediately see that a BGA with over 2000 pins presents a daunting routing task. Of course some large percentage of the pins will be power and ground; but even figuring out a good fanout pattern for those pins so they dont block routing is a challenge. Even if 40% of the pins are for power distribution, potential for 1400 signal connections still exists.
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For the 1mm pitch BGAs, I consider a pin-count over 1500 to be one threshold for difficult routing. In the context of laminated FR-4 boards with through-vias, the following are some of the potential problems: Layer Count The sheer number of pins could require additional layers just to breakout the device. If you have multiple instances of BGAs over 1500 pins, then the route density will certainly force you to have more routing layers. Layer counts over 28 need thinner FR-4 dielectrics and de-lamination can occur at the lead-free assembly temperatures (at least 270 C). Via Aspect Ratio Maintaining high fabrication yields and long-term reliability requires the via length-to-hole diameter ratio to be less than 10:1, preferably 8:1. Boards with over 28 layers make it difficult to keep the through-via size small enough to allow effective routing. As the via pad size increases, it is more likely the differential pairs will have to be split during the breakout as well.
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Chapter Two BGA Packages Nightmare of Circular Dependencies High pin-counts dictate additional layers to route, additional layers require a larger via hole and pad size, and then larger vias reduce routing space, thus forcing additional layers. Once caught in this cycle, the best way to break out of it is to abandon through-vias and start using blind and buriedvias or HDI with applied dielectrics and micro-vias.
Greater than 2000 pins at 1mm pitch is a tipping point, especially if you have multiple instances of them on a single board as you might see in a network or emulation card. The layer count and via aspect ratio problems with laminated FR-4 boards will be even more severe with this many pins. When using blind and buried-vias or HDI micro-vias, effective fanout patterns can be used to increase route density from 24% to 36% with a corresponding layer reduction. Figure 2-2 shows increased route density on the first inner layer of a design when using blind-vias arranged in a pattern that allows for greater route density.
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0.8mm Pin-Pitch
The next figure not a real device, it just shows what could be done at 0.8mm pin-pitch in the same size package as the current 1mm pitch Virtex5. It could contain 3025 pins.
Figure 2-4: 3025 pins at 0.8mm pitch (not real) If you took the TI GTM (N2377) package and packed the pins in at 0.8mm instead of 1mm, it could have 3721 pins. 23
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Fabrication Vendors
Stackups should be designed in conjunction with the fabrication vendor to minimize cost and meet signal integrity requirements. The board fabrication vendor ultimately builds a board that meets your requirements 25
BGA Breakouts and Routing for cost, reliability, overall thickness, and impedance control. There may be additional requirements related to plating and specific materials. As a general rule, the vendor will adjust all the stackup variables as needed during their process to meet your goals. The most productive method is to collaborate with the vendor on a stackup prior to designing the board. That way, the fabricator will be able to make minimal adjustments to meet your goals. A good example of these adjustments is impedance control. Regardless of how carefully the stackup is defined with trace widths, material choices, dielectric and copper thicknesses, the fabrication process is not so exact. Each vendor has different equipment and methods. The lamination process shrinks the dielectrics and materials may be changed if not in stock or readily available. The tolerances in all areas add up and ultimately a reliable vendor has to make the right combination of adjustments in-process so that when measuring impedance on the test coupon, it fulfills your spec. Trace widths and material thicknesses may change a little but if the measured impedance is within spec then it really doesnt matter what changes were made as long as the other requirements are not fatally compromised of course. If the initial stackup is not defined properly, minor acceptable adjustments by the fabrication vendor will not be adequate to fulfill your overall requirements. A wise and experienced vendor will not accept the risk of making major changes to the design data.
Dependencies
Unfortunately there are many dependencies, some of them circular when defining a stackup. The process of determining an effective stackup can be overwhelming. Forgive the next meandering and confusing paragraph, but it is a good example of the difficult process of deciding which variables need to be compromised or emphasized to reach your goals:
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It is necessary to reduce the layer count to keep costs down. It is also required to have an adequate number of layers to route the board. On some of the largest PCBs, there are well over ten thousand nets to route. To control crosstalk, increase the spacing between traces which requires more layers. Also consider running the differential pairs together through the via array under the BGA, which means the via must be small enough to not only allow the diff pair to run together, but still space the traces far enough apart to attain the desired coupling. These traces also need to be the appropriate width in correlation to the thickness of the dielectrics and their material attributes to provide the desired impedance. But if you have too many layers, then the via needs to be bigger otherwise the aspect ratio of hole size to length becomes too great to drill with a good yield. If you make the via hole smaller, you can enable more dense routing but may sacrifice manufacturing yields. If you make the via hole larger, you may have to split the differential pairs through the via array and you will impact signal integrity and require more layers to breakout the BGA. If you have more layers, you will need an even larger via. These factors may require you to develop special fanout patterns in the context of the stackup to support the manufacturing, signal integrity and routing goals. This paragraph just touches a few of the dependencies; yet even so, it describes a daunting task. Where do you begin? A number of example stackups will be presented with the advantages and disadvantages itemized along with a basic description of which via models, design rules work best. Some signal and power integrity concerns will also be discussed.
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1. Standard Lamination with Through Vias Advantages o Low cost (until layer count becomes too high) o Simple via models o Simple dielectrics Primarily FR-4 o Mature process, everybody does it o High reliability (until layer count becomes too high) Disadvantages o If layer count becomes too high Fewer fabrication vendors can obtain good yields, costs skyrocket Board can delaminate under high temperatures required for ROHS lead-free soldering o Via has to be large, reducing route-ability, increasing layers o Difficult to implement for BGA pin-pitches below 1mm o Through hole vias capacitively couple to every plane layer and signal losses increase with thickness o Long via stubs create impedance mismatches, reflections on single-ended nets o Large via pads often force differential pairs to be split under BGAs Notes o There are a number of tipping points where standard lamination with through vias is not viable o Once the board is over 28 layers, it becomes difficult to manufacture with acceptable yields and therefore can become cost prohibitive. o If the board is over 28 layers, the dielectrics can be so thin that de-lamination can occur under the higher temperatures required for lead-free soldering. o Generally when using a few BGAs with less than 1500 pins and a 1mm pin-pitch, the breakout and routing of these devices is feasible using through vias.
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Chapter Three HDI Stackups o However, if you have a large number these on a single design, then the route density may force the layer count up high enough to limit the effectiveness of this stackup. o If you have multiple BGAs with over 1500 pins and 0.8mm pin-pitch (or less) it is likely that through vias will make it very difficult to route these devices. o When the thickness of the board due to the number of layers forces the via to be so large that it inhibits routeability. o Via length to hole diameter should be <10x otherwise reliability declines significantly o Pad diameter should be hole size plus 0.01 inch o If the via pad is so large that it prevents differential pairs or multiple single-ended traces from being routed between the BGA via arrays, then more layers will be required to complete the routing. o Vias can be shifted off the standard matrix under BGAs; however, with through vias, not much is gained. 2. Sequential Lamination with Blind and Buried Vias Advantages o Potentially shorter via stubs o Fairly simple via models o Generally smaller vias than required for through hole vias Minimum size for mechanically drilled vias are the same as for standard laminate; however blind and buried vias will likely have a smaller aspect ratio enabling more use of minimum via hole size, which is 8th. o Simple dielectrics Primarily FR-4 o Effective use of blind and buried vias opens up routing channels, potential for fewer layers Disadvantages o Not a widely adopted process, more and more fabricators do HDI instead o Minimum size for drilled vias is 8th 29
BGA Breakouts and Routing o Costs more than through hole laminated, yet minimum trace widths are still the same o Practical reliability limits the number of sequential laminations to 2 or 3 Notes o Sequentially laminated boards have the same tipping points as standard laminates; however, since the via length to hole size aspect ratio will be less and pad sizes can be smaller, route-ability improves and it is less likely that the design would exceed 28 layers. o Since the feature sizes for traces can vias are still the same as with standard laminate, designing with multiple large BGAs of < 1mm is very difficult. 3. Buildup with Micro-Vias (HDI) Advantages o Smaller feature sizes for vias and traces enables higher density and fewer layers o Effective use of micro-vias opens up routing channels, potential for fewer layers o Only practical way to design with multiple large BGAs having <0.8 mm pitch o Lowest cost for high density boards o Improved signal and power integrity with appropriate stackup definition o Materials do well in processes requiring ROHS o Newer materials available with higher performance and lower costs, which are not suitable for standard or sequential lamination Disadvantages o Complex via models with many variations and still evolving o Complex stackup definition o Effective design methods on large dense designs have not been widely understood and documentation is sparse o Predictive design guides and cost estimates not yet available 30
Chapter Three HDI Stackups o Although HDI fabrication is pervasive in PAC Rim and China, North America slow to adopt Notes o HDI is the best alternative to high layer-count and expensive standard laminate or sequentially laminated boards. o The trend is for higher pin-count and finer pin-pitch. The tipping point will occur when the >1500 pin BGAs use a .8mm pitch. o The only way to effectively breakout and route multiple instances of these devices on a single board will be with the smaller HDI feature sizes. o HDI currently dominates the fabrication technology for handheld and consumer electronics. For large board designs, it will continue to grow.
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HDI Type I
This construction uses both micro-vias and through-vias in a structure consisting of a laminated core and a single micro-via layer on at least one side.
Figure 3-1: IPC HDI Type I Notes The number of layers in the laminated core varies and is limited by two factors o The through-via should have an aspect ratio (total length to hole diameter) less than 10x to maintain reasonable reliability. o If the FR-4 dielectrics become too thin, they will delaminate under higher temperatures required for lead-free soldering. Recommendations In the context of large dense boards with multiple high pin-count BGAs, this stackup will not be significantly better than laminate. o The through via pads will need to be large. o Using only a single micro-via layer will limit the ability to benefit from the smaller via and trace feature sizes.
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HDI Type II
This construction uses micro-vias, buried-vias, and may have through-vias. There is a single micro-via layer on at least one side. Via holes are drilled in a laminated core and become buried when the dielectric material is added for the micro-vias. Micro-vias are staggered from other micro-vias and may be stacked or staggered relative to the buried vias. Additional Notes See Type I note above on limiting the number of laminated core layers which applies to all variations of Type II through and buried vias.
Figure 3-3: IPC Type II, variable-depth micro-vias The variable-depth micro-vias can be in the form of skip-vias that connect only on the start and end layers. 33
Figure 3-4: IPC Type II, stacked vias Recommendations In the context of large dense boards with multiple high pin-count BGAs, this stackup is better than Type I; however, is not adequate for the more difficult designs. o Using buried vias instead of the through vias is a significant advantage. o Using only a single micro-via layer span will limit the ability to benefit from the smaller via and trace feature sizes. o The single micro-via layer span also restricts the viability of using the outer layers for a GND plane. Having only one buildup layer for routing traces isnt nearly as effective as two.
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Chapter Three HDI Stackups Additional Notes See Type I note above on limiting the number of laminated core layers which applies to all variations of Type III through and buried vias.
Figure 3-6: IPC Type III, stacked vias Recommendations Type III HDI is the best stackup configuration for large dense boards with multiple high pin-count BGAs. o With two micro-via layers there is considerable routing area available using the smaller via and trace feature sizes. o Using the outer layers for a GND plane is feasible because there are still enough micro-via layers available for signal routing. o Using stacked vias will allow for greater route density; however, the cost will be higher. 35
Via Models
HDI Type III accommodates numerous via models and spans. Ultimately the via model that suits your design best will be driven by finding the least expensive method that will still enable adequate route density within the constraints of signal integrity. The graphic below represents some of the via models that may be used in HDI Type III.
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Figure 3-7: Type III via model examples Skip Vias This via model is effective for transitioning layers (because it emulates the stacked via); however it is not as efficient as stacked vias for route space due to the fact that the minimum diameter is 8th. Buried-vias As a general rule, all unused pads on the buried-vias should be removed. This will significantly reduce the crosstalk. Micro-via Pad Sizes Although the pad size will vary by fabricator, using a pad .15mm (6th) larger than the hole is adequate. Via Aspect Ratio Hole length to diameter: Micro-vias 5:1, buriedvias 10:1 37
Figure 3-8: Extended buried-via Advantages o If you have power and ground nets that need to extend all the way through the board, using the extended buried-via requires less space. Disadvantages o Single-ended nets that use the extended blind via may suffer from additional via-stub effects; however, the additional stub length may be insignificant depending on the frequency. o Depending on the fabricator, the cost of extending the buried-via may be slightly more than just having the buriedvia in the laminated core.
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Chapter Three HDI Stackups Stacking Micro-Vias and Buried-Vias As shown below, the micro-vias may be stacked with themselves and/or with the buried-vias.
Figure 3-9: Stacked vias Advantages o If you have power and ground nets that need to extend all the way through the board, using the extended buried-via uses the minimum space. o Using stacked vias enables the most flexible and efficient via configuration for routing. Disadvantages o Stacking vias generally costs more due to additional steps required to ensure a good connection between the vias.
BGA Breakouts and Routing appropriate location of planes is a much deeper and more complicated subject than can be addressed in this book; however, certain methodologies are recognized as effective and will be described at a high level herein. In the stackups shown, the number of layers in the laminated core is variable of course. Sixteen layers is just convenient for the purpose of showing plane layer assignments graphically. Outer Layer GND A stackup such as the one pictured is typical when GND is assigned to the outer layers.
Figure 3-10: Outer layer GND Advantages o GND on the outer layers provide an excellent EMI shield. o If the bypass capacitors for the BGA are placed on the same layer as the BGA, then you may minimize the number of vias 40
Chapter Three HDI Stackups used for GND underneath the BGA. This will open routing channels which may be critical for an extremely dense board o You may still want vias for some of the GND pins to improve the return paths Disadvantages o If the return paths are managed with a minimum number of GND vias, there really isnt a downside to using this method. o It is often thought that using the outer layers for GND will limit the number of buildup (smaller features) layers for routing signals. Although this is true, it is also important to consider that controlling the signal integrity of those nets will be more difficult and burying the first GND plane in the laminate structure will result in the routing on the micro-via layers to not have a good reference plane. Outer Layer GND and VCC A stackup such as this one is typical when GND is assigned to the outer layers.
BGA Breakouts and Routing Advantages This scheme has the same advantages as listed for Outer Layer GND plus these additional ones: o The capacitive coupling between the GND and VCC layers will be excellent minimizing the bypass capacitors needed for the BGA (assuming you use a relatively thin dielectric less than .05mm or 2th). o This is also an opportunity to use embedded capacitors and pull-up resistors effectively; resulting in opening up considerable routing space on the signal layers. Disadvantages o If the return paths are managed with a minimum number of GND vias, then there really isnt a downside to using this method. Recommendations o Using a skip-via or stacked-vias would be good for this kind of stackup if it can be cost justified. Split Planes Often large BGAs require multiple voltage supplies. You can use split planes or dedicated voltage layers for this power distribution. If this method is used, it is best to add a couple voltage supply layers in the center of the board surrounded by GND planes to avoid having signal layers affected by crossing the splits or different voltages.
Layer Count
The number of buildup and core layers required to route the board and fulfill the performance and signal integrity requirements will vary depending on the route density and manner in which you decide to manage the plane layer assignments. Determining the route density is a subject outside the scope of this book; however, as a general rule for large dense boards start with 8-10 signal layers and increase them as needed during the routing process.
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Since the thickness of the laminated core will be limited by the aspect ratio of the buried via (10:1), work with your board fabricator to determine core and prepreg thicknesses. Doing this in conjunction with trying to minimize via pad size for routing will enable you to determine the high-end number of layers available in the laminated core.
Design Rules
Throughout this book, the minimum values for via hole and pad diameter as well as the aspect ratios have been described. These minimums are used as a guide to enable high yields. Minimum trace widths and clearances are based upon the fabricators capabilities; however, they are more than likely to be set based on signal integrity requirements such as impedance control and minimizing crosstalk.
Fanout Patterns
The method used for fanout of BGAs is a subject of an entire chapter and can significantly contribute to the success or failure of the design. Here are some of the considerations: Via location relative to BGA pad o Adjacent (dog-bone) o Partial via-in-pad o Offset via-in-pad o Via-in-pad When using a combination of micro-vias and buried-vias, each via span can have its own pattern within the BGA and as such can affect the route-ability of the device. o Via-in-pad methods provide the greatest opportunity to increase route density. o Shifting and aligning the vias may be useful to improve route-ability. 43
BGA Breakouts and Routing o Using a complimentary patterns for the micro-vias and buried-vias can improve route-ability o The goal should be to reduce the overall effective number of pins by the time you get to the laminated core, thus reducing the number of layers required to breakout and route the BGA.
Signal Integrity
This is a subject that has many dependencies, variables and thousands of articles. The desire here is to simply point out a few design methods related to large board HDI stackups that could positively affect signal integrity: Remove unused pads on buried vias to reduce crosstalk. Route the high-speed single-ended nets on the buildup layers closest to the component. The potential for via stub effects is eliminated because buried-vias are not used. Route differential pairs on the laminated core layers. The via stubs affect the differential pairs less than the single-ended nets and the crosstalk between the diff pair vias (if the unused pads are removed) is likely to be insignificant. A stripline configuration, where pairs of signal layers are sandwiched between plane layers, not only provides the best return paths but also reduce crosstalk. This supports the notion that using a ground plane on the outer layers is a good practice.
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Stackup A
Figure 3-12: Stackup A Stackup A Comments: Total score = 13 This is a great average of the variables and a good stackup if you are starting out with HDI. The via models are simple and it wont be difficult to find vendors who can fabricate them. The ground plane on the outer layers provides a high rating for power and signal integrity.
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Stackup B
Figure 3-13: Stackup B Stackup B Comments: Total score = 15 The GND and VCC on the outer layers provide the best power and signal integrity. The additional buildup layer increases the cost (more laminations, drills, and plating steps) but also improves the route density as opposed to losing an HDI routing layer due to the VCC plane. The via models are simple and it wont be difficult to find vendors who can fabricate them.
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Stackup C
Figure 3-14: Stackup C Stackup C Comments: Total score = 14 The stacked vias enable the best route density but also increases the cost and may limit the number of vendors who can fabricate this stackup. The ground plane on the outer layers provides the high rating for power and signal integrity.
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Stackup D
Figure 3-15: Stackup D Stackup D Comments: Total score = 12 The ground plane on the outer layers provides the high rating for power and signal integrity. The skip via reduces laminations and plating steps, which lowers cost; however, contributes to a relatively low route density.
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Stackup E
Figure 3-16: Stackup E Stackup E Comments: Total score = 10 The lack of a ground plane on the outer layers reduces power and signal integrity; however it does provide for improved route density assuming routing would be done on the outer layers. The via models are simple and it wont be difficult to find vendors who can fabricate them.
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Stackup F
Figure 3-17: Stackup F Stackup F Comments: Total score = 14 The ground plane on the outer layers provides the high rating for power and signal integrity. The extended buried via reduces the lamination and plating steps which lowers cost; however it reduces route density.
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Stackup G
Figure 3-18: Stackup G Stackup G Comments: Total score =14 The ground plane on the outer layers provides the high rating for power and signal integrity. The extended buried via and the skip via reduces the lamination and plating steps which lowers cost; however it also reduces route density.
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Any-Layer-Via Stackups
The any-layer-via stackup is an HDI variation that although currently expensive will become affordable over time and in my opinion provide the kind of stackup and via models that will be required for successful routing of very large and very fine-pitch BGAs. As you can see in Figure 3-19, vias can span any set of layers.
The micro-vias are either punched or laser-drilled and are filled with a conductive material after each buildup stage in the metallization process to connect them. Although Matsushita Corporation originated the ALIVH (Any
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Chapter Three HDI Stackups Layer Interstitial Via Holes) numerous other companies are developing new processes that allow for micro-vias to span any layers. Chapter 6, 0.8mm Pitch BGA Tests, applies the any-layer-via method and demonstrates the great advantages of this via model.
Summary
There are many variations available for HDI stackups. The one you choose to use will have to balance the cost, route density, signal and power, and integrity. New fabrication methodologies continue to evolve and within a few years you will have even more possibilities. Happy Holden, PCB Technologist at Mentor Graphics, has written scores of articles and presentations on HDI. His body of work may be found at www.mentor.com/pcb and www.westwoodpcb.com. His expertise and knowledge is described in tremendous depth and will certainly provide great insight to HDI materials, best practices and the impact on signal and power integrity.
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Simulate fast driver edges and new bus technologies with HyperLynx, the most widely used high-speed PCB simulation software. HyperLynx provides both pre- and post-layout analysis of signal integrity, flight times, cross-talk, and multi-gigabit SERDES technologies and is compatible with all major PCB design flows. To connect with other innovators and visionaries of future high-speed design join Mentors PCB community at http://communities.mentor.com, call us at 800.547.3000 or for more information visit www.mentor.com/products/pcb/analysis_verification
BGA Breakouts and Routing o Using a complimentary patterns for the micro-vias and buried-vias can improve route-ability o Goal should be to reduce the overall effective number of pins by the time you get to the laminated core, thus reducing the number of layers required to breakout and route the BGA.
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Chapter Four Fanout Patterns stackup with power and ground on the outer layers) can open up considerable routing space. Figure 4-1 shows an ideal distribution of ground pins (green). If the BGA could have the ground pins aligned in this way, and if the mount layer was a ground plane, room is made available on the inner routing layers.
Figure 4-1: Alignment of ground pins Yet, rarely are the power and ground pins aligned in such a way. In fact, most FPGA vendors sprinkle the power and ground pins or use some
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BGA Breakouts and Routing pattern other than columns and rows. The purpose of distributing power and ground pins is to improve the power integrity. Xilinx often uses a Sparse Chevron pattern as shown in Figure 4-2. In this figure the ground pins are green and the power pins are brown.
Figure 4-2: Xilinx Sparse Chevron pattern for power and ground pins There may be some ASICs that have power and ground pins aligned in columns and rows, which indeed could help open up routing channels on inner layers and reduce layer count. However, such an ideal condition is not common and therefore effective fanout and routing solutions must find other ways to reduce the layer count.
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Chapter Four Fanout Patterns These devices support multiple I/O standards ranging in performance that could require differential routing. Differential pairs require different trace widths and spacing than singleended nets to maintain the desired impedance and although it is possible to use the same spacing rules inside the BGA area, the impedance discontinuity may become significant in some high-speed circuits. For example, it is common to have a target of 50 for single-ended nets and 100 for differential pairs. Of course the stackup thicknesses and materials will affect the impedance; yet it is common to see a 0.15mm (6th) for differential pair spacing while single-ended nets can have 0.1mm (4th). Actual trace widths and clearances will vary depending on the specific highspeed and fabrication requirements for each design. If the fanouts are positioned such that differential pairs need to be split to maintain the trace width and clearance rules, that could also be a significant signal integrity problem. This is illustrated in Figure 4-3.
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BGA Breakouts and Routing The point is that a theoretical fanout and breakout solution that does not take into consideration the potential for varied trace widths and clearances is not very useful. The problem becomes even more difficult when each I/O pin or bank of I/O pins may be programmed to require either differential pair or single-ended routing. An effective fanout solution that enables the most efficient escape routing needs to be flexible enough to support the trace width and clearance requirements for a potential mixture of serial and parallel.
Chapter Four Fanout Patterns Routing fast single-ended nets on buildup layers using micro-vias will also greatly reduce crosstalk.
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Design Rules
The design rules used for the fanout patterns will be as listed in these tables:
Table 4-2: Design rules for 0.8mm pin pitch BGA Ball Pads The size of the ball pad varies depending on the soldering process and if lead-free solder is being used. Since lead-free solder does not spread like 63
BGA Breakouts and Routing leaded solder, the ball pad sizes are generally more effective if they are smaller. In the context of fanout patterns, the size of the ball pad does not have much impact since the gains in space for routing will be generally attained on the inner layers. A smaller ball pad will enable greater coverage of a ground plane; whereas a larger ball pad enables more flexibility regarding the location of a via-in-pad. Via Hole Sizes The via hole size for buried and through vias will need to maintain an aspect ratio less than 10:1 (board thickness to hole size). If the aspect ratio is larger, the fabrication yield will be significantly reduced and consequently the cost of the board will rise.
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Through-Vias
When using through vias, there are not too many options due to the large 0.5mm via pad relative to the 1mm ball pitch. Either a Quadrant Dog-Bone or Via-in-Pad method is appropriate.
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Figure 4-4: Xilinx Virtex-4 with power (orange) and ground (green) vias It is clear that the vias for power and ground are scattered such that even if they were all removed, little would be gained. The outer perimeter of through-vias dictates how much space is available for routing, and at least in the case of the Virtex-4, few of them are assigned to power and ground.
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Figure 4-5: Xilinx Virtex-4 with power and ground vias removed. In figure 4-5, few additional route channels are opened by removing the through vias for GND. If an ASIC can be packaged to provide adequate power integrity and have the power and ground pins aligned in such a manner to open up route channels (by not using fanout vias) that would be a good circumstance; yet, it is likely to be a rare condition.
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Quadrant Dog-Bone
This fanout pattern has the fanout vias spaced in the center between the ball pads and angled in one of four directions. See Figures 4-6 and 4-7. Advantages (Over Via-in-Pad) Opens up additional routing channels in the center row and column. However, there is room for two or three more routes which is very unlikely to contribute to reducing layer count. See Figure 4-8. On the side of the board opposite the BGA mount, the column and row channel is a convenient place to add capacitors and pull-up resistors. Lower cost and less risk of soldering problems related to the via-inpad. Disadvantages (Over Via-in-Pad) If you have a ground or power plane on the BGA mount side, the fanout via pads prevent a continuous plane fill under the BGA.
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Shifting Through-Vias
Placing the fanout via anywhere but in the center of the ball pad array has a relatively small benefit to routing because there is so little wiggle-room. The benefit depends on the design rules. You could move the vias offcenter a little to form columns and rows, but for every additional route channel opened on one side, it will close a route channel on the other side the net result will be the same number of route channels (or possibly even less) across the entire BGA. However, if the design rules are such that differential pairs cannot be routed together between the through-vias, and a little more space is required to enable it, then shifting the through-vias only slightly might make sense. In Figures 4-9 and 4-10, note that by shifting the vias to the left on one column and to the right on the next column, you can gain 0.17mm in one and lose 0.17mm in the other. These values could be greater or smaller depending on your ball pad size and clearance rules. This method could be useful if you have some critical signals that require greater spacing within the BGA breakout area. For example, when routing a diff pair on inner layers, the clearance between the compliments can be increased from 0.44mm to 0.61mm and still maintain a 0.1mm clearance to the via pads. Another reason for shifting through-vias while using Quad Dog-Bone patterns is to maximize the amount of plane fill on the mount layer. Again, the benefit is dependent on the design rules.
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Via-in-Pad
This pattern is quite simple, add a through-via in the center of each of the desired BGA ball pads. See Figures 4-14 and 4-15. Advantages (Over Quadrant Dog-Bone) If you have a ground or power plane on the BGA mount side, the fanout via pads allow a continuous plane fill under the BGA. See Figure 4-16. If you do not use the mount layer for a plane, then you have an additional routing layer for the BGA - albeit a surface layer which is not recommended for high-speed nets. Disadvantages (Over Quadrant Dog-Bone)
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BGA Breakouts and Routing There are no additional route channels in the center column and row. There is less room for capacitors and resistors on the opposite side under the BGA since the fanout via array is full. If the BGA has unused pins and you do not add fanout vias for them; there will be some room in those locations for components. There will be a slightly higher cost for filling the vias and ensuring a smooth surface for the soldering of the ball pads. There is some risk of BGA soldering problems (de-lamination or pop-corning) with via-in-pad while using lead-free solder. An experienced assembly company should be able to manage this risk and make it a non-issue.
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Chapter Four Fanout Patterns reduction and higher density routing can be achieved due to the smaller via sizes compared to through-vias; however, these gains are not as significant as can be achieved with micro-via HDI methods. The gains are dependent on the size of the blind-via. Since a minimum drilled hole size of 0.2mm (8th) applies to these blind-vias, the pad size should be 0.44mm (17th). These feature sizes will be used in this analysis of fanout patterns.
Table 4-3: Blind and buried-via pad diameters This analysis assumes a layer 1:2 blind-via with the intent to route as much as possible on layer 2. The example in Figure 4-17 has the first 5 rows in from the perimeter using the blind vias in a shifted column and row pattern. If the shifted blind-vias exist on layers 1:3, then it is likely you could breakout an addition 5 or 6 rows inside the perimeter, depending on the number of power, ground and unused pins. This is a substantial notion in the context of layer reduction.
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BGA Breakouts and Routing capacitors, or any signals that need pull-up resistors, would have another blind-via between layers n and n-1. o One alternative to using the blind/buried/blind vias in the center would be to just put in a through-via either in a quadrant dog-bone pattern or via-in-pad configuration. This will simplify the fanout and since most of the pins in the center area are power and ground, it will not impact the route density in a significant manner. 2. Quadrant dog-bone in the corners. The corners of the BGA are always the easiest to breakout because you have half as many pins to route to the edge, split along the diagonal. Using a simple quadrant dog-bone pattern actually allows for more routing density than if you tried to mix some kind of staggered via pattern along the diagonal of the corner. See Figure 419. Most any pattern will result in the same number of escape traces plus or minus a few so you may as well go with a simple pattern. 3. Short dog-bone in the transition areas. The pins between the pins using the dog-bone via patterns and the shifted vias lack space for the fanouts. I recommend using a row around the perimeter for the transition as shown in Figure 4-19.
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Figure 4-19: Corner via and transition via patterns 4. Shifted Columns and Rows. Using a blind-via pattern around the perimeter of the BGA, in which the vias are shifted into columns and rows, results in 24% greater route density per layer.
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c Figure 4-20: Mount layer with frilled blind-vias shifted into columns
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BGA Breakouts and Routing Advantages 24% increased route density per layer over through-vias and unshifted blind-vias. More room for a ground plane on the mount layer. It is not as much as can attained with the vias-in-pad; but certainly more than if the vias are centered in a simple 1mm matrix. If you route the high-speed single-ended nets on the layers using blind-vias, via stubs are eliminated and via-via crosstalk is minimized. Any signal routed on the blind-via layers, will not need to have a buried via, thus opening up route space on the buried via layers. Disadvantages A blind and buried via stackup is more expensive than a through-via stackup.
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A good solution, especially for FPGAs is to pin swap so that the ball pads are aligned in a manner that results in the fanout vias remaining close to each other. In the above figures, swapping the differential-pair compliments into the A and A locations will optimize the coupling. The ability to swap pins will be limited by bank locations and power and ground pin distribution. Finding the most effective swapping patterns (aligned vertically or horizontally or on a diagonal) will depend on the fanout via pattern used in that area.
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HDI Micro-Vias
Fanouts for laser drilled micro-via stackups use the same principles as with mechanically drilled blind & buried vias. The variety of stackups and smaller via sizes provide for tighter shifted column and row patterns, improved route density and greater flexibility in assigning routes to buildup layers as opposed to laminated cores. When using HDI, the blind micro-vias allow for greater route density and therefore potentially fewer total layers required for routing. Of course the number of layers accessible by the micro-vias will significantly affect the
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BGA Breakouts and Routing overall route density. The fanout patterns analyzed in this context will be for the following types of HDI construction: 1+N+1 = Type II (layer 1:2 micro-vias with buried vias in laminated core) 2+N+2 = Type III (layer 1:2, 2-3 micro-vias with buried vias in laminated core) Layer 1:2 micro-vias (1+N+1) If Layer 1 is used for a ground plane and not for routing, then the fanouts need to be patterned to maximize layer 2 route density. The same patterns for the blind-vias can be used for micro-vias; however, since the micro-vias are smaller, you can compact them more and gain additional route space. In Figure 4-26, the 1:2 micro-vias are aligned in columns (and rows) to maximize route density (12% improvement over shifted blind-vias, 36% improvement over quadrant dog-bone through-vias)
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Chapter Four Fanout Patterns Figure 4-27 shows how route density can be increased when using via-inpad methods. If the vias are shifted inside the pads, you can open up additional room for the escape traces.
Figure 4-27: Micro-via pattern using via-in-pad method If only one layer is available for the escape traces as is the case with a 1+N+1 stackup that has a ground plane on the surface layer, then it is important to use a shifted via pattern that is allows for aligned micro-vias around the BGA perimeter and space for the power and ground to extend through the board with additional buried and blind-vias. Layer 1:2, 2-3 micro-vias (2+N+2) Again assuming the layer 1 will not generally be used for routing, then the fanouts need to be patterned to maximize layer 2 and layer 3 route density. With layers 2 and 3 available for routing with micro-vias, you can use either a quadrant style breakout or layer biased. This shows how effective the general principle of aligning the vias works to open additional route space on the inner layers.
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Figure 4-28: Layer 1 with 1:2 micro-vias for all ball pads The above figure shows plenty of room on the mount layer for the ground plane to fill with little interruption. The shifting of vias not only provides additional route density, it also opens space for ground fill. Also note how nicely in Mentor Graphics Expedition PCB the ground via fits and the copper fill and clearance around it provides for good manufacturing.
Chapter Four Fanout Patterns In Figure 4-29 note the significant space for routes after shifting the vias. In this case, the traces are routed as single-ended nets; however, if the nets were differential pairs, there would be plenty of room to route three sets of differential pairs between the aligned vias. Of course actual amounts may vary depending on design rules. The power (orange) and ground (green) vias are paired because you are seeing not only the 1:2 vias, but also the 2:3 vias.
Figure 4-30: Layer 3 with 2-3 micro-vias and buried-vias The large via is the buried-via that extends through the laminated core.
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Figure 4-31: Layers 2 and 3 shown together In Figure 4-31 you can see the combination of layers 2 and 3 with the escape traces on layer 2 and the wide open space for traces on layer 3.
Summary
Effective fanout patterns can increase the route density significantly. Designs with through-vias have limited options under BGAs. When using laminated blind-vias, route density can be increased 24%. HDI micro-vias enables the possibility of increasing route density by 36%. My discussion in this chapter clearly shows that using blind-vias or micro-vias and aligning them is a very effective method for potential layer reduction through increased route density.
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Driven by the need for denser, higher performing, and lower cost products, the use of High Density Interconnects (HDI) and Microvias is rapidly emerging in many industries. By using this technology a designer can effectively break out from dense, fine pitch BGAs, reduce PCB layer counts and size, and improve performance. But designers need the tools that fully understand the complex via stacking rules as well as automate the routing process. Mentors Expedition Enterprise and Board Station XE flows enable highly efficient automatic and interactive routing of HDI/Microvia layers to provide the productivity you need to get the job done quickly and develop the most competitive products for your company. To connect with other innovators and visionaries of future HDI and microvia technology join Mentors PCB community at http:// communities.mentor.com, call us at 800.547.3000 or for more information visit www.mentor.com/pcb
2009 Mentor Graphics Corporation. All rights reserved.
Board Description
18x14 34 layers, 22 signal layers HDI with 2 buildup layers on top and bottom, 30 layer laminated core inside. 52,513 pins 11,529 nets 7,729 parts 18 BGAs each with 1513 pins/1mm pitch (Xilinx Virtex-4 XC4VLX100 FPGA) 1 BGA with 1520 pins/1mm pitch (Xilinx Virtex-4 XC4VLX200 FPGA)
BGA Breakouts and Routing through the board. This requires considerable space and prevents use of some breakout methods that could help in routing the signals.
Fanout Patterns
The need is to develop fanout patterns that facilitates routing and supports the requirement for so many bypass capacitors. Also consider a stackup that provides excellent direct coupling between power and ground by using buildup layers and a very thin dielectric, thus reducing the need for such a large number of bypass capacitors.
Rule Areas
Use Rule Areas around the BGAs to enable spacing that provides dense routing in the area under the device and wide spacing between traces outside the BGA areas.
Stackup
The stackup used for this study is 16 layers using micro-vias and buried vias in a common HDI structure. See Figure 5-1. Red = laser drilled micro-vias, 10th pad, 4th hole range = mechanically drilled buried-vias, 18th pad, 8th hole
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Figure 5-3: Routing with NESW escape traces In Figure 5-3 that the NESW escape traces are blocked by a normally biased autorouter. This shows a problem with NSEW breakouts when trying to auto route with a layer biased router. The breakouts that are perpendicular to the layer bias are not going to be routed.
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Figure 5-4: Layer biased breakouts In the above image, the green traces are on the horizontally biased routing layer and the red on the vertical. This kind of bias is more natural for an autorouter and if the escape traces are generated in the direction of the target pin, the routing effectiveness is even higher. Notes Multiple fanout patterns will be needed to support the bias and to most effectively use the buildup layer micro-vias. 100
Chapter Five Layer Biased Breakouts Use Rule Areas around the BGAs to enable spacing that provides dense routing in the area under the device and wide spacing between traces outside the BGA areas.
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Figure 5-5: Layer 16-15 fanouts You might be thinking, One trace? Whats the big deal? Figure 5-6 shows the fanouts and escape traces when the buried-vias are added for power and ground. There is less room for the traces. However, compared to if the micro-vias vias were just placed in the center of the pad and the buried vias staggered from that location, there is more total room for traces. This method makes it so that the buried-via eliminates one trace at most.
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Figure 5-6: Layer 16-15 fanouts with buried vias for power and ground
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Figure 5-8: All layers shown with fanouts with escape traces
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Chapter Five Layer Biased Breakouts In the end, the auto routing showed higher total completion rates with six rows of pins. A high total completion rate for auto-routing is the goal of effective breakouts, especially on very large designs with upwards of 10,000 nets.
Once the fanout patterns were established, different escape routing patterns can be explored. As mentioned previously, the first attempts with NSEW breakouts resulted with ineffective auto-routing due to the fact that the bias of the escape traces was in conflict with the layer bias. Indeed, the auto-router performed so much better with layer biased breakouts. Does this mean that NSEW breakouts are useless? No, in fact, on boards with four or less signal layers, NSEW breakouts are much more effective because with so few routing layers, the routes usually end up unbiased and often the routing is done manually.
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Figure 5-12: First signal layer This layer has a vertical bias and the netlines that are generally in the vertical direction are routed on this layer using the micro-vias. There are some horizontal routes, but notice they have an additional via to bring it to the nearest horizontal layer. Of course if you dont want additional vias, try to find a horizontal layer that has room to route to the original fanout via.
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Figure 5-13: Second signal layer Similar to the first layer using the micro-vias, except this layer has a horizontal bias.
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Figure 5-14: Buried via layer biased breakouts These escape traces are for the netlines that run in a horizontal direction. You can see this clearly in Figure 5-15. Not all the netlines are strictly horizontal, rather generally horizontal and at least valid for a horizontally biased routing layer.
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Route Results
Table 5-1: Layer biased route results * Rule Areas: In the final test, a rule area was added around the outside of all the BGAs so the width/spacing inside was 4th/4th and outside 4th/7th for single ended nets. ** Via Obstructs: Originally a via obstruct around the BGA was added to prevent additional vias from being added inside, potentially modifying the alignment of the existing via fanout pattern. However, the route results were better when the via obstruct was removed and the fanouts didnt really get messed up.
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BGA Breakouts and Routing With the escape traces unfixed, the router was free to push and shove them to make room for routing. With the layer biased breakouts, the router was able to complete 8% or 54 more connections. This is significant, especially if similar results would be obtained for all 19 of the large BGAs on this board.
Attempts 4-10 These attempts compare the results of routing layers 2-15 using micro-vias and buried-vias. In these cases, a total of 1140 connections were tried by the autorouter. The key attempts are: 4 (no breakouts) 76% completion 6 (NSEW breakouts) 89% completion 10 (Layer Biased breakouts) 97%. Using the layer biased breakouts improved the routing 21% over not using breakouts and 8% over NSEW breakouts. Using a Rule Area to increase the spacing between traces outside the BGA actually helped to increase the routing completion by three connections. This is not a significant number, but it is interesting. With the increased spacing, the router took some different paths for the routing and as chance would have it, the overall routing was better. With spacing increased, there is more room for vias in critical areas. It is also interesting that using layer biased breakouts took half the time (24 minutes compared to 48) of not using breakouts at all. This is an indication that without the breakouts, the router struggled and spent more time doing rip-up and retry which inherently takes more time than if it can find a path just using push and shove.
Summary
It is clear that on large board with multiple large BGAs, layer biased breakouts can make a significant difference in auto route completion percentage and time to route. 120
Once a technology for very specific applications, Flex and Rigid-flex technology is rapidly emerging in many industries, especially consumer. But the design of these complex boards requires following very strict routing and component placement rules. Following these rules is the only way to insure proper folding of the structures into the enclosure and the high reliability required in the flexible layers. Mentors Expedition Enterprise and Board Station XE flows enable designers to efficiently route flex and rigid-flex boards with specialized rules such as: enhanced pad entry, controlled arcs, teardrops, selective pad modification, and multiple plane fill options. These design flows provide the productivity you need to get the job done quickly and develop the most competitive products for your company. To connect with other innovators and visionaries of future flex and rigid-flex design join Mentors PCB community at http://communities.mentor.com/mgcx/index.jspa, call us at 800.547.3000 or for more information visit www.mentor.com/pcb
2009 Mentor Graphics Corporation, All rights reserved.
Test Scenario
I took a footprint for a Virtex-5 with 1760 pins at 1mm pitch and converted it to 0.8mm pitch. In the next two figures, observe that reducing the pin pitch only 20% requires a significantly smaller set of features and a first impression that screams, How am I going to route that?
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Figure 6-2: Virtex-5, 1760 pins with 1mm pitch I performed fanout patterns and NSEW breakout patterns for three different via configurations: Test 1: Through-vias Total Signal Layers for Breakout: 7 Test 2: Through-vias, 1:2 micro-vias, 1:3 micro-vias Total Signal Layers for Breakout: 5 Test 3: Any-layer-vias Total Signal Layers for Breakout: 3 123
Test 1: Through-Vias
The first test used only through-vias to demonstrate the number of layers required for such a method so it could be compared to the other more efficient solutions.
Design Rules
The design rules for the first test are the same as used in the 1mm pitch tests from the previous chapters, except the ball pads are a little smaller due to the smaller pin-pitch.
Fanout Patterns
Except for the outer row of ball pads, this test used a standard Quad DogBone Matrix for the fanout vias.
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Figure 6-3: Fanout pattern (Test 1) In Figure 6-4, you can see why the vias are staggered on the outer row. The pink traces are on the second layer and by staggering the outer row vias, you can get two traces between the vias as opposed only one. This makes a big difference for routing the escape traces belonging to the outer rows of ball pads.
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Test 1 Summary
When using through-vias on 0.8mm pitch devices, the layer count goes up very quickly because the maximum number of traces between the vias is just one. For this 1760 pin device, it took a minimum of 7 signal layers and there is the potential of signal degradation since the differential pairs need to be split. 133
Design Rules
With the finer pin-pitch smaller ball pads are required. However the rest of the design rules were the same as those applied to the 1mm pitch parts. The second test used smaller rules.
Test 2 Stackup
An HDI stackup was used with 1:2 micro-vias, 1:3 skip-vias and a throughvia. The through-via was used for fanout of the power and ground pins so they could attach to all the planes and the discrete components on the opposite side of the board. I chose the through-via over a buried-via because it turns out that the through-via is the same size as the buried-via would have to be and the through-via is more direct and simple. The through-via in this case did not affect the route density significantly so from a cost and simplicity point of view, it was more appropriate.
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Fanout Patterns
Figure 6-13 initially appears to present a very different set of fanout patterns. However, a closer look shows that the principles of aligning vias and combining different patterns to maximize the route density are applied.
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Figure 6-14: Power and ground quadrant matrix fanouts in center (Test 2)
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Figure 6-15: Power and ground fanouts around perimeter layer 1 (Test 2) Notice in the above figure, power and ground through-vias are aligned vertically in every-other channel of ball pads. This section of the BGA is in the lower center of the device as shown in Figure 6-13. As you will note in figures later in this chapter, the power and ground vias generally do not block routing channels, except with the outer row around the perimeter. The ground fanouts have been added some distance away from the ball pads so that an extra trace could be added as you can see in Figure 6-16.
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Figure 6-16: Power and ground fanouts around perimeter layer 2 (Test 2) By moving the ground via down and away from the ball pads, an extra route channel is opened between the through-vias and the micro-vias on layer 2.
I/O Pins
As you can see in Figure 6-13, the center of the BGA has I/O pins with through-vias in a Quadrant Matrix. You might ask, If through vias can be used in the center, why not for the whole BGA? By using micro-vias on the perimeter, the effective size of the BGA (to be routed using through-vias) has been reduced from 1760 pins to 784. 139
BGA Breakouts and Routing Since the center of the BGA is primarily power and ground pins, the actual number of I/Os that need to be routed (after the micro-vias are used around the perimeter) with through-vias is reduced to 544. This is a reasonable number of pins to be routed out of the throughvia array without forcing the addition of layers that would otherwise not be needed for general routing of the board. When through-vias are used, there is room for only one trace between the through-via array and as such, the number of layers would be significantly increased if through-vias were used for all pins. Also, differential pairs will need to be split since only one trace can fit through the through-via array. This requirement can be effectively minimized by using micro-vias around the perimeter.
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Figure 6-17: Layer 1:2 micro-vias (Test 2) In the above figure, the colors have been changed to emphasize the 1:2 micro-vias. At the top, you can see the micro-vias connected to pins AW26 through AW28 are not aligned in a column. This is because the through-vias for the power and ground take up enough space that there isnt room for the micro-vias to be aligned. It turns out that it really doesnt affect the route density. Since there are no additional traces on layer 2 (purple traces) that have to come through that area, placing the vias horizontally doesnt block any other traces.
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BGA Breakouts and Routing This is a general principle when placing the fanout vias. In this case we are using 1:2 micro-vias for the four rows of ball pads around the perimeter. The innermost row of ball pads can have their vias placed in almost any manner because they will not block routing on any other layer. These vias dont exist after layer 2, so obviously they wont block routing on layer 3. If you are routing differential pairs through the columns of vias, you could spread them out a little when feasible.
Figure 6-18: Layer 1:3 micro-vias (Test 2) The layer 1:2 micro-vias are used for the first four rows of pins and the layer 1:3 micro-vias are used for the next three rows of pins. Due to the 142
Chapter Six 0.8mm Pin-Pitch BGA Tests through-vias used for the eighth row of pins, the 1:3 micro-vias had to be packed into a smaller area. This means the 1:3 micro-vias are not aligned in columns, however, there is a pattern to the madness. You can see the pattern in Figure 6-16. On layer 3, there is considerable room for the routing. In fact, I suspect that if I had spent more time packing in the traces, there might even be room for one more row of pins to be routed on layer 3 using the 1:3 micro-vias.
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Test 2 Summary
Applying NSEW breakouts with good fanout patterns enables breakouts on large BGAs in five-to-six signal layers. With increased spacing for differential pairs, it probably could be done with eight-to-ten signal layers. This method can maintain normal trace widths and clearances If the BGA has over 2000 pins, may have to compromise trace widths and clearances.
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Test 3: Any-Layer-Vias
The third test uses an any-layer-via stackup in which each layer is buildup and has a via-hole in it. Via spans are created by continuous coincident locations up and down the stackup.
Design Rules
Smaller design rules are used in this test because it is expected that when any-layer-vias are widely adopted, the fabrication process will have gone through another miniaturization cycle.
Stackup
This stackup allows vias to span any set of consecutive layers. Chapter 3 has a description of the any-layer-via stackup.
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Via Patterns
The any-layer-via provides a unique opportunity to try different patterns. The pad is small and only exists on the layer-pairs that are needed.
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Figure 6-27: Top layer ground plane detail (Test 3) Notes Each ball pad connected to ground uses a thermal relief and a via that goes to the bottom side of the board. These vias are embedded in the plane and are located nearby each ground ball pad. The hole for the ground and power vias are larger than the vias for the signals to ensure adequate current carrying capacity.
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BGA Breakouts and Routing The vias are aligned in a diagonal at the corners. This provides additional routing space as you can see in Figure 6-29.
Figure 6-28: Top layer ground plane detail without net class colors (Test 3)
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Figure 6-29: Test 3 layer 2 corner via patterns and breakouts (Test 3) Notes All the 1:2 fanout vias that are connected on this layer do not need to extend to layer 3. The ground and power vias extend layer-bylayer all the way through the board. The route density has been maximized by shifting the vias into a diagonal, horizontal or vertical alignment.
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Figure 6-30: Layer 3 corner via patterns and breakouts (Test 3) Notes You can see that all the 1:2 vias do not exist on this layer. There is a tremendous amount of room for routing.
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Figure 6-31: Layer 1 center via patterns (Test 3) Notes The vias in the center area of the BGA are aligned either vertically or horizontally and diagonally in the corners. This fanout pattern again uses the basic principle of swinging the vias to align them into columns.
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Figure 6-32: Layer 2 center via patterns (Test 3) Notes This method of breakout also allows for spacing requirements of differential pairs. Remember that if through-vias are used, then only one trace can fit between the array of vias under the BGA.
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Test 3 Summary
162 Applying NSEW breakouts with good fanout patterns enables breakouts on large BGAs in 3 signal layers With increased spacing for differential pairs, it probably could be done on 6 signal layers The any-layer-via eliminates via stubs Using smaller feature sizes makes a significant difference
Chapter Six 0.8mm Pin-Pitch BGA Tests If over 2000 pins and 0.8mm pitch, ALIVH is a great solution if you want absolute minimum layer count
Summary
Although 0.8mm pin-pitch BGAs are clearly more difficult to route, using micro-vias and specifically any-layer-vias make the task quite reasonable. When 0.8mm BGAs with over 2000 pins are commonplace, I am hopeful that the any-layer-via method will have been adopted world-wide.
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Method
This dialog uses the concept of Regions (as described in chapter 4) in which the BGA is divided into four areas; each area should get a different via pattern to optimize the route density. 166
Regions
Figure 7-2 shows four regions plus the Diagonal Via area. Each region has its own characteristics and allows the user to have some flexibility in the fanout via pattern style.
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Figure 7-3: Effects of changing via-pad spacing in region 1 and 2 Region 2 This region contains the BGA pins inside Region 1 and extends into the BGA with a user defined number of rows. The patterns that can be created are the same as in region 1. It is likely that the via span for region 2 would be some blind via that extends from layer 1 down to layer 3 or 4 depending on your stackup.
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Chapter Seven Software for Generating BGA Fanouts Region 3 This region is a transition area between Region 2 and Region 4. Region 4 will get some kind of dog-bone pattern and it conflicts with the Region 2 pattern and without a transition pattern, the vias would have DRC errors.
Figure 7-4: Region 3 transition pattern Region 4 All the remaining BGA pins inside of the other regions are in Region 4. A dog-bone pattern is used and the user has control over the center to center spacing between the via and ball pad. Most likely this region will use a through-via since the pins in the center are usually power and ground.
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Chapter Seven Software for Generating BGA Fanouts You may also want to use this section to define fanouts that go all the way through the board for the power and ground pins. To accomplish this, you should use the Net Filter and thereby select only the power and ground pins that should have the defined fanout pattern applied. Via Locations Default If you leave the two fields blank for a given span, then we apply a default spacing and angle that results in the following: The initial buried-via span is placed directly underneath the ball pad.
Figure 7-6: Default buried via pattern The blind via span added to the buried via is placed directly underneath the mount-side blind-via.
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BGA Breakouts and Routing Via-Via Spacing You can use this parameter to adjust the distance that the via-span has from the previous span. For example, if you change the spacing to 30th then the via will be pushed out along the same angle.
Figure 7-8: Layer 1 and layer 6 view Angle The angle controls the angle of the trace being added and of course affects the location of the via span. This angle is relative to the previous span. For example, a 0 angle will result in the trace continuing in the same direction as the previous span.
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Additional Example
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Conclusion
One of the factors that make routing large BGAs so difficult is the high number of variables involved in the process. For example, while one fanout method may work with one set of design rules, it may not work with others. I believe the solutions explored in this book involve sufficient variety to cover a broad spectrum of design challenges. The most important technique for meeting your layer reduction and signal integrity goals is applying an effective fanout pattern that increases route density. Usually each BGA will require two or three different via patterns for best routing results. At a minimum, the fanout patterns presented in this book should give you some valuable insight to what is possible; at best, you will be able to apply these patterns directly to the design challenges faced in the near future. Once the fanout patterns are established, the escape traces do help the routing process. The chapter on Layer Biased Breakouts demonstrates a significant improvement in to overall routing completion rates. The research conducted during the process of writing this book is also the source for the functional enhancements to Mentor Graphics Expedition PCB and Board Station XE as described in chapter seven. Component technology and fabrication methods will continue to evolve; however, the design principles revealed in this book should apply for many years to come.
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The creation of fabricaion and assembly data and documentation have always been an extremely intregal part of PCB design. Mentor Graphics presents FabLinK XE, an integrated manufacturing data creation, generation and verification environment. FabLink XD, available in Mentors Expedition Enterprise and Board Station XE flows, enables designers to control their fabrication data at either the board or panel level, thus ensuring design and manufacturing data integrity.
To connect with other innovators and visionaries of future manufacturing processes, join Mentors PCB community at http://communities.mentor.com/mgcx/index.jspa call us at 800.547.3000, or for more information visit http://www.mentor.com/products/pcb
2009 Mentor Graphics Corporation, All rights reserved.
Pfeil r stems Design Charles P is an Engineering Director at Mentor Graphics, Sys Division. He was the or riginal produc architect for Expedition P and is an ct r PCB inventor of XtremePCB TeamPCB an XtremeAut B, nd toRoute. Char has been rles er s owner of a serv bureau, vice in the PCB industry ove 40 years as a designer, o and has a worked in marketing an also n nd/or enginee ering managem ment at Racal-Red ASI, Cade dac, ence, PADS, an VeriBest. H can be cont nd He tacted through e email at charles_pfeil@men ntor.com To find m more information about Mentor PCB design solutions, go to www.me entor.com/pcb b
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There are many benefits to using the BGA package; however, its greatest asset, the ability to provide an extremely dense array of thousands of pins, also turns out to be a tremendous problem for PCB designers. The BGA density and pin count continues to increase; yet, our ability to effectively design with these devices has not kept pace. Fortunately, significant advancements in PCB fabrication technology have enabled further miniaturization in the manufacturing process. These improvements, along with new software and design methods specifically for BGAs provide a means to successfully design using these devices. This book explores the impact of dense BGAs with high pin-count on PCB design and provides solutions for inherent design challenges.
Charles Pfeil