Linear Feedback Shift Register
Linear Feedback Shift Register
Linear Feedback Shift Register
11, 86, 82, 52, 60, 46, 64, 10, 98, 2, ...
Do statistical simulations
Simulate customers in a shopping center (find the best spot for a new Chuck E Cheese)
Encrypt documents
Use random numbers as key stream
Encrypt Documents
stream of bytes plaintext XOR Random Number Generator 'one-time pad' XOR decrypted stream of bytes plaintext
feedback network
10
100
1001
10011
100110
0001
1000
0100
0010
...
0001
1000
0100
0010
1001
1100
0110
1011
0101
1010
1101
1110
1111
0111
0011
Galois
8 7 6 5 4 3 2 1
Galois
8 7 6 5 4 3 2 1
Galois
char_v = (char_v >> 1) ^ (-(signed char) (char_v & 1) & 0xe)
FF
A Flip flop
module flipflop(q, clk, rst, d); input clk; input rst; input d; output q; reg q; always @(posedge clk or posedge rst) begin if (rst) q = 0; else q = d; end endmodule
A Flip flop
Setup Time:
Time D has to be stable before a clock edge
Hold Time:
Time D has to be stable after clock edge
Propagation Delay:
Delay from clock edge to Q Delay from reset to Q
A Flip flop
module flipflop(q, clk, rst, d); input clk; input rst; input d; output q; reg q; always @(posedge clk or posedge rst) begin if (rst) q = 0; else q = d; end endmodule
A Flip flop
module flipflop(q, clk, rst, d); input clk; input rst; input d; output q; reg q; always @(posedge clk or posedge rst) begin if (rst) #2 q = 0; else q = #3 d; end specify $setup(d, clk, 2); $hold(clk, d, 0); endspecify
ECE 4514 Digital Design II Lecture 6: A Random Number Generator in Verilog
endmodule
output (1 bit)
output (1 bit)
Multiplexer symbol
control
module mux(q, control, a, b); output q; reg q; input control, a, b; wire notcontrol; always @(control or notcontrol or a or b) q = (control & a) | (notcontrol & b); not (notcontrol, control); endmodule;
bit multiplexer
LFSR, structural
seed (4 bit) load (1 bit)
1 0 1 1 1
output (1 bit)
module lfsr(q, clk, rst, seed, load); ... wire [3:0] state_out; wire [3:0] state_in; flipflop F[3:0] (state_out, clk, rst, state_in); endmodule
LFSR, structural
seed (4 bit) load (1 bit)
1 0 1 1 1
output (1 bit) module ... wire wire wire lfsr(q, clk, rst, seed, load); [3:0] state_out; [3:0] state_in; nextbit;
LFSR, structural
seed (4 bit) load (1 bit)
1 0 1 1 1
output (1 bit) module ... wire wire wire lfsr(q, clk, rst, seed, load); [3:0] state_out; [3:0] state_in; nextbit;
mux M1[3:0] (state_in, load, seed, {state_out[2], state_out[1], state_out[0], nextbit}); assign q = nextbit;
ECE 4514 Digital Design II Lecture 6: A Random Number Generator in Verilog
endmodule
LFSR testbench
module lfsrtst; reg clk; reg rst; reg [3:0] seed; reg load; wire q; lfsr L(q, clk, rst, seed, load); // initialization // apply reset pulse initial begin clk = 0; load = 0; seed = 0; rst = 0; #10 rst = 1; #10 rst = 0; end
ECE 4514 Digital Design II Lecture 6: A Random Number Generator in Verilog
// drive clock always #50 clk = !clk; // program lfsr initial begin #100 seed = 4'b0001; load = 1; #100 load = 0; end endmodule
Simulation ..
Synthesis ..
So this bitstream has much more '0' then '1'. It has a bias.
Can a random number generator have flaws? Problem #1: it can have bias
Do LFSR have a bias ?
Can a random number generator have flaws? Problem #1: it can have bias
Do LFSR have a bias ? Yes, they have a small bias because the all-zero state never appears. However, for a very long LFSR, the bias becomes negligible
Can a random number generator have flaws? Problem #2: it can be predicted
Not when truly random phsysical phenomena But, if it is a Pseudo RNG (like an LFSR), it is a deterministic sequence. Is this really a problem? Yes!
Don't want to use a predictable RNG for dealing cards, driving a slot machine, ... (at least not if you own the place). Don't want to use predicatable RNG in security. Predicability = weakness
Can a random number generator have flaws? Problem #2: it can be predicted
The real issue for PRNG is: can the value of bit N+1 be predicted when someone observes the first N bits.
closed box
8 7 6 5 4 3 2 1
010111011..
So let's say we have and 8-bit LFSR, then we need only 16 bits of the RNG stream before it becomes predicatble LFSR are unsuited for everything that should be unpredictable
ECE 4514 Digital Design II Lecture 6: A Random Number Generator in Verilog Patrick Schaumont Spring 2008
B C
out
Eg. out = AB ^ BC ^ C
Patrick Schaumont Spring 2008
from 37 ... to 37 1 2
from 1 3
from 2 ...
Patrick Schaumont Spring 2008
Sample Implementation
On opencores you can find an implementation of Tkacik's design - assigned reading of today
(this design has a few minor differences with the spec written by Tkacik - but OK for our purpose)
Module interface
module rng(clk,reset,loadseed_i,seed_i,number_o); input clk; input reset; input loadseed_i; input [31:0] seed_i; output [31:0] number_o; reg [31:0] number_o; reg [42:0] LFSR_reg; reg [36:0] CASR_reg; // internal state // internal state
always (.. CASR ..) always (.. LFSR ..) always (.. combine outputs ..)
endmodule
ECE 4514 Digital Design II Lecture 6: A Random Number Generator in Verilog Patrick Schaumont Spring 2008
LFSR Part
reg[42:0] LFSR_varLFSR; // temporary working var reg outbitLFSR; // temporary working var always @(posedge clk or negedge reset) begin if (!reset ) begin ... end else begin if (loadseed_i ) begin ... end else begin ... end end end
ECE 4514 Digital Design II Lecture 6: A Random Number Generator in Verilog Patrick Schaumont Spring 2008
LFSR Part
reg[42:0] LFSR_varLFSR; // temporary working var reg outbitLFSR; // temporary working var always @(posedge clk or negedge reset) begin if (!reset ) begin LFSR_reg = (1); end assemble bits else begin if (loadseed_i ) LFSR_varLFSR begin LFSR_varLFSR [42:32]=0; LFSR_varLFSR [31:0]=seed_i ; LFSR_reg LFSR_reg = (LFSR_varLFSR ); end else begin ... end end ECE 4514 Digital Design II Patrick Schaumont Lecture 6: A Random Number Generator in Verilog Spring 2008 end
LFSR Part
reg[42:0] LFSR_varLFSR; // temporary working var reg outbitLFSR; // temporary working var always @(posedge clk or negedge reset) LFSR_reg begin if (!reset ) LFSR_varLFSR else begin if (loadseed_i ) LFSR_varLFSR else begin LFSR_reg LFSR_varLFSR = LFSR_reg; LFSR_varLFSR [42] = LFSR_varLFSR [41]; outbitLFSR = LFSR_varLFSR [42]; LFSR_varLFSR [42] = LFSR_varLFSR [41]; LFSR_varLFSR [41] = LFSR_varLFSR [40]^outbitLFSR ; // some lines skipped ... LFSR_varLFSR [0] = LFSR_varLFSR [42]; LFSR_reg = LFSR_varLFSR; end end end ECE 4514 Digital Design II Patrick Schaumont
Lecture 6: A Random Number Generator in Verilog Spring 2008
Combine outputs
always @(posedge clk or negedge reset) begin if (!reset ) begin number_o = (0); end else begin number_o = (LFSR_reg [31:0]^CASR_reg[31:0]); end end
Simulation ..
Synthesis ..
Summary
Random number generators
Many useful applications