AN2548 Application Note: Using The STM32F101xx and STM32F103xx DMA Controller
AN2548 Application Note: Using The STM32F101xx and STM32F103xx DMA Controller
AN2548 Application Note: Using The STM32F101xx and STM32F103xx DMA Controller
Introduction
This application note describes how to use the STM32F101xx and STM32F103xx direct memory access (DMA) controller. The STM32F101xx and STM32F103xx DMA controller, the Cortex-M3 core, the advanced microcontroller bus architecture (AMBA) bus and the memory system contribute to provide a high data bandwidth and to develop very-low latency response time software. This application note also describes how to take full advantage of these features and ensure correct response times for different peripherals and subsystems. The STM32F101xx and STM32F103xx will be referred to as STM32F10xxx, and the DMA controller as DMA throughout the document.
April 2009
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Contents
AN2548
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 DMA controller description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Performance considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 3.2 3.3 3.4 3.5 Round robin priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Multi-layer structure and bus stealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DMA latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Databus bandwidth limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Choosing channel priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.1 3.5.2 Application requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal data bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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2.1
Main features
The DMA(s) offer(s):
Twelve DMA channels (7 for DMA1 and 5 for DMA2) supporting unidirectional data transfers from source to destination Hardware- and software-programmable channel priority for each DMA Memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-toperipheral transfers (memory can be SRAM or Flash) Control of hardware/software transfers Automatic increment of peripheral and memory pointers Programmable data size Automatic bus-error management Non-circular/circular mode Transfer of up to 65536 data tokens
The DMA aims to offer a relatively large data buffer to all peripherals. This buffer is usually located in system SRAM. Each channel is assigned to a unique peripheral (data channel) at a given time. Peripherals connected to the same DMA channel (CH1 to CH7 in Table 1, CH1 to CH5 in Table 2) cannot be used simultaneously with active DMA (DMA function active in the peripheral register). The different peripherals supporting DMA transfers are shown in Table 1 and Table 2. The peripherals served by the DMA and the bus system structure are represented in Figure 1.
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DMA controller description Table 1. Peripherals served by DMA1 and channel allocation
CH1 ADC1 SPI1_RX SPI1_TX SPI2_RX SPI2_TX CH2 CH3 CH4 CH5 CH6
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Peripherals ADC ADC1 SPI1 SPI SPI2 USART1 USART USART2 USART3 I2C I2C1 I2C2
CH7
USART1_ USART1_RX TX USART2_RX USART2_TX USART3_TX USART3_RX I2C1_TX I2C2_TX TIM1_CH4 TIM1_CH2 TIM1_TRIG TIM1_COM I2C2_RX I2C1_RX
TIM1
TIM1_CH1
TIM1_UP
TIM
TIM2_CH3
TIM2_CH1
TIM4_CH1
TIM4_CH3
TIM4_UP
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AN2548 Table 2.
SPI/I2S3 SPI/I2S3_RX SPI/I2S3_TX USART4 SDIO TIM5 TIM6 TIM5_CH4 TIM5_TRIG TIM5_CH3 TIM5_UP TIM6_UP/ DAC_Channel1 TIM7_UP/ DAC_Channel2 TIM8_CH3 TIM8_UP TIM8_CH4 TIM8_TRIG TIM8_COM TIM8_CH1 TIM8_CH2 USART1_TX SDIO TIM5_CH2 TIM5_CH1 USART1_RX
TIM TIM7
TIM8
Figure 1.
SRAM FSMC
SDIO AHB system bus Bridge 2 Bridge 1
APB2 APB 1
DMA1
Ch.1 Ch.2
DMA
Ch.7
DMA Request
DMA2
GPIOC ADC1 ADC2 GPIOD ADC3 GPIOE USART1 GPIOF SPI1 GPIOG TIM1 EXTI TIM8 AFIO GPIOA GPIOB
DAC SPI3/I2S PWR SPI2/I2S IWDG BKP bxCAN WWDG RTC USB TIM7 I2C2 TIM6 I2C1 TIM5 UART5 TIM4 UART4 USART3 TIM3 USART2 TIM2
DMA request
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Performance considerations
AN2548
Performance considerations
The STM32F10xxxs three master modules are the Cortex-M3 processor and the two DMAs. They are connected to the slave buses, the Flash memory bus, the SRAM bus, the FSMC bus and the AHB system bus, through a bus matrix. The AHB system bus is in turn connected to the two APB buses that serve all the embedded peripherals (see Figure 1) but one the SDIO peripheral which is directly connected to the AHB system bus. The bus matrix has two main features that allow to maximize the system performance and reduce the latency:
3.1
3.2
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AN2548 Figure 2.
Performance considerations Bus stealing vs. burst mode for DMA transfer
CPU rq2 CPU rq3 CPU rq1 CPU stall SRAM DMA CPU CPU DMA CPU APB DMA DMA End of SW execution CPU rq4 DMA CPU
DMA data transfers using bus stealing CPU rq3 CPU rq2 DMA
CPU rq1
CPU stall
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3.3
DMA latency
Three operations are required to perform a DMA data transfer from peripheral to SRAM memory. When storing ADC continuous conversion data in SRAM, the following steps must be followed: 1. 2. 3. DMA request arbitration & address computation Reading data from the peripheral (DMA source) Writing loaded data in SRAM (DMA destination)
When transferring data from SRAM to peripheral (for example SPI transmission), the operations are performed in the opposite order: 1. 2. 3. DMA request arbitration & address computation Reading data from SRAM memory (DMA source) Writing data to the peripheral through the APB bus (DMA destination)
t S = t A + t Acc + t SRAM
The service time per channel, tS, is given by the equation below:
where:
tA is the arbitration time tA = 2 AHB clock cycle tACC is the peripheral access time tACC = 1 AHB clock cycle (bus matrix arbitration) + 2 APB clock cycles (effective data transfer) + 1 AHB clock cycle (bus synchronization)
tSRAM is the SRAM read or write access time tSRAM = 1 AHB clock cycle (bus matrix arbitration) + 1 AHB clock cycles (single read/write operation) or 2 AHB clock cycles in case of SRAM read-after-write access.
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Performance considerations
AN2548
When the DMA is idle or after the third operation has completed on one channel, the DMA compares the priorities of all pending DMA requests (software and hardware priorities, in this order). The highest priority channel is served next and the DMA jumps to execute the second operation. While a channel is being served (operation 2 or 3 ongoing), no other channel can be served whatever its priority. As a results, when at least two DMA channels are enabled, the DMA latency for the highest priority channel is the sum of the ongoing transfer time (without the arbitration phase) and the transfer time for the next DMA channel to be served (highest pending priority). For the case where only one DMA channel is active, a new request cannot be treated before completely closing the previous one (DMA rq/ack handshake). For this the total service time, tTS, must be used:
t TS = t A + t Acc + t SRAM + t BF + t Ack , where:
tBF is the bus free time (bus left free for CPU access) tBF = 1 AHB clock cycle tAck is the DMA acknowledge time (closing the handshake between peripheral & DMA) tAck = 1 AHB clock cycle
3.4
2.
The maximum APB clock division factor is given by the equation below: if
1N 2 N 1 N 1 ----- f AHB B max , where: 16
fAHB is the AHB clock frequency, N1 and N2 are APB1 and APB2 clock division factors, respectively, Bmax is the maximum peripheral data bandwidth on APB2 expressed in transfers/s.
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Performance considerations
DMA1 rq1
DMA1 rq2
APB2
CPU DMAy
DMA1
CPU
APB1
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Performance considerations
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3.5
The application requirements for each peripheral The internal data bandwidth
3.5.1
Application requirements
As an example, the data bandwidth for an SPI interface is obtained by dividing the baud rate by the data word length used by the SPI (since one full data needs to be transferred to/from the SPI before/after each transmission). Let us take the example of an SPI interface performing 8-bit data transfers at 18 MBaud, and configured to operate in simplex mode. In this case, the internal data bandwidth requirement are of 2.25 Mtransfers/s.
Note:
The data bandwidth can be divided by 2 when using the SPI in 16-bit mode: with the same baud rate, it only requires a transfer speed of 1.125 Mtransfers/s. It is strongly recommended, whenever possible, to use the 16-bit mode in order to minimize bus usage and power consumption.
3.5.2
The bus frequencies The available data bandwidth is directly proportional to the bus clock frequency. The bus type AHB data transfers take 2 clock cycles, except for SRAM read-after-write accesses that take 3 cycles. Data transfers to a peripheral through an APB bus takes 2 APB clock cycles plus 2 AHB clock cycles dedicated to bus matrix arbitration and data synchronization.
It is recommended to keep the DMA bus usage below 2/3 in order to maintain the system and CPU performance at a reasonable level.
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4.1
4.2
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4.3
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Revision history
Revision history
Table 3.
Date 29-June-2007
10-Dec-2007
30-Apr-2009
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AN2548
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