RNIC Verbs Overview2
RNIC Verbs Overview2
RNIC Verbs Overview2
Renato Recio
RNIC Verbs
! The
RDMA Protocol Verbs Specification describes the behavior of RNIC hardware, firmware, and software as viewed by the host,
"not
the host software itself, and "not the programming interface viewed by the host.
! The
behavioral description is specified in the form of an RNIC Interface (RI) and a set of RNIC Verbs:
"A
RNIC Interface defines the semantics of the RDMA services that are provided by an RNIC that supports the RNIC Verb Specification. The RI can be implemented through a combination of hardware, firmware, and software. Verb is an operation which an RNIC Interface is expected to be able to perform.
"A
First Principles
! Strove ! Strove
to minimize semantic and interface delta from existing standards (i.e. InfiniBand). Verbs Specification supports TCP transport.
! RNIC
"Some
effort was placed on provisioning for SCTP, but additional work would be needed for SCTP.
! Define
a common RNIC Interface that can be used by O/Ss and appliances to access RNIC functions. does not directly access queue elements.
! Consumer
"IB
! Background
"NICs
are in the process of incorporating layer 3 and layer 4 functions. scope of the RNIC Verbs Spec is Layer 4 access to RDMA functions:
#
Host
"The
Definition of the verbs (and their associated semantics) needed to access RDMA Protocol Layer functions.semantics. Except for connection management and teardown semantics, access to other layers is not semantically defined by the RNIC verbs.
! Verb
consumer SW that uses RNIC to communicate to other nodes. ! Communication is thru verbs, which:
"Manage
connection state. "Manage memory and queue access. "Submit work to RNIC. "Retrieve work and events from RNIC.
! RNIC
RI
RNIC
SQ Send Queue RQ Receive Queue SRQ Shared RQ QP Queue Pair QP = SQ + RQ CQ = Completion Queue
of software, firmware, and hardware. "Performs queue and memory mgt. "Converts Work Requests (WRs) to Work Queue Elements (WQEs). "Supports the standard RNIC layers (RDMA, DDP, MPA, TCP, IP, and Ethernet). "Converts Completion Queue Elements (CQEs) to Work Completions (WCs). "Generates asynchronous events.
"Consumer
# #
Verb consumer
WR WR WR
For all outbound messages, Consumer uses SQ. For inbound Send message types, Consumer uses: $ RQ, or $ SRQ (if QP was created with SRQ association).
"Work
#
"WR
#
types:
Send (four types), RDMA Write, RDMA Read, Bind MW, Fast-Register MR, and Invalidate STag
"RI
# #
RDMA/DDP/MPA/TCP/IP
RNIC
RI returns control to consumer immediately after WR has been converted to WQE and submitted to WQ. After control is returned to consumer, RI can not modify WR.
"Consumer
Verb consumer
WR WR WR
"Consumer
! RI
"Consumer
RDMA/DDP/MPA/TCP/IP
RNIC
Handler. "Asynchronous events are sent to consumer through Async Event Handler.
WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR
traditional RQ models (e.g. VIA, IB), for each WR WR connection the Consumer posts the number of receive WR WR MRs WRs necessary to handle incoming receives on that connection. WR SGLs ! If the Data Sink Consumer cannot predict the incoming rate on a given connection, the Data Sink Consumer WR WR WR WR must either: WR
A. Post the a sufficient number of RQ WQEs to handle the highest incoming rate for each connection.
WQE WQE WQE WQE
RQ
! Under
Post RQ WQE Rate >= Incoming rate Where Incoming rate may equal link B/W.
B. Let message flow control cause the Data Source to back off until Data Sink posts more WRs.
RNIC
Shared RQ enables more efficient use of memory or wire. ! Some Consumers (e.g. storage subsystems) manage a fixed-size pool of buffers amongst several different transport connections to RQ WQEs reduce buffer space requirements. are returned
to Consumer using the CQ.
"
WR WR WR WR WR
The SRQ model, enables these to post receive WRs to a queue that is shared by a (Consumer defined) set of connections.
! Under
the SRQ model the Consumer posts receive WRs to the SRQ and, as incoming segments arrive on a given QP that is associated with the SRQ, the SRQ WQEs are transferred from the SRQ to the RQ of the given QP.
"
SRQ
RQ
RQ
RQ
RNIC
! RNIC
"On
a given RQ, message WCs are returned in the order the associated messages were sent. "For a Send type message that arrives in order on a given RDMAP Stream:
# #
RNIC
SRQ
RQ
RQ
Next available WQE is pulled from SRQ, RNIC must behaves as if WQE is moved to RQ $ Whether it actually does or not is implementers choice.
"For
WQE
3 4 1
RNIC
SRQ
RQ
RQ
Sequential ordering: $ RNIC dequeues one WQE for the incoming message plus one WQE each message with an MSN lower than the out-of-order message that doesnt already have a WQE. Arrival ordering: $ RNIC dequeues one WQE. WQEs required for messages with lower MSNs, will be dequeued when those messages arrive.
Query RNIC has output modifier stating which Number represents arrival order. of the above options is supported by the RNIC. Color represents when WQE is dequeued. Order, from bottom, in RQ represents MSN order.
If QP is not associated with SRQ, WR posted to RQ. If QP associated with SRQ, WR posted SRQ.
SQ Errors, by where detected, and how it is returned: 1) Local Immediate, returned before WQE posted. Returned through CQE on associated CQ: 2) Local Completion, pre-WQE processing 3) Local Completion, post WQE processing 4) Remote Completion
(2)
WRs
(3)
WQE
WCs AEs
V (1) E R RI b s
(D) (4)
(C)
WQE
(B)
WQE RQ SQ
SQ WQE RQ CQ
CQE AEQE
CQE AEQE
CQ
AEQ
AEQ
(A) V E RI R b s
WRs
WCs AEs
RNIC - Requestor
RNIC - Responder
Asynchronous Error and Event: - Locally detected SQ, RQ, or RNIC errors or event that cannot be returned through CQ. - Returned instead through RNICs Asynchronous Event Queue.
Consumer Managed
User Kernel
Privile g
aged
! Memory
"Base
Regions
! Memory
TO to physical mapping of a (portion of) consumer process address space "RNIC Driver is responsible for pinning and translation. "Explicit registration by consumer with the RNIC Driver through RI registration mechanisms. "QP access to Regions managed through Protection Domains "QP consumers use Base TO addressing, RNIC performs Base TO to Physical mapping
Windows
"Windows
enable flexible & efficient dynamic RDMA access control to underlying Memory Regions "Consumer uses Send Queue to bind a pre-allocated Window to a specified portion of an existing Region. "QP access to Windows managed through QP ID.
QPC
X X
SQRQCQ SQRQCQ AE RNIC
Transport/Network/Link
Transport/Network/Link RNIC
! Considered
" When
#
a single server process communicates with multiple processes at the clients, two options are available from protecting STag access control:
Option 1: Use the same PD on all QPs. $ Problem: When multiple clients, or when multiple processes running on the same client, connect to the server process, process A can access the STag exposed to process B. Option 2: Use different PDs on each QP. $ Problem: If the same region is to be exposed to multiple clients/processes, the server process would need to create multiple windows, one for each client. Each MW would consumes one Memory Translation and Protection Table entry. PD based MW access control is not fine grained enough to support 1:N server:client models.
" Net:
#
! RNIC
" At
bind time QP ID is associated with the MW (vs the PD). " At access time, QP ID of MW must match QP ID of QP.
Consumer Managed
Privile g
aged
! Memory
"Driver
Regions
Page 1 performs Base TO to physical address mapping "Driver is responsible for pinning and Page 3 translation. ! Memory Windows "Consumer registers mappings with "Consumer uses Send Queue to RNIC through: bind a pre-allocated Window to a "RI registration mechanisms specified portion of an existing "Post SQ Fast-Register mechanism Region. "STag 0 is a special STag that "QP access to Windows managed requires no registration. through QP ID. "QP access to Regions managed through Protection Domains "Consumer uses Base TO, RNIC performs Base TO to physical mapping
VA based TO
First address has a non-zero value. To offset into address space: TO = Base VA + offset
Tagged Offset (Base TO) - The offset assigned to the first byte of a Memory Region. RNICs support two addressing types:
"Virtual
Address Based Tagged Offset (VA Base TO) The Base TO of an MR or MW that starts at a non-zero TO (and the address is associated with an address of the local hosts processor). Based Tagged Offset (Zero Base TO) - A Region or Window that starts with a TO of zero.
#
"Zero
Zero based TO
First address has a zero value. To offset into address space: TO = offset
Zero Based TO Created to meet the needs of Consumers that dont want to exchange addresses in their request/respond handshakes. $ For example, iSCSI Extensions for RDMA dont exchange a TO in the iSCSI Command or iSCSI Response. For iSER, the TO is only used in the RDMA Write and Read operations (more will be said later on iSER).
Buffer - A set of physically contiguous memory locations that can be directly accessed by the RNIC through Physical Addresses.
"Physical
#
The input modifier to register Non-Shared Memory Regions. $ Each Physical Buffer List Entry references a physical buffer.
"RNICs
# #
Page List - Created to support consumers that have page aligned physical buffers. Block List - Created to support consumers (e.g. storage) that have control information before and/or after each block on the list and the control information is not transferred.
! First
Byte Offset (FBO) - The offset into the first Physical Buffer of a Memory Region. List (SGL)
! Scatter/Gather
"The
#
input modifier to Post Send and Post Receive Verbs which indicate the data buffer location information.
Each Scatter/Gather List Entry references an existing Memory Region.
list attributes:
size:
"Page
"Data
#
boundaries:
Page 2
Data can start at an offset into the first page (First Byte Offset) Data can end on a non-page boundary (i.e. last page may be partially filled)
"Page
(starting) addresses:
# #
! Page
list modifiers:
size
Page N-1
Legend: - Pink = Data - Blue = Reserved
"Page "FBO
"Length
Page N
"Address
list
list attributes:
size:
"Block
Arbitrary (depends on sizes supported by RNIC) All pages have the same size
"Data
#
boundaries:
Block 2
Data can start at an offset into the first block (First Byte Offset) Data can end at an offset into the last block (i.e. last block may be partially filled)
"Block
#
(starting) addresses:
Arbitrary.
! Page
list modifiers:
size
Block N-1
Legend: - Pink = Data - Blue = Reserved
"Block "FBO
"Length
Block N
"Address
list
Memory Management
! Memory
Region (MR) - An area of memory that the Consumer wants the RNIC to be able to (locally or locally and remotely) access directly in a logically contiguous fashion.
"A
Memory Region is identified by an STag, a Base TO, and a length. "A Memory Region is associated with a Physical Buffer List through the STag.
! Two
types of MRs:
"Non-Shared
Memory Region - A Memory Region that solely owns the Physical Buffer List associated with the Memory Region. Specifically, the PBL is not shared and has never been shared with another Memory Region. Memory Region - An MR that currently shares, or at one time shared, the Physical Buffer List associated with the Memory Region. Specifically, the PBL is currently shared or was previously shared with another Memory Region.
"Shared
addressed by Fast-Register:
privileged consumer, compared to I/O transaction models over PCI, the synchronous RI-Registration mechanism is inefficient:
Hosts wastes CPU resources to perform registration $ RNIC driver issues PIO Writes to create the MR. Latency incurred waiting for RNIC to confirm the MR has been registered. $ Specially if the RNIC is attached through a PCI bus.
! More
"Allocate
#
STag - A mechanism used to allocate memory registration resources for use in subsequent Fast-Registrations or RI-Reregistrations.
Resources that get allocated are: $ Protection Domain, PBL, and Remote Access Enablement
"Fast-Register
Queue.
#
The Fast Register Work Request uses a Memory Region STag, that is in the Invalid state, to register the PBL and access controls passed in through Post Send Queue verb.
initialization (and possibly, at other intervals), consumer invokes Allocates STag with several size classes.
"For
# # # # #
example:
Large Size (65536 PhyPages) Medium-Large (1024 PhyPages) Medium (64 PhyPages) Medium-Small (16 PhyPages) Small (1 Physical Page)
! At
run-time, consumer chooses a previously allocated STag that has a size class which is higher or equal to the size of the Memory Region that is to be registered.
However, Verbs spec is silent on the above (it is up to the consumer to decide how to use the allocation).
6. Submit WR 4. Fast-Reg WR Verb 1. Allocate (PBL (that uses MR) capacity, PD, STag Key) (TO, length, STag, etc..) consumer
WR 1 WR 2
Animated Introductory Slide Depicting 10,000 Foot Overview of Memory Region Fast-Registration and Local Access
Verbs
3. Return (STag)
Memory TPT
SQ or RQ
MPA/TCP/IP
RNIC
! Privileged
Registers a Memory Region using an existing Non-Shared MR STag. If total # of pages <= Allocated STag PAT size and QP PD matches PD associated with the STag, then RNIC uses the Allocated STag to Register the MR (i.e. fills out Memory TPT entry). Otherwise it returns an error through the CQ.
"Key
Input Modifiers:
# # #
Allocated STag. Addressing type $ VA if VA based TO Access rights: $ Local Read, Local Write, Remote Read, and Remote Write $ Bind Enabled Physical Buffer List. $ FBO Length of Region to be registered in bytes and offset into first page.
"Key
! Problem
"Some
#
For these consumers the MR is created, used once, and never used again.
"RI
#
! RNIC
"Assuming
all STag checks pass, an incoming Send with Invalidate or Send with SE and Invalidate, invalidates access to an MR or MW. "An Invalidate STag Post SQ WR invalidates a local MR or MW through an asynchronous process.
! WR
# #
"Function:
"Key
# #
Input Modifiers:
"Key
# # #
Underlying Memory Valid Memory Window Region TO TO base base Zero based Zero based No Zero based VA based VA based VA based Zero based VA based No Yes Yes
Summary
!The
"Provides
#
a rich set of semantics that meet the needs of several application environments:
General networking, # Storage networking, and # Cluster networking.
"Enables
integration with existing RDMA APIs/KPIs, and provides extensions to those APIs/KPIs that improve performance. NIC Vendors with implementation flexibility, for:
"Provides
#
Queue management and memory management structures, as well as, integration with other NIC layer 3 and 4 offload functions.