Sprs 276 K
Sprs 276 K
Sprs 276 K
1 Features
12
High-Performance Fixed-Point DSP (C6455) 1.39-, 1.17-, 1-, and 0.83-ns Instruction Cycle Time 720-MHz, 850-MHz, 1-GHz, and 1.2-GHz Clock Rate Eight 32-Bit Instructions/Cycle 9600 MIPS/MMACS (16-Bits) Commercial Temperature [0C to 90C] Extended Temperature [-40C to 105C] TMS320C64x+ DSP Core Dedicated SPLOOP Instruction Compact Instructions (16-Bit) Instruction Set Enhancements Exception Handling TMS320C64x+ Megamodule L1/L2 Memory Architecture: 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped] 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative] 16M-Bit (2048K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation] 256K-Bit (32K-Byte) L2 ROM Time Stamp Counter Enhanced Viterbi Decoder Coprocessor (VCP2) Supports Over 694 7.95-Kbps AMR Programmable Code Parameters Enhanced Turbo Decoder Coprocessor (TCP2) Supports up to Eight 2-Mbps 3GPP (6 Iterations) Programmable Turbo Code and Decoding Parameters Endianess: Little Endian, Big Endian 64-Bit External Memory Interface (EMIFA) Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM) Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.) 32M-Byte Total Addressable External Memory Space
1
Four 1x Serial RapidIO Links (or One 4x), v1.2 Compliant 1.25-, 2.5-, 3.125-Gbps Link Rates Message Passing, DirectIO Support, Error Mgmt Extensions, Congestion Control IEEE 1149.6 Compliant I/Os DDR2 Memory Controller Interfaces to DDR2-533 SDRAM 32-Bit/16-Bit, 533-MHz (data rate) Bus 512M-Byte Total Addressable External Memory Space EDMA3 Controller (64 Independent Channels) 32-/16-Bit Host-Port Interface (HPI) 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification (v2.3) One Inter-Integrated Circuit (I2C) Bus Two McBSPs 10/100/1000 Mb/s Ethernet MAC (EMAC) IEEE 802.3 Compliant Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII) 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels Two 64-Bit General-Purpose Timers, Configurable as Four 32-Bit Timers UTOPIA UTOPIA Level 2 Slave ATM Controller 8-Bit Transmit and Receive Operations up to 50 MHz per Direction User-Defined Cell Format up to 64 Bytes 16 General-Purpose I/O (GPIO) Pins System PLL and PLL Controller Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller Advanced Event Triggering (AET) Compatible Trace-Enabled Device IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 697-Pin Ball Grid Array (BGA) Package (ZTZ or GTZ Suffix), 0.8-mm Ball Pitch 0.09-m/7-Level Cu Metal Process (CMOS)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
Copyright 20052011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
3.3-/1.8-/1.5-/1.25-/1.2-V I/Os,
1.25-/1.2-V Internal
1.1
AJ AH AF AD AB Y V U T R P M K J H G F D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 10 12 14 16 18 20 22 24 26 28 E N L AG AE AC AA W
NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls. For more detailed information, see the Mechanical Data section of this document.
1.2
Description
The TMS320C64x+ DSPs (including the TMS320C6455 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The C6455 device is based on the third-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible from previous devices that are part of the C6000 DSP platform. Based on 90-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6455 device offers cost-effective solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle. The TCI6482 device includes Serial RapidIO. This high bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.
TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
The C6455 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on the C6455 device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The level-2 (L2) memory is shared between program and data space and is 2048KB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp. The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient interface between the C6455 DSP core processor and the network; a management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA), which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM interface. The I2C ports on the C6455 device allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The C6455 DSP has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
1.3
DDR2 SDRAM
32
C6455
McBSP0 McBSP1
C64x+ DSP Core Instruction Fetch 16-/32-bit Instruction Dispatch L2Cache Memory 2048K Bytes Primary Switched Central Resource M e g a m o d u l e .L1 Instruction Decode Data Path A A Register File A31A16 A15A0 Control Registers SPLOOP Buffer In-Circuit Emulation Data Path B B Register File B31B16 B15B0 Interrupt and Exception Controller System Power Control L2 Memory Controller (Memory Protect/ Bandwidth Mgmt) Internal DMA (IDMA)
(A)
UTOPIA
(B)
.S1
.M1 xx .D1 xx
.D2
.M2 xx .S2 xx
.L2
(C)
EDMA 3.0
(C)
Timer1 HI LO
Boot Configuration
A. McBSPs: Framing Chips - H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs. B. The PCI peripheral pins are muxed with some of the HPI peripheral pins and the UTOPIA address pins. For more detailed information, see the Device Configuration section. C. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as a 64-bit general-purpose timer, dual 32-bit general-purpose timers, or a watchdog timer. D. The PLL2 controller also generates clocks for the EMAC. E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
................................................... 1 1.1 ZTZ/GTZ BGA Package (Bottom View) ............. 2 1.2 Description ........................................... 2 1.3 Functional Block Diagram ............................ 4 Revision History .............................................. 6 2 Device Overview ........................................ 7 2.1 Device Characteristics ............................... 7 2.2 CPU (DSP Core) Description ........................ 8 2.3 Memory Map Summary ............................. 11 2.4 Boot Sequence ..................................... 13 2.5 Pin Assignments .................................... 16 2.6 Signal Groups Description .......................... 20 2.7 Terminal Functions ................................. 26 2.8 Development ........................................ 51 2.9 Community Resources ............................. 54 3 Device Configuration ................................. 55 3.1 Device Configuration at Device Reset .............. 55 3.2 Peripheral Configuration at Device Reset .......... 57 3.3 Peripheral Selection After Device Reset ........... 58 3.4 Device State Control Registers ..................... 60 3.5 Device Status Register Description ................ 71 3.6 JTAG ID (JTAGID) Register Description ........... 73 3.7 Pullup/Pulldown Resistors .......................... 74 3.8 Configuration Examples ............................ 74 4 System Interconnect .................................. 77 4.1 Internal Buses, Bridges, and Switch Fabrics ....... 77 4.2 Data Switch Fabric Connections ................... 78 4.3 Configuration Switch Fabric ........................ 80 4.4 Bus Priorities ....................................... 82 5 C64x+ Megamodule ................................... 83 5.1 Memory Architecture ............................... 83 5.2 Memory Protection ................................. 85 5.3 Bandwidth Management ............................ 86 5.4 Power-Down Control ............................... 87 5.5 Megamodule Resets ................................ 87
1 Features
5.6 5.7
Megamodule Revision
.............................. .......................
88
97
Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) .... 97 Recommended Operating Conditions .............. 97 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) ............ 99
.......................................... ................................... PLL1 and PLL1 Controller ......................... PLL2 and PLL2 Controller ......................... DDR2 Memory Controller ......................... External Memory Interface A (EMIFA) ............ I2C Peripheral ..................................... Host-Port Interface (HPI) Peripheral .............. Multichannel Buffered Serial Port (McBSP) ....... Ethernet MAC (EMAC) ............................ Timers .............................................
Interrupts Reset Controller Enhanced Viterbi-Decoder Coprocessor (VCP2) Enhanced Turbo Decoder Coprocessor (TCP2) Peripheral Component Interconnect (PCI)
121 125 133 148 157 159 170 175 186 200 218 220 221 223 230 234 246 248
.....................................................
..................................................... ........ 7.19 UTOPIA ........................................... 7.20 Serial RapidIO (SRIO) Port ....................... 7.21 General-Purpose Input/Output (GPIO) ............ 7.22 Emulation Features and Capability ............... Mechanical Data ...................................... 8.1 Thermal Data ...................................... 8.2 Packaging Information ............................
250
250 250
TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made to the document in this revision. Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6455 device, have been incorporated. C6455 DSP Revision History
SEE Section 2.8.2.1 Section 2.9 Section 7.7.1.1 ADDITIONS/MODIFICATIONS/DELETIONS Device and Development-Support Tool Nomenclature: Modified Figure 2-13, TMS320C64x+ DSP Device Nomenclature (including the TMS320C6455 DSP) Added new section: Community Resources Internal Clocks and Maximum Operating Frequencies: Modified example to "PLLOUT is set to 1000 MHz" in fifth paragraph
TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
2 Device Overview
2.1 Device Characteristics
Table 2-1, provides an overview of the C6455 DSP. The tables show significant features of the C6455 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1. Characteristics of the C6455 Processor
HARDWARE FEATURES EMIFA (64-bit bus width) (clock source = AECLKIN or SYSCLK4) DDR2 Memory Controller (32-bit bus width) [1.8 V I/O] (clock source = CLKIN2) EDMA3 (64 independent channels) [CPU/3 clock rate] High-speed 1x/4x Serial Rapid IO Port Peripherals Not all peripherals pins are available at the same time (For more detail, see Section 3, Device Configuration). I2C HPI (32- or 16-bit user selectable) PCI (32-bit), [66-MHz or 33-MHz] McBSPs (internal CPU/6 or external clock source up to 100 Mbps) UTOPIA (8-bit mode, 50-MHz, Slave-only) 10/100/1000 Ethernet MAC (EMAC) Management Data Input/Output (MDIO) 64-Bit Timers (Configurable) (internal clock source = CPU/6 clock frequency) General-Purpose Input/Output Port (GPIO) Decoder Coprocessors VCP2 (clock source = CPU/3 clock frequency) TCP2 (clock source = CPU/3 clock frequency) Size (Bytes) On-Chip Memory C6455 1 1 1 1 1 1 (HPI16 or HPI32) 1 (PCI66 or PCI33) 2 1 1 1 2 64-bit or 4 32-bit 16 1 1 2192K 32K-Byte (32KB) L1 Program Memory Controller [SRAM/Cache] 32KB Data Memory Controller [SRAM/Cache] 2048KB L2 Unified Memory/Cache 32KB L2 ROM See Section 5.6, Megamodule Revision See Section 3.6, JTAG ID (JTAGID) Register Description 720, 850, 1000 (1 GHz), and 1200 (1.2 GHz) 1.39 ns (C6455-720), 1.17 ns (C6455-850), 1 ns (C6455 A-1000, -1000) [1-GHz CPU] (1) 0.83 ns (C6455-1200) [1.2-GHz CPU] 1.25 V (A-1000/-1000/-1200) 1.2 V (-850/-720) 1.25/1.2 [RapidIO], 1.5/1.8 [EMAC RGMII], and 1.8 and 3.3 V [I/O Supply Voltage] Bypass (x1), x15, x20, x25, x30, x32 x20 697-Pin Flip-Chip Plastic BGA (ZTZ) 697-Pin Plastic BGA (GTZ)
Organization
Megamodule Revision ID Register (address location: 0181 2000h) JTAGID register (address location: 0x02A80008) MHz ns Core (V)
Voltage I/O (V) PLL1 and PLL1 Controller Options PLL2 BGA Package CLKIN1 frequency multiplier CLKIN2 frequency multiplier [DDR2 Memory Controller and EMAC support only] 24 x 24 mm
(1)
The extended temperature device's (A-1000) electrical characteristics and ac timings are the same as those for the corresponding commercial temperature devices (-1000). Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320C6455 7
TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
(2)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
2.2
TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
Other new features include: SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible. Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools. Instruction Set Enhancements - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. Exception Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls. For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents: TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732) TMS320C64x+ DSP Cache User's Guide (literature number SPRU862) TMS320C64x+ Megamodule Reference Guide (literature number SPRU871) TMS320C6455 Technical Reference (literature number SPRU965) TMS320C64x to TMS320C64x+ CPU Migration Guide (literature number SPRAA84)
TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011
src1
.L1
src2
odd dst
long src
Data path A
.M1
LD1b LD1a
32 MSB 32 LSB
DA1
src2
DA2
src2 .D2
src1 dst
LD2a LD2b
32 LSB 32 MSB
src2 src1
Data path B
32 MSB 32 LSB
src1
A. B. C. D.
On .M unit, dst2 is 32 MSB. On .M unit, dst1 is 32 LSB. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
10
8 8 32 32 32 32 8 8
www.ti.com
(D)
(A) (B)
(C)
2x 1x Odd register file B (B1, B3, B5...B31) Even register file B (B0, B2, B4...B30)
(D)
(D)
Control Register
TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
2.3
Reserved Internal ROM Reserved Internal RAM (L2) [L2 SRAM] Reserved L1P SRAM Reserved L1D SRAM Reserved Reserved C64x+ Megamodule Registers Reserved HPI Control Registers McBSP 0 Registers McBSP 1 Registers Timer 0 Registers Timer 1 Registers PLL1 Controller (including Reset Controller) Registers Reserved PLL2 Controller Registers Reserved EDMA3 Channel Controller Registers Reserved EDMA3 Transfer Controller 0 Registers EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers EDMA3 Transfer Controller 3 Registers Reserved Chip-Level Registers Device State Control Registers GPIO Registers I2C Data and Control Registers UTOPIA Control Registers Reserved VCP2 Control Registers TCP2 Control Registers Reserved PCI Control Registers Reserved EMAC Control EMAC Control Module Registers MDIO Control Registers
11
TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
BLOCK SIZE (BYTES) 8K 496K 256K 768K 16K 2M - 16K 16M 192M 256M 256M 256 64M - 256 256 64M - 256 64M 1K 1K 16M - 2K 48M 256M 128M 128M 256M 128M 128M 256M 256M 8M 256M - 8M 8M 256M - 8M 8M 256M - 8M 8M 256M - 8M 512M
HEX ADDRESS RANGE 02C8 2000 - 02C8 3FFF 02C8 4000 - 02CF FFFF 02D0 0000 - 02D3 FFFF 02D4 0000 - 02DF FFFF 02E0 0000 - 02E0 3FFF 02E0 4000 - 02FF FFFF 0300 0000 - 03FF FFFF 0400 0000 - 0FFF FFFF 1000 0000 - 1FFF FFFF 2000 0000 - 2FFF FFFF 3000 0000 - 3000 00FF 3000 0100 - 33FF FFFF 3400 0000 - 3400 00FF 3400 0100 - 37FF FFFF 3800 0000 - 3BFF FFFF 3C00 0000 - 3C00 03FF 3C00 0400 - 3C00 07FF 3C00 0800 - 3CFF FFFF 3D00 0000 - 3FFF FFFF 4000 0000 - 4FFF FFFF 5000 0000 - 57FF FFFF 5800 0000 - 5FFF FFFF 6000 0000 - 6FFF FFFF 7000 0000 - 77FF FFFF 7800 0000 - 7FFF FFFF 8000 0000 - 8FFF FFFF 9000 0000 - 9FFF FFFF A000 0000 - A07F FFFF A080 0000 - AFFF FFFF B000 0000 - B07F FFFF B080 0000 - BFFF FFFF C000 0000 - C07F FFFF C080 0000 - CFFF FFFF D000 0000 - D07F FFFF D080 0000 - DFFF FFFF E000 0000 - FFFF FFFF
The EMIFA CE0 and CE1 are not functionally supported on the C6455 device and, therefore, are not pinned out.
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TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
2.4
Boot Sequence
The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections and the DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, max reset, and system reset. For more details on the initiators of these resets, see Section 7.6, Reset Controller. There are several methods by which the memory and register initialization can take place. Each of these methods is referred to as a boot mode. The boot mode to be used is selected at reset through the BOOTMODE[3:0] pins. Each boot mode can be classified as a hardware boot mode or as a software boot mode. Software boot modes require the use of the on-chip bootloader. The bootloader is DSP code that transfers application code from an external source into internal or external program memory after the DSP is taken out of reset. The bootloader is permanently stored in the internal ROM of the DSP starting at byte address 0010 0000h. Hardware boot modes are carried out by the boot configuration logic. The boot configuration logic is actual hardware that does not require the execution of DSP code. Section 2.4.1, Boot Modes Supported, describes each boot mode in more detail. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz. Therefore, when using a software boot mode, care must be taken such that the CPU frequency does not exceed 750 MHz at any point during the boot sequence. After the boot sequence has completed, the CPU frequency can be programmed to the frequency required by the application.
2.4.1
13
TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt is generated by the host. The host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back-End Application Interrupt Enable Set Register (PCIBINTSET) and the Status Set Register (PCISTATSET). Note that the HPI host boot is a hardware boot mode while the PCI host boot is a software boot mode. If PCI boot is selected, the on-chip bootloader configures the PLL1 Controller such that CLKIN1 is multiplied by 15. More specifically, PLLM is set to 0Eh (x15) and RATIO is set to 0 (1) in the PLL1 Multiplier Control Register (PLLM) and PLL1 Pre-Divider Register (PREDIV), respectively. The CLKIN1 frequency must not be greater than 50 MHz so that the maximum speed of the internal ROM, 750 MHz, is not violated. The CFGGP[2:0] pins must be set to 000b during reset for proper operation of the PCI boot mode. As mentioned previously, a DSP interrupt must be generated at the end of the host boot process to begin execution of the loaded application. Since the DSP interrupt generated by the HPI and PCI is mapped to the EDMA event DSP_EVT (DMA channel 0), it will get recorded in bit 0 of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0. EMIFA 8-bit ROM boot (BOOTMODE[3:0] = 0100b) After reset, the device will begin executing software out of an Asynchronous 8-bit ROM located in EMIFA CE3 space using the default settings in the EMIFA registers. This boot mode is a hardware boot mode. Master I2C boot (BOOTMODE[3:0] = 0101b) After reset, the DSP can act as a master to the I2C bus and copy data from an I2C EEPROM or a device acting as an I2C slave to the DSP using a predefined boot table format. The destination address and length are contained within the boot table. This boot mode is a software boot mode. Slave I2C boot (BOOTMODE[3:0] = 0110b) A Slave I2C boot is also implemented, which programs the DSP as an I2C Slave and simply waits for a Master to send data using a standard boot table format. Using the Slave I2C boot, a single DSP or a device acting as an I2C Master can simultaneously boot multiple slave DSPs connected to the same I2C bus. Note that the Master DSP may require booting via an I2C EEPROM before acting as a Master and booting other DSPs. The Slave I2C boot is a software boot mode. Serial RapidIO boot (BOOTMODE[3:0] = 1000b through 1111b) After reset, the following sequence of events occur: The on-chip bootloader configures device registers, including SerDes, and EDMA3 The on-chip bootloader resets the peripheral's state machines and registers RapidIO ports send idle control symbols to initialize SerDes ports The host explores the system with RapidIO maintenance packets The host identifies, enumerates, and initializes the RapidIO device The host controller configures DSP peripherals through maintenance packets The application software is sent from the host controller to DSP memory The DSP CPU is awakened by interrupt such as a RapidIO DOORBELL packet The application software is executed and normal operation follows For Serial RapidIO boot, BOOTMODE2 (L26 pin) is used in conjunction with CFGGP[2:0] (T26, U26, and U25 pins, respectively) to determine the device address within the RapidIO network. BOOTMODE2 is the MSB of the address, while CFGGP[2:0] are used as the three LSBsgiving the user the opportunity to have up to 16 unique device IDs. BOOTMODE[1:0] (L25 and P26, respectively) denote the configuration of the RapidIO peripheral; i.e., "00b" refers to RapidIO Configuration 0. For exact device RapidIO configurations, see the TMS320C645x/C647x DSP Bootloader User's Guide (literature number SPRUEC6).
Copyright 20052011, Texas Instruments Incorporated
14
TMS320C6455
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2.4.2
2nd-Level Bootloaders
Any of the boot modes can be used to download a 2nd-level bootloader. A 2nd-level bootloader allows for any level of customization to current boot methods as well as definition of a completely customized boot. TI offers a few 2nd-level bootloaders, such as an EMAC bootloader and a UTOPIA bootloader, which can be loaded using the Master I2C boot.
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TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
2.5 2.5.1
AJ
DVDD33
GP[5]
FSX0
CLKS
DR0
TINPL1
DVDD33
VSS
TCK
TMS
RSV26
RSV40
SYSCLK4/ GP[1]
VSS
DVDD33
AJ
AH
VSS
GP[4]
FSR0
NMI
DR1/ GP[8]
TINPL0
TRST
TDO
TDI
EMU17
RSV27
EMU16
EMU9
DVDD33
VSS
AH
AG
CLKR0
GP[7]
GP[6]
FSX1/ GP[11]
DX1/ GP[9]
CLKX0
TOUTL1
EMU6
EMU2
RSV38
RSV39
DVDD33
VSS
RESET
RIOCLK
AG
AF
DVDD33
VSS
HD11/ AD11
CLKR1/ GP[0]
CLKX1/ GP[3]
DX0
EMU0
TOUTL0
EMU4
EMU3
EMU8
EMU7
EMU14
POR
RIOCLK
AF
AE
HD22/ AD22
HD0/ AD0
HD10/ AD10
VSS
FSR1/ GP[10]
DVDD33
VSS
DVDD33
EMU15
EMU12
EMU1
EMU5
EMU18
RESETSTAT
DVDD33
AE
AD
HD21/ AD21
HD25/ AD25
HD5/ AD5
HD3/ AD3
DVDD33
VSS
DVDD33
EMU13
RSV37
EMU10
RSV36
EMU11
VSS
DVDD33
VSS
AD
AC
HD19/ AD19
HD13/ AD13
HD23/ AD23
HD29/ AD29
HD27/ AD27
DVDD33
VSS
VSS
DVDD33
VSS
DVDD33
VSS
DVDD33
VSS
AVDDA
AC
AB
HD17/ AD17
HD15/ AD15
HD9/ AD9
HD7/ AD7
HD1/ AD1
VSS
DVDD33
AB
AA
DVDD33
VSS
HD31/ AD31
HD28/ AD28
HD30/ AD30
DVDD33
VSS
AA
HD26/ AD26
HD18/ AD18
HD16/ AD16
HD6/ AD6
HD4/ AD4
VSS
DVDD33
HD24/ AD24
HD20/ AD20
RSV03
HD14/ AD14
HD8/ AD8
HD2/ AD2
VSS
VSS
CVDD
VSS
CVDD
VSS
DVDD33
VSS
HHWIL/ PCLK
HD12/ AD12
RSV02
VSS
DVDD33
CVDD
VSS
CVDD
VSS
DVDDRM
HDS2/ PCBE1
HDS1/ PSERR
HINT/ PFRAME
HCNTL1/ PDEVSEL
HCNTL0/ PSTOP
HCS/ PPERR
VSS
VSS
CVDD
VSS
CVDD
VSS
RSV15
RSV16
HAS/ PPAR
HRDY/ PIRDY
HR/W/ PCBE2
VSS
DVDD33
CVDD
VSS
CVDD
VSS
CVDD
DVDD33
VSS
UXADDR1/ PIDSEL
DVDD33
VSS
VSS
CVDD
VSS
CVDD
VSS
10
11
12
13
14
15
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www.ti.com
16 17 18 19 20 21 22 23 24
AJ
VSS
AVDDT
RIORX2
RIORX2
VSS
RIORX1
RIORX1
AVDDT
VSS
DVDD33
AED5
AED6
AED20
DVDD33
AJ
AH
DVDD33
RIORX3
RIORX3
VSS
AVDDT
VSS
RIORX0
RIORX0
DVDD33
VSS
AED14
AED2
AED18
VSS
AH
AG
VSS
DVDD33
RIOTX2
RIOTX2
VSS
RIOTX1
RIOTX1
DVDD33
VSS
AED3
SCL
AED9
AED16
AED30
AG
AF
DVDD33
RIOTX3
RIOTX3
VSS
AVDDT
VSS
RIOTX0
RIOTX0
DVDD33
AED1
SDA
AED10
AED15
AED19
AF
AE
VSS
AVDDT
VSS
AVDDT
VSS
RSV17
VSS
AVDDT
VSS
AED7
AED12
AED4
AED13
AED17
AE
AD
AVDDA
VSS
DVDD33
VSS
DVDDR
VSS
DVDD33
VSS
DVDD33
AED0
AED11
AED8
AED22
AED21
AD
AC
VSS
AVDDA
VSS
DVDD33
VSS
DVDD33
VSS
DVDD33
VSS
AED24
AED26
AED28
VSS
DVDD33
AC
AB
VSS
DVDD33
AAWE/ ASWE
AED23
AED25
AED27
AED29
AB
AA
DVDD33
VSS
ABE1
ABE0
AED31
ABE2
ABE3
AA
VSS
DVDD33
RSV43
RSV42
RSV44
AAOE/ ASOE
PCI_EN
DVDD12
VSS
DVDD12
VSS
DVDD33
VSS
AR/W
ACE3
ACE2
RSV41
ABE7
VSS
DVDDRM
VSS
CVDD
VSS
DVDD33
ABA1/ EMIFA_EN
ABA0/ DDR2_EN
ACE5
ACE4
AECLKOUT V
DVDDRM
VSS
CVDD
VSS
DVDD33
VSS
AEA0/ CFGGP0
AEA1/ CFGGP1
AEA6/ PCI66
RSV20
VSS
CVDD
VSS
CVDD
VSS
DVDD33
AEA11
AEA2/ CFGGP2
AEA3
PLLV1
CVDD
VSS
CVDD
VSS
DVDD33
VSS
ASADS/ ASRE
AEA13/ LENDIAN
AEA12/ UTOPIA_EN
AHOLD
16
17
18
19
20
21
22
23
24
26
27
28
29
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16
17
18
19
20
21
22
23
24
25
26
27
28
29
VSS
CVDD
VSS
CVDD
RSV30
RSV31
AEA8/ PCI_EEAI
DVDD33
VSS
CVDD
VSS
CVDD
VSS
VSS
DVDD33
AHOLDA
AEA7
CLKIN1
AECLKIN
VSS
CVDD
VSS
CVDD
DVDD33
VSS
AEA10/ MACSEL1
VSS
AEA9/ MACSEL0
DVDD33
VSS
CVDD
VSS
CVDD
VSS
VSS
DVDD33
ABUSREQ
ABE4
ABE5
DVDD33
VSS
AED33
ABE6
AED32
AED34
AARDY
VSS
DVDD33
AED38
AED46
AED44
AED42
AED40
DVDD33
VSS
AED47
AED45
AED43
DVDD33
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
AED55
AED54
AED50
AED48
AED35
VSS
DVDD18
RSV19
DVDD18
VSS
DSDDQ GATE3
VSS
DVDD18
VSS
AED63
AED36
AED56
AED52
AED37
DEODT0
DEA4
AVDLL2
VSS
DSDDQS2
DSDDQ GATE2
DVDD18
DSDDQS3
DVDD18
VSS
DVDD33
AED59
DVDD33
VSS
DEA8
DEA5
DEA0
DED19
DSDDQS2
DED23
DED27
DSDDQS3
RSV11
RSV32
RSV09
AED57
AED58
AED39
DEA9
DEA6
DEA1
DED18
DSDDQM2
DED22
DED26
DSDDQM3
RSV12
RSV33
RSV23
AED61
AED60
AED41
DEA10
DEA7
DEA2
DED16
DVDD18
DED21
DED25
DVDD18
DED29
DED31
RSV22
AED49
AED51
VSS
DEA11
DEODT1
DEA3
DED17
VSS
DED20
DED24
VSS
DED28
DED30
DVDD18MON
AED62
AED53
DVDD33
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
10
11
12
13
14
15
UXADDR0/ PTRDY
UXADDR2/ PCBE3
DVDD33
VSS
RSV05
VSS
CVDD
VSS
CVDD
CVDDMON
VSS
UXADDR3/ MDIO
UXDATA7/ MTXD7
RSV29
RSV28
RSV04
CVDD
VSS
CVDD
VSS
URDATA7/ MRXD7
UXDATA6/ MTXD6
UXDATA2/ MTXD2
UXADDR4/ MDCLK
VSS
DVDD33
CVDD
VSS
CVDD
VSS
CVDD
URDATA4/ MRXD4
URDATA5/ MRXD5
UXDATA4/ MTXD4
UXDATA5/ MTXD5
DVDD33MON
VSS
VSS
CVDD
VSS
CVDD
VSS
DVDD33
VSS
UXSOC/ MCOL
UXDATA3/ MTXD3
UXCLAV/ GMTCLK
VSS
DVDD33
URDATA2/ MRXD2
URDATA3/ MRXD3
DVDD33
VSS
URCLK/ MRCLK
URDATA6/ MRXD6
URENB/ MRXDV
VSS
DVDD15
VSS
DVDD33
CLKIN2
RSV07
VSS
DVDD15
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
RSV14
RSV13
DVDD15MON
VSS
DVDD15
VSS
DVDD18
VSS
DED11
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
RGRXD0
RGRXD1
RGRXC
RGRXD2
VSS
RSV34
VSS
DSDDQS1
DED10
DVDD18
DSDDQS0
DVDD18
RSV18
DCE0
DBA2
VSS
DVDD15
RGTXCTL
RGTXC
DVDD15
RSV35
DED14
DSDDQS1
DED9
DED7
DSDDQS0
DED3
DSDCAS
DSDCKE
DBA1
RGRXD3
RGRXCTL
RGTXD2
RGREFCLK
VSS
RSV25
DED15
DSDDQM1
DED8
DED6
DSDDQM0
DED2
DSDRAS
VREFSSTL
DBA0
VSS
VREFHSTL
RGTXD1
RGMDCLK
DVDD15
RSV24
DED12
DVDD18
DSDDQ GATE1
DED5
DVDD18
DED1
DSDWE
DDR2 CLKOUT
DEA13
DVDD15
RGTXD3
RGTXD0
RGMDIO
PLLV2
RSV21
DED13
VSS
DSDDQ GATE0
DED4
VSS
DED0
AVDLL1
DDR2 CLKOUT
DEA12
10
11
12
13
14
15
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TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
2.6
TMS TDO TDI TCK TRST Reserved EMU0 EMU1 IEEE Standard 1149.1 (JTAG) Emulation
RSV42 RSV43 RSV44
Peripheral Enable/Disable
PCI_EN
Control/Status
A.
This pin functions as GP[1] by default. For more details, see Section 3.
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TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
TINPL1 TOUTL1
Timer 1
Timer 2
TOUTL0 TINPL0
Timers (64-Bit)
URADDR3/PREQ/GP[15] (C) URADDR2/PINTA/GP[14] (C) URADDR1/PRST/GP[13] (C) URADDR0/PGNT/GP[12] (B) FSX1/GP[11] (B) FSR1/GP[10] (B) DX1/GP[9] (B) DR1/GP[8]
(C)
GPIO
GP[7] GP[6] GP[5] GP[4] (B) CLKX1/GP[3] (C) URADDR4/PCBE0/GP[2] (A) SYSCLK4/GP[1] (B) CLKR1/GP[0]
RIOTX[3:0] RIOTX[3:0]
RIORX[3:0] RIORX[3:0]
4 4 Receive RapidIO
A. This pin functions as GP[1] by default. B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and, by default, these signals function as GPIO peripheral pins. For more details, see the Device Configuration section of this document. C. These UTOPIA and PCI peripheral pins are muxed with the GPIO peripheral pins and, by default, these signals function as GPIO peripheral pins. For more details, see the Device Configuration section of this document.
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TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
64 AED[63:0] ACE5(A) ACE4(A) ACE3(A) ACE2(A) 20 AEA[19:0] ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0 Address Data AECLKIN Memory Map Space Select External Memory I/F Control AECLKOUT
Byte Enables
32 DED[31:0] Data
DDR2CLKOUT DDR2CLKOUT DSDCKE DSDCAS External Memory I/F Control DSDRAS DSDWE DSDDQS[3:0] DSDDQS[3:0] DSDDQGATE[0] DSDDQGATE[1] DSDDQGATE[2] DSDDQGATE[3] DEODT[1:0]
DCE0
DEA[13:0]
Address
Byte Enables
Bank Address
DBA[2:0]
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TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
32
Data
HPI(A) (Host-Port Interface) HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME
Receive
Receive
Clock
I2C
SCL SDA
A.
B.
These HPI pins are muxed with the PCI peripheral. By default, these pins function as HPI. When the HPI is enabled, the number of HPI pins used depends on the HPI configuration (HPI16 or HPI32). For more details on these muxed pins, see the Device Configuration section of this document. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For more details, see the Device Configuration section of this document.
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TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
Ethernet MAC (EMAC) Transmit MII UXDATA[7:2]/MTXD[7:2], UXDATA[1:0]/MTXD[1:0]/RMTXD[1:0] RMII GMII RGTXD[3:0] RGMII(A) MDIO Input/Output MII Receive RMII MII URDATA[7:2]/MRXD[7:2], URDATA[1:0]/MRXD[1:0]/RMRXD[1:0] RMII GMII RGRXD[3:0] RGMII(A) Clock MII RMII GMII RGMII(A) RGMDCLK UXADDR4/MDCLK GMII RGMII(A) RGMDIO UXADDR3/MDIO
Error Detect and Control URSOC/MRXER/RMRXER, URENB/MRXDV, URCLAV/MCRS/RMCRSDV, UXSOC/MCOL, UXENB/MTXEN/RMTXEN RGTXCTL, RGRXCTL MII RMII GMII RGMII(A)
Clocks MII UXCLK/MTCLK/RMREFCLK, URCLK/MRCLK, UXCLAV/GMTCLK RMII GMII RGTXC, RGRXC, RGREFCLK RGMII(A)
Ethernet MAC (EMAC) and MDIO(B) A. RGMII signals are mutually exclusive to all other EMAC signals. B. These EMAC pins are muxed with the UTOPIA peripheral. By default, these signals function as EMAC. For more details on these muxed pins, see the Device Configuration section of this document.
Figure 2-10. EMAC/MDIO [MII, GMII, RMII, and RGMII] Peripheral Signals
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TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
UTOPIA (SLAVE)(A)
Receive
Transmit
Control/Status
Control/Status
URCLK/MRCLK
Clock
Clock
UXCLK/MTCLK/ RMREFCLK
A. These UTOPIA pins are muxed with the PCI or EMAC or GPIO peripherals. By default, these signals function as GPIO or EMAC peripheral pins or have no function. For more details on these muxed pins, see the Device Configuration section of this document.
Control
URADDR0/PGNT/GP[12] URADDR3/PREQ/GP[15]
Arbitration Error
HDS1/PSERR HCS/PPERR
PCI Interface(A)
A. These PCI pins are muxed with the HPI or UTOPIA or GPIO peripherals. By default, these signals function as GPIO or EMAC. For more details on these muxed pins, see the Device Configuration section of this document.
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TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
2.7
Terminal Functions
The terminal functions table (Table 2-3) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see Section 3, Device Configuration. Table 2-3. Terminal Functions
SIGNAL NAME NO. N28 G3 T29 A5 AJ13 TYPE (1) IPD/IPU (2) CLOCK/PLL CONFIGURATIONS DESCRIPTION
I I A A I/O/Z
IPD IPD
Clock Input for PLL1. Clock Input for PLL2. 1.8-V I/O supply voltage for PLL1 1.8-V I/O supply voltage for PLL2 SYSCLK4 is the clock output at 1/8 of the device speed (O/Z) or this pin can be programmed as the GP1 pin (I/O/Z) [default]. JTAG EMULATION JTAG test-port mode select JTAG test-port data out JTAG test-port data in JTAG test-port clock JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see Section 7.22.3.1.1. Emulation pin 0 Emulation pin 1 Emulation pin 2 Emulation pin 3 Emulation pin 4 Emulation pin 5 Emulation pin 6 Emulation pin 7 Emulation pin 8 Emulation pin 9 Emulation pin 10 Emulation pin 11 Emulation pin 12 Emulation pin 13 Emulation pin 14 Emulation pin 15 Emulation pin 16 Emulation pin 17 Emulation pin 18
IPD
TMS TDO TDI TCK TRST EMU0 (4) EMU1 (4) EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMU10 EMU11 EMU12 EMU13 EMU14 EMU15 EMU16 EMU17 EMU18
AJ10 AH8 AH9 AJ9 AH7 AF7 AE11 AG9 AF10 AF9 AE12 AG8 AF12 AF11 AH13 AD10 AD12 AE10 AD8 AF13 AE9 AH12 AH10 AE13
I O/Z I I I I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
IPU IPU IPU IPU IPD IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. For most systems, a 1-k resistor can be used to oppose the IPU/IPD. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.7, Pullup/Pulldown Resistors. These pins are multiplexed pins. For more details, see Section 3, Device Configuration. The C6455 DSP does not require external pulldown resistors on the EMU0 and EMU1 pins for normal or boundary-scan operation. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320C6455
Copyright 20052011, Texas Instruments Incorporated
TMS320C6455
www.ti.com SPRS276K MAY 2005 REVISED FEBRUARY 2011
NO. AG14 AH4 AE14 AF14 AG2 AG3 AJ2 AH2 P2 / P3 R5 R4 AG4 AE5 AG5 AH5 AF5 P1 AJ13 AF4
TYPE (1)
IPD/IPU (2)
DESCRIPTION
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS I I O I I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z O/Z I/O/Z IPD IPD PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:8], or PCI peripherals. This pin works in conjunction with the MCBSP1_EN (AEA5 pin) to enable/disable other peripherals (for more details, see Section 3, Device Configuration). Host interrupt from DSP to host (O/Z) or PCI frame (I/O/Z) Host control - selects between control, address, or data registers (I) [default] or PCI device select (I/O/Z) Host control - selects between control, address, or data registers (I) [default] or PCI stop (I/O/Z) Host half-word select - first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I) [default] or PCI clock (I) Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z) Host address strobe (I) [default] or PCI parity (I/O/Z) Host chip select (I) [default] or PCI parity error (I/O/Z) Host data strobe 1 (I) [default] or PCI system error (I/O/Z) Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z) Host ready from DSP to host (O/Z) [default] or PCI initiator ready (I/O/Z) UTOPIA received address pin 3 (URADDR3) (I) or PCI bus request (O/Z) or GP[15] (I/O/Z) [default] IPD IPD IPD IPD IPD UTOPIA received address pins or PCI peripheral pins or General-purpose input/output (GPIO) [15:12, 2] pins (I/O/Z) [default] PCI PCI PCI PCI PCI bus request (O/Z) or GP[15] (I/O/Z) [default] interrupt A (O/Z) or GP[14] (I/O/Z) [default] reset (I) or GP[13] (I/O/Z) [default] bus grant (I) or GP[12] (I/O/Z) [default] command/byte enable 0 (I/O/Z) or GP[2] (I/O/Z) [default] IPD IPD IPD IPD General-purpose input/output (GPIO) pins (I/O/Z). IPD Device reset Nonmaskable interrupt, edge-driven (rising edge) Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded versus relying on the IPD. Reset Status pin. The RESETSTAT pin indicates when the device is in reset Power on reset.
McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default] McBSP1 receive clock (I/O/Z) or GP[0] (I/O/Z) [default] GP[1] pin (I/O/Z). SYSCLK4 is the clock output at 1/8 of the device speed (O/Z) or this pin can be programmed as a GP[1] pin (I/O/Z) [default].
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) PCI_EN HINT/PFRAME HCNTL1/PDEVSEL HCNTL0/PSTOP HHWIL/PCLK HR/W/PCBE2 HAS/PPAR HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY URADDR3/PREQ/ GP[15] (5) (6)
(6)
Y29 U3 U4 U5 V3 T5 T3 U6 U2 U1 T4 P2
I I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
IPD
These pins function as open-drain outputs when configured as PCI pins. These pins function as open-drain outputs when configured as PCI pins. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320C6455 27
TMS320C6455
SPRS276K MAY 2005 REVISED FEBRUARY 2011 www.ti.com
NO. / P3 R5 R4 P1 P5 R3 P4 AA3 AA5 AC4 AA4 AC5 Y1 AD2 W1 AC3 AE1 AD1 W2 AC1 Y2 AB1 Y3 AB2 W4 AC2 V4 AF3 AE3 AB3 W5 AB4 Y4 AD3 Y5 AD4 W6 AB5 AE2
IPD/IPU (2)
DESCRIPTION UTOPIA received address pin 2 (URADDR2) (I) or PCI interrupt A (O/Z) or GP[14] (I/O/Z) default] UTOPIA received address pin 1 (URADDR1) (I) or PCI reset (I) or GP[13] (I/O/Z) [default] UTOPIA received address pin 0 (URADDR0) (I) or PCI bus grant (I) or GP[12] (I/O/Z)[default] UTOPIA received address pin 4 (URADDR4) (I) or PCI command/byte enable 0 (I/O/Z) or GP[2] (I/O/Z)[default] UTOPIA transmit address pin 2 (UXADDR2) (I) or PCI command/byte enable 3 (I/O/Z). By default, this pin has no function. UTOPIA transmit address pin 1 (UXADDR1) (I) or PCI initialization device select (I). By default, this pin has no function. UTOPIA transmit address pin 0 (UXADDR0) (I) or PCI target ready (PRTDY) (I/O/Z). By default, this pin has no function.
I/O/Z
Host-port data [31:16] pin (I/O/Z) [default] or PCI data-address bus [31:16] (I/O/Z)
I/O/Z
Host-port data [15:0] pin (I/O/Z) [default] or PCI data-address bus [15:0] (I/O/Z)
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EMIFA (64-BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY O/Z IPD EMIFA bank address control (ABA[1:0]) Active-low bank selects for the 64-bit EMIFA. When interfacing to 16-bit Asynchronous devices, ABA1 carries bit 1 of the byte address. For an 8-bit Asynchronous interface, ABA[1:0] are used to carry bits 1 and 0 of the byte address DDR2 Memory Controller enable (DDR2_EN) [ABA0] 0 - DDR2 Memory Controller peripheral pins are disabled (default) 1 - DDR2 Memory Controller peripheral pins are enabled EMIFA enable (EMIFA_EN) [ABA1] 0 - EMIFA peripheral pins are disabled (default) 1 - EMIFA peripheral pins are enabled ACE5 ACE4 ACE3 ACE2 ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0 AHOLDA AHOLD ABUSREQ V27 V28 W26 W27 W29 K26 L29 L28 AA29 AA28 AA25 AA26 N26 R29 L27 O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O I O IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU EMIFA (64-BIT) - BUS ARBITRATION IPU IPU IPU EMIFA hold-request-acknowledge to the host EMIFA hold request from the host EMIFA bus request output EMIFA external input clock. The EMIFA input clock (AECLKIN or SYSCLK4 clock) is selected at reset via the pullup/pulldown resistor on the AEA[15] pin. Note: AECLKIN is the default for the EMIFA input clock. EMIFA output clock [at EMIFA input clock (AECLKIN or SYSCLK4) frequency] Asynchronous memory write-enable/Programmable synchronous interface write-enable Asynchronous memory ready input Asynchronous memory read/write Asynchronous/Programmable synchronous memory output-enable Programmable synchronous address strobe or read-enable For programmable synchronous interface, the R_ENABLE field in the Chip Select x Configuration Register selects between ASADS and ASRE: If R_ENABLE = 0, then the ASADS/ASRE signal functions as the ASADS signal. If R_ENABLE = 1, then the ASADS/ASRE signal functions as the ASRE signal. EMIFA byte-enable control Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. Byte-write enables for most types of memory. EMIFA memory space enables Enabled by bits 28 through 31 of the word address Only one pin is asserted during any external data access Note: The C6455 device does not have ACE0 and ACE1 pins
ABA0/DDR2_EN
V26
O/Z
IPD
EMIFA (64-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL AECLKIN AECLKOUT AAWE/ASWE AARDY AR/W AAOE/ASOE N29 V29 AB25 K29 W25 Y28 I O/Z O/Z I O/Z O/Z IPD IPD IPU IPU IPU IPU
ASADS/ASRE
R26
O/Z
IPU
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AEA11
T25
O/Z
IPD
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O/Z
IPD
AEA0/CFGGP0 U25
Note: For proper C6455 device operation, the AEA11 pin must be externally pulled up at device reset with a 1-k resistor. The AEA3 pin must be pulled up at device reset using a 1-k resistor if power is applied to the SRIO supply pins. If the SRIO peripheral is not used and the SRIO supply pins are connected to VSS, the AEA3 pin must be pulled down to VSS using a 1-k resistor.
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MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP1 and McBSP0) CLKS AJ4 I IPD McBSP external clock source (as opposed to internal) (I) [shared by McBSP1 and McBSP0] McBSP1 receive clock (I/O/Z) or GP[0] (I/O/Z) [default] McBSP1 receive frame sync (I/O/Z) or GP[10] (I/O/Z) [default] McBSP1 receive data (I) or GP[8] (I/O/Z) [default] McBSP1 transmit data (O/Z) or GP[9] (I/O/Z) [default] McBSP1 transmit frame sync (I/O/Z) or GP[11] (I/O/Z) [default] McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default] McBSP0 receive clock (I/O/Z) McBSP0 receive frame sync (I/O/Z) McBSP0 receive data (I) McBSP0 transmit data (O/Z) McBSP0 transmit frame sync (I/O/Z) McBSP0 transmit clock (I/O/Z)
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKR1/GP[0] FSR1/GP[10] DR1/GP[8] DX1/GP[9] FSX1/GP[11] CLKX1/GP[3] CLKR0 FSR0 DR0 DX0 FSX0 CLKX0 AF4 AE5 AH5 AG5 AG4 AF5 AG1 AH3 AJ5 AF6 AJ3 AG6 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I I/O/Z I/O/Z I/O/Z IPD IPD IPD IPD IPD IPD IPU IPD IPD IPD IPD IPU
UNIVERSAL TEST AND OPERATIONS PHY INTERFACE for ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE] UTOPIA SLAVE (ATM CONTROLLER) - TRANSMIT INTERFACE UXCLK/MTCLK/ RMREFCLK Source clock for UTOPIA transmit driven by Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is either EMAC MII transmit clock (MTCLK) or the EMAC RMII reference clock. The EMAC function is controlled by the MACSEL[1:0] (AEA[10:9] pins). For more detailed information, see Section 3, Device Configuration. Transmit cell available status output signal from UTOPIA Slave. 0 indicates a complete cell is NOT available for transmit 1 indicates a complete cell is available for transmit When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is EMAC GMII transmit clock. MACSEL[1:0] dependent. UTOPIA transmit interface enable input signal. Asserted by the Master ATM Controller to indicate that the UTOPIA Slave should put out on the Transmit Data Bus the first byte of valid data and the UXSOC signal in the next clock cycle. When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is either the EMAC MII transmit enable [default] or EMAC RMII transmit enable or EMAC GMII transmit enable. MACSEL[1:0] dependent. Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the rising edge of the UXCLK, indicating that the first valid byte of the cell is available on the 8-bit Transmit Data Bus (UXDATA[7:0]). When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is either the EMAC MII collision sense or EMAC GMII collision sense. MACSEL[1:0] dependent. UTOPIA transmit address pins (UXADDR[4:0]) (I) As UTOPIA transmit address pins, UTOPIA_EN (AEA12 pin) = 1: 5-bit Slave transmit address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System. When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0) and if the PCI_EN pin = 1, these pins are PCI peripheral pins: PCI command/byte enable 3(PCBE3) [I/O/Z], PCI initialization device select (PIDSEL) [I], and PCI target ready (PTRDY) [I/O/Z].
N4
I/O/Z
UXCLAV/GMTCLK
K5
I/O/Z
UXENB/MTXEN/ RMTXEN
J5
I/O/Z
UXSOC/MCOL
K3
I/O/Z
M5 N3 P5 R3
I I I I
UXADDR0/PTRDY
P4
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URCLAV/MCRS/ RMCRSDV
J4
I/O/Z
URENB/MRXDV
H5
I/O/Z
URSOC/MRXER/ RMRXER
H4
I/O/Z
P1 P2 / P3 R5
I I I I
URADDR0/PGNT/ GP[12]
R4
URDATA7/MRXD7 URDATA6/MRXD6 URDATA5/MRXD5 URDATA4/MRXD4 URDATA3/MRXD3 URDATA2/MRXD2 URDATA1/MRXD1/ RMRXD1 URDATA0/MRXD0/ RMRXD0 (1)
M2 H2 L2 L1 J3 J1 H3 J2 I/O/Z When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9] pins) to select the MII, RMII, GMII, or RGMII EMAC interface. (For more details, see Section 3, Device Configuration). UTOPIA 8-bit Receive Data Bus (I/O/Z) [default] or EMAC receive data bus [MII] [default] (I/O/Z) or [GMII] (I/O/Z) or [RMII] (I/O/Z) Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller.
These pins function as open-drain outputs when configured as PCI pins. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320C6455 37
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MANAGEMENT DATA INPUT/OUTPUT (MDIO) FOR RGMII RGMDCLK RGMDIO B4 A4 O/Z I/O/Z
J4
I/O/Z
H4
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UXCLAV/GMTCLK
K5
O/Z
UXCLK/MTCLK/ RMREFCLK
N4
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RGREFCLK
C4
O/Z
RGTXC RGTXD3 RGTXD2 RGTXD1 RGTXD0 RGTXCTL RGRXC RGRXD3 RGRXD2 RGRXD1 RGRXD0 RGRXCTL
D4 A2 C3 B3 A3 D3 E3 C1 E4 E2 E1 C2
O/Z
O/Z
RGMII transmit data [3:0] (O). This pin is available only when RGMII mode is selected (MACSEL[1:0] =11).
O/Z I I I I I I
RGMII transmit enable (O). This pin is available only when RGMII mode is selected (MACSEL[1:0] =11). RGMII receive clock (I). This pin is available only when RGMII mode is selected (MACSEL[1:0] =11).
RGMII receive data [3:0] (I). This pin is available only when RGMII mode is selected (MACSEL[1:0] =11).
RGMII receive control (I). This pin is available only when RGMII mode is selected (MACSEL[1:0] =11). RESERVED FOR TEST
V5 W3 N11 P11 G4 I Reserved. This pin must be connected directly to 1.5-/1.8-V I/O supply (DVDD15) for proper device operation. NOTE: If the EMAC RGMII is not used, these pins can be connected directly to ground (VSS). Reserved. This pin must be connected directly to the 1.8-V I/O supply (DVDD18) for proper device operation. Reserved. This pin must be connected to ground (VSS) via a 200- resistor for proper device operation. NOTE: If the DDR2 Memory Controller is not used, the VREFSSTL, RSV11, and RSV12 pins can be connected directly to ground (VSS) to save power. However, connecting these pins directly to ground will prevent boundary-scan from functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2 Memory Controller pins, see Section 7.3.4. Reserved. This pin must be connected to the 1.8-V I/O supply (DVDD18) via a 200- resistor for proper device operation. NOTE: If the DDR2 Memory Controller is not used, the VREFSSTL, RSV11, and RSV12 pins can be connected directly to ground (VSS) to save power. However, connecting these pins directly to ground will prevent boundary-scan from functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2 Memory Controller pins, see Section 7.3.4. Reserved. These pins must be connected directly to core supply (CVDD) for proper device operation.
RSV09
D26
RSV11
D24
RSV12
C24
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RSV13
F2
RSV14
F1
RSV15
T1
RSV16 RSV17 RSV18 RSV19 RSV20 RSV21 RSV22 RSV23 RSV24 RSV25 RSV26 RSV27 RSV36 RSV37 RSV38 RSV39 RSV40 RSV41 RSV42 RSV43 RSV44 RSV28 RSV29 RSV30 RSV31 RSV32 RSV33 RSV34 RSV35
T2 AE21 E13 F18 U29 A6 B26 C26 B6 C6 AJ11 AH11 AD11 AD9 AG10 AG11 AJ12 W28 Y26 Y25 Y27 N7 N6 P23 P24 D25 C25 E6 D6
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CVDDMON
N1
DVDD33MON
L6
DVDD15MON
F3
DVDD18MON
A26
VREFSSTL
C14
VREFHSTL
B2
DVDDR
AD20 AC15
AVDDA
AC17 AD16
AVDLL1 AVDLL2
A13 E18
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2.8 2.8.1
2.8.2
2.8.2.1
Device Support
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320C6455ZTZ2). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX TMP TMS Experimental device that is not necessarily representative of the final device's electrical specifications. Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. Fully qualified production device.
Support tool development evolutionary flow: TMDX TMDS Development-support product that has not yet completed Texas Instruments internal qualification testing. Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped with against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZTZ), the temperature range (for example, blank is the default commercial temperature range), and the device speed range, in megahertz (for example, 2 is 1200 MHz [1.2 GHz]). Figure 2-13 provides a legend for reading the complete device name for any TMS320C64x+ DSP generation member. For device part numbers and further ordering information for TMS320C6455 in the ZTZ/GTZ package type, see the TI website (www.ti.com) or contact your TI sales representative.
TMS PREFIX TMX = Experimental device TMS = Qualified device 320 C6455 ( ) ZTZ ( ) 2 DEVICE SPEED RANGE 7 = 720 MHz 8 = 850 MHz Blank = 1 GHz 2 = 1.2 GHz (A) TEMPERATURE RANGE Blank = 0C to 90C (default commercial temperature) A = -40C to 105C (extended temperature) PACKAGE TYPE ZTZ = 697-pin plastic BGA, with Pb-Free solder balls GTZ = 697-pin plastic BGA with Pb-ed solder balls SILICON REVISION B = silicon revision 2.1 D = silicon revision 3.1
(C) (B)
DEVICE FAMILY 320 = TMS320 DSP family DEVICE C64x+ DSP: C6455
A. B. C.
The extended temperature "A version" devices may have different operating conditions than the commercial temperature devices. For more details, see Section 6.2, Recommended Operating Conditions. BGA = Ball Grid Array For silicon revision information, see the TMS320C6455/54 Digital Signal Processor Silicon Errata (literature number SPRZ234).
Figure 2-13. TMS320C64x+ DSP Device Nomenclature (including the TMS320C6455 DSP) 2.8.2.2 Documentation Support
The following documents describe the TMS320C6455 Fixed-Point Digital Signal Processor. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. SPRU871 TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set. TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included. High-Speed DSP Systems Design Reference Guide. Provides recommendations for meeting the many challenges of high-speed DSP system design. These recommendations include information about DSP audio, video, and communications systems for the C5000 and C6000 DSP platforms. TMS320C6455 Technical Reference. An introduction to the TMS320C6455 DSP and discusses the application areas that are enhanced.
Copyright 20052011, Texas Instruments Incorporated
SPRU732
SPRAA84
SPRU889
SPRU965
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TMS320C645x DSP External Memory Interface (EMIF) User's Guide. This document describes the operation of the external memory interface (EMIF) in the TMS320C645x DSPs. TMS320C645x DSP DDR2 Memory Controller User's Guide. This document describes the DDR2 memory controller in the TMS320C645x digital-signal processors (DSPs). TMS320C645x DSP Host Port Interface (HPI) User's Guide. This guide describes the host port interface (HPI) on the TMS320C645x digital signal processors (DSPs). The HPI enables an external host processor (host) to directly access DSP resources (including internal and external memory) using a 16-bit (HPI16) or 32-bit (HPI32) interface. TMS320C645x/C647x Bootloader User's Guide. This document describes the the on-chip Bootloader provided with the TMS320C645x/C647x digital signal (DSPs). Included are descriptions of the available boot modes and any requirements associated with them, instructions on generating the boot information on the different versions of the Bootloader. features of processors interfacing table, and
SPRUEC6
SPRU966
TMS320C645x DSP Enhanced DMA (EDMA3) Controller User's Guide. This document describes the Enhanced DMA (EDMA3) Controller on the TMS320C645x digital signal processors (DSPs). TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide. Describes the operation of the multichannel buffered serial port (McBSP) in the digital signal processors (DSPs) of the TMS320C6000 DSP family. The McBSP consists of a data path and a control path that connect to external devices. Separate pins for transmission and reception communicate data to these external devices. The C6000 CPU communicates to the McBSP using 32-bit-wide control registers accessible via the internal peripheral bus. TMS320C645x DSP EMAC/MDIO Module User's Guide. This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with the TMS320C645x digital signal processors (DSPs). TMS320C645x DSP Peripheral Component Interconnect (PCI) User's Guide. This document describes the peripheral component interconnect (PCI) port in the TMS320C645x digital signal processors (DSPs). See the PCI Specification revision 2.3 for details on the PCI interface. TMS320C645x DSP Turbo-Decoder Coprocessor (TCP) User's Guide. Channel decoding of high bit-rate data channels found in third generation (3G) cellular standards requires decoding of turbo-encoded data. The turbo-decoder coprocessor (TCP) in some of the digital signal processor (DSPs) of the TMS320C6000 DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards. This document describes the operation and programming of the TCP. TMS320C645x DSP Viterbi-Decoder Coprocessor (VCP) User's Guide. Channel decoding of voice and low bit-rate data channels found in third generation (3G) cellular standards requires decoding of convolutional encoded data. The Viterbi-decoder coprocessor 2 (VCP2) provided in C645x devices has been designed to perform Viterbi-Decoding for IS2000 and 3GPP wireless standards. The VCP2 coprocessor has been designed to perform forward error correction for 2G and 3G wireless systems. The VCP2 coprocessor offers a very cost effective and synergistic solution when combined with Texas Instruments (TI) DSPs. The VCP2 can support 1941 12.2 Kbps class A 3G voice channels running at 333 MHZ. This document describes the operation and programming of the VCP2. TMS320C645x DSP Serial RapidIO User's Guide. This document describes the Serial RapidIO (SRIO) on the TMS320C645x digital signal processors (DSPs). TMS320C645x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide. This document describes the operation of the software-programmable
Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320C6455 53
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SPRU973
SPRU972
SPRU976 SPRUE56
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phase-locked loop (PLL) controller in the TMS320C645x digital signal processors (DSPs). The PLL controller offers flexibility and convenience by way of software-configurable multipliers and dividers to modify the input signal internally. The resulting clock outputs are passed to the TMS320C645x DSP core, peripherals, and other modules inside the TMS320C645x digital signal processors (DSPs). SPRUE48 TMS320C645x DSP Universal Test & Operations PHY Interface for ATM 2 (UTOPIA2) User's Guide. This document describes the universal test and operations PHY interface for asynchronous transfer mode (ATM) 2 (UTOPIA2) in the TMS320C645x digital signal processors (DSPs). TMS320C645x DSP Inter-Integrated Circuit (I2C) Module User's Guide. This document describes the inter-integrated circuit (I2C) module in the TMS320C645x Digital Signal Processor (DSP). The I2C provides an interface between the TMS320C645x device and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. This document assumes the reader is familiar with the I2C-bus specification. TMS320C645x DSP 64-Bit Timer User's Guide. This document provides an overview of the 64-bit timer in the TMS320C645x digital signal processors (DSPs). The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer. When configured as a dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other. TMS320C645x DSP General-Purpose Input/Output (GPIO) User's Guide. This document describes the general-purpose input/output (GPIO) peripheral in the TMS320C645x digital signal processors (DSPs). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin.
SPRU974
SPRU968
SPRU724
2.9
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.
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3 Device Configuration
On the C6455 device, certain device configurations like boot mode, pin multiplexing, and endianess, are selected at device reset. The status of the peripherals (enabled/disabled) is determined after device reset. By default, the peripherals on the C6455 device are disabled and need to be enabled by software before being used.
3.1
Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN)
CONFIGURATION PIN NO. IPD/ IPU (1) FUNCTIONAL DESCRIPTION Boot Mode Selections (BOOTMODE [3:0]). These pins select the boot mode for the device. 0000 0001 0010 0011 AEA[19:16] [N25, L26, L25, P26] 0100 IPD 0101 0110 0111 No boot (default mode) Host boot (HPI) Reserved Reserved EMIFA 8-bit ROM boot Master I2C boot Slave I2C boot Host boot (PCI)
1000 thru Serial Rapid I/O boot configurations 1111 If selected for boot, the corresponding peripheral is automatically enabled after device reset. For more detailed information on boot modes, see Section 2.4, Boot Sequence. CFGGP[2:0] pins must be set to 000b during reset for proper operation of the PCI boot mode. EMIFA input clock source select (AECLKIN_SEL). 0 AEA15 P27 IPD 1 AECLKIN (default mode) SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software selectable via the Software PLL1 Controller. By default, SYSCLK4 is selected as CPU/8 clock rate.
(1)
IPD = Internal pulldown, IPU = Internal pullup. For most systems, a 1-k resistor can be used to oppose the IPU/IPD. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.7, Pullup/Pulldown Resistors. Device Configuration Submit Documentation Feedback Product Folder Link(s): TMS320C6455 55
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Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued)
CONFIGURATION PIN NO. IPD/ IPU (1) 0 AEA14 R25 IPD 1 FUNCTIONAL DESCRIPTION HPI peripheral bus width select (HPI_WIDTH). HPI operates in HPI16 mode (default). HPI bus is 16 bits wide; HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state. HPI operates in HPI32 mode. HPI bus is 32 bits wide; HD[31:0] pins are used.
Applies only when HPI function of HPI/PCI multiplexed pins is selected (PCI_EN pin = 0). Device Endian mode (LENDIAN). AEA13 R27 IPU 0 1 System operates in Big Endian mode. System operates in Little Endian mode (default).
UTOPIA pin function enable bit (UTOPIA_EN). This pin selects the function of the UTOPIA/EMAC and UTOPIA/MDIO multiplexed pins. 0 AEA12 R28 IPD 1 UTOPIA pin function disabled; EMAC and MDIO pin function enabled (default). This means all multiplexed UTOPIA/EMAC and UTOPIA/MDIO pins function as EMAC and MDIO pins. The interface used by EMAC/MDIO (MII, RMII, GMII or the standalone RGMII) is controlled by the MACSEL[1:0] pins (AEA[10:9]). UTOPIA pin function enabled; EMAC and MDIO pin function disabled. This means all multiplexed UTOPIA/EMAC and UTOPIA/MDIO pins now function as UTOPIA. The EMAC/MDIO peripheral can still be used with RGMII (MACSEL[1:0] = 11).
AEA11
T25
IPD
For proper C6455 device operation, this pin must be externally pulled up with a 1-k resistor at device reset. EMAC Interface Selects (MACSEL[1:0]). These pins select the interface used by the EMAC/MDIO peripheral. 00 01 10 10/100 EMAC/MDIO with MII Interface [default] 10/100 EMAC/MDIO with RMII Interface 10/100/1000 EMAC/MDIO with GMII Interface 10/100/1000 EMAC/MDIO with RGMII Interface
AEA[10:9]
[M25, M27]
IPD
11
If the UTOPIA pin function is selected [UTOPIA_EN (AEA12 pin) = 1] for multiplexed UTOPIA/EMAC and UTOPIA/MDIO pins, the EMAC/MDIO peripheral can only be used with RGMII. For more detailed information on the UTOPIA_EN and MAC_SEL[1:0] control pin selections, see Table 3-3. PCI I2C EEPROM Auto-Initialization (PCI_EEAI). PCI auto-initialization via external I2C EEPROM 0 AEA8 P25 IPD 1 PCI auto-initialization through external I2C EEPROM is disabled. The PCI peripheral uses the specified PCI default values (default). PCI auto-initialization through external I2C EEPROM is enabled. The PCI peripheral is configured through external I2C EEPROM provided the PCI peripheral pins are enabled (PCI_EN = 1).
Note: If the PCI pin function is disabled (PCI_EN pin = 0), this pin must not be pulled up. AEA7 N27 IPD For proper C6455 device operation, do not oppose the IPD on this pin. PCI Frequency Selection (PCI66). Selects the operating frequency of the PCI (either 33 MHz or 66 MHz). AEA6 U27 IPD 0 1 PCI operates at 33 MHz (default) PCI operates at 66 MHz
Note: If the PCI pin function is disabled (PCI_EN pin = 0), this pin must not be pulled up. McBSP1 pin function enable bit (MCBSP1_EN). Selects which function is enabled on the McBSP1/GPIO multiplexed pins. AEA5 U28 IPD 0 1 GPIO pin function enabled (default). This means all multiplexed McBSP1/GPIO pins function as GPIO pins. McBSP1 pin function enabled. This means all multiplexed McBSP1/GPIO pins function as McBSP1 pins.
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Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued)
CONFIGURATION PIN NO. IPD/ IPU (1) FUNCTIONAL DESCRIPTION SYSCLKOUT Enable bit (SYSCLKOUT_EN). Selects which function is enabled on the SYSCLK4/GP[1] muxed pin. AEA4 T28 IPD 0 1 AEA3 T27 IPD GP[1] pin function is enabled (default) SYSCLK4 pin function is enabled
For proper C6455 device operation, the AEA3 pin must be pulled up at device reset using a 1-k resistor if power is applied to the SRIO supply pins. If the SRIO peripheral is not used and the SRIO supply pins are connected to VSS, the AEA3 pin must be pulled down to VSS using a 1-k resistor. Configuration General-Purpose Inputs (CFGGP[2:0]) The value of these pins is latched to the Device Status Register following device reset and is used by the on-chip bootloader for some boot modes. For more information on the boot modes, see Section 2.4, Boot Sequence. PCI pin function enable bit (PCI_EN). Selects which function is enabled on the HPI/PCI and the PCI/UTOPIA multiplexed pins. 0
AEA[2:0]
IPD
PCI_EN
Y29
IPD 1
HPI and UTOPIA pin function enabled (default) This means all multiplexed HPI/PCI and PCI/UTOPIA pins function as HPI and UTOPIA pins, respectively . PCI pin function enabled This means all multiplexed HPI/PCI and PCI/UTOPIA pins function as PCI pins. DDR2 Memory Controller peripheral pins are disabled (default) DDR2 Memory Controller peripheral pins are enabled EMIFA peripheral pins are disabled (default) EMIFA peripheral pins are enabled
DDR2 Memory Controller enable (DDR2_EN). ABA0 V26 IPD 0 1 ABA1 V25 IPD 0 1
3.2
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Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI and PCI)
CONFIGURATION PIN SETTING (1) PCI_EN PIN [Y29] 0 0 1 1 1 1 (1) PCI66 AEA6 PIN [U27] 0 0 1 1 0 0 PCI_EEAI AEA8 PIN [P25] (1) 0 0 1 0 0 1 HPI_WIDTH AEA14 PIN [R25] 0 1 X X X X HPI DATA LOWER Enabled Enabled Disabled Disabled Disabled Disabled Enabled (33 MHz) PERIPHERAL FUNCTION SELECTED HPI DATA UPPER Hi-Z Enabled 32-BIT PCI (66-/33-MHz) Disabled Disabled Enabled (66 MHz) PCI AUTO-INIT N/A N/A Enabled (via External I2C EEPROM) Disabled Disabled (default values) Enabled (via External I2C EEPROM)
PCI_EEAI is latched at reset as a configuration input. If PCI_EEAI is set as one, then default values are loaded from an external I2C EEPROM.
The UTOPIA and EMAC/MDIO pins are also multiplexed on the TCI6482 device. The UTOPIA_EN function (AEA12 pin) controls the function of these multiplexed pins. The MAC_SEL[1:0] configuration pins (AEA[10:9) control which interface is used by the EMAC/MDIO. Note that since the PCI shares some pins with the UTOPIA peripheral, its state also affects the operation of the UTOPIA. Table 3-3 describes the effect of the UTOPIA_EN, PCI_EN, and MACSEL[1:0] configuration pins. Table 3-3. UTOPIA_EN, and MAC_SEL[1:0] Peripheral Selection (UTOPIA and EMAC)
CONFIGURATION PIN SETTING UTOPIA_EN AEA12 PIN [R28] 0 0 0 0 1 1 1 1 (1) PCI_EN PIN [Y29] x x x x 0 0 1 1 MAC_SEL[1:0] AEA[10:9] PINS [M25, M27] 00b 01b 10b 11b 00b, 01b, or 10b 11b 00b, 01b, or 10b 11b PERIPHERAL FUNCTION SELECTED EMAC/MDIO 10/100 EMAC/MDIO with MII Interface [default] 10/100 EMAC/MDIO with RMII Interface 10/100/1000 EMAC/MDIO with GMII Interface 10/100/1000 EMAC/MDIO with RGMII Interface (1) Disabled 10/100/1000 EMAC/MDIO with RGMII Interface (1) Disabled 10/100/1000 EMAC/MDIO with RGMII Interface (1) Disabled Disabled Disabled Disabled UTOPIA Slave with Full Functionality UTOPIA Slave with Full Functionality UTOPIA Slave with Single PHY Mode Only UTOPIA Slave with Single PHY Mode Only UTOPIA
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Static powerdown
Peripheral pin function has been completely disabled through the device configuration pins. Peripheral is held in reset and clock is turned off.
Disabled
Peripheral is held in reset and clock is turned off. Default state for all peripherals not in static powerdown mode.
Enabled
Clock to the peripheral is turned on and the peripheral is taken out of reset.
Enable in progress
Not a user-programmable state. This is an intermediate state when transitioning from an disabled state to an enabled state.
Following device reset, all peripherals that are not in the static powerdown state are in the disabled state by default. Peripherals used for boot such as HPI and PCI are enabled automatically following a device reset. Peripherals are only allowed certain transitions between states (see Figure 3-1).
Static Powerdown
Disabled Enabled
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Figure 3-2 shows the flow needed to change the state of a given peripheral on the C6455 device.
Write to the PERCFG0 register within 16 SYSCLK3 clock cycles to change the state of the peripherals.
Figure 3-2. Peripheral State Change Flow A 32-bit key (value = 0x0F0A 0B00) must be written to the Peripheral Lock register (PERLOCK) in order to allow access to the PERCFG0 register. Writes to the PERCFG1 register can be done directly without going through the PERLOCK register. NOTE
The instructions that write to the PERLOCK and PERCFG0 registers must be in the same fetch packet if code is being executed from external memory. If the instructions are in different fetch packets, fetching the second instruction from external memory may stall the instruction long enough such that PERCFG0 register will be locked before the instruction is executed.
3.4
REGISTER NAME
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Figure 3-3. Peripheral Lock Register (PERLOCK) - 0x02AC 0004 Table 3-6. Peripheral Lock Register (PERLOCK) Field Descriptions
Bit 31:0 Field LOCKVAL Value Description When programmed with 0x0F0A 0B00 allows one write to the PERCFG0 register within 16 SYSCLK3 clock cycles.
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3.4.2
30
29 Reserved R/W-0
24
Figure 3-4. Peripheral Configuration Register 0 (PERCFG0) - 0x02AC 0008 Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions
Bit 31:30 Field SRIOCTL Value Description Mode control for SRIO. SRIO does not have a corresponding status bit in the Peripheral Status Registers. Once SRIOCTL is set to 11b, the SRIO peripheral can be used within 16 SYSCLK3 cycles. 00b 11b 29:23 22 Reserved UTOPIACTL 0 1 21 20 Reserved PCICTL 0 1 19 18 Reserved HPICTL 0 1 17 Reserved 1 Set SRIO to disabled mode Set SRIO to enabled mode Reserved. Mode control for UTOPIA Set UTOPIA to disabled mode Set UTOPIA to enabled mode Reserved. Mode control for PCI. This bit defaults to 1 when host boot is used (BOOTMODE[3:0] = 0111b). Set PCI to disabled mode Set PCI to enabled mode Reserved. Mode control for HPI. This bit defaults to 1 when host boot is used (BOOTMODE[3:0] = 0001b). Set HPI to disabled mode Set HPI to enabled mode Reserved.
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31 Reserved R-0x00 7 Reserved R-0x00 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 2 1 DDR2CTL R/W-0 0
EMIFACTL R/W-0
Figure 3-5. Peripheral Configuration Register 1 (PERCFG1) - 0x02AC 002C Table 3-8. Peripheral Configuration Register 1 (PERCFG1) Field Descriptions
Bit 31:2 1 Field Reserved DDR2CTL 0 1 0 EMIFACTL 0 1 Value Description Reserved. Mode Control for DDR2 Memory Controller. Once this bit is set to 1, it cannot be changed to 0. Set DDR2 to disabled Set DDR2 to enabled Mode control for EMIFA. Once this bit is set to 1, it cannot be changed to 0. This bit defaults to 1 if EMIFA 8-bit ROM boot is used (BOOTMODE[3:0] = 0100b). Set EMIFA to disabled Set EMIFA to enabled
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GPIOSTAT R-0 7
Figure 3-6. Peripheral Status Register 0 (PERSTAT0) - 0x02AC 0014 Table 3-9. Peripheral Status Register 0 (PERSTAT0) Field Descriptions
Bit 31:30 29:27 Field Reserved HPISTAT 000 001 011 100 101 Others 26:24 McBSP1STAT 000 001 011 100 101 Others 23:21 McBSP0STAT 000 001 011 100 101 Others Value Description Reserved. HPI status HPI is in the disabled state HPI is in the enabled state HPI is in the static powerdown state HPI is in the disable in progress state HPI is in the enable in progress state Reserved McBSP1 status McBSP1 is in the disabled state McBSP1 is in the enabled state McBSP1 is in the static powerdown state McBSP1 is in the disable in progress state McBSP1 is in the enable in progress state Reserved McBSP0 status McBSP0 is in the disabled state McBSP0 is in the enabled state McBSP0 is in the static powerdown state McBSP0 is in the disable in progress state McBSP0 is in the enable in progress state Reserved
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Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018 Table 3-10. Peripheral Status Register 1 (PERSTAT1) Field Descriptions
Bit 31:6 5:3 Field Reserved UTOPIASTAT 000 001 011 101 Others 2:0 PCISTAT 000 001 011 101 Others Value Description Reserved. UTOPIA status UTOPIA is in the disabled state UTOPIA is in the enabled state UTOPIA is in the static powerdown state UTOPIA is in the enable in progress state Reserved PCI status PCI is in the disabled state PCI is in the enabled state PCI is in the static powerdown state PCI is in the enable in progress state Reserved
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3.4.5
15
Figure 3-8. EMAC Configuration Register (EMACCFG) - 0x02AC 0020 Table 3-11. EMAC Configuration Register (EMACCFG) Field Descriptions
Bit 31:19 18 Field Reserved RMII_RST 0 1 17:0 Reserved Value Description Reserved. Writes to this register must keep the default values of these bits. RMII reset bit. This bit is used to reset the RMII logic of the EMAC. RMII logic reset is released. RMII logic reset is asserted. Reserved. Writes to this register must keep this bit as 0.
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3.4.6
31 Reserved R-0 7 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 1 0
EMUCTL R/W-0
Figure 3-9. Emulator Buffer Powerdown Register (EMUBUFPD) - 0x02AC 0054 Table 3-12. Emulator Buffer Powerdown Register (EMUBUFPD) Field Descriptions
Bit 31:1 0 Field Reserved EMUCTL 0 1 Value Description Reserved Buffer powerdown for EMU[18:2] pins Power-up buffers Power-down buffers
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3.5
LEGEND: R/W = Read/Write; R = Read only; -x = value after reset Note: The default values of the fields in the DEVSTAT register are latched from device configuration pins, as described in Section 3.1, Device Configuration at Device Reset. The default values shown here correspond to the setting dictated by the internal pullup or pulldown resistor.
Figure 3-10. Device Status Register (DEVSTAT) - 0x02A8 0000 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions
Bit 31:23 22 Field Reserved EMIFA_EN 0 1 21 DDR2_EN 0 1 20 PCI_EN 0 1 19:17 16 15 CFGGP[2:0] Reserved SYSCLKOUT_EN 0 1 Value Description Reserved. Read-only, writes have no effect. EMIFA Enable (EMIFA_EN) status bit Shows the status of whether the EMIFA peripheral pins are enabled/disabled. EMIFA peripheral pins are disabled (default) EMIFA peripheral pins are enabled DDR2 Memory Controller Enable (DDR2_EN) status bit Shows the status of whether the DDR2 Memory Controller peripheral pins are enabled/disabled. DDR2 Memory Controller peripheral pins are disabled (default) DDR2 Memory Controller peripheral pins are enabled PCI Enable (PCI_EN) status bit Shows the status of which function is enabled on the HPI/PCI and PCI/UTOPIA multiplexed pins. HPI and UTOPIA pin functions are enabled (default) PCI pin functions are enabled Used as General-Purpose inputs for configuration purposes. These pins are latched at reset. These values can be used by S/W routines for boot operations. Reserved. Read-only, writes have no effect. SYSCLKOUT Enable (SYSCLKOUT_EN) status bit Shows the status of which function is enabled on the SYSCLK4/GP[1] muxed pin. GP[1] pin function of the SYSCLK4/GP[1] pin enabled (default) SYSCLK4 pin function of the SYSCLK4/GP[1] pin enabled
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For more detailed information on the boot modes, see Section 2.4, Boot Sequence.
3.6
0 LSB R-1
Figure 3-11. JTAG ID (JTAGID) Register - 0x02A8 0008 Table 3-14. JTAG ID (JTAGID) Register Field Descriptions
Bit Field Value Description Variant (4-Bit) value. The value of this field depends on the silicon revision being used. For more information, see the TMS320C6455/54 Digital Signal Processor Silicon Errata (literature number SPRZ234) . Note: the VARIANT field may be invalid if no CLKIN1 signal is applied. 27:12 PART NUMBER 11:1 0 MANUFACTURER LSB Part Number (16-Bit) value. C6455 device value: 0000 0000 1000 1010b. Manufacturer (11-Bit) value. C6455 device value: 0000 0010 111b. LSB. This bit is read as a "1" for the C6455 device. 31:28 VARIANT
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3.7
Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the C6455 device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The C6455 device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors. An external pullup/pulldown resistor needs to be used in the following situations: Device Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state. Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. For the device configuration pins (listed in Table 3-1), if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes. Tips for choosing an external pullup/pulldown resistor: Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors. Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels. Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net. For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin). Remember to include tolerances when selecting the resistor value. For pullup resistors, also remember to include tolerances on the DVDD rail. For most systems, a 1-k resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. For most systems, a 20-k resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for the C6455 device, see Section 6.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature. To determine which pins on the C6455 device include internal pullup/pulldown resistors, see Table 2-3, Terminal Functions.
3.8
Configuration Examples
Figure 3-12 and Figure 3-13 illustrate examples of peripheral selections/options that are configurable on the C6455 device.
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64 AED[63:0] UTOPIA EMIFA AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[7:0], AECLKOUT, ASDCKE, AHOLDA, ABUSREQ, ASADS/ASRE, AAOE/ASOE, AAWE/ASWE 32 DDR2 EMIF ED[31:0] DEA[21:2], DCE[1:0], DBE[3:0], DDRCLK, DDRCLK, DSDCKE, DDQS, DDQS, DSDCAS, DSDRAS, DSDWE CLKIN2, PLLV2
GP[15:12,2,1]
GPIO
McBSP1
EMAC
RapidIO
MDIO
I2C
SCL SDA
Shading denotes a peripheral module not available for this configuration. DEVSTAT Register: 0x0061 8161 PCI_EN = 0 (PCI disabled, default) ABA1 (EMIFA_EN) = 1(EMIFA enabled) ABA0 (DDR2_EN) = 1 (DDR2 Memory Controller enabled) AEA[19:16] (BOOTMODE[3:0]) = 0001, (HPI Boot) AEA[15] (AECLKIN_SEL) = 0, (AECLKIN, default) AEA[14] (HPI_WIDTH) = 1, (HPI, 32-bit Operation) AEA[13] (LENDIAN) = IPU, (Little Endian Mode, default) AEA[12] (UTOPIA_EN) = 0, (UTOPIA disabled, default) AEA[10:9] (MACSEL[1:0]) = 00, (10/100 MII Mode) AEA[8] (PCI_EEAI) = 0, (PCI I2C EEPROM Auto-Init disabled, default) AEA[7] = 0, (do not oppose IPD) AEA[6] (PCI66) = 0, (PCI 33 MHz [default, dont care]) AEA[5] (MCBSP1_EN) = 0, (McBSP1 disabled, default) AEA[4] (SYSCLKOUT_EN) = 1, (SYSCLK4 pin function) AEA[2:0] (CFGGP[2:0]) = 000 (default)
Figure 3-12. Configuration Example A (McBSP + HPI32 + I2C + EMIFA + DDR2 Memory Controller + TIMERS + RapidIO + EMAC (MII) + MDIO)
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64 AED[63:0] UTOPIA EMIFA AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[7:0], AECLKOUT, ASDCKE, AHOLDA, ABUSREQ, ASADS/ASRE, AAOE/ASOE, AAWE/ASWE 32 DDR2 EMIF ED[31:0] DEA[21:2], DCE[1:0], DBE[3:0], DDRCLK, DDRCLK, DSDCKE, DDQS, DDQS, DSDCAS, DSDRAS, DSDWE CLKIN2, PLLV2
GP[15:12,2,1]
GPIO
McBSP1
EMAC
RapidIO
MDIO
I2C
SCL SDA
Shading denotes a peripheral module not available for this configuration. DEVSTAT Register: 0x0061 C161 PCI_EN = 0 (PCI disabled, default) ABA1 (EMIFA_EN) = 1(EMIFA enabled) ABA0 (DDR2_EN) = 1 (DDR2 Memory Controller enabled) AEA[19:16] (BOOTMODE[3:0]) = 0001, (HPI Boot) AEA[15] (AECLKIN_SEL) = 0, (AECLKIN, default) AEA[14] (HPI_WIDTH) = 1, (HPI, 32-bit Operation) AEA[13] (LENDIAN) = IPU, (Little Endian Mode, default) AEA[12] (UTOPIA_EN) = 0, (UTOPIA disabled, default) AEA[10:9] (MACSEL[1:0]) = 00, (10/100 MII Mode) AEA[8] (PCI_EEAI) = 0, (PCI I2C EEPROM Auto-Init disabled, default) AEA[7] = 0, (do not oppose IPD) AEA[6] (PCI66) = 0, (PCI 33 MHz [default, dont care]) AEA[5] (MCBSP1_EN) = 1, (McBSP1 enabled) AEA[4] (SYSCLKOUT_EN) = 1, (SYSCLK4 pin function) AEA[2:0] (CFGGP[2:0]) = 000 (default)
Figure 3-13. Configuration Example B (2 McBSPs + HPI32 + I2C + EMIFA + DDR2 Memory Controller + TIMERS + RapidIO + EMAC (GMII) + MDIO
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4 System Interconnect
On the C6455 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between master peripherals and slave peripherals. The switch fabrics also allow for seamless arbitration between the system masters when accessing system slaves.
4.1
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Events
MASTER
Data SCR 128 (SYSCLK2) M 128 (SYSCLK2) M S2 S3 128 (SYSCLK2) M Bridge Bridge Bridge
M0 M1 M2 M3
S0 S1
64 (SYSCLK2) S VCP2
32 (SYSCLK2) S
CFG SCR
128-bit (SYSCLK2)
Bridge
UTOPIA
PCI
128 (SYSCLK2)
Bridge
64 (SYSCLK2)
128 (SYSCLK2)
Bridge
64 (SYSCLK2)
EMIFA
128 (SYSCLK2)
128 (SYSCLK2)
Megamodule
Megamodule
128 (SYSCLK2)
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(1)
4.3
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CFG SCR
TCP2
VCP2
32 (SYSCLK2)
PCI
32-bit (SYSCLK2)
32 (SYSCLK3)
32 (SYSCLK3) S I2C
Bridge 7
MUX
32 (SYSCLK3) S Timers
Data SCR
32 (SYSCLK2) S
S 32 (SYSCLK3) S 32 (SYSCLK3) S
EMAC/MDIO
32 (SYSCLK2)
Serial RapidIO
32 (SYSCLK2) S EDMA3 CC
32 (SYSCLK2)
EDMA3 TC0
32 (SYSCLK2)
MUX
32 (SYSCLK2)
EDMA3 TC1
32 (SYSCLK2)
EDMA3 TC2
32 (SYSCLK2)
EDMA3 TC3
A. Only accessible by the C64x+ Megamodule. B. All clocks in this figure are generated by the PLL1 controller.
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4.4
Bus Priorities
On the C6455 device, bus priority is programmable for each master. The register bit fields and default priority levels for C6455 bus masters are shown in Table 4-2. The priority levels should be tuned to obtain the best system performance for a particular application. Lower values indicate higher priorities. For some masters, the priority values are programmed at the system level by configuring the PRI_ALLOC register. Details on the PRI_ALLOC register are shown in Figure 4-3. The C64x+ megamodule , SRIO, and EDMA masters contain registers that control their own priority values. The priority is enforced when several masters in the system are vying for the same endpoint. Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the C64x+ megamodule. In the PRI_ALLOC register, the HOST field applies to the priority of the HPI and PCI peripherals. The EMAC field specifies the priority of the EMAC peripheral. The SRIO field is used to specify the priority of the Serial RapidIO when accessing descriptors from system memory. The priority for Serial RapidIO data accesses is set in the peripheral itself. Table 4-2. C6455 Default Bus Master Priorities
BUS MASTER EDMA3TC0 EDMA3TC1 EDMA3TC2 EDMA3TC3 SRIO (Data Access) SRIO (Descriptor Access) EMAC PCI HPI C64x+ Megamodule (MDMA port) DEFAULT PRIORITY LEVEL 0 0 0 0 0 0 1 2 2 7 PRIORITY CONTROL QUEPRI.PRIQ0 (EDMA3 register) QUEPRI.PRIQ1 (EDMA3 register) QUEPRI.PRIQ2 (EDMA3 register) QUEPRI.PRIQ3 (EDMA3 register) PER_SET_CNTL.CBA_TRANS_PRI (SRIO register) PRI_ALLOC.SRIO PRI_ALLOC.EMAC PRI_ALLOC.HOST PRI_ALLOC.HOST MDMAARBE.PRI (C64x+ Megamodule Register) 16 Reserved R-0000 0000 0000 0000
31
15 Reserved R-000 0
12
11 SRIO R/W-001
8 Reserved R-100
5 HOST R/W-010
2 EMAC R/W-001
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5 C64x+ Megamodule
The C64x+ Megamodule consists of several components the C64x+ CPU, the L1 program and data memory controllers, the L2 memory controller, the internal DMA (IDMA), the interrupt controller, power-down controller, and external memory controller. The C64x+ Megamodule also provides support for memory protection (for L1P, L1D, and L2 memories) and bandwidth management (for resources local to the C64x+ Megamodule). Figure 5-1 shows a block diagram of the C64x+ Megamodule.
L1P cache/SRAM 256 L1 program memory controller 256 L2 cache/ SRAM 256 L2 memory controller Cache control 256 Bandwidth management Memory protection 128 External memory controller To Chip registers 32 128 Slave DMA To primary switch fabric 128 Master DMA Configuration Registers 256 L1 256 IDMA Cache control Bandwidth management Memory protection 256 256 C64x+ CPU Instruction fetch SPLOOP buffer 16/32bit instruction dispatch Instruction decode Data path 1 Data path 2 S1 M1 xx xx D1 D2 M2 xx xx S2 L2 Advanced event triggering (AET)
Internal ROM(A)
A register file 64 L1 data memory controller Cache control Bandwidth management Memory protection 64
B register file
256
32 L1D cache/SRAM A. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Figure 5-1. 64x+ Megamodule Block Diagram For more detailed information on the TMS320C64x+ Megamodule on the C6455 device, see the TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).
5.1
Memory Architecture
The TMS320C6455 device contains a 2048KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The L1P memory configuration for the C6455 device is as follows: Region 0 size is 0K bytes (disabled). Region 1 size is 32K bytes with no wait states. The L1D memory configuration for the C6455 device is as follows: Region 0 size is 0K bytes (disabled). Region 1 size is 32K bytes with no wait states.
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L1D is a two-way set-associative cache while L1P is a direct-mapped cache. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+ Megamodule. After device reset, L1P and L1D cache are configured as all cache or all SRAM. The on-chip Bootloader changes the reset configuration for L1P and L1D. For more information, see the TMS320C645x Bootloader User's Guide (literature number SPRUEC6) . Figure 5-2 and Figure 5-3 show the available SRAM/cache configurations for L1P and L1D, respectively.
L1P mode bits 000 001 010 011 100 L1P memory Block base address 00E0 0000h
16K bytes
All SRAM
dm cache
16K bytes
All SRAM
Figure 5-3. TMS320C6455 L1D Memory Configurations The L2 memory configuration for the C6455 device is as follows: Port 0 configuration:
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Memory size is 2048KB Starting address is 0080 0000h 2-cycle latency 4 128-bit bank configuration Port 1 configuration: Memory size is 32K bytes (this corresponds to the internal ROM) Starting address is 0010 0000h 1-cycle latency 1 256-bit bank configuration
L2 memory can be configured as all SRAM or as part 4-way set-associative cache. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C64x+ Megamodule. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.
L2 mode bits 000 001 010 011 111 L2 memory Block base address 0080 0000h
1792K bytes
All SRAM
63/64 SRAM
009C 0000h 128K bytes 4-way cache 64K bytes 4-way cache 4-way cache 32K bytes 32K bytes 009F 0000h 009F 8000h 00A0 0000h
009E 0000h
4-way
Figure 5-4. TMS320C6455 L2 Memory Configurations For more information on the operation L1 and L2 caches, see the TMS320C64x+ DSP Cache User's Guide (literature number SPRU862). All memory on the C6455 device has a unique location in the memory map (see Table 2-2). When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz. Therefore, when using a software boot mode, care must be taken such that the CPU frequency does not exceed 750 MHz at any point during the boot sequence. After the boot sequence has completed, the CPU frequency can be programmed to the frequency required by the application. For more detailed information ont he boot modes, see Section 2.4, Boot Sequence.
5.2
Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (64KB each). The L1D, L1P, and L2 memory controllers in the C64x+ Megamodule are equipped with a set of registers that specify the permissions for each memory page.
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Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. Additionally, a page may be marked as either (or both) locally or globally accessible. A local access is a direct CPU access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the CPU count as global accesses. The CPU and the system masters on the C6455 device are all assigned a privilege ID of 0. Therefore it is only possible to specify whether memory pages are locally or globally accessible. The AID0 and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see Table 5-1. Table 5-1. Available Memory Page Protection Schemes
AID0 Bit 0 0 1 1 LOCAL Bit 0 1 0 1 Description No access to memory page is permitted. Only direct access by CPU is permitted. Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the CPU). All accesses permitted
For more information on memory protection for L1D, L1P, and L2, see the TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).
5.3
Bandwidth Management
When multiple requestors contend for a single C64x+ Megamodule resource, the conflict is solved by granting access to the highest priority requestor. The following four resources are managed by the Bandwidth Management control hardware: Level 1 Program (L1P) SRAM/Cache Level 1 Data (L1D) SRAM/Cache Level 2 (L2) SRAM/Cache Memory-mapped registers configuration bus The priority level for operations initiated within the C64x+ Megamodule; e.g., CPU-initiated transfers, user-programmed cache coherency operations, and IDMA-initiated transfers, are declared through registers in the C64x+ Megamodule. The priority level for operations initiated outside the C64x+ Megamodule by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC), see Section 4.4. System peripherals with no fields in PRI_ALLOC have their own registers to program their priorities. More information on the bandwidth management features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).
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5.4
Power-Down Control
The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache control hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used to design systems for lower overall system power requirements. NOTE
The C6455 device does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).
5.5
Megamodule Resets
Table 5-2 shows the reset types supported on the C6455 device and they affect the resetting of the Megamodule, either both globally or just locally. Table 5-2. Megamodule Reset (Global or Local)
RESET TYPE Power-On Reset Warm Reset Max Reset System Reset CPU Reset GLOBAL MEGAMODULE RESET Y Y Y Y N LOCAL MEGAMODULE RESET Y Y Y Y Y
For more detailed information on the global and local megamodule resets, see the TMS320C64x+ Megamodule Reference Guide (literature number SPRU871) and for more detailed information on device resets, see Section 7.6, Reset Controller.
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5.6
Megamodule Revision
The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5 and described in Table 5-3. The C64x+ Megamodule revision is dependant on the silicon revision being used. For more information, see the TMS320C6455/54 Digital Signal Processor Silicon Errata (literature number SPRZ234) .
16 15 REVISION(A) R-n
The C64x+ Megamodule revision is dependant on the silicon revision being used. For more information, see the TMS320C6455/54 Digital Signal Processor Silicon Errata (literature number SPRZ234) .
Figure 5-5. Megamodule Revision ID Register (MM_REVID) [Hex Address: 0181 2000h] Table 5-3. Megamodule Revision ID Register (MM_REVID) Field Descriptions
Bit 31:16 15:0 Field VERSION REVISION Value 1h Description Version of the C64x+ Megamodule implemented on the device. This field is always read as 1h. Revision of the C64x+ Megamodule version implemented on the device. The C64x+ Megamodule revision is dependant on the silicon revision being used. For more information, see the TMS320C6455/54 Digital Signal Processor Silicon Errata (literature number SPRZ234) .
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These addresses correspond to the L2 memory protection page attribute registers 32-63 (L2MPPA32-L2MPPA63) of the C64x+ megamaodule. These registers are not supported for the C6455 device. These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C64x+ megamaodule. These registers are not supported for the C6455 device. C64x+ Megamodule Submit Documentation Feedback Product Folder Link(s): TMS320C6455
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ACRONYM L1PMPPA17 L1PMPPA18 L1PMPPA19 L1PMPPA20 L1PMPPA21 L1PMPPA22 L1PMPPA23 L1PMPPA24 L1PMPPA25 L1PMPPA26 L1PMPPA27 L1PMPPA28 L1PMPPA29 L1PMPPA30 L1PMPPA31 L1DMPFAR L1DMPFSR L1DMPFCR L1DMPLK0 L1DMPLK1 L1DMPLK2 L1DMPLK3 L1DMPLKCMD L1DMPLKSTAT L1DMPPA16 L1DMPPA17 L1DMPPA18 L1DMPPA19 L1DMPPA20 L1DMPPA21 L1DMPPA22 L1DMPPA23 L1DMPPA24 L1DMPPA25 L1DMPPA26 L1DMPPA27 L1DMPPA28 L1DMPPA29 L1DMPPA30 L1DMPPA31 -
REGISTER NAME L1P memory protection page attribute register 17 L1P memory protection page attribute register 18 L1P memory protection page attribute register 19 L1P memory protection page attribute register 20 L1P memory protection page attribute register 21 L1P memory protection page attribute register 22 L1P memory protection page attribute register 23 L1P memory protection page attribute register 24 L1P memory protection page attribute register 25 L1P memory protection page attribute register 26 L1P memory protection page attribute register 27 L1P memory protection page attribute register 28 L1P memory protection page attribute register 29 L1P memory protection page attribute register 30 L1P memory protection page attribute register 31 Reserved L1 data (L1D) memory protection fault address register L1D memory protection fault status register L1D memory protection fault command register Reserved L1D memory protection lock key bits [31:0] L1D memory protection lock key bits [63:32] L1D memory protection lock key bits [95:64] L1D memory protection lock key bits [127:96] L1D memory protection lock key command register L1D memory protection lock key status register Reserved Reserved L1D memory protection page attribute register 16 L1D memory protection page attribute register 17 L1D memory protection page attribute register 18 L1D memory protection page attribute register 19 L1D memory protection page attribute register 20 L1D memory protection page attribute register 21 L1D memory protection page attribute register 22 L1D memory protection page attribute register 23 L1D memory protection page attribute register 24 L1D memory protection page attribute register 25 L1D memory protection page attribute register 26 L1D memory protection page attribute register 27 L1D memory protection page attribute register 28 L1D memory protection page attribute register 29 L1D memory protection page attribute register 30 L1D memory protection page attribute register 31 Reserved
These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C64x+ megamaodule. These registers are not supported for the C6455 device.
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EMCSDMAARBE EMC Slave DMA Arbitration Control Register EMCMDMAARBE EMC Master DMA Arbitration Control Resgiter L2DCPUARBU L2DIDMAARBU L2DSDMAARBU L2DUCARBU L1DCPUARBD L1DIDMAARBD L1DSDMAARBD L1DUCARBD Reserved L2D CPU Arbitration Control Register L2D IDMA Arbitration Control Register L2D Slave DMA Arbitration Control Register L2D User Coherence Arbitration Control Resgiter Reserved L1D CPU Arbitration Control Register L1D IDMA Arbitration Control Register L1D Slave DMA Arbitration Control Register L1D User Coherence Arbitration Control Resgiter
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DVDD33 DVDD15
DVDD12, DVDDRM, AVDDT, AVDDA PLLV1, PLLV2 Input voltage (VI) range:
(2)
-0.5 V to 1.5 V -0.5 V to 2.5 V -0.5 V to DVDD33 + 0.5 V -0.5 V to DVDD33 + 0.5 V -0.5 V to 2.5 V -0.5 V to 2.5 V -0.5 V to DVDD33 + 0.5 V -0.5 V to DVDD33 + 0.5 V -0.5 V to 2.5 V -0.5 V to 2.5 V 0C to 90C -40C to 105C -65C to 150C
3.3-V pins (except PCI-capable pins) PCI-capable pins RGMII pins DDR2 memory controller pins
3.3-V pins (except PCI-capable pins) PCI-capable pins RGMII pins DDR2 memory controller pins
Operating case temperature range, TC: Storage temperature range, Tstg (1) (2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS.
6.2
CVDD
DVDDRM
DVDD12, AVDDA, AVDDT DVDD33 DVDD18 AVDLL1 AVDLL2 VREFSSTL DVDD15 VREFHSTL PLLV1, PLLV2 VSS
Supply voltage, I/O [required only for RapidIO] Supply voltage, I/O Supply voltage, I/O Supply voltage, I/O Supply voltage, I/O Reference voltage Supply voltage, I/O [required only for EMAC RGMII] Reference voltage Supply voltage, PLL Supply ground
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0.8 0.3DVDD33 0.3DVDD33 VREFHSTL - 0.1 VREFSSTL - 0.125 1.560 1.625 1.950
V V V V V
V 2.340
-1.000
4.300
0 -40
90 C 105
TC
These rated numbers are from the PCI Local Bus Specification (version 2.3). The DC specifications and AC specifications are defined in Table 4-3 and Table 4-4, respectively, of the PCI Local Bus Specification. PCI-capable pins can withstand a maximum overshoot/undershoot for up to 11 ns as required by the PCI Local Bus Specification (version 2.3). Duration of overshoot/undershoot must not exceed 30% of the cycle period.
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6.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
PARAMETER 3.3-V pins (except PCI-capable and I2C pins) TEST CONDITIONS (1) DVDD33 = MIN, IOH = MAX IOH = -0.5 mA, DVDD33 = 3.3 V MIN 0.8DVDD33 0.9DVDD33 DVDD15 - 0.4 1.4 DVDD33 = MIN, IOL = MAX IOL = 1.5 mA, DVDD33 = 3.3 V Pulled up to 3.3 V, 3 mA sink current 0.22DVDD33 0.1DVDD33 0.4 0.4 0.4 VI = VSS to DVDD33, pins without internal pullup or pulldown resistor VI = VSS to DVDD33, pins with internal pullup resistor VI = VSS to DVDD33, pins with internal pulldown resistor I2C pins PCI-capable pins (4) RGMII pins AECLKOUT, CLKR1/GP[0], CLKX1/GP[3], SYSCLK4/GP[1], EMU[18:0], CLKR0, CLKX0 EMIF pins (except AECLKOUT), NMI, TOUT0L, TINP0L, TOUT1L, TINP1L, PCI_EN, EMAC-capable pins (except RGMII pins), RESETSTAT, McBSP-capable pins (except CLKR1/GP[0], CLKX1/GP[3], CLKR0, CLKX0), GP[7:4], and TDO PCI-capable pins (2) RGMII pins DDR2 memory controller pins 0.1DVDD33 VI 0.9DVDD33 -1 50 -400 -10 -1000 100 -100 1 400 -50 10 1000 0.4 TYP MAX UNIT V V V V V V V V V uA uA uA uA uA V
VOH
PCI-capable pins (2) RGMII pins DDR2 memory controller pins 3.3-V pins (except PCI-capable and I2C pins) PCI-capable pins (2)
VOL
II
(3)
-8
mA
IOH
-4
mA
-0.5 -8 4
mA mA mA
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. These rated numbers are from the PCI Local Bus Specification (version 2.3). The DC specifications and AC specifications are defined in Table 4-3 and Table 4-4, respectively, of the PCI Local Bus Specification. II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II includes input leakage current and off-state (hi-Z) output leakage current. PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs. Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320C6455 99
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Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) (continued)
PARAMETER AECLKOUT, CLKR1/GP[0], CLKX1/GP[3], SYSCLK4/GP[1], EMU[18:0], CLKR0, CLKX0 EMIF pins (except AECLKOUT), NMI, TOUT0L, TINP0L, TOUTP1L, TINP1L, PCI_EN, Low-level output EMAC-capable pins current [DC] (except RGMII pins), RESETSTAT, McBSP-capable pins (except CLKR1/GP[0], CLKX1/GP[3], CLKR0, CLKX0), GP[7:4], and TDO PCI-capable pins (2) RGMII pins DDR2 memory controller pins IOZ
(5)
MIN
TYP
MAX
UNIT
mA
IOL
mA
1.5 8 -4 VO = DVDD33 or 0 V CVDD = 1.25 V, CPU frequency = 1200 MHz -20 1.76 1.66 1.41 1.29 20
mA mA mA uA W W W W
3.3-V pins
PCDD
(6)
CVDD = 1.25 V, CPU frequency = 1000 MHz CVDD = 1.2 V, CPU frequency = 850 MHz CVDD = 1.2 V, CPU frequency = 720 MHz DVDD33 = 3.3 V, DVDD18 = DVDDR = 1.8 V, PLLV1 = PLLV2 = AVDLL1 = AVDLL2 = 1.8 V, CPU frequency = 1200 MHz DVDD33 = 3.3 V, DVDD18 = DVDDR = 1.8 V, PLLV1 = PLLV2 = AVDLL1 = AVDLL2 = 1.8 V, CPU frequency = 1000 MHz DVDD33 = 3.3 V, DVDD18 = DVDDR = 1.8 V, PLLV1 = PLLV2 = AVDLL1 = AVDLL2 = 1.8 V, CPU frequency = 850 MHz DVDD33 = 3.3 V, DVDD18 = DVDDR = 1.8 V, PLLV1 = PLLV2 = AVDLL1 = AVDLL2 = 1.8 V, CPU frequency = 720 MHz
0.54
0.53
PDDD
0.53
0.52
Ci Co (5) (6)
10 10
pF pF
IOZ applies to output-only pins, indicating off-state (hi-Z) output leakage current. Assumes the following conditions: 60% CPU utilization; DDR2 at 50% utilization (250 MHz), 50% writes, 32 bits, 50% bit switching; two 2-MHz McBSPs at 100% utilization, 50% switching; two 75-MHz Timers at 100% utilization; device configured for HPI32 mode with pull-up resistors on HPI pins; room temperature (25C). The actual current draw is highly application-dependent. For more details on core and I/O activity, see the TMS320C6455/54 Power Consumption Summary application report (literature number SPRAAE8). Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320C6455
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42
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 7-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.
7.1.1
Vref = 1.5 V
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
7.1.2
7.1.3
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adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 7-1 and Figure 7-4). Figure 7-4 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device. Table 7-1. Board-Level Timing Example (see Figure 7-4)
NO. 1 2 3 4 5 6 7 8 9 10 11 Clock route delay Minimum DSP hold time Minimum DSP setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time DSP hold time requirement DSP setup time requirement Data route delay DESCRIPTION
AECLKOUT (Output from DSP) 1 AECLKOUT (Input to External Device) Control (Output from DSP) Signals (A) 3 4 5 Control Signals (Input to External Device) Data Signals (B) (Output from External Device) Data Signals (B) (Input to DSP) A. B. 6 7 8 2
10 11
Control signals include data for Writes. Data signals are generated during Reads from an external device.
7.2
C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6455
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7.3 7.3.1
Figure 7-5. Power-Supply Sequence Table 7-2. Timing Requirements for Power-Supply Sequence
-720 -850 A-1000/-1000 -1200 MIN 1 2 tsu(DVDD33-CVDD12) Setup time, DVDD33 supply stable before CVDD12 supply stable tsu(CVDD12-ALLSUP) Setup time, CVDD12 supply stable before all other supplies stable 0.5 0 MAX 200 200 ms ms
NO.
UNIT
7.3.2
Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. As with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered.
7.3.3
Power-Down Operation
One of the power goals for the C6455 device is to reduce power dissipation due to unused peripherals. There are different ways to power down peripherals on the C6455 device. Some peripherals can be statically powered down at device reset through the device configuration pins (see Section 3.1, Device Configuration at Device Reset). Once in a static power-down state, the peripheral is held in reset and its clock is turned off. Peripherals cannot be enabled once they are in a static power-down state. To take a peripheral out of the static power-down state, a device reset must be executed with a different configuration pin setting. After device reset, all peripherals on the C6455 device are in a disabled state and must be enabled by software before being used. It is possible to enable only the peripherals needed by the application while keeping the rest disabled. Note that peripherals in a disabled state are held in reset with their clocks gated. For more information on how to enable peripherals, see Section 3.3, Peripheral Selection After Device Reset. Peripherals used for booting, like I2C and HPI, are automatically enabled after device reset. It is not possible to disable these peripherals after the boot process is complete.
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The C64x+ Megamodule also allows for software-driven power-down management for all of the C64x+ megamodule components through its Power-Down Controller (PDC). The CPU can power-down part or the entire C64x+ megamodule through the power-down controller based on its own execution thread or in response to an external stimulus from a host or global controller. More information on the power-down features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).
7.3.4
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7.4
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7.4.1
7.4.2
BINARY 000 0000 000 0001 000 0010 000 0011 000 0100 000 0101 000 0110 000 0111 000 1000 000 1001 000 1010 000 1011 000 1100 000 1101 000 1110 000 1111 001 0000 001 0001
EVENT NAME DSP_EVT TEVTLO0 TEVTHI0 XEVT0 REVT0 XEVT1 REVT1 TEVTLO1 TEVTHI1 HPI/PCI-to-DSP event
EVENT DESCRIPTION
Timer 0 lower counter event Timer 0 high counter event None None None None None None None None None McBSP0 transmit event McBSP0 receive event McBSP1 transmit event McBSP1 receive event Timer 1 lower counter event Timer 1 high counter event
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C645x DSP Enhanced DMA (EDMA3) Controller User's Guide (literature number SPRU966) . HPI boot and PCI boot are terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0. C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6455 107
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7.4.3
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The C6455 device has 256 EDMA3 parameter sets total. Each parameter set can be used as a DMA entry, a QDMA entry, or a link entry.
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7.5 7.5.1
9 (1)
EMU_DTDMA
10 11 (1) 12
(1)
None EMU_RTDXRX EMU_RTDXTX IDMA0 IDMA1 DSPINT I2CINT MACINT AEASYNCERR Reserved INTDST0 INTDST1 INTDST4 Reserved EDMA3CC_GINT Reserved VCP2_INT TCP2_INT Reserved UINT Reserved RINT0
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INTERRUPT EVENT Reserved L1P_ED1 Reserved L2_ED1 L2_ED2 PDC_INT Reserved L1P_CMPA L1P_DMPA L1D_CMPA L1D_DMPA L2_CMPA L2_DMPA IDMA_CMPA IDMA_BUSERR
DESCRIPTION Reserved. These system events are not connected and, therefore, not used. L1P single bit error detected during DMA read Reserved. These system events are not connected and, therefore, not used. L2 single bit error detected L2 two bit error detected Powerdown sleep interrupt Reserved. This system event is not connected and, therefore, not used. L1P CPU memory protection fault L1P DMA memory protection fault L1D CPU memory protection fault L1D DMA memory protection fault L2 CPU memory protection fault L2 DMA memory protection fault IDMA CPU memory protection fault IDMA bus error interrupt
114 - 115 116 (2) 117 (2) 118 (2) 119 120 (2) 121
(2)
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7.5.2
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. 2
1 NMI
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7.6
Reset Controller
The reset controller detects the different type of resets supported on the C6455 device and manages the distribution of those resets throughout the device. The C6455 device has several types of resets: power-on reset, warm reset, max reset, system reset, and CPU reset. Table 7-12 explains further the types of reset, the reset initiator, and the effects of each reset on the chip. For more information on the effects of each reset on the PLL controllers and their clocks, see Section 7.6.8, Reset Electrical Data/Timing. Table 7-12. Reset Types
TYPE INITIATOR POR pin RESET pin RapidIO [through INTDST5 (1)] Emulator HPI/PCI EFFECT(s) Resets the entire chip including the test and emulation logic. Resets everything except for the test and emulation logic and PLL2. Emulator stays alive during Warm Reset. Same as Warm Reset. A system reset maintains memory contents and does not reset the test and emulation circuitry. The device configuration pins are also not re-latched and the state of the peripherals is also not affected. (2) CPU local reset.
Power-on Reset Warm Reset Max Reset System Reset CPU Local Reset (1) (2)
INTDST5 is used generate a MAX reset only. It is not connected to the device interrupt controller. For more detailed information on the INTDST5, see the TMS320C645x DSP Serial Rapid I/O User's Guide (literature number SPRU976). On the C6455 device, peripherals can be in one of several states. These states are listed in Table 3-4.
7.6.1
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all the system clocks are invalid at this point. The RESETSTAT pin stays asserted (low), indicating the device is in reset. 3. The POR pin may now be deasserted (driven high). When the POR pin is deasserted, the configuration pin values are latched and the PLL controllers change their system clocks to their default divide-down values. PLL2 is taken out of reset and automatically starts its locking sequence. Other device initialization is also started. 4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time, PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. After the pause the system clocks are restarted at their default divide-by settings. 5. The device is now out of reset, device execution begins as dictated by the selected boot mode (see Section 2.4, Boot Sequence). NOTE
To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period of the POR pin, most of the device will remain in reset. The only exception being that PLL2 is taken out of reset as soon as POR is de-asserted (driven high), regardless of the state of the RESET pin. The RESET pin should not be tied together with the POR pin.
7.6.2
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4. The device is now out of reset, device execution begins as dictated by the selected boot mode (see Section 2.4, Boot Sequence). NOTE
The POR pin should be held inactive (high) throughout the Warm Reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied together with the POR pin.
7.6.3
Max Reset
A Max Reset is initiated by the RapidIO peripheral and has the same affect as a Warm Reset.
7.6.4
System Reset
The emulator initiates a System Reset via the ICEPick module. This ICEPick-initiated reset is non-maskable. To invoke the maximum reset via the ICEPick module, the user can perform the following from the Code Composer Studio menu: Debug Advanced Resets System Reset. The following memory contents are maintained during a System Reset: DDR2 Memory Controller: The DDR2 Memory Controller registers are not reset. In addition, the DDR2 SDRAM memory content is retained if the user places the DDR2 SDRAM in self-refresh mode before invoking the System Reset. EMIFA: The contents of the memory connected to the EMIFA are retained. The EMIFA registers are not reset. Test, emulation, and clock logic are unaffected. The device configuration pins are also not re-latched and the state of the peripherals (see Table 3-4) is not affected. During a System Reset, the following happens: 1. The System Reset is initiated by the emulator. During this time, the following happens: The reset signals flow to the entire chip resetting all the modules on chip except the test and emulation logic. The PLL controllers are not reset. Internal system clocks are unaffected. If PLL1/PLL2 were locked before the System Reset, they remain locked. The RESETSTAT pin goes low to indicate an internal reset is being generated. 2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL controllers pause their system clocks for about 10 cycles. At this point: The state of the peripherals before the System Reset is not changed. For example, if McBSP0 was in the enabled state before System Reset, it will remain in the enabled state after System Reset. The I/O pins are controlled as dictated by the DEVSTAT register. The DDR2 Memory Controller and EMIFA registers retain their previous values. Only the DDR2 Memory Controller and EMIFA state machines are reset by the System Reset. The PLL controllers are operating in the mode prior to System Reset. System clocks are unaffected. The boot sequence is started after the system clocks are restarted. Since the configuration pins (including the BOOTMODE[3:0] pins) are not latched with a System Reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.
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7.6.5
CPU Reset
A CPU Reset is initiated by the HPI or PCI peripheral. This reset only affects the CPU. During a PCI-initiated CPU Reset, the PCI pins are set to their reset state. With the exception of the HRDY/PIRDY pin, the PCI pins have a reset state of high-impedance; the HRDY/PIRDY pin goes high during reset.
7.6.6
Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority reset request. The rest request priorities are as follows (high to low): Power-on Reset Maximum Reset Warm Reset System Reset CPU Reset
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7.6.7
7.6.7.1
The rest type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The reset type status register is shown in Figure 7-7 and described in Table 7-13.
31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 4 3 SRST R-0 2 MRST R-0 1 WRST R-0 0 POR R-0 16
Figure 7-7. Reset Type Status Register (RSTYPE) [Hex Address: 029A 00E4] Table 7-13. Reset Type Status Register (RSTYPE) Field Descriptions
Bit 31:4 3 Field Reserved SRST 0 1 2 MRST 0 1 1 WRST 0 1 0 POR 0 1 Value Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. System reset. System Reset was not the last reset to occur. System Reset was the last reset to occur. Max reset. Max Reset was not the last reset to occur. Max Reset was the last reset to occur. Warm reset. Warm Reset was not the last reset to occur. Warm Reset was the last reset to occur. Power-on reset. Power-on Reset was not the last reset to occur. Power-on Reset was the last reset to occur.
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7.6.8
NO.
UNIT
C = 1/CLKIN1 clock frequency in ns. D = 1/CLKIN2 clock frequency in ns. P = 1/CPU clock frequency in nanoseconds (ns). Note that after power-on reset , warm reset, and max reset the CPU frequency is equal to the CLKIN1 frequency divided by three due to the PLL1 controller being reset (see Section 7.6, Reset Controller). If CLKIN2 is not used, tw(POR) must be measured in terms of CLKIN1 cycles; otherwise, use CLKIN2 cycles. AEA[19:0], ABA[1:0], and PCI_EN are the boot configuration pins during device reset. Note: If a configuration pin must be routed out from the device and 3-stated (not driven), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.7, Pullup/Pulldown Resistors.
Table 7-15. Switching Characteristics Over Recommended Operating Conditions During Reset (1)
(see Figure 7-9)
-720 -850 A-1000/-1000 -1200 MIN 9 (1) td(PORH-RSTATH) Delay time, POR high AND RESET high to RESETSTAT high MAX 15000C ns
NO.
PARAMETER
UNIT
For Figure 7-8, note the following: Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high impedance as soon as their respective power supply has reached normal operating coditions. Pins remain in high impedance until configured otherwise by their respective peripheral. Low group consists of: UXDATA0/MTXD0/RMTXD0, UXDATA1/MTXD1/RMTXD1, UXDATA2/MTXD2/RMTXD2, UXDATA3/MTXD3/RMTXD3, UXDATA4/MTXD4/RMTXD4, and UXENB/MTXEN/RMTXEN. Pins become low as soon as their respective power supply has reached normal operating conditions. Pins remain low until configured otherwise by their respective peripheral. High group consists of: AHOLD, ABUSREQ, and HRDY/PIRDY. Pins become high as soon as their respective power supply has reached normal operating conditions. Pins remain high until configured otherwise by their respective peripheral. The ABUSREQ pin remains high until the EMIFA is enabled through the PERCFG1 register. Once the EMIFA is enabled, the ABUSREQ pin is driven to its inactive state (driven low). All peripherals must be enable through software following a Power-on Reset; for more details, see Section 7.6.1, Power-on Reset. For power-supply sequence requirements, see Section 7.3.1, Power-Supply Sequencing.
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Power Supplies Ramping Power Supplies Stable
RESET 9 RESETSTAT
SYSREFCLK (PLL1C) SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 AECLKOUT (Internal) 7 Boot and Device Configuration Pins Z Group Low Group High Group CLKIN2 Internal Reset PLL2C SYSREFCLK (PLL2C) SYSCLK1 (PLL2C) Undefined PLL2 Locked(A) Clock Valid Clock Valid (B) Undefined Undefined Undefined High-Z 8
Low High
Undefined Undefined
A. B. C. D. E.
SYSREFCLK of the PLL2 controller runs at CLKIN2 10. SYSCLK1 of PLL2 controller runs at SYSREFCLK/2 (default). Power supplies, CLKIN1, CLKIN2 (if used), and PCLK (if used) must be stable before the start of tw(POR). Do not tie the RESET and POR pins together. The RESET pin can be brought high after the POR pin has been brought high. In this case, the RESET pin must be held low for a minimum of tw(RESET) after the POR pin has been brought high.
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CLKIN1 CLKIN2 POR 6 RESET(A)(B) 9 RESETSTAT 7 8 Boot and Device Configuration Pins(C) A. B. C. RESET should only be used after device has been powered up. For more details on the use of the RESET pin, see Section 7.6, Reset Controller. A reset signal is generated internally during a Warm Reset. This internal reset signal has the same effect as the RESET pin during a Warm Reset. Boot and Device Configurations Inputs (during reset) include: AEA[19:0], ABA[1:0], and PCI_EN.
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7.7
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CLKIN1
(B)
DIVIDER PREDIV /1, /2, /3 ENA PLLM x1, x15, x20, x25, x30, x32
SYSCLK2
PREDEN (PREDIV.[15])
SYSCLK3
DIVIDER D4 /2, /4, ..., /16 ENA DIVIDER D5 /1, /2, ..., /8 ENA SYSCLK5 (Emulation and Trace) SYSCLK4 (Internal EMIF Clock Input)
D4EN (PLLDIV4.[15])
D5EN (PLLDIV5.[15])
AECLKIN (External EMIF Clock Input) GP0 0 (EMIF Input Clock) 1 AECLKINSEL (AEA[15] pin) 1 0 SYSCLKOUT_EN (AEA[4] pin)
EMIFA
AECLKOUT
GP1/SYSCLK4
A. B.
7.7.1
7.7.1.1
As shown in Figure 7-10, the PLL1 controller generates several internal clocks including the system reference clock (SYSREFCLK), and the system clocks (SYSCLK2/3/4/5). The high-frequency clock signal SYSREFCLK is directly used to clock the C64x+ megamodule (including the CPU) and also serves as a reference clock for the rest of the DSP system. Dividers D2, D3, D4, and D5 divide the high-frequency clock SYSREFCLK to generate SYSCLK2, SYSCLK3, SYSCLK4, and SYSCLK5, respectively. The system clocks are used to clock different portions of the DSP: SYSCLK2 is used to clock the switched central resources (SCRs), EDMA3, VCP2, TCP2, and RapidIO, as well as the data bus interfaces of the EMIFA and DDR2 Memory Controller. SYSCLK3 clocks the PCI, HPI, UTOPIA, McBSP, GPIO, TIMER, and I2C peripherals, as well as the configuration bus of the PLL2 Controller.
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SYSCLK4 is used as the internal clock for the EMIFA. It is also used to clock other logic within the DSP. SYSCLK5 clocks the emulation and trace logic of the DSP.
The divider ratio bits of dividers D2 and D3 are fixed at 3 and 6, respectively. The divider ratio bits of dividers D4 and D5 are programmable through the PLL controller divider registers PLLDIV4 and PLLDIV5, respectively. The PLL multiplier controller (PLLM) and the dividers (D4 and D5) must be programmed after reset. There is no hardware CLKMODE selection on the C6455 device. Since the divider ratio bits for dividers D2 and D3 are fixed, the frequency of SYSCLK2 and SYSCLK3 is tied to the frequency of SYSREFCLK. However, the frequency of SYSCLK4 and SYSCLK5 depends on the configuration of dividers D4 and D5. For example, with PLLM in the PLL1 multiply control register set to 10011b (x20 mode) and a 50-MHz CLKIN1 input, the PLL output PLLOUT is set to 1000 MHz and SYSCLK2 and SYSCLK3 run at 400 MHz and 200 MHz, respectively. Divider D4 can be programmed through the PLLDIV4 register to divide SYSREFCLK by 10 such that SYSCLK4 and, hence, the EMIF internal clock, runs at 120 MHz. All hosts (HPI, PCI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed. Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, SYSCLK4, and SYSCLK5. The PLL1 Controller must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). For the PLL clocks input and output frequency ranges, see Table 7-16. Table 7-16. PLL1 Clock Frequency Ranges
CLOCK SIGNAL CLKIN1 PLLREF (PLLEN = 1) (1) PLLOUT
(1)
SYSCLK4 SYSCLK5 (1) Only applies when the PLL1 Controller is set to PLL mode (PLLEN = 1 in the PLLCTL register).
7.7.1.2
The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM. In bypass mode, CLKIN1 is fed directly to SYSREFCLK. All hosts (HPI, PCI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed. 7.7.1.3 PLL1 Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device powerup. The PLL should not be operated until this stabilization time has expired. The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL1 reset time value, see Table 7-17.
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The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The PLL1 lock time is given in Table 7-17. Table 7-17. PLL1 Stabilization, Lock, and Reset Times
MIN PLL stabilization time PLL lock time PLL reset time (1) 128*C (1) 150 2000*C (1) TYP MAX UNIT s ns ns
C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
7.7.2
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7.7.3
7.7.3.1
The PLL control register (PLLCTL) is shown in Figure 7-11 and described in Table 7-19.
31
Reserved
16 R-0
15
Reserved
7
Rsvd
6
Rsvd
5
Reserved
3
PLLRST
2
Rsvd
1
PLL PWRDN
0
PLLEN
R/W-0
R-1
R/W-0
R/W-1
R-0
R/W-0
R/W-0
Figure 7-11. PLL1 Control Register (PLLCTL) [Hex Address: 029A 0100] Table 7-19. PLL1 Control Register (PLLCTL) Field Descriptions
Bit 31:8 7 6 5:4 3 Field Reserved Reserved Reserved Reserved PLLRST 0 1 2 1 Reserved PLLPWRDN 0 1 0 PLLEN 0 1 Value Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Reserved. Writes to this register must keep this bit as 0. Reserved. The reserved bit location is always read as 1. A value written to this field has no effect. Reserved. Writes to this register must keep this bit as 0. PLL reset bit PLL reset is released PLL reset is asserted Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PLL power-down mode select bit PLL is operational PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off PLL enable bit Bypass mode. Divider PREDIV and PLL are bypassed. All the system clocks (SYSCLKn) are divided down directly from input reference clock. PLL mode. Divider PREDIV and PLL are not bypassed. PLL output path is enabled. All the system clocks (SYSCLKn) are divided down from PLL output.
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7.7.3.2
The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-20. The PLLM register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits (RATIO) in the PLL controller pre-divider register (PREDIV).
31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 5 4 PLLM R/W-0h 0 16
Figure 7-12. PLL Multiplier Control Register (PLLM) [Hex Address: 029A 0110] Table 7-20. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit 31:5 4:0 Field Reserved PLLM 0h Eh 13h 18h 1Dh 1Fh Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. PLL multiplier bits. Defines the frequency multiplier of the input reference clock in conjunction with the PLL divider ratio bits (RATIO) in PREDIV. x1 multiplier rate x15 multiplier rate x20 multiplier rate x25 multiplier rate x30 multiplier rate x32 multiplier rate
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7.7.3.3
The PLL pre-divider control register (PREDIV) is shown in Figure 7-13 and described in Table 7-21.
31
Reserved
16 R-0
15
PREDEN
14
Reserved
5 R-0
4
RATIO
0 R/W-2h
R/W-1
Figure 7-13. PLL Pre-Divider Control Register (PREDIV) [Hex Address: 029A 0114] Table 7-21. PLL Pre-Divider Control Register (PREDIV) Field Descriptions
Bit 31:16 15 Field Reserved PREDEN 0 1 14:5 4:0 Reserved RATIO 0 0-1Fh 0 1h 2h 3h-1Fh Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Pre-divider enable bit. Pre-divider is disabled. No clock output. Pre-divider is enabled. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Divider ratio bits. 1. Divide frequency by 1. 2. Divide frequency by 2. 3. Divide frequency by 3. Reserved, do not use.
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7.7.3.4
The PLL controller divider 4 register (PLLDIV4) is shown in Figure 7-14 and described in Table 7-22. Besides being used as the EMIFA internal clock, SYSCLK4 is also used in other parts of the system. Disabling this clock will cause unpredictable system behavior. Therefore, the PLLDIV4 register should never be used to disable SYSCLK4.
31 Reserved R-0 15 D4EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-3 0 16
Figure 7-14. PLL Controller Divider 4 Register (PLLDIV4) [Hex Address: 029A 0160] Table 7-22. PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions
Bit 31:16 15 Field Reserved D4EN 0 1 14:5 4:0 Reserved RATIO 0 0-1Fh 0 1h 2h 3h 4h-7h 8h-1Fh Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Divider 4 enable bit. Divider 4 is disabled. No clock output. Divider 4 is enabled. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Divider ratio bits. 2. Divide frequency by 2. 4. Divide frequency by 4. 6. Divide frequency by 6. 8. Divide frequency by 8. 10 to 16. Divide frequency by 10 to divide frequency by 16. Reserved, do not use.
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7.7.3.5
The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-15 and described in Table 7-23.
31 Reserved R-0 15 D5EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-3 0 16
Figure 7-15. PLL Controller Divider 5 Register (PLLDIV5) [Hex Address: 029A 0164] Table 7-23. PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions
Bit 31:16 15 Field Reserved D5EN 0 1 14:5 4:0 Reserved RATIO 0 0-1Fh 0 1h 2h 3h 4h-7h 8h-1Fh Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Divider 5 enable bit. Divider 5 is disabled. No clock output. Divider 5 is enabled. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Divider ratio bits. 1. Divide frequency by 1. 2. Divide frequency by 2. 3. Divide frequency by 3. 4. Divide frequency by 4. 5 to 8. Divide frequency by 5 to divide frequency by 8. Reserved, do not use.
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7.7.3.6
The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-16 and described in Table 7-24.
31
Reserved
16 R-0
15
Reserved
2 R-0
1
Rsvd
0
GOSET
R/W-0
R/W-0
Figure 7-16. PLL Controller Command Register (PLLCMD) [Hex Address: 029A 0138] Table 7-24. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit 31:2 1 0 Field Reserved Reserved GOSET Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1 to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have completed. 0 1 No effect. Write of 0 clears bit to 0. Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further writes of 1 can initiate the GO operation.
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7.7.3.7
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-17 and described in Table 7-25.
31
Reserved
16 R-0
15
Reserved
1 R-0
0
GOSTAT
R-0
Figure 7-17. PLL Controller Status Register (PLLSTAT) [Hex Address: 029A 013C] Table 7-25. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit 31:1 0 Field Reserved GOSTAT 0 1 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. GO operation status. GO operation is not in progress. SYSCLK divide ratios are not being changed. GO operation is in progress. SYSCLK divide ratios are being changed.
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7.7.3.8
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-18 and described in Table 7-26.
31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 5 4 ALN5 R-1 3 ALN4 R-1 2 Reserved R-1 0 16
Figure 7-18. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029A 0140] Table 7-26. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit 31:5 4:3 Field Reserved ALNn 0 1 2:0 Reserved 0 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SYSCLKn alignment. Do not change the default values of these fields. Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set to 1, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set. Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set. The SYSCLKn ratio is set to the ratio programmed in the RATIO bit in PLLDIVn. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
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7.7.3.9
Whenever a different ratio is written to the PLLDIVn registers, the PLLCTRL flags the change in the PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in Figure 7-19 and described in Table 7-27.
31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 5 4 SYS5 R-0 3 SYS4 R-0 2 Reserved R-0 0 16
Figure 7-19. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029A 0144] Table 7-27. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit 31:5 4 Field Reserved SYS5 0 1 3 SYS4 0 1 2:0 Reserved 0 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Identifies when the SYSCLK5 divide ratio has been modified. SYSCLK5 ratio has not been modified. When GOSET is set, SYSCLK5 will not be affected. SYSCLK5 ratio has been modified. When GOSET is set, SYSCLK5 will change to the new ratio. Identifies when the SYSCLK4 divide ratio has been modified. SYSCLK4 ratio has not been modified. When GOSET is set, SYSCLK4 will not be affected. SYSCLK4 ratio has been modified. When GOSET is set, SYSCLK4 will change to the new ratio. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
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7.7.3.10 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLKn). SYSTAT is shown in Figure 7-20 and described in Table 7-28.
31 Reserved R-0 15 Reserved R-0 7 Reserved R-0 LEGEND: R = Read only; -n = value after reset 5 4 SYS5ON R-1 3 SYS4ON R-1 2 SYS3ON R-1 1 SYS2ON R-1 0 Reserved R-1 8 16
Figure 7-20. SYSCLK Status Register (SYSTAT) [Hex Address: 029A 0150] Table 7-28. SYSCLK Status Register (SYSTAT) Field Descriptions
Bit 31:4 4:1 Field Reserved SYSnON 0 1 0 Reserved 1 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SYSCLKn on status. SYSCLKn is gated. SYSCLKn is on. Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
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7.7.4
UNIT
15 0.4C 0.4C
Pulse duration, CLKIN1 high Pulse duration, CLKIN1 low Transition time, CLKIN1 Period jitter (peak-to-peak), CLKIN1
The reference points for the rise and fall transitions are measured at 3.3 V VIL MAX and VIH MIN. For more details on the PLL multiplier factors (x1 [BYPASS], x 15, x20, x25, x30, x32), see Section 7.7.1.2, PLL1 Controller Operating Modes. C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns. The PLL1 multiplier factors (x1 [BYPASS], x 15, x20, x25, x30, x32) further limit the MIN and MAX values for tc(CLKIN1). For more detailed information on these limitations, see Section 7.7.1.1, Internal Clocks and Maximum Operating Frequencies. 5 2 1 4
CLKIN1 3 4
Figure 7-21. CLKIN1 Timing Table 7-30. Switching Characteristics Over Recommended Operating Conditions for SYSCLK4 [CPU/8 - CPU/12] (1) (2)
(see Figure 7-22)
-720 -850 A-1000/-1000 -1200 MIN 2 3 4 (1) (2) tw(CKO3H) tw(CKO3L) tt(CKO3) Pulse duration, SYSCLK4 high Pulse duration, SYSCLK4 low Transition time, SYSCLK4 4P - 0.7 4P - 0.7 MAX 6P + 0.7 6P + 0.7 1 ns ns ns
NO.
PARAMETER
UNIT
The reference points for the rise and fall transitions are measured at 3.3 V VOL MAX and VOH MIN. P = 1/CPU clock frequency in nanoseconds (ns) 2 4
SYSCLK4 3 4
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7.8
TMS320C6455 DSP SYSCLK3 (From PLL1 Controller) +1.8 V 560 pF 0.1 mF EMI Filter C161 C162 CLKIN2
(B)(C)
PLLV2
PLL2
/2
PLLM x20
DIVIDER D1 1 0 1 SYSREFCLK /x
(A)
SYSCLK1
EMAC
PLL2 Controller
A. B. C.
/x must be programmed to /2 for GMII (default) and to /5 for RGMII. If EMAC is enabled with RGMII, or GMII, CLKIN2 frequency must be 25 MHz. CLKIN2 is a 3.3-V signal.
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7.8.1
7.8.1.1
As shown in Figure 7-23, the output of PLL2, PLLOUT, is divided by 2 and directly fed to the DDR2 memory controller. This clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUT. Note that, internally, the data bus interface of the DDR2 memory controller is clocked by SYSCLK2 of the PLL1 controller. The PLLOUT/2 clock is also fed back into the PLL2 controller where it becomes SYSREFCLK. Divider D1 of the PLL2 controller generates SYSCLK1 for the Ethernet media access controller (EMAC). The EMAC uses SYSCLK1 to generate the necessary clock for each of its interfaces. Divider D1 should be programmed to 2 mode [default] when using the Gigabit Media Independent Interface (GMII) mode and to 5 mode when using the Reduce Gigabit Media Independent Interface (RGMII). Divider D1 is software programmable and, if necessary, must be programmed after device reset to 5 when the RGMII mode of the EMAC is used. Note that, internally, the data bus interface of the EMAC is clocked by SYSCLK3 of the PLL2 controller. Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, and SYSCLK1. The clock generator must not be configured to exceed any of these constraints. For the PLL clocks input and output frequency ranges, see Table 7-31. Also, when EMAC is enabled with RGMII or GMII, CLKIN2 must be 25 MHz. Table 7-31. PLL2 Clock Frequency Ranges
CLOCK SIGNAL PLLREF (PLLEN = 1) PLLOUT SYSCLK1 (1) (1) MIN 12.5 250 50 MAX 26.7 533 125 UNIT MHz MHz MHz
SYSCLK1 restriction applies only when the EMAC is enabled and the RGMII or GMII modes are used. SYSCLK1 must be programmed to 125 MHz when the GMII mode is used and to 50 MHz when the RGMII mode is used.
7.8.1.2
Unlike the PLL1 controller which can operate in bypass and a PLL mode, the PLL2 controller only operates in PLL mode. In this mode, SYSREFCLK is generated outside the PLL2 controller by dividing the output of PLL2 by two. The PLL2 controller is affected by power-on reset , warm reset, and max reset . During these resets the PLL2 controller registers get reset to their default values. The internal clocks of the PLL2 controller are also affected as described in Section 7.6, Reset Controller. PLL2 is only unlocked during the power-up sequence (see Section 7.6, Reset Controller ) and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
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7.8.2
7.8.3
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7.8.3.1
The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-24 and described in Table 7-33.
31 Reserved R-0 15 D1EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-1 0 16
Figure 7-24. PLL Controller Divider 1 Register (PLLDIV1) [Hex Address: 029C 0118] Table 7-33. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
Bit 31:16 15 Field Reserved D1EN 0 1 14:5 4:0 Reserved RATIO 0 0-1Fh 1h 4h Others Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Divider D1 enable bit. Divider D1 is disabled. No clock output. Divider D1 is enabled. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Divider ratio bits. 2. Divide frequency by 2. 5. Divide frequency by 5. Reserved
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7.8.3.2
The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-25 and described in Table 7-34.
31
Reserved
16 R-0
15
Reserved
2 R-0
1
Rsvd
0
GOSET
R/W-0
R/W-0
Figure 7-25. PLL Controller Command Register (PLLCMD) [Hex Address: 029C 0138] Table 7-34. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit 31:2 1 0 Field Reserved Reserved GOSET Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1 to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have completed. 0 1 No effect. Write of 0 clears bit to 0. Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further writes of 1 can initiate the GO operation.
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7.8.3.3
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-26 and described in Table 7-35.
31
Reserved
16 R-0
15
Reserved
1 R-0
0
GOSTAT
R-0
Figure 7-26. PLL Controller Status Register (PLLSTAT) [Hex Address: 029C 013C] Table 7-35. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit 31:1 0 Field Reserved GOSTAT 0 1 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. GO operation status. Go operation is not in progress. SYSCLK divide ratios are not being changed. GO operation is in progress. SYSCLK divide ratios are being changed.
7.8.3.4
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-27 and described in Table 7-36.
31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 1 0 ALN1 R/W-1 16
Figure 7-27. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029C 0140] Table 7-36. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit 31:1 0 Field Reserved ALN1 0 1 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SYSCLK1 alignment. Do not change the default values of these fields. Do not align SYSCLK1 during GO operation. If SYS1 in DCHANGE is set to 1, SYSCLK1 switches to the new ratio immediately after the GOSET bit in PLLCMD is set. Align SYSCLK1 when the GOSET bit in PLLCMD is set. The SYSCLK1 ratio is set to the ratio programmed in the RATIO bit in PLLDIV1.
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7.8.3.5
Whenever a different ratio is written to the PLLDIV1 register, the PLLCTRL flags the change in the DCHANGE status register. During the GO operation, the PLL controller will only change the divide ratio SYSCLK1 if SYS1 in DCHANGE is 1. The PLLDIV divider ratio change status register is shown in Figure 7-28 and described in Table 7-37.
31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 1 0 SYS1 R-0 16
Figure 7-28. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029C 0144] Table 7-37. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit 31:1 0 Field Reserved SYS1 0 1 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SYSCLK1 divide ratio has been modified. SYSCLK1 ratio will be modified during GO operation. SYSCLK1 ratio has not been modified. When GOSET is set, SYSCLK1 will not be affected. SYSCLK1 ratio has been modified. When GOSET is set, SYSCLK1 will change to the new ratio.
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7.8.3.6
The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT is shown in Figure 7-29 and described in Table 7-38.
31
Reserved
16 R-0
15
Reserved
1 R-0
0
SYS1ON
R-1
Figure 7-29. SYSCLK Status Register [Hex Address: 029C 0150] Table 7-38. SYSCLK Status Register Field Descriptions
Bit 31:1 0 Field Reserved SYS1ON 0 1 Value 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SYSCLK1 on status. SYSCLK1 is gated. SYSCLK1 is on.
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7.8.4
NO.
UNIT
The reference points for the rise and fall transitions are measured at 3.3 V VIL MAX and VIH MIN. C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns. If EMAC is enabled with RGMII or GMII, CLKIN2 cycle time must be 40 ns (25 MHz). 5 2 1 4
CLKIN2 3 4
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7.9
7.9.1
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7.9.2
7.9.3
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NO.
UNIT
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA. Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. This timing only applies when AECLKIN is used for EMIFA. 5 2 1 4
AECLKIN 3 4
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Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module (1) (2) (3)
(see Figure 7-32)
-720 -850 A-1000/-1000 -1200 MIN 1 2 3 4 5 6 (1) (2) (3) tc(EKO) tw(EKOH) tw(EKOL) tt(EKO) td(EKIH-EKOH) td(EKIL-EKOL) Cycle time, AECLKOUT Pulse duration, AECLKOUT high Pulse duration, AECLKOUT low Transition time, AECLKOUT Delay time, AECLKIN high to AECLKOUT high Delay time, AECLKIN low to AECLKOUT low 1 1 E - 0.7 EH - 0.7 EL - 0.7 MAX E + 0.7 EH + 0.7 EL + 0.7 1 8 8 ns ns ns ns ns ns
NO.
PARAMETER
UNIT
E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA. The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
AECLKIN 1 6 5 2 3 4 4
AECLKOUT1
Figure 7-32. AECLKOUT Timing for the EMIFA Module 7.10.3.1 Asynchronous Memory Timing
(2) (3)
Table 7-44. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module (1)
(see Figure 7-33 and Figure 7-34)
-720 -850 A-1000/-1000 -1200 MIN 3 4 5 6 7 8 9 (1) (2) (3) tsu(EDV-A OEH) th(AOEH-EDV) tsu(ARDY-EKOH) th(EKOH-ARDY) tw(ARDY ) td(ARDY-HOLD) tsu(ARDY-HOLD) Setup time, AEDx valid before AAOE high Hold time, AEDx valid after AAOE high Setup time, AARDY valid before AECLKOUT low Hold time, AARDY valid after AECLKOUT low Pulse width, AARDY assertion and deassertion Delay time, from AARDY sampled deasserted on AECLKOUT falling to beginning of programmed hold period Setup time, before end of programmed strobe period by which AARDY should be asserted in order to insert extended strobe wait states. 2E 6.5 0 1 2 2E + 5 4E
NO.
UNIT
MAX ns ns ns ns ns ns ns
E = AECLKOUT period in ns for EMIFA To ensure data setup time, simply program the strobe width wide enough. AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E to ensure setup and hold time is met.
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Table 7-45. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module (1) (2) (3)
(see Figure 7-33 and Figure 7-34)
-720 -850 A-1000/-1000 -1200 MIN 1 2 10 11 12 13 (1) (2) (3) tosu(SELV-AOEL) toh(AOEH-SELIV) td(EKOH-AOEV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKOH-AWEV) Output setup time, select signals valid to AAOE low Output hold time, AAOE high to select signals invalid Delay time, AECLKOUT high to AAOE valid Output setup time, select signals valid to AAWE low Output hold time, AAWE high to select signals invalid Delay time, AECLKOUT high to AAWE valid RS * E - 1.5 RS * E - 1.9 1 WS * E - 1.7 WH * E - 1.8 1.3 7.1 7 MAX ns ns ns ns ns ns
NO.
PARAMETER
UNIT
E = AECLKOUT period in ns for EMIFA RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIFA CE Configuration registers (CEnCFG). Select signals for EMIFA include: ACEx, ABE[7:0], AEA[19:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[63:0]. Strobe = 4 Setup = 1 AECLKOUT 1 ACEx 1 ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] 10 AAOE/ASOE(A) 1 Address 3 4 Read Data 10 Byte Enables 2 2 Hold = 1 2
A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous memory accesses. B Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC).
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Strobe = 4 Setup = 1 AECLKOUT 11 ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE(A) AAWE/ASWE(A) 11 12 AR/W DEASSERTED AARDY(B) A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous memory accesses. B Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC). 13 11 Address 11 Write Data 13 12 11 Byte Enables 12 12 12 Hold = 1
6 7
A Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC).
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7.10.3.2
Table 7-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 7-36)
-720 -850 A-1000/-1000 -1200 MIN 6 7 tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read AEDx valid before AECLKOUT high Hold time, read AEDx valid after AECLKOUT high 2 1.5 MAX ns ns
NO.
UNIT
Table 7-47. Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA Module (1)
(see Figure 7-36 through Figure 7-38)
-720 -850 A-1000/-1000 -1200 MIN 1 2 3 4 5 8 9 10 11 12 (1) td(EKOH-CEV) td(EKOH-BEV) td(EKOH-BEIV) td(EKOH-EAV) td(EKOH-EAIV) td(EKOH-ADSV) td(EKOH-OEV) td(EKOH-EDV) td(EKOH-EDIV) td(EKOH-WEV) Delay time, AECLKOUT high to ACEx valid Delay time, AECLKOUT high to ABEx valid Delay time, AECLKOUT high to ABEx invalid Delay time, AECLKOUT high to AEAx valid Delay time, AECLKOUT high to AEAx invalid Delay time, AECLKOUT high to ASADS/ASRE valid Delay time, AECLKOUT high to ASOE valid Delay time, AECLKOUT high to AEDx valid Delay time, AECLKOUT high to AEDx invalid Delay time, AECLKOUT high to ASWE valid 1.3 1.3 4.9 1.3 1.3 1.3 4.9 4.9 4.9 1.3 4.9 1.3 MAX 4.9 4.9 ns ns ns ns ns ns ns ns ns ns
NO.
PARAMETER
UNIT
The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG): Read latency (R_LTNCY): 0-, 1-, 2-, or 3-cycle read latency Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CE_EXT = 1). Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (R_ENABLE = 1).
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READ latency = 2 AECLKOUT 1 ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] 8 ASADS/ASRE(B) 9 AAOE/ASOE(B) AAWE/ASWE(B) A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn): Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1). Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1). In this figure R_LTNCY = 2, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1. B AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses. 9 2 BE1 4 EA1 EA2 6 Q1 EA3 EA4 7 Q2 Q3 Q4 8 3 BE2 BE3 BE4 5 1
Figure 7-36. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)(A)
AECLKOUT 1 ACEx 2 BE1 4 EA1 10 AED[63:0] ASADS/ASRE(B) AAOE/ASOE(B) 12 12 AAWE/ASWE(B) A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn): Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1). Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1). In this figure W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1. B AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses. 10 Q1 8 3 BE2 BE3 BE4 5 EA2 Q2 EA3 Q3 EA4 11 Q4 8 1
ABE[7:0]
AEA[19:0]/ABA[1:0]
Figure 7-37. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)(A)
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Write Latency = 1 (B) AECLKOUT 1 ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] 8 ASADS/ASRE (B) AAOE/ASOE (B) 12 AAWE/ASWE (B) A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn): Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1). Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1). In this figure W_LTNCY = 1, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1. B AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses. 12 2 BE1 4 EA1 10 3 BE2 EA2 10 Q1 BE3 EA3 Q2 BE4 5 EA4 11 Q3 Q4 8 1
Figure 7-38. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) (A)
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7.10.4
HOLD/HOLDA Timing
Table 7-48. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module (1)
NO.
UNIT
Table 7-49. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA Cycles for EMIFA Module (1) (2)
(see Figure 7-39)
-720 -850 A-1000/-1000 -1200 MIN 1 2 4 5 (1) (2) (3) td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) Delay time, HOLD low to EMIFA Bus high impedance Delay time, EMIF Bus high impedance to HOLDA low Delay time, HOLD high to EMIF Bus low impedance Delay time, EMIFA Bus low impedance to HOLDA high 2E 0 2E 0 MAX
(3)
NO.
PARAMETER
UNIT
ns ns ns ns
2E 7E 2E
E = the EMIF input clock (ECLKIN) period in ns for EMIFA. EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ ASOE, and AAWE/ASWE. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. DSP Owns Bus External Requestor Owns Bus 3 HOLD 2 HOLDA 1 EMIF Bus (A) DSP 4 DSP 5 DSP Owns Bus
AECLKOUT A. EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ ASOE, and AAWE/ASWE.
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NO.
PARAMETER
UNIT
1 ABUSREQ
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I2C Module Clock Prescale I2CPSC Control Bit Clock Generator Noise Filter I2CCLKH I2CCLKL I2CMDR I2CCNT Transmit Shift Transmit Buffer Interrupt/DMA Noise Filter Receive I2CDRR Receive Buffer Receive Shift I2CIMR I2CSTR I2CIVR Interrupt Mask/Status Interrupt Status Interrupt Vector I2CEMDR Mode Data Count Extended Mode I2COAR I2CSAR Own Address Slave Address Peripheral Clock (CPU/6)
Transmit I2CXSR
I2CRSR
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NO.
UNIT MAX 2.5 0.6 0.6 1.3 0.6 100 (2) 0 (3) 1.3 0.9 (4) s s s s s ns s s 300 300 300 300 ns ns ns ns s 50 400 ns pF
MAX
Cycle time, SCL Setup time, SCL high before SDA low (for a repeated START condition) Hold time, SCL low after SDA low (for a START and a repeated START condition) Pulse duration, SCL low Pulse duration, SCL high Setup time, SDA valid before SCL high Hold time, SDA valid after SCL low (For I C bus devices) Pulse duration, SDA high between STOP and START conditions Rise time, SDA Rise time, SCL Fall time, SDA Fall time, SCL Setup time, SCL high before SDA high (for STOP condition) Pulse duration, spike (must be suppressed) Capacitive load for each bus line
2
0.6 0 400
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 11 SDA 8 4 10 SCL 1 7 3 Stop Start Repeated Start 12 3 2 5 6 14 13 9
Stop
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NO.
PARAMETER
0.6
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 26 SDA 23 19 25 SCL 16 22 18 Stop Start Repeated Start 27 18 17 20 21 28 24
Stop
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0288 0004
PWREMU_MGMT
0288 0008 - 0288 0024 0288 0028 0288 002C 0288 0030 0288 0034 0288 0038 0288 000C - 028B 007F 0288 0080 - 028B FFFF (1) (2)
Reserved Reserved Reserved HPI control register HPI address register (Write) HPI address register (Read) Reserved Reserved The Host and the CPU have read/write access to the HPIC register. (1) The Host has read/write access to the HPIA registers. The CPU has only read access to the HPIA registers.
The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an interrupt from the host. There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969) .
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(2)
NO.
UNIT
MAX ns ns ns ns ns ns ns ns ns ns ns ns
5 2 5 5 15 2M 5 5 5 1 0 1.1
Hold time, select signals (3) valid after HAS low Pulse duration, HSTROBE low Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals
(3)
Hold time, select signals (3) valid after HSTROBE low Setup time, host data valid before HSTROBE high Hold time, host data valid after HSTROBE high Setup time, HCS low before HSTROBE low Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. M = SYSCLK3 period = 6/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns. Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
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(2)
NO.
PARAMETER
UNIT
Case 1. HPIC or HPIA read Case 2. HPID read with no auto-increment (3) 1 td(HSTBL-HDV) Delay time, HSTROBE low to DSP data valid Case 3. HPID read with auto-increment and read FIFO initially empty (3) Case 4. HPID read with auto-increment and data previously prefetched into the read FIFO 2 3 4 5 tdis(HSTBH-HDV) ten(HSTBL-HD) td(HSTBL-HRDYH) td(HSTBH-HRDYH) Disable time, HD high-impedance from HSTROBE high Enable time, HD driven from HSTROBE low Delay time, HSTROBE low to HRDY high Delay time, HSTROBE high to HRDY high Delay time, HSTROBE low to HRDY low Case 1. HPID read with no auto-increment (3) Case 2. HPID read with auto-increment and read FIFO initially empty (3)
ns
ns ns ns ns
td(HSTBL-HRDYL)
ns 10 * M + 20 0 5 * M + 20 5 * M + 20 40 * M + 20 12 ns ns
7 34
td(HDV-HRDYL) td(DSH-HRDYL)
Delay time, HD valid to HRDY low Delay time, HSTROBE high to Case 2. HPID write with no HRDY low auto-increment (3) Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not empty (3) Delay time, HAS low to HRDY high Case 1. HPIA write (3)
td(HSTBL-HRDYL) td(HASL-HRDYH)
ns ns
M = SYSCLK3 period = 6/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.
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HCS HAS HCNTL[1:0] HR/W HHWIL 13 16 15 37 HSTROBE(A) 3 1 HD[15:0] 38 4 6 HRDY(B) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969) . 7 2 3 1 2 37 14 15 13 16
Figure 7-44. HPI16 Read Timing (HAS Not Used, Tied High)
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HCS
HAS 12 11 HCNTL[1:0] 12 11 HR/W 12 11 HHWIL 10 9 37 HSTROBE(A) 1 3 HD[15:0] 7 36 HRDY(B) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969) . 6 38 1 3 2 10 13 37 14 9 13 12 11 12 11 12 11
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4 35 HRDY(B) A. B.
34
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969) .
Figure 7-46. HPI16 Write Timing (HAS Not Used, Tied High)
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HCS
HAS 12 11 HCNTL[1:0] 12 11 HR/W 12 11 HHWIL 10 9 HSTROBE(A) 37 13 18 17 HD[15:0] 35 36 HRDY(B) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969) . 38 34 5 5 34 17 14 37 13 9 10 12 11 12 11 12 11
18
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HR/W (input) 13 HSTROBE(A) (input) 37 HCS (input) 1 3 HD[31:0] (output) 38 7 6 4 HRDY(B) (output) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969) . The timing tw(HSTBH), HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 mode.
C.
Figure 7-48. HPI32 Read Timing (HAS Not Used, Tied High)
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37 HCS (input) 1 3 HD[31:0] (output) 7 38 6 36 HRDY(B) (output) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969) . The timing tw(HSTBH), HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 mode.
C.
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HR/W (input)
13 HSTROBE(A) (input) 37 HCS (input) 18 17 HD[31:0] (input) 38 34 35 4 HRDY(B) (output) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969) . The timing tw(HSTBH), HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 mode. 5
C.
Figure 7-50. HPI32 Write Timing (HAS Not Used, Tied High)
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17 HD[31:0] (input)
35 36 HRDY(B) (output) A. B. 38
34 5
C.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969) . The timing tw(HSTBH), HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 mode.
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NO.
UNIT MAX ns ns ns ns ns ns ns ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP (1)
(see Figure 7-52)
-720 -850 A-1000/-1000 -1200 MIN 1 2 3 4 9 12 13 td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV) td(CKXH-FXV) tdis(CKXH-DXHZ) td(CKXH-DXV) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input (3) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Delay time, CLKR high to internal FSR valid Delay time, CLKX high to internal FSX valid Disable time, DX high impedance following last data bit from CLKX high Delay time, CLKX high to DX valid Delay time, FSX high to DX valid 14 (1) (2) (3) (4) (5) (6) (7) td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode CLKR/X int CLKR/X int CLKR int CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext 6P or 10 (4) 1.4
(5) (6)
NO.
PARAMETER
(8) (9)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. The CLKS signal is shared by both McBSP0 and McBSP1 on this device. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. Use whichever value is greater. C = H or L S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency) S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above). Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 6P, D2 = 12P Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 6P, D2 = 12P
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CLKS 1 3 3 CLKR 4 FSR (int) 5 FSR (ext) 7 DR 2 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX A. B. Bit 0 14 13 (A) Bit(n-1) 13 (A) (n-2) (n-3) 3 Bit(n-1) 8 (n-2) (n-3) 6 4 2
Parameter No. 13 applies to the first data bit only when XDATDLY 0. The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
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NO.
UNIT
Figure 7-53. FSR Timing When GSYNC = 1 Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (1)
(see Figure 7-54)
-720 -850 A-1000/-1000 -1200 MASTER MIN 4 5 (1) (2) tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low 12 4 MAX SLAVE MIN 2 - 18P 5 + 36P MAX ns ns
(2)
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
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Table 7-63. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (1) (2)
(see Figure 7-54)
-720 -850 A-1000/-1000 -1200 MASTER MIN 1 2 3 6 7 8 (1) (2) (3) th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ) td(FXL-DXV) Hold time, FSX low after CLKX low (4) Delay time, FSX low to CLKX high (5) Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low Disable time, DX high impedance following last data bit from FSX high Delay time, FSX low to DX valid T-2 L-2 -2 L-2
(3)
NO.
PARAMETER
18P + 2.8
30P + 17
ns ns
6P + 3 12P + 2
18P + 17 24P + 17
ns ns
(4)
(5)
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency) S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 3 Bit(n-1) 5 (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) 2
Figure 7-54. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Table 7-64. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (1)
(see Figure 7-55)
-720 -850 A-1000/-1000 -1200 MASTER MIN 4 5 (1) (2) tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 18P 5 + 36P MAX
NO.
UNIT
ns ns
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
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Table 7-65. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (1) (2)
(see Figure 7-55)
-720 -850 A-1000/-1000 -1200 MASTER MIN 1 2 3 6 7 (1) (2) (3) th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ) td(FXL-DXV) Hold time, FSX low after CLKX low (4) Delay time, FSX low to CLKX high (5) Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX low Delay time, FSX low to DX valid L-2 T-2 -2 -2 H-2
(3)
NO.
PARAMETER
ns ns ns
(4)
(5)
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency) S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 FSX 6 Bit 0 7 Bit(n-1) 4 DR Bit 0 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
DX
Figure 7-55. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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Table 7-66. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (1)
(see Figure 7-56)
-720 -850 A-1000/-1000 -1200 MASTER MIN 4 5 (1) (2) tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 18P 5 + 36P MAX
NO.
UNIT
ns ns
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
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Table 7-67. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (1) (2)
(see Figure 7-56)
-720 -850 A-1000/-1000 -1200 MASTER MIN 1 2 3 6 7 8 (1) (2) (3) th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) td(FXL-DXV) Hold time, FSX low after CLKX high (4) Delay time, FSX low to CLKX low (5) Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX high Disable time, DX high impedance following last data bit from FSX high Delay time, FSX low to DX valid T-2 H-2 -2 H-2
(3)
NO.
PARAMETER
18P + 2.8
30P + 17
ns ns
6P + 3 12P + 2
18P + 17 24P + 17
ns ns
(4)
(5)
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency) S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 Bit(n-1) 5 (n-2) (n-3) (n-4) 3 (n-2) (n-3) (n-4) 2
Figure 7-56. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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Table 7-68. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (1)
(see Figure 7-57)
-720 -850 A-1000/-1000 -1200 MASTER MIN 4 5 (1) (2) tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 18P 5 + 36P MAX
NO.
UNIT
ns ns
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
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Table 7-69. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (1) (2)
(see Figure 7-57)
-720 -850 A-1000/-1000 -1200 MASTER MIN 1 2 3 6 7 (1) (2) (3) th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) td(FXL-DXV) Hold time, FSX low after CLKX high (4) Delay time, FSX low to CLKX low (5) Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX high Delay time, FSX low to DX valid H-2 T-2 -2 -2 L-2
(3)
NO.
PARAMETER
ns ns ns
(4)
(5)
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency) S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 FSX 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 7 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
Figure 7-57. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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Interrupt Controller
Configuration Bus
Peripheral Bus
Ethernet Bus
MDIO Bus
Figure 7-58. EMAC, MDIO, and EMAC Control Modules For more detailed information on the EMAC/MDIO, see the TMS320C645x DSP EMAC/MDIO Module Reference Guide (literature number SPRU975) .
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Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes)
BALL NUMBER DEVICE PIN NAME MII (MAC_SEL = 00b) MRXD0 MRXD1 MRXD2 MRXD3 RMII (MAC_SEL = 01b) RMRXD0 RMRXD1 GMII (MAC_SEL = 10b) MRXD0 MRXD1 MRXD2 MRXD3 MRXD4 MRXD5 MRXD6 MRXD7 MTXD0 MTXD1 MTXD2 MTXD3 RMTXD0 RMTXD1 MTXD0 MTXD1 MTXD2 MTXD3 MTXD4 MTXD5 MTXD6 MTXD7 MRXER MRXDV MTXEN MCRS MCOL RMTXEN RMCRSDV RMRXER MRXER MRXDV MTXEN MCRS MCOL GMTCLK MRCLK MTCLK MDIO MDCLK RMREFCLK MDIO MDCLK MRCLK MTCLK MDIO MDCLK
J2 H3 J1 J3 L1 L2 H2 M2 M1 L4 M4 K4 L3 L5 M3 N5 H4 H5 J5 J4 K3 K5 H1 N4 N3 M5
URDATA0/MRXD0/RMRXD0 URDATA1/MRXD1/RMRXD1 URDATA2/MRXD2 URDATA3/MRXD3 URDATA4/MRXD4 URDATA5/MRXD5 URDATA6/MRXD6 URDATA7/MRXD7 UXDATA0/MTXD0/RMTXD0 UXDATA1/MTXD1/RMTXD1 UXDATA2/MTXD2 UXDATA3/MTXD3 UXDATA4/MTXD4 UXDATA5/MTXD5 UXDATA6/MTXD6 UXDATA7/MTXD7 URSOC/MRXER/RMRXER URENB/MRXDV UXENB/MTXEN/RMTXEN URCLAV/MCRS/RMCRSDV UXSOC/MCOL UXCLAV/GMTCLK URCLK/MRCLK UXCLK/MTCLK/REFCLK UXADDR3/GMDIO UXADDR4/GMDCLK
Using the RMII Mode of the EMAC The Ethernet Media Access Controller (EMAC) contains logic that allows it to communicate using the Reduced Media Independent Interface (RMII) protocol. This logic must be taken out of reset before being used. To use the RMII mode of the EMAC follow these steps: 1. Enable the EMAC/MDIO through the Device State Control Registers. Unlock the PERCFG0 register by writing 0x0F0A 0B00 to the PERLOCK register. Set bit 4 in the PERCFG0 register within 16 SYSCLK3 clock cycles to enable the EMAC/MDIO. Poll the PERSTAT0 register to verify state change. 2. Initialize the EMAC/MDIO as needed. 3. Release the RMII logic from reset by clearing the RMII_RST bit of the EMAC Configuration Register (see Section 3.4.5). As described in the previous section, the RMII mode of the EMAC must be selected by setting MACSEL[1:0] = 01b at device reset.
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Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate the clocks to the EMAC module in RGMII or GMII mode. When the EMAC is enabled with these modes, the input clock to the PLL2 Controller (CLKIN2) must have a 25-MHz frequency. For more information, see Section 7.8, PLL2 and PLL2 Controller. The EMAC uses SYSCLK1 of the PLL2 Controller to generate the necessary clocks for the GMII and RGMII modes. When these modes are used, the frequency of CLKIN2 must be 25 MHz. Also, divider D1 should be programmed to 2 mode [default] when using the GMII mode and to 5 mode when using the RGMII mode. Divider D1 is software programmable and, if necessary, must be programmed after device reset to 5 when the RGMII mode of the EMAC is used.
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NO.
UNIT
Figure 7-59. MRCLK Timing (EMAC - Receive) [MII and GMII Operation] Table 7-76. Timing Requirements for MTCLK - MII and GMII Operation
(see Figure 7-60)
-720 -850 A-1000/-1000 -1200 100 Mbps MIN 1 2 3 4 tc(MTCLK) tw(MTCLKH) tw(MTCLKL) tt(MTCLK) Cycle time, MTCLK Pulse duration, MTCLK high Pulse duration, MTCLK low Transition time, MTCLK 40 14 14 3 4 1 2 MTCLK (Input) 3 4 MAX 10 Mbps MIN 400 140 140 3 MAX ns ns ns ns
NO.
UNIT
Figure 7-60. MTCLK Timing (EMAC - Transmit) [MII and GMII Operation]
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Table 7-77. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII Operation
(see Figure 7-61)
-720 -850 A-1000/-1000 -1200 1000 Mbps MIN 1 2 3 4 tc(GMTCLK) tw(GMTCLKH) tw(GMTCLKL) tt(GMTCLK) Cycle time, GMTCLK Pulse duration, GMTCLK high Pulse duration, GMTCLK low Transition time, GMTCLK 4 1 2 GMTCLK (Output) 3 4 8 2.8 2.8 1 MAX ns ns ns ns
NO.
UNIT
Figure 7-61. GMTCLK Timing (EMAC - Transmit) [GMII Operation] Table 7-78. Timing Requirements for EMAC MII and GMII Receive 10/100/1000 Mbit/s (1)
(see Figure 7-62)
-720 -850 A-1000/-1000 -1200 1000 Mbps MIN 1 2 (1) tsu(MRXD-MRCLKH) th(MRCLKH-MRXD) Setup time, receive selected signals valid before MRCLK high Hold time, receive selected signals valid after MRCLK high 2 0 MAX 100/10 Mbps MIN 8 8 MAX ns ns
NO.
UNIT
For MII, Receive selected signals include: MRXD[3:0], MRXDV, and MRXER. For GMII, Receive selected signals include: MRXD[7:0], MRXDV, and MRXER. 1 2 MRCLK (Input) MRXD7MRXD4(GMII only), MRXD3MRXD0, MRXDV, MRXER (Inputs)
Figure 7-62. EMAC Receive Interface Timing [MII and GMII Operation]
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Table 7-79. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII Transmit 10/100 Mbit/s (1)
(see Figure 7-63)
-720 -850 A-1000/-1000 -1200 100/10 Mbps MIN 1 (1) td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid 5 MAX 25 ns
NO.
PARAMETER
UNIT
For MII, Transmit selected signals include: MTXD[3:0] and MTXEN. For GMII, Transmit selected signals include: GMTXD[7:0] and MTXEN. 1 MTCLK (Input)
Figure 7-63. EMAC Transmit Interface Timing [MII and GMII Operation] Table 7-80. Switching Characteristics Over Recommended Operating Conditions for EMAC GMII Transmit 1000 Mbit/s (1)
(see Figure 7-64)
-720 -850 A-1000/-1000 -1200 1000 Mbps MIN 1 (1) td(GMTCLKH-MTXD) Delay time, GMTCLK high to transmit selected signals valid 0.5 MAX 5 ns
NO.
PARAMETER
UNIT
For GMII, Transmit selected signals include: GMTXD[7:0] and MTXEN. 1 GMTCLK (Output)
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7.14.3.2 EMAC RMII Electrical Data/Timing The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation. The RMREFCLK frequency should be 50 MHz 50 PPM with a duty cycle between 35% and 65%, inclusive. Table 7-81. Timing Requirements for RMREFCLK - RMII Operation
(see Figure 7-65)
-720 -850 A-1000/-1000 -1200 MIN 1 2 3 tw(RMREFCLKH) tw(RMREFCLKL) tt(RMREFCLK) Pulse duration, RMREFCLK high Pulse duration, RMREFCLK low Transition time, RMREFCLK 3 7 7 MAX 13 13 2 ns ns ns
NO.
PARAMETER
UNIT
1 RMREFCLK (Input) 2
Figure 7-65. RMREFCLK Timing Table 7-82. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10/100 Mbit/s (1)
(see Figure 7-66)
-720 -850 A-1000/-1000 -1200 1000 Mbps MIN 1 (1) td(RMREFCLKH-RMTXD) Delay time, RMREFCLK high to transmit selected signals valid 3 MAX 10 ns
NO.
PARAMETER
UNIT
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Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps (1)
(see Figure 7-67)
-720 -850 A-1000/-1000 -1200 MIN 1 2 (1) tsu(RMRXDRMREFCLK)
NO.
UNIT
MAX ns ns
Setup time, receive selected signals valid before RMREFCLK (at DSP) high/low Hold time, receive selected signals valid after RMREFCLK (at DSP) high/low
4.0 2.0
th(RMREFCLKRMRXD)
For RMII, receive selected signals include: RMRXD[1:0], RMRXER, and RMCRSDV.
1 RMREFCLK (Input) 4 5 RMRXD1-RMRXD0, RMCRSDV, RMRXER (Inputs) 2 3 3
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7.14.3.3 EMAC RGMII Electrical Data/Timing An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user. Note that this reference clock is not a free-running clock. This should only be used by an external device if it does not expect a valid clock during device reset. Table 7-84. Switching Characteristics Over Recommended Operating Conditions for EMAC RGREFCLK RGMII Operation
(see Figure 7-68)
-720 -850 A-1000/-1000 -1200 MIN 1 2 3 4 tc(RGFCLK) tw(RGFCLKH) tw(RGFCLKL) tt(RGFCLK) Cycle time, RGREFCLK Pulse duration, RGREFCLK high Pulse duration, RGREFCLK low Transition time, RGREFCLK 1 2 RGREFCLK (Output) 3 4 4 8 - 0.8 3.2 3.2 MAX 8 + 0.8 4.8 4.8 0.75 ns ns ns ns
NO.
PARAMETER
UNIT
Figure 7-68. RGREFCLK Timing Table 7-85. Timing Requirements for RGRXC - RGMII Operation
(see Figure 7-69)
-720 -850 A-1000/-1000 -1200 MIN 10 Mbps 1 tc(RGRXC) Cycle time, RGRXC 100 Mbps 1000 Mbps 10 Mbps 2 tw(RGRXCH) Pulse duration, RGRXC high 100 Mbps 1000 Mbps 10 Mbps 3 tw(RGRXCL) Pulse duration, RGRXC low 100 Mbps 1000 Mbps 10 Mbps 4 tt(RGRXC) Transition time, RGRXC 100 Mbps 1000 Mbps 360 36 7.2 0.40*tc(RGRXC) 0.40*tc(RGRXC) 0.45*tc(RGRXC) 0.40*tc(RGRXC) 0.40*tc(RGRXC) 0.45*tc(RGRXC) MAX 440 44 8.8 0.60*tc(RGRXC) 0.60*tc(RGRXC) 0.55*tc(RGRXC) 0.60*tc(RGRXC) 0.60*tc(RGRXC) 0.55*tc(RGRXC) 0.75 0.75 0.75 ns ns ns ns
NO.
UNIT
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Table 7-86. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps (1)
(see Figure 7-69)
-720 -850 A-1000/-1000 -1200 MIN 5 6 (1) tsu(RGRXD-RGRXCH) th(RGRXCH-RGRXD) Setup time, receive selected signals valid before RGRXC (at DSP) high/low Hold time, receive selected signals valid after RGRXC (at DSP) high/low 1.0 1.0 MAX ns ns
NO.
UNIT
4 3 4
RGRXD[3:0]
RGRXD[7:4]
RGRXCTL
(B)
RXDV
RXERR
A. B.
RGRXC must be externally delayed relative to the data and control pins. Data and control information is received using both edges of the clocks. RGRXD[3:0] carries data bits 3-0 on the rising edge of RGRXC and data bits 7-4 on the falling edge of RGRXC. Similarly, RGRXCTL carries RXDV on rising edge of RGRXC and RXERR on falling edge.
Figure 7-69. EMAC Receive Interface Timing [RGMII Operation] Table 7-87. Switching Characteristics Over Recommended Operating Conditions for RGTXC - RGMII Operation for 10/100/1000 Mbit/s
(see Figure 7-70)
-720 -850 A-1000/-1000 -1200 MIN 10 Mbps 1 tc(RGTXC) Cycle time, RGTXC 100 Mbps 1000 Mbps 10 Mbps 2 tw(RGTXCH) Pulse duration, RGTXC high 100 Mbps 1000 Mbps 10 Mbps 3 tw(RGTXCL) Pulse duration, RGTXC low 100 Mbps 1000 Mbps 10 Mbps 4 tt(RGTXC) Transition time, RGTXC 100 Mbps 1000 Mbps 360 36 7.2 0.40*tc(RGTXC) 0.40*tc(RGTXC) 0.45*tc(RGTXC) 0.40*tc(RGTXC) 0.40*tc(RGTXC) 0.45*tc(RGTXC) MAX 440 44 8.8 0.60*tc(RGTXC) 0.60*tc(RGTXC) 0.55*tc(RGTXC) 0.60*tc(RGTXC) 0.60*tc(RGTXC) 0.55*tc(RGTXC) 0.75 0.75 0.75 ns ns ns ns
NO.
UNIT
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Table 7-88. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit (1)
(see Figure 7-70)
-720 -850 A-1000/-1000 -1200 MIN 5 6 (1) tsu(RGTXD-RGTXCH) th(RGTXCH-RGTXD) Setup time, transmit selected signals valid before RGTXC (at DSP) high/low Hold time, transmit selected signals valid after RGTXC (at DSP) high/low 1.2 1.2 MAX ns
NO.
PARAMETER
UNIT
RGTXD[3:0]
(B)
RGTXCTL
(B)
TXEN
A. B.
RGTXC is delayed internally before being driven to the RGTXC pin. Data and control information is transmitted using both edges of the clocks. RGTXD[3:0] carries data bits 3-0 on the rising edge of RGTXC and data bits 7-4 on the falling edge of RGTXC. Similarly, RGTXCTL carries TXEN on rising edge of RGTXC and TXERR of falling edge.
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7.14.4
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. The EMAC control module is the main interface between the device core processor, the MDIO module, and the EMAC module. The relationship between these three components is shown in Figure 7-58. The MDIO uses the same pins for the MII, GMII, and RMII modes. Standalone pins are included for the RGMII mode due to specific voltage requirements. Only one mode can be used at a time. The mode used is selected at device reset based on the MACSEL[1:0] configuration pins (for more detailed information, see Section 3, Device Configuration). Table 7-70 above shows which multiplexed pin are used in the MII, GMII, and RMII modes on the MDIO. For more detailed information on the EMAC/MDIO, see the TMS320C645x DSP EMAC/MDIO Module Reference Guide (literature number SPRU975) . 7.14.4.1 MDIO Device-Specific Information Clocking Information The MDIO clock is based on a divide-down of the SYSCLK3 (from the PLL1 controller) and is specified to run up to 2.5 MHz, although typical operation is 1.0 MHz. Since the peripheral clock frequency is variable, the application software or driver controls the divide-down amount. 7.14.4.2 MDIO Peripheral Register Descriptions Table 7-89. MDIO Registers
HEX ADDRESS RANGE 02C8 1800 02C8 1804 02C8 1808 02C8 180C 02C8 1810 02C8 1814 02C8 1818 - 02C8 181C 02C8 1820 02C8 1824 02C8 1828 02C8 182C 02C8 1830 - 02C8 187C 02C8 1880 02C8 1884 02C8 1888 02C8 188C 02C8 1890 - 02C8 1FFF ACRONYM VERSION CONTROL ALIVE LINK LINKINTRAW LINKINTMASKED USERINTRAW USERINTMASKED USERINTMASKSET USERINTMASKCLEAR USERACCESS0 USERPHYSEL0 USERACCESS1 USERPHYSEL1 MDIO Version Register MDIO Control Register MDIO PHY Alive Status Register MDIO PHY Link Status Register MDIO Link Status Change Interrupt (Unmasked) Register MDIO Link Status Change Interrupt (Masked) Register Reserved MDIO User Command Complete Interrupt (Unmasked) Register MDIO User Command Complete Interrupt (Masked) Register MDIO User Command Complete Interrupt Mask Set Register MDIO User Command Complete Interrupt Mask Clear Register Reserved MDIO User Access Register 0 MDIO User PHY Select Register 0 MDIO User Access Register 1 MDIO User PHY Select Register 1 Reserved REGISTER NAME
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7.14.4.3 MDIO Electrical Data/Timing Table 7-90. Timing Requirements for MDIO Input (R)(G)MII
(see Figure 7-71)
-720 -850 A-1000/-1000 -1200 MIN 1 2a 2b 3 4 5 tc(MDCLK) tw(MDCLK) tw(MDCLK) tt(MDCLK) tsu(MDIO-MDCLKH) th(MDCLKH-MDIO) Cycle time, MDCLK Pulse duration, MDCLK high Pulse duration, MDCLK low Transition time, MDCLK Setup time, MDIO data input valid before MDCLK high Hold time, MDIO data input valid after MDCLK high 10 10 400 180 180 5 MAX ns ns ns ns ns ns
NO.
UNIT
MDCLK
3 4
MDIO (input)
Figure 7-71. MDIO Input Timing Table 7-91. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 7-72)
-720 -850 A-1000/-1000 -1200 MIN 7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid MAX 100 ns
NO.
PARAMETER
UNIT
MDCLK
MDIO (output)
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7.15 Timers
The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the EDMA3 channel controller.
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NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 7-95. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs (1)
(see Figure 7-73)
-720 -850 A-1000/-1000 -1200 MIN 3 4 (1) tw(TOUTH) tw(TOUTL) Pulse duration, TOUTLx high Pulse duration, TOUTLx low 12P - 3 12P - 3 MAX ns ns
NO.
PARAMETER
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. 2 1 TINPLx 3 TOUTLx 4
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7.17 Enhanced Turbo Decoder Coprocessor (TCP2) 7.17.1 TCP2 Device-Specific Information
The C6455 device has a high-performance embedded coprocessor [Turbo-Decoder Coprocessor (TCP2) that significantly speeds up channel-decoding operations on-chip. With the CPU operating at 1 GHz, the TCP2 can decode up to forty 384-Kbps or eight 2-Mbps turbo-encoded channels (assuming 8 iterations). The TCP2 implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the TCP2 and the CPU are carried out through the EDMA3 controller. The TCP2 supports: Parallel concatenated convolutional turbo decoding using the MAP algorithm All turbo code rates greater than or equal to 1/5 3GPP and CDMA2000 turbo encoder trellis 3GPP and CDMA2000 block sizes in standalone mode Larger block sizes in shared processing mode Both max log MAP and log MAP decoding Sliding windows algorithm with variable reliability and prolog lengths The prolog reduction algorithm Execution of a minimum and maximum number of iterations The SNR stopping criteria algorithm The CRC stopping criteria algorithm For more detailed information on the TCP2, see the TMS320C645x DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide (literature number SPRU973).
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The on-chip Bootloader supports a host boot which allows an external PCI device to load application code into the DSP's memory space. The PCI boot is terminated when the Host generates a DSP interrupt. The Host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back-End Application Interrupt Enable Set Register (PCIBINTSET) and the Status Set Register (PCISTATSET). For more information on the boot sequence of the C6455 DSP, see Section 2.4. NOTE
After the host boot is complete, the DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.
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PCIBAR0TRLPRG PCI Base Address Translation Register 0 Program Register PCIBAR1TRLPRG PCI Base Address Translation Register 1 Program Register PCIBAR2TRLPRG PCI Base Address Translation Register 2 Program Register PCIBAR3TRLPRG PCI Base Address Translation Register 3 Program Register PCIBAR4TRLPRG PCI Base Address Translation Register 4 Program Register PCIBAR5TRLPRG PCI Base Address Translation Register 5 Program Register PCIBASENPRG PCI Base En Prog Register Reserved
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NO.
UNIT
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 1 2 4
UXCLK 3 4
Figure 7-74. UXCLK Timing Table 7-107. Timing Requirements for URCLK (1)
(see Figure 7-75)
-720 -850 A-1000/-1000 -1200 MIN 1 2 3 4 (1) tc(URCK) tw(URCKH) tw(URCKL) tt(URCK) Cycle time, URCLK Pulse duration, URCLK high Pulse duration, URCLK low Transition time, URCLK 20 0.4tc(URCK) 0.4tc(URCK) 0.6tc(URCK) 0.6tc(URCK) 2 MAX ns ns ns ns
NO.
UNIT
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 1 2 4
URCLK 3 4
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NO.
UNIT
Table 7-109. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave Transmit Cycles
(see Figure 7-76)
-720 -850 A-1000/-1000 -1200 MIN 1 4 5 6 7 10 td(UXCH-UXDV) td(UXCH-UXCLAV) td(UXCH-UXCLAVL) td(UXCH-UXCLAVHZ) tw(UXCLAVL-UXCLAVHZ) td(UXCH-UXSV) UXCLK 1 UXDATA[7:0] P45 P46 P47 P48 3 2 UXADDR[4:0] 0 x1F N 0x1F N 0x1F 6 7 4 UXCLAV N 9 UXENB 10 UXSOC A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC signals). 8 N 5 N+1 0x1F H1 Delay time, UXCLK high to UXDATA valid Delay time, UXCLK high to UXCLAV driven active value Delay time, UXCLK high to UXCLAV driven inactive low Delay time, UXCLK high to UXCLAV going Hi-Z Pulse duration (low), UXCLAV low to UXCLAV Hi-Z Delay time, UXCLK high to UXSOC valid 3 3 3 9 3 3 12 MAX 12 12 12 18.5 ns ns ns ns ns ns
NO.
PARAMETER
UNIT
232
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UNIT
Table 7-111. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave Receive Cycles
(see Figure 7-77)
-720 -850 A-1000/-1000 -1200 MIN 5 6 7 8 td(URCH-URCLAV) td(URCH-URCLAVL) td(URCH-URCLAVHZ) tw(URCLAVL-URCLAVHZ) URCLK 2 1 URDATA[7:0] P48 4 3 URADDR[4:0] N 0x1F N+1 0x1F 7 5 URCLAV N 10 URENB 11 URSOC A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and URSOC signals). 12 9 N+1 6 8 N+2 N+2 0x1F H1 H2 H3 Delay time, URCLK high to URCLAV driven active value Delay time, URCLK high to URCLAV driven inactive low Delay time, URCLK high to URCLAV going Hi-Z Pulse duration (low), URCLAV low to URCLAV Hi-Z 3 3 9 3 MAX 12 12 18.5 ns ns ns ns
NO.
PARAMETER
UNIT
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NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 24P to allow the DSP enough time to access the GPIO register through the CFGBUS.
Table 7-115. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (1)
(see Figure 7-78)
-720 -850 A-1000/-1000 -1200 MIN 3 4 (1) (2) tw(GPOH) tw(GPOL) Pulse duration, GPOx high Pulse duration, GPOx low 36P - 8 (2) 36P - 8
(2)
NO.
PARAMETER
UNIT MAX ns ns
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. 2 1 GPIx 3 GPOx 4
C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6455
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7.22 Emulation Features and Capability 7.22.1 Advanced Event Triggering (AET)
The C6455 device supports Advanced Event Triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides the following capabilities: Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture. Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate events such as halting the processor or triggering the trace capture. Counters: count the occurrence of an event or cycles for performance monitoring. State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences. For more information on AET, see the following documents: Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report (literature number SPRA753) Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems application report (literature number SPRA387)
7.22.2 Trace
The C6455 device supports Trace. Trace is a debug technology that provides a detailed, historical account of application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information for analysis. Trace works in real-time and does not impact the execution of the system. For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and Trace Headers Technical Reference Manual (literature number SPRU655).
248
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NO.
UNIT
Table 7-117. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 7-79)
-720 -850 A-1000/-1000 -1200 MIN 2 td(TCKL-TDOV) Delay time, TCK low to TDO valid -3 MAX 11 ns
NO.
PARAMETER
UNIT
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8 Mechanical Data
8.1 Thermal Data
Table 8-1 shows the thermal resistance characteristics for the PBGA - ZTZ/GTZ mechanical package. Table 8-1. Thermal Resistance Characteristics (S-PBGA Package) [ZTZ/GTZ]
NO. 1 2 3 4 5 6 RJA Junction-to-free air RJC RJB Junction-to-case Junction-to-board C/W 1.45 8.34 16.1 13.0 11.9 10.7 0.37 7 PsiJT Junction-to-package top 0.89 1.01 1.17 7.6 8 PsiJB Junction-to-board 6.7 6.4 5.8 (1) m/s = meters per second AIR FLOW (m/s) (1) N/A N/A 0.00 1.0 2.0 3.0 0.00 1.0 1.5 3.00 0.00 1.0 1.5 3.00
8.2
Packaging Information
The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document.
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PACKAGING INFORMATION
Orderable Device TMS320C6455BGTZ TMS320C6455BGTZ2 TMS320C6455BGTZ7 TMS320C6455BGTZ8 TMS320C6455BGTZA TMS320C6455BZTZ TMS320C6455BZTZ2 TMS320C6455BZTZ7 TMS320C6455BZTZ8 TMS320C6455BZTZA Status
(1)
Package Type Package Drawing FCBGA FCBGA FCBGA FCBGA FCBGA FCBGA FCBGA FCBGA FCBGA FCBGA GTZ GTZ GTZ GTZ GTZ ZTZ ZTZ ZTZ ZTZ ZTZ
Pins 697 697 697 697 697 697 697 697 697 697
Package Qty 44 44 44 44 10 1 1 44 44 1
(2)
Lead/ Ball Finish SNPB SNPB SNPB SNPB SNPB SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU
MSL Peak Temp Level-4-220C-72 HR Level-4-220C-72 HR Level-4-220C-72 HR Level-4-220C-72 HR Level-4-220C-72 HR Level-4-260C-72HR Level-4-260C-72HR Level-4-260C-72HR Level-4-260C-72HR Level-4-260C-72HR
(3)
Samples (Requires Login) Purchase Samples Purchase Samples Purchase Samples Purchase Samples Purchase Samples Purchase Samples Purchase Samples Purchase Samples Purchase Samples Purchase Samples
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Pb-Free (RoHS Exempt) Pb-Free (RoHS Exempt) Pb-Free (RoHS Exempt) Pb-Free (RoHS Exempt) Pb-Free (RoHS Exempt)
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
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Addendum-Page 2
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