Verilog

Download as pdf or txt
Download as pdf or txt
You are on page 1of 18
 
Programmable Logic DevicesVerilog VIICMPE 4151(11/30/05)
UMBC
U M B C
      U
      N
        I
       V
      E
      R
        S
        I
      T
     Y
 
   O
   F
 
  M
 A
  R
 Y
 L
A
 
B  
L  
T    
I    
M   
O    
R    
E     
 
 C 
 O
 U
  N
  T  Y
1
 
9
 
6
 
 6
Synthesis of Combinational Logic
Intheory,synthesistools
 automatically
createanoptimalgate-levelrealizationof a design from a high level HDL description.In reality, the results depend on the skill of the designer using the tool, andhis/her knowledge of how the HDL infers logic from language constructs.It is important to adopt a vendor-specific style that is amenable to synthesis.Otherwise synthesis may fail or produce unexpected results.It is important to know which constructs to avoid, and to be able to predictwhat the outcome will be for a particular construct.A Verilog description consisting only of a netlist of combinational primitives
without feedback 
 can always be synthesized.Some general rules:Allstorageelementsshouldbecontrolledbyanexternalclockandpossiblya reset line.
 
Programmable Logic DevicesVerilog VIICMPE 4152(11/30/05)
UMBC
U M B C
      U
      N
        I
       V
      E
      R
        S
        I
      T
     Y
 
   O
   F
 
  M
 A
  R
 Y
 L
A
 
B  
L  
T    
I    
M   
O    
R    
E     
 
 C 
 O
 U
  N
  T  Y
1
 
9
 
6
 
 6
Synthesis of Combinational Logic
Some general rules:• The combinational part should be driven by primary inputs (through theports) or internal storage elements.• Avoid referencing the same variable in more than one
 always
 behavior.This can cause races, resulting in differences in pre-synthesized andpost-synthesized behavior.• Use only synchronous, resettable FFs in the design.primaryinputsresetclockCOMBINATIONAL LOGICprimaryoutputs
5
 
Programmable Logic DevicesVerilog VIICMPE 4153(11/30/05)
UMBC
U M B C
      U
      N
        I
       V
      E
      R
        S
        I
      T
     Y
 
   O
   F
 
  M
 A
  R
 Y
 L
A
 
B  
L  
T    
I    
M   
O    
R    
E     
 
 C 
 O
 U
  N
  T  Y
1
 
9
 
6
 
 6
Synthesis of Combinational Logic
Some general rules:• Timing constructs are ignored.• Avoid code expressions that perform
 explicit
 Boolean operations on thelogic values "x" and "z".
Commonly Supported Verilog Constructs
• Module declaration• Port modes:
 input
,
 output
 and
 inout
• Port binding by name or position• Parameter declaration• Connectivity nets:
 wire
,
 tri
,
 wand
,
 wor
,
 supply0
 and
 supply1
• Register variables:
 reg
 and
 integer
• Integer types in binary, decimal, octal and hex formats• Scalar and vector nets• Subranges of vector nets on RHS of assignment• Module and primitive instantiation• Continuous assignment• Shift operator
5
 
Programmable Logic DevicesVerilog VIICMPE 4154(11/30/05)
UMBC
U M B C
      U
      N
        I
       V
      E
      R
        S
        I
      T
     Y
 
   O
   F
 
  M
 A
  R
 Y
 L
A
 
B  
L  
T    
I    
M   
O    
R    
E     
 
 C 
 O
 U
  N
  T  Y
1
 
9
 
6
 
 6
Commonly Supported Verilog Constructs
• Conditional and concatenation operators• Arithmetic, bitwise, reduction, logical and relational operatorsProcedural-continuous assignments (
assign
 ...
deassign
)• Procedural block statements (
begin
 and
end
)
case
,
casex
,
casez
,
default
• Branching:
if
,
if ... else
,
disable
 (of procedural block)
for
 loops• Tasks:
task ... endtask
• Functions:
function ... endfunction
Synthesis tools do not support constructs used for transistor/switch leveldescriptions of behavior.Constructs to avoid:• Assignment with a variable used as bit select on LHS• Global variables• case equality, inequality (===, !===)
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

Reward Your Curiosity

Everything you want to read.
Anytime. Anywhere. Any device.
No Commitment. Cancel anytime.
576648e32a3d8b82ca71961b7a986505