Features: 0 - Advanced RISC Architecture
Features: 0 - Advanced RISC Architecture
0
0
130 Powerful Instructions Most Single-clock Cycle Execution 32 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16MHz On-chip 2-cycle Multiplier 0 High Endurance Non-volatile Memory segments 8Kbytes of In-System Self-programmable Flash program memory 512Bytes EEPROM 1Kbyte Internal SRAM Write/Erase Cycles: 10,000 Flash/100,000 EEPROM Data retention: 20 years at 85C/100 years at 25C (1) Optional Boot Code Section with Independent Lock Bits InSystem Programming by On-chip Boot Program True Read-While-Write Operation Programming Lock for Software Security 0 Peripheral Features Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Three PWM Channels 8-channel ADC in TQFP and QFN/MLF package Eight Channels 10-bit Accuracy 6-channel ADC in PDIP package Six Channels 10-bit Accuracy Byte-oriented Two-wire Serial Interface Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator 0 Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby 0 I/O and Packages 23 Programmable I/O Lines 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF 0 Operating Voltages 2.7V - 5.5V (ATmega8L) 4.5V - 5.5V (ATmega8) 0 Speed Grades
8-bit
Rev. 2486ZSAVR02/11
ATmega8(L)
Pin Configurations
(RESET) PC6 1 28
PDIP
PC5 (ADC5/SCL)
2
(RXD) PD0 27
3
(TXD) PD1
(INT0) PD2 (INT1) PD3 (XCK/T0) PD4 VCC GND (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0
4 5 6 7 8 9 10 11 12 13 14
25 24 23 22 21 20 19 18 17 16 15
PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) GND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A)
(I N T 0)
( T X D )
( R X D )
(R E S E T)
(A D C 4/ S D A)
( A D C 3 ) P D 2
(ADC2 ) P P P P P P D D C C C C 1 0 6 5 4 3 PC2
3 3 3 2 2 2 2 2 1 0 9 8 7 6 25 PC1 (ADC1) 23 22 21 20 19 18 17 1 1 1 1 1 0 1 2 3 4 15 P P P P P D D B B B P 6 7 0 1 2 B3 (M ( ( (S O O S/ SI/ A (I (A I C C O O 1 C IN N P A 1 C 0) 1) 1) ) B) 2) 1 6 P B 4 ( M I S O ) (INT1) PD3 1 (XCK/T0) PD4 GND VCC GND VCC 2 3 4 5 6
7 (XTAL2/TOSC2) PB7 8
(INT1) PD3
1 2 3 4 5 6 7 8 9
24
(XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7
PD5
(T1)
(XTAL1/TOSC1) PB6
P P P P P P D D D B B B 5 6 7 0 1 2
( R (I ( ( E N T R S T X X E 0 D D T ) ) ) ) P P P P D D D C 2 1 0 6 3 3 3 2 2 1 0 9 P C 5 2 8 P C 4 2 7 P C 3 2 6 P C 2 2 5
( A D C 3 )
( A D C 2 )
( T 1 )
( ( O A (I C I (A C 1 N IN P A 0) 1) 1) )
(S S/ O C 1 B) 24 23 22 21 20 19 18 17 PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK)
NOTE: The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.
1 1 1 1 1 1 1 9 0 1 2 3 4 5 6
2
2486ZSAVR02/11
ATmega8(L)
Overview
The ATmega8 is a low-power CMOS 8-bit
microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize speed. Figure 1. Block Diagram
XTAL 1 RESET PC0 - PC6 VCC
Block Diagram
power
consumption
ver-sus
processing
PB0 - PB
PORTC DRIVERS/BUFFERS
PORTB DRIVERS
GND
PORTB DIGITAL IN
ADC
TWI ADC
INTERFACE
PROGRAM FLASH
SRAM
INTERNAL OSCILLATO R
INSTRUCTION REGISTER
WATCHDOG TIMER
INSTRUCTION DECODER
CONTROL LINES
AVR CPU
STATUS REGISTER
EEPROM
PROGRAMMING LOGIC
SPI
USART
+ -
COMP. INTERFACE
PORTD DIGITAL IN
PORTD DRIVERS/BUFFERS
PD0 - PD7
3
2486ZSAVR02/11