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74LS175

The document summarizes the key specifications and functionality of the SN54/74LS175 Quad D Flip-Flop integrated circuit. The IC contains four D flip-flops that store input states on the rising edge of a common clock signal. It features individual data inputs and true/complement outputs for each flip-flop, as well as a common master reset input that asynchronously resets all flip-flops. The document provides timing diagrams, logic symbol, and definitions to explain the device operation and parameters.

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Yesenia Rojo
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284 views

74LS175

The document summarizes the key specifications and functionality of the SN54/74LS175 Quad D Flip-Flop integrated circuit. The IC contains four D flip-flops that store input states on the rising edge of a common clock signal. It features individual data inputs and true/complement outputs for each flip-flop, as well as a common master reset input that asynchronously resets all flip-flops. The document provides timing diagrams, logic symbol, and definitions to explain the device operation and parameters.

Uploaded by

Yesenia Rojo
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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QUAD D FLIP-FLOP

The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.

SN54/74LS175

QUAD D FLIP-FLOP
LOW POWER SCHOTTKY

Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Clock to Output Delays of 30 ns Asynchronous Common Reset True and Complement Output Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1

J SUFFIX CERAMIC CASE 620-09

16 1

N SUFFIX PLASTIC CASE 648-08

1 MR

2 Q0

3 Q0

4 D0

5 D1

6 Q1

7 Q1

8 GND LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L.
16 1

PIN NAMES

D SUFFIX SOIC CASE 751B-03

D0 D3 CP MR Q0 Q3 Q0 Q 3

Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input True Outputs (Note b) Complemented Outputs (Note b)

0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L.

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.

LOGIC SYMBOL
4 5 12 13

LOGIC DIAGRAM
MR CP D3
1 9 13

D2
12

D1
5

D0
4

CP

D0

D1

D2

D3

D Q CP Q CD
14 15

D Q CP Q CD
11 10

D Q CP Q CD
6 7

D Q CP Q CD
3 2

MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3

11

10 14 15

VCC = PIN 16 Q3 Q3 GND = PIN 8 = PIN NUMBERS

Q2 Q2

Q1Q1

Q0 Q0

VCC = PIN 16 GND = PIN 8

FAST AND LS TTL DATA 5-1

SN54/74LS175
FUNCTIONAL DESCRIPTION The LS175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW to HIGH Clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The LS175 is useful for general logic applications where a common Master Reset and Clock are acceptable.

TRUTH TABLE
Inputs (t = n, MR = H) D L H Outputs (t = n+1) Note 1 Q L H Q H L

Note 1: t = n + 1 indicates conditions after next clock.

GUARANTEED OPERATING RANGES


Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 0.4 4.0 8.0 Unit V C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)


Limits S b l Symbol VIH VIL VIK VOH P Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current 20 0.4 100 18 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 0.65 3.5 0.8 1.5 V V Min 2.0 0.7 V Typ Max U i Unit V T Test C Conditions di i Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input p LOW Voltage g for All Inputs VCC = MIN, IIN = 18 mA , IOH = MAX, , VIN = VIH VCC = MIN, or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA 5-2

SN54/74LS175
AC CHARACTERISTICS (TA = 25C)
Limits S b l Symbol fMAX tPLH tPHL tPLH tPHL P Parameter Maximum Input Clock Frequency Propagation Delay, MR to Output Propagation Delay, Clock to Output Min 30 Typ 40 20 20 13 16 30 30 25 25 Max U i Unit MHz ns ns VCC = 5.0 50V CL = 15 pF T Test C Conditions di i

AC SETUP REQUIREMENTS (TA = 25C)


Limits S b l Symbol tW ts th trec P Parameter Clock or MR Pulse Width Data Setup Time Data Hold Time Recovery Time Min 20 20 5.0 25 Typ Max U i Unit ns ns ns ns VCC = 5 5.0 0V T C di i Test Conditions

AC WAVEFORMS
1/fmax CP 1.3 V ts(H) D * 1.3 V t th(H) s(L) 1.3 V tPLH Q Q 1.3 V tPHL 1.3 V

tw 1.3 V th(L) 1.3 V tPHL 1.3 V tPLH 1.3 V Q CP Q tPLH 1.3 V 1.3 V tPHL 1.3 V MR 1.3 V tW 1.3 V trec 1.3 V 1.3 V

*The shaded areas indicate when the input is permitted to *change for predictable output performance.

Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock

Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time

DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.

FAST AND LS TTL DATA 5-3

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