2.5V To 6.0V Micropower CMOS Op Amp: Features

2009 Microchip Technology Inc.
DS11177F-page 1
MCP606/7/8/9
Features
Low Input Offset Voltage: 250 V (maximum)
Rail-to-Rail Output
Low Input Bias Current: 80 pA (maximum at
+85C)
Low Quiescent Current: 25 A (maximum)
Power Supply Voltage: 2.5V to 6.0V
Unity-Gain Stable
Chip Select (CS) Capability: MCP608
Industrial Temperature Range: -40C to +85C
No Phase Reversal
Available in Single, Dual and Quad Packages
Typical Applications
Battery Power Instruments
High-Impedance Applications
Strain Gauges
Medical Instruments
Test Equipment
Design Aids
SPICE Macro Models
FilterLab
Software
Mindi Circuit Designer & Simulator
Analog Demonstration and Evaluation Boards
Application Notes
Typical Application
Description
The MCP606/7/8/9 family of operational amplifiers (op
amps) from Microchip Technology Inc. are unity-gain
stable with low offset voltage (250 V, maximum).
Performance characteristics include rail-to-rail output
swing capability and low input bias current (80 pA at
+85C, maximum). These features make this family of
op amps well suited for single-supply, precision,
high-impedance, battery-powered applications.
The single is available in standard 8-lead PDIP, SOIC
and TSSOP packages, as well as in a SOT-23-5
package. The single MCP608 with Chip Select (CS) is
offered in the standard 8-lead PDIP, SOIC and TSSOP
packages. The dual MCP607 is offered in the standard
8-lead PDIP, SOIC and TSSOP packages. Finally, the
quad MCP609 is offered in the standard 14-lead PDIP,
SOIC and TSSOP packages. All devices are fully
specified from -40C to +85C, with power supplies
from 2.5V to 6.0V.
Package Types
Low-Side Battery Current Sensor
R
F
To Load
2.5V
R
G
5 k 50 k
To Load
V
OUT
R
SEN
10 (V
LM
)
(V
LP
)
I
L
to
6.0V
V
OUT
V
LM
I +
L
R
SEN
R
F
R
G
( ) =
MCP606
V
IN
+
V
IN
V
SS
V
DD
V
OUT
1
2
3
4
8
7
6
5 NC
NC NC
PDIP, SOIC,TSSOP
PDIP, SOIC,TSSOP PDIP, SOIC,TSSOP
PDIP, SOIC,TSSOP
SOT-23-5
V
IN
+
V
SS
V
IN
1
2
3
5
4
V
DD
V
OUT
V
INA
+
V
INA
V
SS
V
OUTB
V
INB
1
2
3
4
8
7
6
5 V
INB
+
V
DD
V
OUTA
V
IN
+
V
IN
V
SS
V
DD
V
OUT
1
2
3
4
8
7
6
5 NC
CS NC
V
INA
+
V
INA
V
DD
V
IND
V
IND
+
1
2
3
4
14
13
12
11 V
SS
V
OUTD
V
OUTA
V
INB
V
INB
+
V
OUTB
V
INC
+
V
INC
5
6
7
10
9
8 V
OUTC
MCP606 MCP606
MCP607 MCP608
MCP609
2.5V to 6.0V Micropower CMOS Op Amp
MCP606/7/8/9
DS11177F-page 2 2009 Microchip Technology Inc.
NOTES:
2009 Microchip Technology Inc. DS11177F-page 3
MCP606/7/8/9
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings
V
DD
V
SS
........................................................................7.0V
Current at Input Pins ....................................................2 mA
Analog Inputs (V
IN
+, V
IN
) ........ V
SS
1.0V to V
DD
+1.0V
All Other Inputs and Outputs ......... V
SS
0.3V to V
DD
+0.3V
Difference Input Voltage ...................................... |V
DD
V
SS
|
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ............................30 mA
Storage Temperature .................................65 C to +150 C
Maximum J unction Temperature (T
J
)........................ .+150 C
ESD Protection On All Pins (HBM; MM).............. 3 kV; 200V
Notice: Stresses above those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
See Section 4.1.2 Input Voltage and Current Limits.
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, V
DD
=+2.5V to +5.5V, V
SS
=GND, T
A
=+25C, V
CM
=V
DD
/2,
V
OUT
V
DD
/2, V
L
=V
DD
/2, R
L
=100 k to V
L
, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage V
OS
-250 +250 V
Input Offset Drift with Temperature V
OS
/T
A
1.8 V/C T
A
=-40C to +85C
Power Supply Rejection Ratio PSRR 80 93 dB
Input Bias Current and Impedance
Input Bias Current I
B
1 pA
At Temperature I
B
80 pA T
A
=+85C
Input Offset Bias Current I
OS
1 pA
Common Mode Input Impedance Z
CM
10
13
||6 ||pF
Differential Input Impedance Z
DIFF
10
13
||6 ||pF
Common Mode
Common Mode Input Range V
CMR
V
SS
0.3 V
DD
1.1 V CMRR 75 dB
Common Mode Rejection Ratio CMRR 75 91 dB V
DD
=5V, V
CM
=-0.3V to 3.9V
Open-Loop Gain
DC Open-Loop Gain
(Large-signal)
A
OL
105 121 dB R
L
=25 k to V
L
,
V
OUT
=50 mV to V
DD
50 mV
DC Open-Loop Gain
(Large-signal)
A
OL
100 118 dB R
L
=5 k to V
L
,
V
OUT
=0.1V to V
DD
0.1V
Output
Maximum Output Voltage Swing V
OL
, V
OH
V
SS
+15 V
DD
20 mV R
L
=25 k to V
L
,
0.5V input overdrive
V
OL
, V
OH
V
SS
+45 V
DD
60 mV R
L
=5 k to V
L
,
0.5V input overdrive
Linear Output Voltage Range V
OUT
V
SS
+50 V
DD
50 mV R
L
=25 k to V
L
,
A
OL
105 dB
V
OUT
V
SS
+100 V
DD
100 mV R
L
=5 k to V
L
,
A
OL
100 dB
Output Short Circuit Current I
SC
7 mA V
DD
=2.5V
I
SC
17 mA V
DD
=5.5V
Power Supply
Supply Voltage V
DD
2.5 6.0 V
Quiescent Current per Amplifier I
Q
18.7 25 A I
O
=0
Note 1: All parts with date codes November 2007 and later have been screened to ensure operation at V
DD
=6.0V. However,
the other minimum and maximum specifications are measured at 2.5V and 5.5V.
MCP606/7/8/9
AC CHARACTERISTICS
MCP608 CHIP SELECT CHARACTERISTICS
FIGURE 1-1: Timing Diagram for the CS
Pin on the MCP608.
DD
=+2.5V to +5.5V, V
SS
=GND, T
A
=+25C, V
CM
=V
DD
/2,
V
OUT
V
DD
/2, V
L
=V
DD
/2, R
L
=100 k to V
L
and C
L
=60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
AC Response
Gain Bandwidth Product GBWP 155 kHz
Phase Margin PM 62 G =+1 V/V
Slew Rate SR 0.08 V/s
Noise
Input Noise Voltage E
ni
2.8 V
P-P
f =0.1 Hz to 10 Hz
Input Noise Voltage Density e
ni
38 nV/Hz f =1 kHz
Input Noise Current Density i
ni
3 fA/Hz f =1 kHz
DD
=+2.5V to +5.5V, V
SS
=GND, T
A
=+25C, V
CM
=V
DD
/2,
V
OUT
V
DD
/2, V
L
=V
DD
/2, R
L
=100 k to V
L
and C
L
=60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
CS Low Specifications
CS Logic Threshold, Low V
IL
V
SS
0.2 V
DD
V
CS Input Current, Low I
CSL
-0.1 0.01 A CS =0.2V
DD
CS High Specifications
CS Logic Threshold, High V
IH
0.8 V
DD
V
DD
V
CS Input Current, High I
CSH
0.01 0.1 A CS =V
DD
CS Input High, GND Current I
SS
-2 -0.05 A CS =V
DD
Amplifier Output Leakage, CS High I
O(LEAK)
10 nA CS =V
DD
CS Dynamic Specifications
CS Low to Amplifier Output Turn-on Time t
ON
9 100 s CS =0.2V
DD
to V
OUT
=0.9 V
DD
/2,
G =+1 V/V, R
L
=1 k to V
SS
CS High to Amplifier Output Hi-Z t
OFF
0.1 s CS =0.8V
DD
to V
OUT
=0.1 V
DD
/2,
G =+1 V/V, R
L
=1 k to V
SS
CS Hysteresis V
HYST
0.6 V V
DD
=5.0V
CS
V
OUT
I
SS
I
CS
V
IL
V
IH
t
ON
t
OFF
-50 nA -50 nA
-18.7 A
-50 nA -50 nA
Hi-Z Hi-Z
(typical)
(typical)
(typical)
(typical) (typical)
MCP606/7/8/9
TEMPERATURE CHARACTERISTICS
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.5 Supply Bypass.

FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.

FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.
DD
=+2.5V to +5.5V and V
SS
=GND.
Temperature Ranges
Specified Temperature Range T
A
-40 +85 C
Operating Temperature Range T
A
-40 +125 C Note 1
Storage Temperature Range T
A
-65 +150 C
Thermal Package Resistances
Thermal Resistance, 5L-SOT23
J A
220.7 C/W
Thermal Resistance, 8L-PDIP
J A
89.3 C/W
Thermal Resistance, 8L-SOIC
J A
149.5 C/W
Thermal Resistance, 8L-TSSOP
J A
139 C/W
Thermal Resistance, 14L-PDIP
J A
70 C/W
Thermal Resistance, 14L-SOIC
J A
95.3 C/W
Thermal Resistance, 14L-TSSOP
J A
100 C/W
Note 1: The MCP606/7/8/9 operate over this extended temperature range, but with reduced performance. In any case, the
J unction Temperature (T
J
) must not exceed the Absolute Maximum specification of +150C.
V
DD
R
G
R
F
R
N
V
OUT
V
IN
V
DD
/2
1 F
C
L
R
L
V
L
0.1 F
MCP60X
V
DD
R
G
R
F
R
N
V
OUT
V
DD
/2
V
IN
1 F
C
L
R
L
V
L
0.1 F
MCP60X
MCP606/7/8/9
NOTES:
MCP606/7/8/9
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, V
DD
=+2.5V to +5.5V, V
SS
=GND, T
A
=+25C, V
CM
=V
DD
/2, V
OUT
V
DD
/2,
V
L
=V
DD
/2, R
L
=100 k to V
L
, C
L
=60 pF, and CS is tied low.
FIGURE 2-1: Input Offset Voltage at
V
DD
= 5.5V.
FIGURE 2-2: Input Offset Voltage at
V
DD
= 2.5V.
FIGURE 2-3: Quiescent Current vs.
Power Supply Voltage.

FIGURE 2-4: Input Offset Voltage Drift
Magnitude at V
DD
= 5.5V.

FIGURE 2-5: Input Offset Voltage Drift
Magnitude at V
DD
= 2.5V.
FIGURE 2-6: Quiescent Current vs.
Ambient Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
-
2
5
0
-
2
0
0
-
1
5
0
-
1
0
0
-
5
0 0
5
0
1
0
0
1
5
0
2
0
0
2
5
0
Input Offset Voltage (V)
P
e
r
c
e
n
t
a
g
e

o
f

O
c
c
u
r
a
n
c
e
s

(

)
1200 Samples
V
DD
= 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
-
2
5
0
-
2
0
0
-
1
5
0
-
1
0
0
-
5
0 0
5
0
1
0
0
1
5
0
2
0
0
2
5
0
Input Offset Voltage (V)
P
e
r
c
e
n
t
a
g
e

o
f

O
c
c
u
r
a
n
c
e
s

(

)
1200 Samples
V
DD
= 2.5V
0
2
4
6
8
10
12
14
16
18
20
22
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Q
u
i
e
s
c
e
n
t

C
u
r
r
e
n
t

p
e
r

A
m
p
l
i
f
i
e
r

(
A
)
T
A
= +85C
T
A
= +25C
T
A
= -40C
0%
2%
4%
6%
8%
10%
12%
14%
16%
-8 -6 -4 -2 0 2 4 6 8
Input Offset Voltage Drift (V/C)
P
e
r
c
e
n
t
a
g
e

o
f

O
c
c
u
r
a
n
c
e
s
206 Samples
V
DD
= 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-8 -6 -4 -2 0 2 4 6 8
Input Offset Voltage Drift (V/C)
P
e
r
c
e
n
t
a
g
e

o
f

O
c
c
u
r
a
n
c
e
s
206 Samples
V
DD
= 2.5V
12
14
16
18
20
22
24
-50 -25 0 25 50 75 100
Ambient Temperature (C)
Q
u
i
e
s
c
e
n
t

C
u
r
r
e
n
t
p
e
r

A
m
p
l
i
f
i
e
r

(
A
)
V
DD
= 5.5V
V
DD
= 2.5V
MCP606/7/8/9
DD
=+2.5V to +5.5V, V
SS
=GND, T
A
=+25C, V
CM
=V
DD
/2, V
OUT
V
DD
/2,
V
L
=V
DD
/2, R
L
=100 k to V
L
, C
L
FIGURE 2-7: Input Offset Voltage vs.
Ambient Temperature.

FIGURE 2-8: Open-Loop Gain and Phase
vs. Frequency.
FIGURE 2-9: Channel-to-Channel
Separation (MCP607 and MCP609 only).
FIGURE 2-10: Input Offset Voltage vs.
Common Mode Input Voltage.
FIGURE 2-11: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.

FIGURE 2-12: Input Noise Voltage Density
vs. Frequency.
0
100
200
300
400
500
-50 -25 0 25 50 75 100
I
n
p
u
t

O
f
f
s
e
t

V
o
l
t
a
g
e

(
V
)
V
DD
=2.5V
V
DD
= 5.5V
Representative Part
-20
0
20
40
60
80
100
120
Frequency (Hz)
O
p
e
n
-
L
o
o
p

G
a
i
n

(
d
B
)
-225
-180
-135
-90
-45
0
45
90
O
p
e
n
-
L
o
o
p

P
h
a
s
e

(
)
Gain
Phase
R
L
= 25 k
0.01 1 0.1 10 1k 100 10k 1M 100k
80
90
100
110
120
130
140
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
C
h
a
n
n
e
l

t
o

C
h
a
n
n
e
l

S
e
p
a
r
a
t
i
o
n

(
d
B
)
Referred to Input
100 100k 10k 1k
-20
0
20
40
60
80
100
120
-
0
.
5
0
.
0
0
.
5
1
.
0
1
.
5
2
.
0
2
.
5
3
.
0
3
.
5
4
.
0
4
.
5
5
.
0
Common Mode Input Voltage (V)
I
n
p
u
t

O
f
f
s
e
t

V
o
l
t
a
g
e

(
V
)
T
A
= +85C
T
A
= +25C
T
A
= -40C
V
DD
= 5.5V
0
20
40
60
80
100
120
140
160
-50 -25 0 25 50 75 100
G
a
i
n

B
a
n
d
w
i
d
t
h

P
r
o
d
u
c
t
(
k
H
z
)
0
10
20
30
40
50
60
70
80
P
h
a
s
e

M
a
r
g
i
n

(
)
Phase Margin
GBWP
V
DD
= 5.0V
10
100
1000
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
I
n
p
u
t

N
o
i
s
e

V
o
l
t
a
g
e

D
e
n
s
i
t
y
(
n
V
/
H
z
)
0.1 1 10 100 1k 10k 100k
MCP606/7/8/9
DD
=+2.5V to +5.5V, V
SS
=GND, T
A
=+25C, V
CM
=V
DD
/2, V
OUT
V
DD
/2,
V
L
=V
DD
/2, R
L
=100 k to V
L
, C
L
FIGURE 2-13: Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-14: DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-15: CMRR, PSRR vs.
Frequency.
FIGURE 2-16: Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
FIGURE 2-17: DC Open-Loop Gain vs.
Power Supply Voltage.
FIGURE 2-18: CMRR, PSRR vs. Ambient
Temperature.
0.1
1
10
100
25 30 35 40 45 50 55 60 65 70 75 80 85
I
n
p
u
t

B
i
a
s

a
n
d

O
f
f
s
e
t

C
u
r
r
e
n
t
s
(
p
A
)
I
B
| I
OS
|
V
DD
= 5.5V
V
CM
= V
DD
100
105
110
115
120
125
130
135
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance ()
D
C

O
p
e
n
-
L
o
o
p

G
a
i
n

(
d
B
)
V
DD
= 2.5V
V
DD
= 5.5V
100 100k 10k 1k
0
20
40
60
80
100
120
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04
Frequency (Hz)
C
M
R
R

a
n
d

P
S
R
R

(
d
B
)
PSRR-
PSRR+
CMRR
0.1 1 10 100 1k 10k
-10
0
10
20
30
40
50
60
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
I
n
p
u
t

B
i
a
s

a
n
d

O
f
f
s
e
t

C
u
r
r
e
n
t
s
(
p
A
)
I
B
I
OS
T
A
= 85C
V
DD
= 5.5V
90
100
110
120
130
140
150
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
D
C

O
p
e
n
-
L
o
o
p

G
a
i
n

(
d
B
) R
L
= 25 k
75
80
85
90
95
100
-50 -25 0 25 50 75 100
C
M
R
R

a
n
d

P
S
R
R

(
d
B
)
CMRR
PSRR
MCP606/7/8/9
DD
=+2.5V to +5.5V, V
SS
=GND, T
A
=+25C, V
CM
=V
DD
/2, V
OUT
V
DD
/2,
V
L
=V
DD
/2, R
L
=100 k to V
L
, C
L
FIGURE 2-19: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-20: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-21: Slew Rate vs. Ambient
Temperature.

FIGURE 2-22: Output Voltage Headroom
vs. Ambient Temperature at R
L
= 5 k.
FIGURE 2-23: The MCP606/7/8/9 Show
No Phase Reversal.
FIGURE 2-24: Output Short Circuit Current
Magnitude vs. Ambient Temperature.
1
10
100
1000
0.1 1 10 100
Output Current (mA)
O
u
t
p
u
t

V
o
l
t
a
g
e

H
e
a
d
r
o
o
m
(
m
V
)
V
DD
= 2.5V
V
DD
= 5.5V
V
DD
- V
OH
V
OL
- V
SS
0.1
1
10
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
M
a
x
i
m
u
m

O
u
t
p
u
t

V
o
l
t
a
g
e

S
w
i
n
g

(
V
)
V
DD
= 2.5V
100 100k 10k 1k
V
DD
= 5.5V
0.00
0.02
0.04
0.06
0.08
0.10
0.12
-50 -25 0 25 50 75 100
S
l
e
w

R
a
t
e

(
V
/
s
)
Low to High
High to Low
0
5
10
15
20
25
30
35
40
-50 -25 0 25 50 75 100
O
u
t
p
u
t

V
o
l
t
a
g
e

H
e
a
d
r
o
o
m
(
m
V
)
R
L
= 5 k
V
DD
= 5.5V
V
DD
= 2.5V
V
DD
- V
OH
V
OL
- V
SS
-1
0
1
2
3
4
5
6
Time (100 s/div)
I
n
p
u
t

a
n
d

O
u
t
p
u
t

V
o
l
t
a
g
e
s

(
V
)
V
OUT
V
IN
G = +2 V/V
V
DD
= 5.0V
0
5
10
15
20
25
-50 -25 0 25 50 75 100
O
u
t
p
u
t

S
h
o
r
t

C
i
r
c
u
i
t

C
u
r
r
e
n
t

M
a
g
n
i
t
u
d
e

(
m
A
)
+I
SC
, V
DD
= 2.5V
| -I
SC
|, V
DD
= 2.5V
+I
SC
, V
DD
= 5.5V
| -I
SC
|, V
DD
= 5.5V
MCP606/7/8/9
DD
=+2.5V to +5.5V, V
SS
=GND, T
A
=+25C, V
CM
=V
DD
/2, V
OUT
V
DD
/2,
V
L
=V
DD
/2, R
L
=100 k to V
L
, C
L
FIGURE 2-25: Large-signal, Non-inverting
Pulse Response.
FIGURE 2-26: Small-signal, Non-inverting
Pulse Response.
FIGURE 2-27: Chip Select (CS) Hysteresis
(MCP608 only).
FIGURE 2-28: Large-signal, Inverting
Pulse Response.
FIGURE 2-29: Small-signal, Inverting Pulse
Response.
FIGURE 2-30: Amplifier Output Response
Times vs. Chip Select (CS) Pulse (MCP608
only).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (50 s/div)
O
u
t
p
u
t

V
o
l
t
g
e

(
V
)
V
DD
= 5.0V
Time (50 s/div)
O
u
t
p
u
t

V
o
l
t
a
g
e

(
2
0

m
V
/
d
i
v
)
V
DD
= 5.0V
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CS Input Voltage (V)
I
n
t
e
r
n
a
l

C
S

S
w
i
t
c
h

O
u
t
p
u
t

(
V
)
Amplifier Output Active
Amplifier Output Hi-Z
V
DD
= 5.0V
Hysteresis
CS Input
High to Low
CS Input
Low to High
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (50 s/div)
O
u
t
p
u
t

V
o
l
t
a
g
e

(
V
)
V
DD
= 5.0V
Time (50 s/div)
O
u
t
p
u
t

V
o
l
t
a
g
e

(
2
0

m
V
/
d
i
v
)
R
L
= 25 k
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (5 s/div)
O
u
t
p
u
t

V
o
l
t
a
g
e

(
V
)
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
C
h
i
p

S
e
l
e
c
t

V
o
l
t
a
g
e

(
V
)
CS
V
OUT
Output
Hi-Z
Output
Hi-Z
Output Enabled
G = +1 V/V
R
L
= 1 k to V
SS
MCP606/7/8/9
DD
=+2.5V to +5.5V, V
SS
=GND, T
A
=+25C, V
CM
=V
DD
/2, V
OUT
V
DD
/2,
V
L
=V
DD
/2, R
L
=100 k to V
L
, C
L
FIGURE 2-31: Measured Input Current vs.
Input Voltage (below V
SS
).
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
I
n
p
u
t

C
u
r
r
e
n
t

M
a
g
n
i
t
u
d
e

(
A
)
+125C
+85C
+25C
-40C
10m
1m
100
10
1
100n
10n
1n
100p
10p
1p
MCP606/7/8/9
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3 Chip Select Digital Input
The Chip Select (CS) pin is a Schmitt-triggered, CMOS
logic input. It is used to place the MCP608 op amp in a
Low-power mode, with the output(s) in a Hi-Z state.
3.4 Power Supply Pins
The positive power supply pin (V
DD
) is 2.5V to 5.5V
higher than the negative power supply pin (V
SS
). For
normal operation, the output pins are at voltages
between V
SS
and V
DD
; while the input pins are at
voltages between V
SS
0.3V and V
DD
+0.3V.
Typically, these parts are used in a single-supply
(positive) configuration. In this case, V
SS
is connected
to ground and V
DD
is connected to the supply. V
DD
will
need bypass capacitors .
MCP606
MCP607 MCP608 MCP609 Symbol Description
PDIP, SOIC,
TSSOP
SOT-23-5
6 1 1 6 1 V
OUT
, V
OUTA
Output (op amp A)
2 4 2 2 2 V
IN
, V
INA
Inverting Input (op amp A)
3 3 3 3 3 V
IN
+, V
INA
+ Non-inverting Input (op amp A)
7 5 8 7 4 V
DD
Positive Power Supply
5 5 V
INB
+ Non-inverting Input (op amp B)
6 6 V
INB
Inverting Input (op amp B)
7 7 V
OUTB
Output (op amp B)
8 V
OUTC
Output (op amp B)
9 V
INC
Inverting Input (op amp C)
10 V
INC
+ Non-inverting Input (op amp C)
4 2 4 4 11 V
SS
Negative Power Supply
12 V
IND
+ Non-inverting Input (op amp D)
13 V
IND
Inverting Input (op amp D)
14 V
OUTD
Output (op amp D)
8 CS Chip Select
1, 5, 8 1, 5 NC No Internal Connection
MCP606/7/8/9
NOTES:
MCP606/7/8/9
4.0 APPLICATIONS INFORMATION
The MCP606/7/8/9 family of op amps is manufactured
using Microchips state-of-the-art CMOS process
These op amps are unity-gain stable and suitable for a
wide range of general purpose applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The MCP606/7/8/9 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-23 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (I
B
). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
SS
. They also clamp any voltages that go too far
above V
DD
; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the V
IN
+and V
IN
pins (see
Absolute Maximum Ratings at the beginning of
Section 1.0 Electrical Characteristics). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(V
IN
+and V
IN
) from going too far below ground, and
the resistors R
1
and R
2
limit the possible current drawn
out of the input pins. Diodes D
1
and D
2
prevent the
input pins (V
IN
+and V
IN
) from going too far above
V
DD
, and dump any currents onto V
DD
. When
implemented as shown, resistors R
1
and R
2
also limit
the current through D
1
and D
2
.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors R
1
and R
2
. In this case, current through the
diodes D
1
and D
2
needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
IN
+and
V
IN
) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (V
CM
) is below
ground (V
SS
); see Figure 2-31. Applications that are
high impedance may need to limit the useable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of the MCP606/7/8/9 op amps use a
PMOS input stage. It operates at low common mode
input voltage (V
CM
), including ground. WIth this
topology, the device operates with V
CM
up to V
DD
1.1V
and 0.3V below V
SS
.
Figure 4-3 shows a unity gain buffer. Since V
OUT
is the
same voltage as the inverting input, V
OUT
must be kept
below V
DD
1.2V for correct operation.

FIGURE 4-3: Unity Gain Buffer has a
Limited V
OUT
Range.
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
V
1
R
1
V
DD
D
1
R
1
>
V
SS
(minimum expected V
1
)
2 mA
R
2
>
V
SS
(minimum expected V
2
)
2 mA
V
2
R
2
D
2
R
3
MCP60X
V
OUT
+
V
IN
MCP60X
MCP606/7/8/9
4.2 Rail-to-Rail Output
There are two specifications that describe the
output-swing capability of the MCP606/7/8/9 family of
op amps. The first specification (Maximum Output
Voltage Swing) defines the absolute maximum swing
that can be achieved under the specified load
conditions. For instance, the output voltage swings to
within 15 mV of the negative rail with a 25 k load to
V
DD
/2. Figure 2-23 shows how the output voltage is
limited when the input goes beyond the linear region of
operation.
The second specification that describes the output-
swing capability of these amplifiers (Linear Output
Voltage Range) defines the maximum output swing that
can be achieved while the amplifier still operates in its
linear region. To verify linear operation in this range, the
large-signal DC Open-Loop Gain (A
OL
) is measured at
points inside the supply rails. The measurement must
meet the specified A
OL
conditions in the specification
table.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage-feedback op amps. As the load
capacitance increases, the feedback loops phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain-peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G =+1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., >60 pF when G =+1), a small series
resistor at the output (R
ISO
in Figure 4-4) improves the
feedback loops phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.

FIGURE 4-4: Output Resistor, R
ISO

stabilizes large capacitive loads.
Figure 4-5 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuits noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
=+2 V/V).

FIGURE 4-5: Recommended R
ISO
Values
for Capacitive Loads.
After selecting R
ISO
for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
s value until the
response is reasonable. Bench evaluation and simula-
tions with the MCP606/7/8/9 SPICE macro model are
helpful.
4.4 MCP608 Chip Select
The MCP608 is a single op amp with Chip Select (CS).
When CS is pulled high, the supply current drops to
50 nA (typical) and flows through the CS pin to V
SS
.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 M (typical)
pull-down resistor connected to V
SS
, so it will go low if
the CS pins is left floating. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
4.5 Supply Bypass
With this family of operational amplifiers, the power
supply pin (V
DD
for single-supply) should have a local
bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 F or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other nearby analog parts.
V
IN
R
ISO
V
OUT
C
L
MCP60X
100
1000
10000
10 100 1000 10000
Normalized Load Capacitance; C
L
/G
N
(F)
R
e
c
o
m
m
e
n
d
e
d

R
I
S
O

(
)
10p 10n 1n 100p
100
10k
1k
G
N
= +1
G
N
= +2
G
N
+4
MCP606/7/8/9
4.6 Unused Op Amps
An unused op amp in a quad package (MCP609)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-6: Unused Op Amps.
4.7 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
12
. A 5V difference would
cause 5pA of current to flow, which is greater than the
MCP606/7/8/9 familys bias current at +25C (1pA,
typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in Figure 4-7.
FIGURE 4-7: Example Guard Ring Layout
for Inverting Gain.
1. Non-inverting Gain and Unity-gain Buffer:
a) Connect the non-inverting pin (V
IN
+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (V
IN
). This biases the guard ring to the
common mode input voltage.
2. Inverting Gain and Transimpedance Gain
(convert current to voltage, such as photo
detectors) amplifiers:
a) Connect the guard ring to the non-inverting
input pin (V
IN
+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., V
DD
/2 or ground).
b) Connect the inverting pin (V
IN
) to the input
with a wire that does not touch the PCB
surface.
4.8 Application Circuits
4.8.1 LOW-SIDE BATTERY CURRENT
SENSOR
The MCP606/7/8/9 op amps can be used to sense the
load current on the low-side of a battery using the
circuit in Figure 4-8. In this circuit, the current from the
power supply (minus the current required to power the
MCP606) flows through a sense resistor (R
SEN
), which
converts it to voltage. This is gained by the the amplifier
and resistors, R
G
and R
F
. Since the non-inverting input
of the amplifier is at the loads negative supply (V
LM
),
the gain from R
SEN
to V
OUT
is R
F
/R
G
.

FIGURE 4-8: Low Side Battery Current
Sensor.
Since the input bias current and input offset voltage of
the MCP606 are low, and the input is capable of
swinging below ground, there is very little error
generated by the amplifier. The quiescent current is
very low, which helps conserve battery power. The
rail-to-rail output makes it possible to read very low
currents.
V
DD
V
DD
R
1
R
2
V
DD
V
REF
V
REF
V
DD
R
2
R
1
R
2
+
------------------- =
MCP609 (A) MCP609 (B)
Guard Ring
V
SS
V
IN
- V
IN
+
V
OUT
V
LM
I +
L
R
SEN
R
F
R
G
( ) =
R
F
To Load
2.5V
R
G
5 k 50 k
To Load
V
OUT
R
SEN
10 (V
LM
)
(V
LP
)
I
L
to
6.0V
MCP606
MCP606/7/8/9
4.8.2 PHOTODIODE AMPLIFIERS
Sensors that produce an output current and have high
output impedance can be connected to a
transimpedance amplifier. The transimpedance
amplifier converts the current into voltage. Photodiodes
are one sensor that produce an output current.
The key op amp characteristics that are needed for
these circuits are: low input offset voltage, low input
bias current, high input impedance and an input
common mode range that includes ground. The low
input offset voltage and low input bias current support
a very low voltage drop across the photodiode; this
gives the best photodiode linearity. Since the
photodiode is biased at ground, the op amps input
needs to function well both above and below ground.
4.8.2.1 Photo-Voltaic Mode
Figure 4-9 shows a transimpedance amplifier with a
photodiode (D
1
) biased in the Photo-voltaic mode (0V
across D
1
), which is used for precision photodiode
sensing.
As light impinges on D
1
, charge is generated, causing
a current to flow in the reverse bias direction of D
1
. The
op amps negative feedback forces the voltage across
the D
1
to be nearly 0V. Resistor R
2
converts the current
into voltage. Capacitor C
2
limits the bandwidth and
helps stabilize the circuit when D
1
s junction
capacitance is large.
FIGURE 4-9: Photodiode (in Photo-voltaic
mode) and Transimpedance Amplifier.
4.8.2.2 Photo-Conductive Mode
Figure 4-9 shows a transimpedance amplifier with a
photodiode (D
1
) biased in the Photo-conductive mode
(D
1
is reverse biased), which is used for high-speed
applications.
As light impinges on D
1
, charge is generated, causing
a current to flow in the reverse bias direction of D
1
.
Placing a negative bias on D
1
significantly reduces its
junction capacitance, which allows the circuit to
operate at a much higher speed. This reverse bias also
increases the dark current and current noise, however.
Resistor R
2
converts the current into voltage. Capacitor
C
2
limits the bandwidth and helps stabilize the circuit
when D
1
s junction capacitance is large.

FIGURE 4-10: Photodiode (in Photo-
conductive mode) and Transimpedance
Amplifier.
4.8.3 TWO OP AMP INSTRUMENTATION
AMPLIFIER
The two op amp instrumentation amplifier shown in
Figure 4-11 serves the function of taking the difference
of two input voltages, level-shifting it and gaining it to
the output. This configuration is best suited for higher
gains (i.e., gain >3 V/V). The reference voltage (V
REF
)
is typically at mid-supply (V
DD
/2) in a single-supply
environment.

FIGURE 4-11: Two Op Amp
Instrumentation Amplifier.
The key specifications that make the MCP606/7/8/9
family appropriate for this application circuit are low
input bias current, low offset voltage and high
common-mode rejection.
V
OUT
I
D1
R
2
=
R
2
D
1
V
OUT
Light
C
2
V
DD
I
D1
MCP606
V
OUT
I
D1
R
2
=
R
2
D
1
V
OUT
Light
C
2
V
DD
I
D1
VB
V
B
0 <
MCP606
V
OUT
V
1
V
2
( ) 1
R
1
R
2
------
2R
1
R
G
---------- + +

V
REF
+ =
R
2
R
1
V
OUT
V
2
V
REF
R
1
R
2
V
1
R
G

MCP607

MCP607
MCP606/7/8/9
4.8.4 THREE OP AMP
INSTRUMENTATION AMPLIFIER
A classic, three op amp instrumentation amplifier is
illustrated in Figure 4-12. The two input op amps
provide differential signal gain and a common mode
gain of +1. The output op amp is a difference amplifier,
which converts its input signal from differential to a sin-
gle ended output; it rejects common mode signals at its
input. The gain of this circuit is simply adjusted with one
resistor (R
G
). The reference voltage (V
REF
) is typically
referenced to mid-supply (V
DD
/2) in single-supply
applications.

FIGURE 4-12: Three Op Amp
Instrumentation Amplifier.
4.8.5 PRECISION GAIN WITH GOOD
LOAD ISOLATION
In Figure 4-13, the MCP606 op amps, R
1
and R
2
provide a high gain to the input signal (V
IN
). The
MCP606s low offset voltage makes this an accurate
circuit.
The MCP601 is configured as a unity-gain buffer. It
isolates the MCP606s output from the load, increasing
the high-gain stages precision. Since the MCP601 has
a higher output current, with the two amplifiers being
housed in separate packages, there is minimal change
in the MCP606s offset voltage due to loading effect.

FIGURE 4-13: Precision Gain with Good
Load Isolation.
V
OUT
V
1
V
2
( ) 1
2R
2
R
G
--------- +

R
4
R
3
------

V
REF
+ =
R
2
V
REF
V
1
R
4
R
3
R
2
R
G
V
OUT
V
2
R
4
R
3

MCP607

MCP607
MCP606
V
OUT
V
IN
1 R
2
R
1
+ ( ) =
R
2
R
1
V
OUT
V
IN
MCP601
MCP606
MCP606/7/8/9
NOTES:
MCP606/7/8/9
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP606/7/8/9 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP606/7/8/9
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amps linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab
Software
Microchips FilterLab
software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3 Mindi Circuit Designer &
Simulator
Microchips Mindi Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
5.4 Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchips product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparasion
reports. Helpful links are also provided for Datasheets,
Purchase, and Sampling of Microchip parts.
5.5 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding users guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especially useful are:
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
5.6 Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental
reference resources.
ADN003: Select the Right Operational Amplifier
for your Filtering Circuits, DS21821
AN722: Operational Amplifier Topologies and DC
Specifications, DS00722
AN723: Operational Amplifier AC Specifications
and Applications, DS00723
AN884: Driving Capacitive Loads With Op
Amps, DS00884
AN990: Analog Sensor Conditioning Circuits
An Overview, DS00990
These application notes and others are listed in the
design guide:
Signal Chain Design Guide, DS21825
MCP606/7/8/9
NOTES:
MCP606/7/8/9
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of J anuary 1 is week 01)
NNN Alphanumeric traceability code
Pb-free J EDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free J EDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3 e
3 e
5-Lead SOT-23 (MCP606)
Example:
XXNN SB25
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP606
I/P256
0722
MCP606
I/SN0722
256
MCP606
I/P 256
0936
MCP606I
SN 0936
256
3 e
OR
OR
3 e
8-Lead TSSOP
Example:
XXXX
YYWW
NNN
606
I936
256
MCP606/7/8/9
Package Marking Information (Continued)
14-Lead TSSOP (MCP609)
Example:
XXXXXXXX
YYWW
NNN
609IST
0936
256
14-Lead PDIP (300 mil) (MCP609) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP609-I/P
0722256
MCP609
0936256
I/P 3 e
OR
14-Lead SOIC (150 mil) (MCP609) Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
MCP609ISL
0722256
MCP609
0936256
I/SL^^ OR 3 e
MCP606/7/8/9

5-Lead PIastic SmaII OutIine Transistor (OT) [SOT-23]
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MLLMETERS
Dimension Limits MN NOM MAX
Number of Pins N 5
Lead Pitch e 0.95 BSC
Outside Lead Pitch e1 1.90 BSC
Overall Height A 0.90 1.45
Molded Package Thickness A2 0.89 1.30
Standoff A1 0.00 0.15
Overall Width E 2.20 3.20
Molded Package Width E1 1.30 1.80
Overall Length D 2.70 3.10
Foot Length L 0.10 0.60
Footprint L1 0.35 0.80
Foot Angle I 0 30
Lead Thickness c 0.08 0.26
Lead Width b 0.20 0.51
N
b
E
E1
D
1 2 3
e
e1
A
A1
A2 c
L
L1
Microchip Technology Drawing C04-091B
MCP606/7/8/9
8-Lead PIastic DuaI In-Line (P) - 300 miI Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
Units NCHES
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing eB .430
N
E1
NOTE 1
D
1 2 3
A
A1
A2
L
b1
b
e
E
eB
c
MCP606/7/8/9

8-Lead PIastic SmaII OutIine (SN) - Narrow, 3.90 mm Body [SOIC]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Units MLLMETERS
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 1.75
Molded Package Thickness A2 1.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 0.50
Footprint L1 1.04 REF
Foot Angle I 0 8
Mold Draft Angle Top D 5 15
Mold Draft Angle Bottom E 5 15
D
N
e
E
E1
NOTE 1
1 2 3
b
A
A1
A2
L
L1
c
h
h

MCP606/7/8/9
8-Lead PIastic SmaII OutIine (SN) - Narrow, 3.90 mm Body [SOIC]
MCP606/7/8/9
8-Lead PIastic Thin Shrink SmaII OutIine (ST) - 4.4 mm Body [TSSOP]
Notes:
Units MLLMETERS
Number of Pins N 8
Pitch e 0.65 BSC
Molded Package Thickness A2 0.80 1.00 1.05
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 2.90 3.00 3.10
Foot Length L 0.45 0.60 0.75
Foot Angle I 0 8
D
N
E
E1
NOTE 1
1 2
b
e
c
A
A1
A2
L1 L

MCP606/7/8/9
MCP606/7/8/9

14-Lead PIastic DuaI In-Line (P) - 300 miI Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
Units NCHES
Number of Pins N 14
Pitch e .100 BSC
Top to Seating Plane A .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .735 .750 .775
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .045 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing eB .430
N
E1
D
NOTE 1
1 2 3
E
c
eB
A2
L
A
A1
b1
b e
MCP606/7/8/9
14-Lead PIastic SmaII OutIine (SL) - Narrow, 3.90 mm Body [SOIC]
Notes:
Units MLLMETERS
Number of Pins N 14
Pitch e 1.27 BSC
Molded Package Thickness A2 1.25
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (optional) h 0.25 0.50
Foot Angle I 0 8
Mold Draft Angle Top D 5 15
Mold Draft Angle Bottom E 5 15
NOTE 1
N
D
E
E1
1 2 3
b
e
A
A1
A2
L
L1
c
h
h


MCP606/7/8/9
MCP606/7/8/9

14-Lead PIastic Thin Shrink SmaII OutIine (ST) - 4.4 mm Body [TSSOP]
Notes:
Units MLLMETERS
Number of Pins N 14
Pitch e 0.65 BSC
Molded Package Thickness A2 0.80 1.00 1.05
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 4.90 5.00 5.10
Foot Length L 0.45 0.60 0.75
Foot Angle I 0 8
NOTE 1
D
N
E
E1
1 2
e
b
c
A
A1
A2
L1 L

MCP606/7/8/9
MCP606/7/8/9
NOTES:
MCP606/7/8/9
APPENDIX A: REVISION HISTORY
Revision F (September 2009)
The following is the list of modifications:
1. Corrected RL text in Figure 2-22 in Section 2.0
Typical Performance Curves.
2. Corrected devices pins in Table 3-1
(Section 3.0 Pin Descriptions).
3. Updated Section 6.0 Packaging Informa-
tion. Updated package outline drawings.
Revision E (March 2008)
1. Increased maximum operating V
DD
.
2. Added test circuits.
3. Updated performance curves.
4. Added Figure 2-31.
5. Added Section 4.1.1 Phase Reversal,
Section 4.1.2 Input Voltage and Current
Limits, ad Section 4.1.3 Normal Opera-
tion.
6. Updated Section 5.0 Design Aids
7. Updated Section 6.0 Packaging Informa-
tion. Updated package outline drawings.
Revision D (February 2005)
1. Added Section 3.0 Pin Descriptions.
2. Updated Section 4.0 Applications Information.
3. Added Section 4.3 Capacitive Loads
4. Updated Section 5.0 Design Aids to include
FilterLab
and to point to the latest SPICE

macro model.
5. Corrected and updated Section 6.0 Packaging
Information.
6. Added Appendix A: Revision History.
Revision C (January 2001)
Undocumented changes
Revision B (May 2000)
Undocumented changes
Revision A (January 2000)
Original Release of this Document.
MCP606/7/8/9
NOTES:
MCP606/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device MCP606 = Single Op Amp
MCP606T = Single Op Amp
Tape and Reel (SOIC, TSSOP)
MCP607 = Dual Op Amp
MCP607T = Dual Op Amp
MCP608 = Single Op Amp with CS
MCP608T = Single Op Amp with CS
MCP609 = Quad Op Amp
MCP609T = Quad Op Amp
Temperature Range I = -40C to +85C
Package OT = Plastic SOT-23, 5-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC (3.90 mm body), 8-lead
SL = Plastic SOIC (3.90 mm body), 14-lead
ST = Plastic TSSOP, 8-lead, 14-lead
Examples:
a) MCP606-I/P: Industrial Temperature,
8LD PDIP package.
b) MCP606-I/SN: Industrial Temperature,
8LD SOIC package.
c) MCP606T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
d) MCP606-I/ST: Industrial Temperature,
8LD TSSOP package.
e) MCP606T-I/OT: Tape and Reel,
5LD SOT-23 package.
8LD PDIP package.
b) MCP607T-I/SN: Tape and Reel,
8LD SOIC package.
a) MCP608-I/SN: Industrial Temperature,
8LD SOIC package.
b) MCP608T-I/SN: Tape and Reel,
8LD SOIC package.
14LD PDIP package.
b) MCP609T-I/SL: Tape and Reel,
14LD SOIC package.
PART NO. X /XX
Package Temperature
Range
Device
MCP606/7/8/9
NOTES:
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyers risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC
32
logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC

MCUs and dsPIC
DSCs, KEELOQ

code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
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03/26/09

2.5V To 6.0V Micropower CMOS Op Amp: Features

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2009 Microchip Technology Inc.

Microchip Technology Drawing C04-057B

Microchip Technology Drawing C04-086B

Microchip Technology Drawing C04-065B

Microchip Technology Drawing C04-087B

and to point to the latest SPICE

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