Hy57v641620hg (16M)
Hy57v641620hg (16M)
Hy57v641620hg (16M)
DESCRIPTION
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications r which require
low power consumption and extended temperature range. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply Note) • Auto refresh and self refresh
• All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type
of pin pitch
- 1, 2, 4, 8 or Full page for Sequential Burst
• All inputs and outputs referenced to positive edge of
system clock - 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
HY57V641620HGLT-KI 133MHz
HY57V641620HGLT-HI 133MHz
Low power
HY57V641620HGLT-8I 125MHz
HY57V641620HGLT-PI 100MHz
HY57V641620HGLT-SI 100MHz
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 1.0/Jan. 02 1
HY57V641620HG
PIN CONFIGURATION
VDD 1 54 VSS
DQ0 2 53 DQ15
VDDQ 3 52 VSSQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VSSQ 6 49 VDDQ
DQ3 7 48 DQ12
DQ4 8 47 DQ11
VDDQ 9 46 VSSQ
DQ5 10 45 DQ10
DQ6 11 44 DQ9
VSSQ 12 43 VDDQ
DQ7 13 54pin TSOP II 42 DQ8
VDD 14 400mil x 875mil 41 VSS
LDQM 15 0.8mm pin pitch 40 NC
/WE 16 39 UDQM
/CAS 17 38 CLK
/RAS 18 37 CKE
/CS 19 36 NC
BA0 20 35 A11
BA1 21 34 A9
A10/AP 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 VSS
PIN DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
CLK Clock
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
CKE Clock Enable
of the states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
NC No Connection No connection
Rev. 1.0/Jan. 02 2
HY57V641620HG
FUNCTIONAL BLOCK DIAGRAM
CS 1Mx16 Bank 0
State Machine
X decoders
RAS DQ0
Memory DQ1
Column Add
Bank Select Counter
A0 Address
A1 Registers
Address buffers
Burst
Counter
A11
BA0
CAS Latency
BA1 Mode Registers Data Out Control Pipe Line Control
Rev. 1.0/Jan. 02 3
HY57V641620HG
ABSOLUTE MAXIMUM RATINGS
Power Dissipation PD 1 W
Note : Operation at above absolute maximum rating can adversely affect device reliability
Note :
1.All voltages are referenced to VSS = 0V
2.VDD(min) of HY57V641620HG(L)T-5I/55I/6I is 3.135V
3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
2.VDD(min) of HY57V641620HG(L)T-5I/55I/6I is 3.135V
Rev. 1.0/Jan. 02 4
HY57V641620HG
CAPACITANCE (TA=25°C, f=1MHz)
Vtt=1.4V
RT=250 Ω
Output Output
50pF
50pF
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6
Rev. 1.0/Jan. 02 5
HY57V641620HG
DC CHARACTERISTICS II (TA= -40 to 85°C, VDD=3.3±0.3VNote5, VSS=0V)
Speed
Parameter Symbol Test Condition Unit Note
-5I -55I -6I -7I -KI -HI -8I -PI -SI
Burst Mode Operating tCK ≥ tCK(min), IOL=0mA CL=3 170 160 150 150 150 150 120 120 120 mA 1
IDD4
Current All banks active
CL=2 NA NA NA NA 120 mA
Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active 160 mA 2
1 mA 3
Self Refresh Current IDD6 CKE ≤ 0.2V
400 uA 4
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V641620HGT-5I/55I/6I/7I/KI/HI/PI/SI
4.HY57V641620HGLT-5I/55I/6I/7I/KI/HI/PI/SI
Rev. 1.0/Jan. 02 6
HY57V641620HG
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
CAS Latency =
tCK3 5 5.5 6 7 7.5 7.5 8 10 10 ns
3
System clock 100
1000 1000 1000 1000 1000 1000 1000 1000
cycle time 0
CAS Latency =
tCK2 10 10 10 10 7.5 10 10 10 12 ns
2
CAS Latency =
tAC3 - 4.5 - 5 - 5.4 - 5.4 - 5.4 5.4 - 6 6 - 6 ns
3
Access time
2
from clock
CAS Latency =
tAC2 - 6 - 6 - 6 - 6 - 5.4 6 - 6 - 6 - 8 ns
2
Data-out hold time tOH 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - ns
Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Data-Input hold time tDH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Address setup time tAS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Address hold time tAH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
CKE setup time tCKS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
CKE hold time tCKH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Command setup time tCS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Command hold time tCH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
CAS Latency =
tOHZ3 3 6 ns
CLK to data 3
output in high 5.4 5.4 5.4 5.4 5.4 5.4 6 6
Z-time CAS Latency =
tOHZ2 3 6 ns
2
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 1.0/Jan. 02 7
HY57V641620HG
AC CHARACTERISTICS II
Operation tRC 55 - 55 - 60 - 62 - 65 - 65 - 68 - 70 - 70 - ns
RAS Cycle
Time
Auto Refresh tRRC 60 - 60 - 60 - 62 - 65 - 65 - 68 - 70 - 70 - ns
100 100
RAS Active Time tRAS 38.5 100K 38.5 100K 42
K
42 120K 45 120K 45 120K 48
K
50 120K 50 120K ns
Data-In to Precharge
Command
tDPL 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 1.0/Jan. 02 8
HY57V641620HG
DEVICE OPERATING OPTION TABLE
HY57V641620HG(L)T-5I
HY57V641620HG(L)T-55I
HY57V641620HG(L)T-6I
HY57V641620HG(L)T-7I
HY57V641620HG(L)T-KI
HY57V641620HG(L)T-HI
Rev. 1.0/Jan. 02 9
HY57V641620HG-I Series
4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HG(L)T-8I
HY57V641620HG(L)T-PI
HY57V641620HG(L)T-SI
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 1.0/Jan. 02 10
HY57V641620HG
COMMAND TRUTH TABLE
A10/
Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR BA Note
AP
H X X X
No Operation H X X X
L H H H
Bank Active H X L L H H X RA V
Read L
H X L H L H X CA V
Read with Autoprecharge H
Write L
H X L H L L X CA V
Write with Autoprecharge H
Burst Stop H X L H H L X X
DQM H X V X
Auto Refresh H H L L L H X X
Entry H L L L L H X
Self Refresh1 H X X X X
Exit L H X
L H H H
H X X X
Entry H L X
Precharge L H H H
X
power down
H X X X
Exit L H X
L H H H
H X X X
Entry H L X
Clock
L V V V X
Suspend
Exit L H X X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 1.0/Jan. 02 11
HY57V641620HG
PACKAGE INFORMATION
UNIT : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720) 10.262(0.4040)
10.058(0.3960)
0.150(0.0059) 1.194(0.0470)
0.050(0.0020) 0.991(0.0390)
Rev. 1.0/Jan. 02 12