Oceans10-Low Cost Modem
Oceans10-Low Cost Modem
Oceans10-Low Cost Modem
I.
INTRODUCTION
Our fundamental knowledge of aquatic ecosystems is increasing at a tremendous rate due to the physical, chemical and biological time-series data from long term sensors. As a result, research sites around the world are being equipped with a broad range of sensors and instruments. Despite the substantial effort to monitor ecological aspects of aquatic systems, the infrastructure needed for sensor networks in marine and freshwater systems without question lags far behind that available for terrestrial counterparts. There is increasing interest in the design and deployment of underwater acoustic communication networks. For example, the Persistent Littoral Undersea Surveillance Network (PLUSNet) demonstrates multi-sensor and multi-vehicle antisubmarine warfare (ASW) by means of an underwater acoustic communications network [1]. A short range shallow water network to monitor pollution indicators in Newport Bay, CA is proposed in [2]. A network of acoustic modems akin to motes is proposed for low power, short range acoustic communications for seismic monitoring [3]. A swarm of acoustically networked autonomous drifters is envisioned to monitor phenomena as they are subjected to ocean currents [4]. A 1km x 1km underwater wireless network of 10s of temperature sensors is envisioned to obtain high temporal and spatial resolution observations within the coral reef lagoon at the Moorea Coral Reef Long Term Ecological Research Station [5]. In order to make more short-range underwater acoustic communication networks a reality, the cost of underwater acoustic modems must come down. Commercial off-the-shelf (COTS) underwater acoustic modems are not suitable for short-range (~ 100m) underwater sensor-nets: their power draws, ranges, and price points are all designed for sparse,
In this paper, we present the design of a short-range underwater acoustic modem starting with the most critical component from a cost perspective the transducer. The design substitutes a commercial underwater transducer with a homemade underwater transducer using cheap piezoceramic
material and builds the rest of the modems components around the properties of the transducer to extract as much performance as possible. We describe the design considerations, implementation details, and initial experimental results of our modem prototype. The remainder of this paper is organized as follows. Section II describes the design of our homemade transducer and its experimentally determined electrical and mechanical properties. Section III describes the design of our analog transceiver and Section IV describes the design transceiver. We present experimental results in Section V and compare the power and cost of our modem to existing modem designs in Section VI. We conclude with a discussion on future work in Section VII. II. TRANSDUCER In this section we describe the design of our homemade transducer, explaining the reasons behind the selection of its piezo-ceramic, urethane compound, and wire leads. We then present the transducers experimentally determined electrical and mechanical properties which are used to govern the rest of the modem design. A. Transducer Design Underwater transducers are typically made from piezoelectric materials materials (notably crystals such as lead zirconate titanate and certain ceramics) that generate an electric potential in response to applied mechanic stress and produce a stress or strain when an electric field is applied. For underwater communication, transducers are usually omnidirectional in the horizontal plane to reduce reflection off the surface and bottom. This is especially important for shallow water communications. The 2D omni-directional beam pattern can be achieved using a radially expanding ring or using a ring made of several ceramics cemented together. A radially expanding ceramic ring provides 2D omni-directionality in the plane perpendicular to the axis and near omni-directionality in planes through the axis if the height of the ring is small compared to the wavelength of sound being sent through the medium [12]. The radially expanding ceramic is relatively inexpensive to manufacture. A ring made of several ceramics cemented together provides greater electromechanical coupling, power output, and electrical efficiency; the piezoelectric constant and coupling coefficient are approximately double that of a one-piece ceramic ring [Ken1]. They work better because the polarization can be placed in the direction of primary stresses and strains along the circumference. However, these are much more difficult to manufacture and are therefore much more expensive than a one piece radial expanding piezoelectric ceramic ring. We thus selected to use a single radially expanding ring, a <$10 Steminc model SMC26D22H13SMQA to achieve an omnidirectional beam pattern at low-cost. The most common method of making transducers from a ring ceramic is to add two leads, and pot it for waterproofing [12]. We used shielded cables for the transducer leads to
ensure the leads would not pick up unwanted electromagnetic noise and attached the leads using solder with 3% silver. The piezoelectric ceramic needs to be encapsulated in a potting compound to prevent contact with any conductive fluids. Urethanes are the most common material used for potting because of their versatility. The most important design consideration is to find a urethane that is acoustically transparent in the medium that the transducer will be used; this is more important for higher frequency or more sensitive applications where the wavelength and amplitude is smaller than the thickness of the potting material. Generally, similar density provides similar acoustical properties. Mineral oil is another good way to pot the ceramics because it is inert and has similar acoustical properties as water. Some prefer using mineral oil to urethane because it is not permanent. However, the oil still needs to be contained by something, which is often a urethane tube. We selected a two-part urethane potting compound, EN12, manufactured by Cytec Industries [13] as it has a density identical to that of water, providing for efficient mechanical to acoustical energy coupling. Creating a transducer by potting the ceramic shifts its resonance frequency due to the additional mass moving immediately around the transducer. The extent of the shift depends on the potting compounds characteristics. Characteristics can vary depending on the type, age, temperature, and mixing method of the compound. The amount of potting can influence resonance frequency as well. Having tight control over these variables to ensure exact reproducibility requires expensive equipment. To keep costs low, we used a simplistic potting method, pouring and mixing the compound by hand in a thermostat controlled lab. Experimental results described in the next subsection indicate that the transducer variations caused in our simplistic potting procedure are suitable for our intended application. Figure 2 shows the piezo-ceramic ring, the potted ceramic, and the transducer in the potting compound mounted to a prototype plate to be attached to the modem housing. The total cost of our transducer, including the ceramic, leads, potting and labor is approximately $50.
Figure 2. From left to right: The raw piezoelectric ring ceramic, the potted ceramic, the transducer in the potting compound mounted to a prototype plate to be attached to a modem housing.
B. Transducer Properties For a single radially expanding ceramic ring, the resonance frequency occurs when the circumference approximately equals the operating wavelength [12, 14]. In air, this frequency is about 41 kHz for every inch in diameter of a solid radially expanding ceramic ring; for the ring made of several ceramics cemented together, in the case that there is not inactive material (such as electrodes or cement), the resonance
frequency is approx 37 kHz for every in nch [12]. The SMC26D22H13SMQA has an outer diameter r of 1.024 inches, a wall thickness of 0.1 inches and a height of 0 0.512 inches. Steminc specifies that the ceramic ring has a nominal resonance frequency of 43kHz +/- 1.5kHz. Experimentally measuring the impedance of two different cer ramics (Figure 3) shows the ceramics do fall within this spe ecification. The resonance frequency (~43kHz) and anti-reso onance frequency (~45kHz) occur at minimum and maximu um impedances, respectively [14, 15].
d the transducers The experimental procedure to determine TVR and RVR included placing our transducer in water 1 meter apart from a reference trans sducer with a known TVR and RVR (in our case, an ITC1042 2 [16]) in the middle of a 3 meter deep, 2 meter wide cylindric cal test tank, and collecting signals swept across frequencie es, 31k-90kHz in 1kHz increments, sent from the reference transducer to our transducer and vice versa. We the en calculated the RVR and TVR of our transducer based on the collected data and the res 5 and 6 show the TVR references TVR and RVR. Figur and RVR of transducer T1.
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Figure 3. The SMC26D22H13SMQA ceram mic impedance (and resonance frequency) in air of two ceramics (T1, T2)
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As stated in the previous subsection, pott tting the ceramic shifts the resonance frequency due to the additional mass moving immediately around the transducer. Figure 4 shows the extent of this shift and the relatively small variation (caused by the ceramics variation and the po otting procedure) between two different transducers (potted us sing the ceramics T1 and T2 from Figure 3). Transmitt ting around the transducers resonance frequency (35kHz) pr rovides the most efficient electrical to acoustical energy couplin ng [12,14].
Frequency y [kHz]
Figure 5. Experimentally determined tr ransmitting voltage response for transducer T1 T
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T1 RVR
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-220 30
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Frequency y [kHz] Figure 6. Experimentally determined re eceiving voltage response for transducer T1 T
Figure 4. The transducer impedance and resonance fr requency (~35kHz) of transducers potted from ceramics T1 and T2
To characterize the transducers ele ectro-mechanical properties, we experimentally measured its transmitting voltage response voltage response (TVR) and its receiving v (RVR). The TVR is defined as the soun nd pressure level experienced at 1m range, generated by the tra ansducer per 1 V of input Voltage and is a function of frequenc cy. The RVR is a measure of the voltage generated by a plan ne wave of unit acoustic pressure at the receiver and is a funct tion of frequency.
The max response of the TVR an nd RVR do not necessarily occur at the transducers electric cal resonance (as seen in Figures 5 and 6), but the transducers resonance frequency still falls near the peak. The sharp peak ks and valleys of TVR and RVR can be attributed to ineffic ciencies in the calibration procedure and characteristics of resonance r that are directly related to geometry of the PZT. To o obtain a flatter, smoother TVR and RVR (such as those for f [16]), more expensive ceramics and manufacturing and calibration procedures are required.
In addition to the TVR and RVR, an important parameter of a transducer is how much voltage it can tolerate before it breaks A typical Type I PZTs can experience up to 12 volts AC per .001 inches wall thickness without much effect to its electro-mechanical properties[17]. Thus, voltages up to 1200Vpp or 425Vrms should be used for our transducer. Using the passive sonar equation we can calculate the expected max distance the transducer will be able to send a signal given a Source Level (SL), the transmission loss (TL, due to spreading and absorption loss in the water), and the noise level (NL) of the ocean. SNR = SL TL - NL (1)
per unit depending on the quantity produced. The transmitter and receiver portions of the analog transceiver are described in more detail in the following subsections.
Figure 7 shows the expected max distance achievable for the transducer transmitting at the transducers resonance frequency at various voltages assuming a noise level of 50 dB r 1 uPa.. Transmitting 425 Vrms, for an SNR of 10 dB re 1 uPa at the receiver, the transducer could theoretically send a signal up to 2800 meters. The receive voltage at 10 dB SNR (determined using the RVR) is 820uV.
120 100 80 60 40 20 0 -20
SNR vs. Range 25 Vrms 125 Vrms 225 Vrms 325 Vrms 425 Vrms
C. Analog Transmitter The transmitter was designed to operate for signal inputs in a range of 0 100kHz. The architecture is unique andconsists of two different amplifiers working in tandem (Figure 9). The primary amplifier is a highly linear Class AB amplifier that provides a voltage gain of 23 while achieving a power efficiency of about 50%. The output of the Class AB amplifier is connected to current sense circuitry that in turn controls the secondary amplifier, which is a Class D switching amplifier. The Class D amplifier is inherently nonlinear but possesses an efficiency of approximately 95%. With both of the amplifiers driving the load and working together, the transmitter achieves a highly linear output signal while maintaining a power efficiency greater than 75%. Due to its high linearity, the transmitter may be used with any modulation technique that can be programmed into the digital hardware platform.
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Figure 7. SNR vs. range for various transmit voltages based on transducer T1s TVR. The graph assumes transmission at 35kHz and an ocean noise level of 50 dB re 1uPa.
The transducers experimentally determined electrical and mechanical properties govern the design choices for the rest of the modem design. The following section describes the analog transceiver. III. ANALOG TRANSCEIVER The analog transceiver (Figure 8) consists of a high power transmitter and a highly sensitive receiver both of which are optimized to operate in the transducers resonance frequency range (Figure 4). The transmitter is responsible for amplifying the modulated signal from the digital hardware platform and sending it to the transducer so that it may be transmitted through the water. The receiver amplifies the signal that is detected by the transducer so that the digital hardware platform can effectively demodulate the signal and analyze the transmitted data. The transceiver costs between $125 and $225
Figure 9. Analog transmitter block diagram. The transmitter uses two amplifiers two achieve efficiency
A power management circuit is provided to adjust the output power in real-time to match it to the actual distance between transmitter and receiver. The ability to provide a low-power output has several important benefits: (1) less interference for nearby ongoing communications; (2) reduced noise pollution and (3) considerable power savings. The current configuration of the transmitter is equipped with a power management system that can switch between output levels of 2, 12, 24 and 40 watts. The power management system has been designed so that the transmitter will maintain maximum efficiency over this wide range of power output
levels. The system is controlled by a low curr rent 5 volt signal from the digital hardware platform so that th he power may be dynamically controlled for different operating g conditions. D. Analog Receiver
Figure 10. Analog receiver block diagram. The receivers provides high gain in a narrow band around the transducers reso onance
The receivers architecture consists of a set t of narrow (high Q) filters with high gain (Figure 10). These filters are based ombine the tasks on biquad band-pass filters, and essentially co of filtering and amplification. The receiver is configured so Hz (to match the that it only amplifies signals around 35 kH electrical resonance frequency of the tra ansducer) while attenuating low frequencies at a rate of 120dB B per decade and high frequencies at rate of 80dB per decade (Figure 11). The receiver must be able to amplify only the e frequencies of interest because of the large amount of noise e associated with underwater acoustic signals. The cu urrent receiver configuration consumes about 375 mW when in standby mode and less than 750 mW when fully engaged. The relatively high power consumption (in comparison to th hat of the WHOI Micromodem (200mW)) [7] is a result of the e receivers high gain (65dB) which is capable of sufficientl ly amplifying an input signal as small as a few hundred microv volts allowing the ces (such as the receiver to pick up signals at longer distanc 820uV received signal described in section II). An ultra-low power wake up circuit will be added to the receiver to considerably reduce power consumption. A few receiver component values can be changed to widen it ts bandwidth (but decrease its gain) to allow for transmission n of modulation schemes that require more bandwidth.
ding, but not limited to, the underwater acoustic modem includ choice of modulation scheme and hardware platform for its implementation. We selected to implement frequency shift keying, (FSK) on a field programm mable gate array (FPGA) for our modem prototype. FSK is a fairly simple modulat tion scheme that has been widely used in underwater commun nications over the past two decades due to its resistance to tim me and frequency spreading of the underwater acoustic channel l [7,18]. Other modulation schemes such as phase shift keying [7], direct sequence spread spectrum (DSSS) [8] and ortho ogonal division frequency multiplexing (OFDM) [19, 20] are e now being considered for higher data rate underwater app plications, but the proven robustness of FSK and its simplic city makes it an attractive modulation scheme as the first pr rototype for our low-cost, low-power, low-data rate application. Reconfigurable systems (e.g., FPGAs) are a class of computing architectures that allow a tradeoffs between flexibility and performance [21-23]. They strike a balance between solely hardware and solely y software solutions, as they have the programmability and non-r recurring engineering costs of software with performance capa acity and energy efficiency approaching that of a custom hard dware implementation [23]. Reconfigurable systems are known to provide the performance needed to process complex digital d signal processing applications and especially provid de increased performance benefits for highly parallel algorithm ms [24]. Furthermore, they are programmable allowing the sa ame device to be used to implement a variety of different communication protocols. Once the designs are ready in FPGA A, they can relatively easily be moved to an ASIC to reduce bot th the area, cost and power consumption. be an overview of the FSK The following subsections describ modem implementation and its HW/SW co-design for accurate control and I/O. A. FSK Modem Design Table I shows the FSK mod dems time and frequency parameters which were selected bas sed on the properties of the transducer. The mark frequency y represents the frequency used to represent a digital 1 when converted to baseband and the space frequency represents s the frequency used to represent a digital 0 when conv verted to baseband. The sampling frequency is used for sending s and receiving the modulated waveform on the car rrier frequency while the baseband frequency is used for all baseband b processing.
TABLE I. RAMETERS FSK MODEM PAR Properties Assignment Modulation FSK Carrier frequency 35 KHz Mark frequency 1 KHz Space frequency 2 KHz Symbol duration 5 ms Sampling Frequency 800 KHz Baseband Frequency 16 KHz
IV. DIGITAL TRANSCEIVER The digital transceiver is responsible for physical layer communication, i.e., implementing a su uitable baseband processing scheme (including modula ation, filtering, synchronization, etc.) for the application and d environment of interest. There are many design choices that must be considered when designing a digital tran nsceiver for the
Figure 12 illustrates a block k diagram of our FPGA implementation of an FSK modem. In receive mode, the input
signal adc_in is the received analog signal from the analog to digital converter, sampled at the sampling frequency, which consists of a modulated wave form (when data is present) and noise. The following digital down converter (DDC) recovers the signal to the digital baseband according to the FSK modulation scheme and known carrier frequency and allows for subsequent processing at the lower, baseband frequency. A symbol synchronizer is then required to locate the start of the first symbol of a data packet to set accurate sampling and decision timing for subsequent demodulation. The synchronizer is based on correlation with a known reference sequence (a 15-bit Gold code translated to an FSK waveform where a -1 is represented with the space frequency and a 1 is represented with the mark frequency). When the reference and receiving sequence exactly align with each other, the correlation result reaches a maximum value and the synchronization point is located. Details of the symbol synchronizers implementation can be found in [25]. The demodulator block is disabled until it obtains a valid symbol synchronization clock from the symbol synchronizer. The demodulator adopts a matched filter FSK demodulation scheme described making use of two bandpass filters (one centered on the mark frequency and one centered on the space frequency) to decode the sequence. The decoded bit stream data_out is then sent to the host computer and translated to a readable message. In transmit mode, the modem receives a bit stream (data_in) and modulates the bit stream into an FSK waveform using a cosine look up table. The modulated waveform, sampled at the sampling frequency, is sent to the analog transceiver through the digital to analog converter (dac_out).
with standard optimization. The resources reported for the total modem include the resources for the complete HW/SW co-design as described in the next subsection (Figure 13). Using the resource values in the XPower Estimator 9.1.03, for an even lower power device, the Spartan-6 XC6SLX150T, the power consumption estimation for the complete modem design is 233 mW. B. FSK HW/SW Co-design We used Xilinx Platform Studio 10.1 to design a HW/SW co-design for the digital modem to allow for accurate control and I/O. The co-design consists of the digital modem, a UART (Universal Asynchronous Receiver Transmitter) to connect to serial sensors or to a computer serial port for debugging, an interrupt controller to process interrupts received by the UART or the modem, logic to configure the on board ADC, DAC, and clock generator, and MicroBlaze, an embedded microprocessor to control the system (Figure 13). The MicroBlaze processor is a 32-bit Harvard reduced instruction set computer (RISC) architecture optimized for implementation in Xilinx FPGAs. It interfaces to the digital modem through two fast simplex links (FSLs), point-to-point, uni-directional asynchronous FIFOs that can perform fast communication between any two design elements on the FPGA that implement the FSL interface. The MicroBlaze interfaces to the interrupt controller and UART core over a peripheral local bus (PLB), based on the IBM standard 64-bit PLB architecture specification.
TABLE II. FSK MODEM RESOURCES Occupied LUTs slices 95 184 284 541 1025 1980 12000 22101 16,706 29,076
BRAMs 9 9 1 2 55
Each component of the digital modem (modulator, digital down converter, synchronizer, and demodulator) was designed in Verilog and tested individually in ModelSim to verify its operation. Table II shows the FPGA hardware resources occupied for each component of the acoustic modem design
Upon start-up, the MicroBlaze initializes communication with the modem by sending a command signal through the FSL bus signaling the modem to turn on. When the modem is ready to begin receiving signals, it sends an interrupt back to MicroBlaze to indicate initialization is complete. The modem then begins the down conversion and synchronization process, processing the signal received from the ADC and looking for a peak above the threshold to indicate a packet has been received. If the modem finds a peak above the threshold, it
finds the synchronization point, and demodulates the packet. The demodulated bits are stored in the FSL FIFO. When the full packet has been demodulated, the modem sends an interrupt indicating a packet has been received and the MicroBlaze may retrieve the packet from the FSL. The modem then returns to synchronization, searching for the next incoming packet. After initialization, the MicroBlaze remains idle, waiting for interrupts either from the modem or UART. If it receives an interrupt from the modem indicating that a packet has been demodulated, the MicroBlaze reads the bits from the FSL FIFO and sends the bits over the UART to be printed on a computers Hyperterminal for verification. If the MicroBlaze receives an interrupt from the UART, indicating that the user would like to send data, the MicroBlaze sends a command to the modem to send the bitstream the MicroBlaze places in the FSL. The modem then modulates the data from the FSL and sends the modulated waveform to the DAC for transmission. The MicroBlaze then returns to waiting for interrupts from the modem or the UART and the modem returns to synchronization, searching for the next incoming packet. This control flow is depicted in Figure 14.
receive signal was just above 200mVpp at this distance and hence could just be detected above the converters noise. This test proved that our analog hardware could transmit a considerable distance and would likely be able to transmit a much farther distance given a low-noise power supply at the receiver and further improvements to the analog transceiver.
V. INITIAL RESULTS In order to verify the operation of our modem, we first tested the analog components (the transducer and analog transceiver) and digital components (the digital transceiver) separately. For the analog testing, we took our modem hardware to Mission Bay, San Diego, CA and placed one transceiver and transducer on the dock to act as the transmitter and placed another transceiver and transducer on a boat to act as the receiver. The transmitter was powered by power supplies on the dock and the receiver was powered by a power supply connected to an inexpensive RadioShack AC/DC converter that unfortunately produced a substantial amount of noise (200mVpp). We sent a 35kHz sinusoid from the transmitter to the receiver placed at three different locations as shown in Figure 15: 1. 75 meters, 2. 235 meters, and 3. 350 meter away. We were able to successfully detect the signal at 350m by applying 66Vrms across the transmit transducer, however the
For digital testing, we purchased a prototype test platform, the DINI DMEG-AD/DA, that includes analog to digital and digital to analog converters, a Xilinx Virtex-4 FPGA, an onboard oscillator, and a serial port and downloaded the HW/SW co-design to the board. We set our initial test sequence as sending the 15 bit Gold Code of 011001010111101 followed by a 100 bit packet of randomized ones and zeros. We sent the signal through a 12 inch bucket of water and used the DINI board to synchronize and demodulate the data. Figure 16 shows a snapshot of the post place and route hardware simulation result for our digital modem design described in Verilog HDL. The four signals in the figure are: the output signal of the down converter (DDC out), the output of the reference cross correlation block (correlation) used for synchronization, and the output of the two bandpass filters in the demodulator. In the DDC out signal one can observe the FSK realization of the Gold Code followed by the first 8 bits of data (the digital 0 being represented by the sparse waveform and the digital 1 being represented by the dense waveform). The bandpass filters are enabled in the demodulator when the correlation result first rises above the threshold (not shown). The vertical arrow labeled Index illustrates the synchronized peak found by the hardware which is a known clock delay from the start of the data (vertical arrow labeled Actual). The bit stream demodulated from the Actual peak are sent to the FSL buffer to be read by the MicroBlaze and printed to the Hyperterminal. The bits written to the Hyperterminal revealed 0% error rate for the 100 bit packet from the 12 inch plastic
bucket. The test was repeated with different d data bits 10 times all producing 0% error.
Figure 16. Snapshot of hardware simula ation result for 12 bucket test
Because the bucket produced such pe erfect data, we generated data in Matlab with packet len ngths of 10000 symbols and sent the signals to the hardware for synchronization and demodulation. These pa ackets achieved a bit error rate of 10-2 at 10dB SNR. digital hardware Feeling confident that our analog and d components worked properly, we conducte ed an initial full system test at the UCSD Canyon View poo ol, a 50m x 25m concrete pool with 1m depth on the shallow e end and 5m depth on the deep end. As the pool provided outdoor power outlets, we were able to power both the transmitter and receiver off power supplies. At 50 meters distance, we sent a packet of 400 symbols followed by a 400 symbol clearing period foll lowed by another packet of 400 symbols using only 6.5Vrms ac cross the transmit transducer. The transducers were submerged d to a depth of 10 cm and placed along the 50m side of the e pool to avoid swimmers. The digital hardware was able e to successfully detect the start of each packet, but faile ed to accurately demodulate the data, achieving 30% bit error r rate. Figure 17 shows the first few symbols of the first rec ceived packet, at 10dB SNR, starting with the 15 symbol ref ference sequence followed by four data bits. The bold yellow v vertical bar marks the start of the reference sequence (easily seen above the initial noise) and the light yellow vertical bar denotes what the synchronizer determined to be the start of data. Sync_symbol_clk denotes the symbol clock synchronized to the start of the first data symbol. Adc_in sh hows the input to the ADC, ddc_out shows the downconverte ed, downsampled signal used for all digital processing and dat ta_out shows the demodulated bits.
It can easily be seen in Figure e 17 that the data can be accurately demodulated for the first f few symbols of the received packet as there is a clea ar distinction between the mark and space frequencies. However, a strong multipath arrives at the receiver after about t the 7th symbol, severely distorting the signal making accurat te demodulation impossible. Concrete pools are one of the most difficult underwater channels due to extremely strong multipath and most other underwater acoustic modems fail in n this environment. Although we obtained 30% error r rate in the concrete pool, we were encouraged by the result ts and are confident in an environment with less severe multipath, m the modem can perform well. We are currently developing d a power supply board, battery pack, and water rtight housing (that can withstand pressures at depth of up to t 100m) so we can test our modem in the open ocean in order to assess its true performance. VI. MODEM COMPARISON AND CONCLUSION Our anticipated cost and pow wer estimates for the full modem prototype (not including batteries or housing) are shown in Table III. The power consumption c of the analog transceiver depends on its mode. The interfaces (ADC and DAC) are specified as TBD (to be e determined) as the ADC and DAC on our evaluation board are over specified and too power consuming for our intended design. d
TABLE III. I COST AND POWER EST TIMATES FOR THE UNDERWATER MODEM M Cost ($) Power (W) N/A 50 Transducer 1- 40 125 Transceiver 0.2 75 Digital Components TBD 100 Power Supply TBD TBD Interfaces Total ~$250
We compare our design with th hree commercial modems, two designed at private firms (LinkQuest ( and Teledyne Benthos) and one designed at Woods W Hole Oceanographic Institute in Table IV. Note that the distance and bit rates reported for the modems are the maximum m distance and rates achievable under ideal conditions. Also note that the price of the commercial modem designs is based on market prices whereas our design cost is based solely on parts costs and assembly labor. However the part ts price of the commercial
Data rate Teledyne Benthos LinkQuest WHOI MicroModem UCSD Modem 2400 bps 9600 bps 80 bps (FHFSK) 300-5400 (PSK) 200 bps
Firmware and software design Proprietary Proprietary All design information is available online. All design information will be available online.
2 km
$600
modems is still much more than the full price of our modem as commercial transducers used in the designs solely cost a few thousand dollars. From this comparison we observe that our modem currently stands as low-cost, comparable power alternative to existing modem designs. In the future, to further reduce power consumption, we plan to explore the possibilities to provide signal detection at even lower power levels. This is paramount to building a modem that has low listening power, which is also a key requirement to ensure long lifetime on a limited battery supply. We plan to eventually utilize a design that has a programmable gain, which is dynamically controlled by the digital hardware platform. In addition, further changes to the circuit design of the transceiver will be made to further increase its efficiency and digital transceiver implementations of advanced modulation techniques will be explored. ACKNOWLEDGMENT This work was supported in part by the China Scholarship Council, National Science Foundation Grant #0816419 and a National Science Foundation Graduate Research Fellowship. We would like to thank Douglas Palmer, Diba Mirza, John Hildebrand, Feng Tong, Brent Hurley for their assistance and support with this project. REFERENCES
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