LEON3 HW/SW Development Tutorial

for the Embedded Systems Hardware/Software Co-design course 02.22.2010 [email protected] mmeslab, nctu, taiwan

This document is a short tutorial to guide you through the process of setting up your development environment and testing the reference design. Our target platform uses a soft-core LEON3 processor as the central processing unit. LEON3 is a Sun SPARC v8 compliant processor core. The reference design is an SoC with a LEON3 core and some IP s as shown in the following diagram.
RS-232 JTAG PHY

Spartan3-1500 FPGA
LEON3 Processor DSU3 Serial Debug Link JTAG Debug Link Ethernet MAC AMBA AHB AMBA APB

AHB Controller

Memory Controller

mcomp

idct

AHB/APB Bridge VGA

Timers

IRQ Controller

8-bit/32-bit memory bus Video DAC PROM SDRAM Memory extension

To be added in future labs

I.

Installing the hardware-software co-implementation environment

The following instructions are for Windows platforms only. Both Windows XP and Vista work fine (Windows 7 has not been tested). If you are using Linux machines, all the tools we need have Linux versions as well, but you have to figure out how to set up the environment by yourself. 1. Software toolchain installation For software development, we will use the gcc-based cross compiler toolchain for the LEON3 processor. GNU development tools usually require a Linux-like environment to run. Under Microsoft Windows, you can install the Cygwin environment in order to use the toolchain. The latest version of Cygwin can be installed by running the network installation program http://www.cygwin.com/setup.exe. The latest version is 1.7.1 (as of writing of this document). Note that in addition to the default packages of Cygwin, you should select the following packages in the installation dialog box: automake gcc

make mpfr sharutils tcltk wget

Now, we have to install the cross compiler for the LEON3 processor. The cross compiler toolchain is called BCC (Barebone C compiler) that includes the following packages: GNU C/C++ cross-compiler 3.4.4 GNU Binutils-2.16.1 (assembler, linker ...) Newlib 1.13.1 Embedded C-library Bare-C run-time system with interrupt support and tasking lwIP and Pthreads libraries Mkprom boot-prom builder for LEON GNU debugger (gdb) with Insight or DDD graphical front-end The BCC package (sparc-elf-3.4.4-1.0.29d-cygwin.tar.bz2) can be downloaded from ftp://gaisler.com/bcc/bcc/bin/windows. To install BCC, you must create a directory /opt if you don t have one. Put all the software packages in your home directory, then type in the following commands (assume that the BCC package is in current directory):
~/$ tar xvfj sparc-elf-3.4.4-1.0.29d-cygwin.tar.bz2 C /opt

In addition, you also need to install a debug monitor, GRMON, to communicate with the Debug Support Unit (DSU) inside the LEON SoC. The debug monitor package (grmon-eval-1.1.39.tar.gz) can be downloaded from ftp://gaisler.com/grmon/grmon. To install GRMON, type in the following commands:
~/$ tar xvfz grmon-eval-1.1.39.tar.gz c /opt

Modify .bashrc under your home directory and append the following line at the end:
export PATH=/opt/grmon-eval/cygwin:/opt/sparc-elf-3.4.4/bin:$PATH

so that the cross compiler tools and the debug monitor are in your command search path.

2. Hardware toolchain installation We will use Xilinx ISE WebPACK 10.1 to synthesize and implement the hardware platform on the GR-XCS3-1500 board. The installation package can be obtained from http://www.xilinx.com/tools/webpack.htm for free. You must register a Xilinx account for it. Note that the latest version of ISE WebPACK is 11.1, however, the RTL models provided in the labs are only verified with the 9.2 and 10.1 versions of ISE. If you are not familiar with EDA tools for FPGA, such as the ISE WebPACK, you can download a tutorial from

(http://www.xilinx.com/support/techsup/tutorials/tutorials10.htm). We also need a waveform simulator to debug your digital circuits. In this course, we use the nice open source GHDL simulator from (http://ghdl.free.fr). Unfortunately, the native Win32 version of GHDL available from the website does not work for the LEON3 platform. The Linux version works fine. If you prefer to use Cygwin, instead of switching over to Linux for logic simulation, you can download the GHDL port for Cygwin from http://home.comcast.net/~bp_labs/software/ghdl/index.htm. Just follow the instructions on the website to install it. You can check whether your installation is correct or not by typing the command:
~/$ ghdl --dispconfig

If your installation is correct, the command will print out some detail information about your installation and exit without error. Another logic simulator is the commercial software ModelSim from Mentor Graphics. You can get a student version, ModelSim PE, and use it for free for 6 months. Please see http://model.com/content/modelsim-pe-student-edition-hdl-simulation for details. ModelSim runs much faster than GHDL. However, since it is commercial software, we do not support it in the teaching lab. If you prefer to do mixed-language design (i.e. mixing VHDL and Verilog), then it is not possible to use GHDL (or the student version of ModelSim) for logic simulation. Full version of ModelSim SE does support mixed-language logic simulation, but you are on your own to obtain a legal copy of the software if you insist on mixing VHDL and Verilog in your design. Finally, to see the signals generated by the logic simulator, you have to install a waveform viewer. Please download GTKWave from (http://www.dspia.com/gtkwave.html) and follow the installation instruction. Don t forget to download and install the required DLL files manually.

II. Installing the reference design packages Now that you have the hardware-software development environment installed, it is time to install the system reference design (including hardware model and software source packages). 1. Installation of the LEON3/GRLIB synthesizable IP RTL model You can download the GRLIB package (grlib-gpl-1.0.22-b4075.zip) from http://www.gaisler.com. To install the RTL source code (in VHDL) of the LEON platform, simply unzip the file under your Cygwin home directory.

2. Installation of eCos source repository with LEON patches We use eCos as embedded system software; you can download the eCos source package (ecos-rep-1.0.8.tar.gz) from ftp://gaisler.com/ecos/ecos/src. From a Cygwin command prompt, type in the following command:
~/$ tar xvfz ecos-rep-1.0.8.tar.gz C /opt

The source tree of eCos will be installed under /opt/ecos-rep-1.0.8. You also need the eCos configuration tool in order to build a customized version of eCos for your application. You can download the installer, configtool-2.11-setup.exe, from ftp://gaisler.com/ecos/ecos/bin/configtool/windows. To install the eCos configuration tool, just run the installer. The eCos configuration tool is a program with nice GUI. The first time you run the tool, it will ask you to select the directory where your eCos source repository sits, as follows.

The procedure to customize an eCos build will be illustrated in the next section. 3. Building the reference design In this section, we will show you how to build the hardware and software platform from scratch. a. To build the hardware reference design, use the following commands:
~/$ cd grlib-gpl-1.0.22-b4075/designs/leon3-gr-xc3s-1500/ ~/$ make ise

This will synthesize the hardware of the system. It may takes anywhere from 30 minutes to several hours to run this command, depending on the speed of your computer. You can skip this step for lab 2 since we do not need to modify the hardware. A pre-built bit file (leon3mp.bit) for configuring FPGA is included in the lab2 package.

b. To build a customized version of eCos system software library, run the eCos configuration tool and select the target platform template LEON3 processor with GRETH ethermac by opening up the dialogue box under Build Template. Note that you have to select the extra package net as shown in the following figure.

A warning dialog will popup and alert you to resolve some symbol conflicts. Simply press Continue to enter the next step.

c. Now, set the build tool directory by opening the dialogue box under Tools Paths Build Tools Path:

d. Set the Cygwin binary tools directory (for the commands such as make, etc.) by opening up the dialogue box under Tools Paths User Tools Path:

In the example above, the user tools are under c:\cygwin\bin\. You must set this directory properly so that you can build the eCos library directly using the eCos configuration tool GUI. e. Optionally, if you want to change your eCos repository directory (remember that you set it the first time you ran the configure tool), you can use the dialogue box under Build Repository. f. Make sure that the TFTP (RFC-1350) support in the Basic networking framework package option is check. Also choose Address setups for eth0 under Initialization options for eth0. Set the address for eth0 to 192.168.0.2 (IP for the LEON platform). Set the server IP address to 192.168.0.1 (IP for your host computer). You may pick any non-conflicting private addresses in the 192.168.0.x range for these two IP addresses. If you want to select the IP from a different range (say, 10.0.0.x) while using Ethernet for debug interface, you may have to change the reference hardware RTL code (see GRMON manual for details). Finally, set the Network mask address to 255.255.255.0.

g. Now, save the configuration file (call it leon.ecc) to your workspace (say, ~/ecos_leon) by selecting the menu item File Save. h. Now, you can build the customized eCos library by selecting the menu item Build Library. The eCos library for the LEON platform will be compiled and put under the directory leon_install along with the configuration file.

4. Building the video decoder for lab2 Download the package lab2_pkg.tgz from the class website and un-tar it under your Cygwin workspace. By now, the directory tree structure of your workspace should be as follows. The makefile in m4v_dec_ecos is written based on this tree structure.
(your_cygwin_home) -+- ecos_leon +- leon_build | | | +- lab2_pkg + m4v_dec_ecos + bitstream + leon_bit_files +- leon_install +- leon_mlt

Change to the directory m4v_dec_ecosand simply type make . This would build the MPEG-4 video decoder executable for the LEON platform. The directory leon_bit_files contains the pre-built FPGA bit file with the latest LEON reference design.

5. Executing the video decoder on the LEON reference design In this section, you will learn how to configure the FPGA with the reference hardware design and to run the video decoder. a. Under ISE WebPACK 10.1 Accessories, there is an FPGA configuration tool called iMPACT. Run iMPACT and create a new project.

b. In the next dialog box, check the item Configure devices using Boundary-Scan (JTAG) and then click Finish. c. An Assign New Configuration Filedialog box will pop up for platform flash configuration assignment. Since we will not use the PROM xcf04s and xcf01s for configuring FPGA, just press the Bypass button twice. When the third Assign New Configuration File dialog pop up, select the bit file leon3mp.bit provided in the lab2 package (under the directory leon_bit_file). Note that a warning message may tell you that the FPGA configuration clock has been changed from CCLK to JTAG clock. This is a normal message.

d. Right click on the xc3s1500 icon and select Program from the drop-down menu. A dialog box will pop up to ask you to set the properties for FPGA programming, just click Ok. The FPGA will be configured and a Program Succeeded message will be displayed.

e. To upload the video decoder program to the board, you must use GRMON debug monitor. GRMON is a host-side program that communicates with the hardware Debug Support Unit (DSU) of the LEON SoC. Under a Cygwin command prompt, change to the program directory of lab2 and issue the following command: ~/$ grmon-eval.exe eth -u This commands instruct GRMON to communicate with the DSU via the Ethernet cable and to send the application program outputs to the GRMON console. You can also use USB JTAG (works only for WinXP) or serial port to connect to the board. Please check the user s manual of GRMON. GRMON will initialize the LEON platform and display the following messages:

[my_host]:../lab2_pkg/m4v_dec_ecos/$ grmon-eval eth -u GRMON LEON debug monitor v1.1.39 evaluation version Copyright (C) 2004-2008 Aeroflex Gaisler - all rights reserved. For latest updates, go to http://www.gaisler.com/ Comments or bug-reports to [email protected] This evaluation version will expire on 2/11/2010 ethernet startup. GRLIB build version: 4075 initialising ............... detected frequency: 9 MHz Component LEON3 SPARC V8 Processor AHB Debug UART AHB Debug JTAG TAP GR Ethernet MAC LEON2 Memory Controller AHB/APB Bridge LEON3 Debug Support Unit Modular Timer Unit General purpose I/O port Vendor Gaisler Research Gaisler Research Gaisler Research Gaisler Research European Space Agenc Gaisler Research Gaisler Research Gaisler Research Gaisler Research

Use command 'info sys' to print a detailed report of attached cores grlib>

f. Under GRMON, type in the following command to load the program into memory:
grlib > load m4v_dec.elf

g. Before you can test the video decoder, you have to run a TFTP server on your host computer. The video decoder in lab2 use TFTP to transfer input bitstream into GR-XC3S-1500 for decoding and to write back the decoded YCBCR file to the host computer. We suggest that you use tftp32 for this purpose (can be downloaded from http://tftpd32.jounin.net). In tftp32, you must set the Current Directory box to the directory which contains the video bitstream and the Server interface box to the IP of the Etherenet card that connects to the LEON board.

At the GRMON console, type in the following command to execute the decoder:
grlib > run

The output messages of the program will be sent to the GRMON console as follows.

Reading bitstream using tftp... bitstream_size = 83860, err = 0 Initializing decoder ... Decoding frames: 0...16...32...48...64...80...96...112...128...144... IDCT Computation: Inverse Quantization: Motion Compensation: Boundary Extension: Boundary Removal: Block Data Transfer: DC/AC Prediction: VLC Decoding: Total decoding time: 9118.00 ms (46.61% of total decoding time) 1009.00 ms ( 5.16% of total decoding time) 4152.00 ms (21.22% of total decoding time) 559.00 ms ( 2.86% of total decoding time) 646.00 ms ( 3.30% of total decoding time) 1724.00 ms ( 8.81% of total decoding time) 160.00 ms ( 0.82% of total decoding time) 349.00 ms ( 1.78% of total decoding time) 19564.00 ms, we measured 17717.00 ms (90.56%)

Writing decoded YCbCr frames using tftp... Finished decoding.