I C, 32-Bit, Binary Counter Clock With 64-Bit ID: General Description Features
I C, 32-Bit, Binary Counter Clock With 64-Bit ID: General Description Features
I C, 32-Bit, Binary Counter Clock With 64-Bit ID: General Description Features
Rev 0; 7/07
Features
Compliant with Microsoft Windows Media DRM 10 for Portable Devices 32-Bit Binary Counter Programmable Alarm 64-Bit Factory-Programmed ID Interrupt Output I2C Serial Interface Two Selectable I2C Addresses 2.4V to 5.5V Operating Voltage Range 1.3V to 5.5V Timekeeping Operating Range -40C to +85C Operating Temperature Range 8-Pin SOP
DS1372
Applications
Portable Audio and Video Players
Pin Configuration
TOP VIEW
X1 X2 AD0 GND 1 2 3 4
Ordering Information
+
8 7 VCC SQW/INT SCL SDA
PART DS1372U+
PIN-PACKAGE 8 SOP
DS1372
6 5
SOP
+Denotes a lead-free package. This symbol also appears on the top mark.
VCC
RPU
RPU SCL
X1
X2 VCC SQW/INT
DS1372
GND
AD0
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.4V to 5.5V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER SCL Clock Frequency (Note 6) Bus-Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition (Note 7) Low Period of SCL Clock High Period of SCL Clock Setup Time for Repeated START Condition Data Hold Time (Notes 8 and 9) SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT CONDITIONS Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode MIN 100 0.04 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 0 TYP MAX 400 100.00 UNITS kHz s s s s s 0.9 s
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DS1372
Setup Time for STOP Condition Capacitive Load for Each Bus Line (Note 11) I/O Capacitance SCL Spike Suppresion Oscillator Stop Flag (OSF) Delay (Note 12) Timeout Interval (Note 13)
CRYSTAL SPECIFICATIONS
PARAMETER Nominal Frequency Capacitive Load Equivalent Series Resistance SYMBOL fO CL ESR MIN TYP 32.768 12.5 50 MAX UNITS kHz pF k
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10:
Limits at -40C are guaranteed by design and not production tested. All voltages are referenced to ground. SCL clocking at maximum frequency = 400kHz. Specified with I2C bus inactive, SCL = SDA = VCC. Measured with a 32.768kHz crystal attached to the X1 and X2 pins. The I2C minimum operating frequency is imposed by the requirement of timeout period. The first clock pulse is generated after this period. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT must only be met if the device does not stretch the low period (tLOW) of the SCL signal. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. CB = Total capacitance of one bus line in pF. The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 2.4V VCC VCC(MAX). The DS1372 can detect any single SCL clock held low longer than T_TIMEOUT (MIN). The I2C interface is in reset state and can receive a new START condition when SCL is held low for at least T_TIMEOUT (MAX). Once the part detects this condition the SDA output is released. The oscillator must be running for this function to work.
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1, 2
X1, X2
AD0
4 5 6
7 8
SQW/INT VCC
RS[2:1] DIVIDER CHAIN X1 4 X2 OSCILLATOR VCC GND SDA SCL AD0 I2C INTERFACE 64-BIT ID ROM 1Hz 4096 CLR 32-BIT COUNTER 24-BIT ALARM COUNTER ACE AF INTCN CONTROL/ STATUS 2 4096 32,768Hz 8192Hz 4096Hz 1Hz MUX SQW MUX N SQW/INT
POWER
DS1372
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DS1372
CRYSTAL
X1 X2
Oscillator Circuit
The DS1372 is designed to operate with a standard 32.768kHz quartz crystal having a 12.5pF specified load capacitance (CL). For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks (RTCs). An external 32.768kHz oscillator can be used as the DS1372s time base. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 is floated. The EOSC bit in the Control Register controls oscillator operation.
LOCAL GROUND PLANE (LAYER 2)
Operation
The block diagram in Figure 1 shows the DS1372s main elements. As shown, communications to and from the DS1372 occur serially over an I2C bidirectional bus. The DS1372 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code followed by a register address. Subsequent registers can be accessed sequentially until a STOP condition is executed.
Clock Accuracy
The initial clock accuracy is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 2 shows a typical PCB layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks (RTCs) for detailed information.
Address Map
Table 1 shows the address map for the DS1372 registers. During a multibyte access, when the address pointer reaches the end of the register space (10h) it wraps around to location 00h. On an I 2C START or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to reread the registers in case the main registers update during a read.
Clock Operation
The clock counter is a 32-bit up counter. The counter counts up once per second. The contents can be read or written by accessing the address range 00h03h. On an I2C START, or when the address pointer rolls over to 00h, the current value is latched into a register, which is output on the serial data line while the counter continues to increment. When writing to the registers, the divider chain is reset when register 00h is written. Once the divider chain is reset, the remaining clock registers should be written within one second to avoid rollover issues. Additionally, to avoid rollover issues the clock registers must also be written from LSB to MSB, and all four bytes should always be written.
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Model Number Serial Number Byte 0 Serial Number Byte 1 Serial Number Byte 2 Serial Number Byte 3 Serial Number Byte 4 Serial Number Byte 5 CRC
Note: Unless otherwise specified, the states of the registers are undefined when power is first applied. Bits shown as 0 always read back as 0.
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DS1372
Bits 2 and 1: Rate Select (RS[2:1]). These bits control the frequency of the square-wave output when the square wave has been enabled. Table 2 shows the square-wave frequencies that can be selected with the RS bits. These bits are both set (logic 1) when power is first applied. Bit 0: Alarm Interrupt Enable (AIE). When set to a logic 1, this bit permits the alarm flag (AF) to assert SQW/INT (when INTCN = 1). The AIE bit is disabled (logic 0) when power is first applied.
Note: When interrupt operation is enabled, the SQW/INT output is the inverse of the AF bit.
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ID Register
A unique 64-bit lasered serial number is located in the address range 09h10h. This serial number is divided into three parts. The first byte in register 09h contains a model number to identify the DS1372 device type. Registers 0Ah0Fh contain a unique binary number. Register 10h contains a CRC byte used to validate the data in registers 09h0Fh. All eight bytes of the serial number are read-only registers. The CRC byte is generated with the polynomial equal to x8 + x5 + x4 + 1 (see Figure 3). The DS1372 is manufactured such that no two devices contain an identical number in locations 0Ah0Fh.
POLYNOMIAL = X8 + X5 + X4 + 1
1ST STAGE X0
2ND STAGE X1
3RD STAGE X2
4TH STAGE X3 X4
5TH STAGE X5
6TH STAGE X6
7TH STAGE X7
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SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 ACK START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED 1 2 37 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
conditions. The DS1372 operates as a slave on the I2C bus. Connections to the bus are made through the SCL input and open-drain SDA I/O lines. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS1372 works in both modes.
The following bus protocol has been defined (Figure 5): Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals.
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10
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DS1372
<DATA (n + X)
...
XXXXXXXX
S - START SLAVE TO MASTER A - ACKNOWLEDGE (ACK) P - STOP R/W - READ/WRITE OR DIRECTION BIT ADDRESS
S - START MASTER TO SLAVE A - ACKNOWLEDGE (ACK) P - STOP A - NOT ACKNOWLEDGE (NACK) R/W - READ/WRITE OR DIRECTION BIT ADDRESS
DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
<DATA (n + X)>
...
XXXXXXXX
S - START MASTER TO SLAVE Sr - REPEATED START A - ACKNOWLEDGE (ACK) P - STOP A - NOT ACKNOWLEDGE (NACK) R/W - READ/WRITE OR DIRECTION BIT ADDRESS
SLAVE TO MASTER DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
Figure 8. Data Read (Write Pointer, Then Read)Slave Receive and Transmit
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Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
PACKAGE 8-pin SOP DOCUMENT NO. 21-0036
Thermal Information
Thermal Resistance (Junction to Ambient) JA: 221C/W Thermal Resistance (Junction to Case) JC: 39C/W
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