ST7540
ST7540
ST7540
Half-duplex frequency shift keying (FSK) transceiver Integrated power line driver with programmable voltage and current control Programmable mains access: Synchronous Asynchronous Single supply voltage (from 7.5V up to 13.5V) Very low power consumption (Iq = 5mA) Integrates 5V voltage regulator (up to 50mA) with short circuit protection Integrated 3.3V voltage regulator (up to 50mA) with short circuit protection 3.3V or 5V digital supply 8 Programmable transmission frequencies Programmable baud rate up to 4800BPS Receiving sensitivity up to 250VRMS Suitable for applications in accordance with EN 50065 Cenelec specification Carrier or preamble detection Band in use detection Programmable control register Watchdog timer 8 or 16 Bit header recognition ST7537 and ST7538 compatible UART/SPI host interface
HTSSOP28 Exposed Pad
Description
The ST7540 is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and two linear regulators for 5V and 3.3V. The device operation is controlled by means of an internal register, programmable through the synchronous serial interface. Additional functions as watchdog, clock output, output voltage and current control, preamble detection, time-out and band in use are included. Realized in Multipower BCD5 technology that allows to integrate DMOS, Bipolar and CMOS structures in the same chip.
Order codes
Part number ST7540 ST7540TR Package HTSSOP28 (Exposed Pad) HTSSOP28 (Exposed Pad) Packaging Tube Tape and reel
September 2006
Rev 2
1/44
www.st.com 44
Contents
ST7540
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 3.3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 5 6
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ST7540
Contents
8 9
3/44
Block diagram
ST7540
1
Figure 1.
Block diagram
Block diagram
TEST1 TEST2 BU/THERM
CARRIER DETECTION
TEST
BU AGC
PLL
DIGITAL FILTER
FSK DEMOD
IF FILTER
SERIAL INTERFACE
CONTROL REGISTER
FSK MODULATOR
DAC
TX FILTER
ALC
VOLTAGE CONTROL
OSC
TIME BASE
VREG
VREG
+ -
X1
X2
WD
RSTO
MCLK
GND VDD
SVSS Vdc
PA_IN+
PA_IND03IN1407A
4/44
ST7540
Pin settings
2
2.1
Pin settings
Pin connection
Figure 2. Pin connection (top view)
CD_PD REG_DATA GND RxD RxTx TxD BU/THERM CLR/T VDD MCLK RSTO UART/SPI WD PA_IN-
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
TEST2 TEST1 VDC RX_IN CL Vsense X2 X1_OSCIN SVSS TX_OUT PA_IN+ VCC VSS PA_OUT
2.2
Pin description
Table 1. Pin description
N 1 Name CD_PD Type Digital/Output Description Carrier, preamble or frame header detect output. "1" No carrier, preamble or frame header detected "0" Carrier, preamble or frame header detected
2 3 4 5
Mains or control register access selector Digital/Input "1" - Control register access with internal pull-down "0" - Mains access Supply Digital/Output Digital/Input with internal pull-up Digital ground RX data output. Rx or Tx mode selection input. "1" - RX Session "0" - TX Session
TxD
5/44
ST7540
BU/THERM Digital/Output
Band in use/Thermal Shutdown event detection output. In Rx mode: "1" Signal within the programmed band "0" No signal within the programmed band In Tx mode: "1" - Thermal Shutdown event occurred "0" - No Thermal Shutdown event occurred (signal not latched) Synchronous mains access clock or control register access clock Digital supply voltage or 3.3V voltage regulator output Master clock output Power ON or watchdog reset output
8 9 10 11 12
Interface type: Digital/Input 0 - Serial peripheral interface with internal pull-down 1 - UART interface Digital/Input with internal pull-up Analog/Input Power/Output Supply Supply Analog/Input Analog/Output Supply Analog/Output Analog/Input Analog/Input Watchdog input. The internal watchdog counter is cleared on the falling edges. Power line amplifier inverting input Power line amplifier output Power analog ground Power supply voltage Power line amplifier not inverting input Small signal analog transmit output Analog signal ground Crystal oscillator output Crystal oscillator input - or external clock input Output voltage sensing input for the voltage control loop Current limiting feedback. A resistor between CL and SVSS sets the PLI current limiting value. An integrated 80pF filtering input capacitance is present on this pin. Receiving analog input 5V voltage regulator output
13 14 15 16 17 18 19 20 21 22 23
24
CL(2)
Analog/Input
25 26 27 28
Analog/Input Power
Digital/Input Test input. Must be connected to GND. with internal pull-down Analog/Input Test input. Must be connected SVSS
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ST7540
Electrical data
3
3.1
Electrical data
Maximum ratings
Table 2. Absolute maximum ratings
Symbol VCC VDD SVSS/GND VI VO IO Vsense, X2,PA_IN,PA_IN+, CL RX_IN TX_OUT, X1 PA_OUT I(PA_OUT) TA TSTG RxD, PA_OUT Pin Other pins Parameter Power supply voltage Digital supply voltage Voltage between SVSS and GND Digital input voltage Digital output voltage Digital output current Voltage range at Vsense, X2, PA_IN-, PA_IN+, CL Inputs Voltage range at RX_IN input Voltage range at TX_OUT, X1 outputs Voltage range at powered PA_OUT Output Power line driver output current (1) Operating ambient temperature Storage temperature Maximum withstanding voltage range Test condition: CDF-AEC-Q100-002- Human Body Model Acceptance criteria: Normal Performance Value -0.3 to + 14 -0.3 to +5.5 -0.3 to +0.3 GND - 0.3 to VDD +0.3 GND - 0.3 to VDD +0.3 -2 to +2 SVSS - 0.3 to 5.6 -5.6 to 5.6 SVSS - 0.3 to 5.6 VSS - 0.3 to +VCC +0.3 650 -40 to +85 -50 to 150 1750 2000 Unit V V V V V mA V V V V mArms C C V V
3.2
Thermal data
Table 3. Thermal data
Symbol RthJA1 RthJA2
1.
Parameter Maximum thermal resistance junction-ambient steady state (1) Maximum thermal resistance junction-ambient Steady State (2)
Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB
2. It is the same condition of the point above, without any heatsinking surface on the board.
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Electrical data
ST7540
3.3
I(VCC)
650
mArms
Maximum voltage Difference between VCC VCC - VDD and VDD during power-up sequence VPA_OUT Output voltage swing for PA_OUT pin
1.2
VPP
500
mArms
8/44
ST7540
Electrical characteristics
Electrical characteristics
Table 5. Electrical characteristics ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40C TA 85C, TJ < 125C, unless otherwise specified)
Symbol VDD VCC Parameter Digital supply voltages Power supply voltage Transmission & receiving mode (MCLK = 4MHz),no load Transmission & Receiving mode (MCLK = OFF), no load TX mode, no load RX mode Test condition 5V Digital supply provided externally Min. 4.75 7.5 Typ. 5 Max. 5.25 13.5 3.5 Unit V V mA
I(VDD)
1.5 60 5
mA mArms mArms
I(VCC)
Power supply current current with digital supply provided externally Under voltage lock out Threshold on VCC UVLO Hysteresis on VCC
3.7
3.9 340
4.1
V mV
-30% -30%
100 100
+30% +30%
k k
Digital I/O - 5V digital supply VIH VIL VOH VOL High logic level input voltage Low logic level input voltage High logic level output voltage Low logic level output voltage IOH= -2mA IOL= 2mA VDD 0.45 GND + 0.3 2 1.2 V V V V
Digital I/O - 3.3V digital supply VIH VIL High logic level input voltage Low logic level input voltage 1.4 0.8 V V
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Electrical characteristics Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40C TA 85C, TJ < 125C, unless otherwise specified)
Symbol VOH VOL Oscillator External Clock X2 voltage swing External Clock X2 DC voltage level DC Xtal XtalESR XTAL Clock duty cycle Crystal oscillator frequency External oscillator esr resistance External oscillator stabilization capacitance Figure 6 External clock. Figure 4 External clock. Figure 4 External clock. fundamental 40 16 40 5 2.5 60 Parameter High logic level output voltage Low logic level output voltage Test condition IOH= -2mA IOL= 2mA Min. VDD 0.75 GND + 0.4 Typ. Max.
ST7540
Unit V V
Vpp V % MHz
XtalCL Transmitter ITX_OUT VTX_OUT VTX_OUTDC HD2TX_OUT HD3TX_OUT G accuracy GST DRNG CCL
16
pF
Output transmitting current on TX_OUT Max carrier output AC voltage Output DC voltage on TX_OUT Second harmonic distortion on TX_OUT Third harmonic distortion on TX_OUT Accuracy on voltage control loop active ALC gain step control loop gain step ALC dynamic range Input capacitance on CL pin Voltage control loop reference threshold on Figure 17 Vsense pin Hysteresis on voltage loop reference threshold Figure 17 160 VTX_OUT = 2VPP; Fc = 86KHz, no load VTX_OUT = 2VPP; Fc = 86KHz, no load RCL = 0 -1 0.6 1 30 80 RCL = 1.4k Vsense = 0V 1.75 1.7 2.3 2.1
VsenseTH
180
200
mVPK
VsenseHYST
18
mV
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ST7540
Electrical characteristics Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40C TA 85C, TJ < 125C, unless otherwise specified)
Symbol VSENSE Parameter VSENSE Input impedance Current control loop reference threshold on Figure 17 CL pin Hysteresis on current loop reference threshold Figure 17 Figure 21 - 600 Baud Xtal = 16MHz Figure 21- 1200 Baud Xtal = 16MHz Carrier activation time Figure 21- 2400 Baud Xtal = 16MHz Figure 21- 4800 Baud Xtal = 16MHz Carrier stabilization time Figure 21 from STEP 16 to zero Xtal = 16MHz or from step 16 to step 31, Tstep Figure 21 Xtal = 16MHz 400 200 s s 1.80 Test condition Min. Typ. 36 Max. Unit k
CLTH
1.90
2.00
CLHYST
210
250
290
mV
1.6 800
ms s
TRxTx
TALC
3.2
ms
200
Input terminals OFFSET Gain bandwidth product Input resistance at PA_IN+ and PA_INpins Input capacitance at PA_IN+ and PA_INpins Common mode rejection ratio PA_IN+ vs. Vss (1) PA_IN- vs. Vss (1) PA_IN+ vs. Vss (1) PA_IN- vs. Vss (1) 100 1 1
18
mV MHz
M M
RIN
5 5 40
pF pF dB
CIN
CMRR
11/44
Electrical characteristics Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40C TA 85C, TJ < 125C, unless otherwise specified)
Symbol Parameter Test condition VPA_OUT = 5.6VPP , VCC = 12V RLOAD = 30 Carrier frequency: 86KHz Figure 3 VPA_OUT = 5.6VPP , VCC = 12V RLOAD = 30 Carrier frequency: 86KHz Figure 3 Min. Typ. Max.
ST7540
Unit
HD2PA_OUT
-63
dBc
HD3PA_OUT
- 63
dBc
Receiver Input sensitivity (Normal Mode) VIN Input sensitivity (High Sens.) Input sensitivity (TxD line forced to 1) VIN RIN Maximum input signal Input impedance Carrier detection sensitivity (Normal Mode) VCD Carrier detection sensitivity (High Sensitivity Mode) Carrier detection sensitivity (TxD forced to 1) VBU Band in Use Detection Level 80 100 0.5 0.5 250 VBU 2 140 2 2 mVrms Vrms dB/ Vrms Vrms k mVrms
250
Vrms
VBU
83.5
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ST7540
Electrical characteristics Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40C TA 85C, TJ < 125C, unless otherwise specified)
Symbol 5V Voltage regulator VDC Linear regulator output 0 < Io < 50mA 7.5V < VCC < 13.5V voltage -5% 5.05 +5% V Parameter Test condition Min. Typ. Max. Unit
3.3V Voltage regulator VDD Other functions TRSTO TWD Reset time See Figure 23; Xtal = 16MHz 50 125 250 1490 1.5 1 3 125 20 500 1 3 5 300 fclock fclock/2 fclock/4 off 600 1200 2400 4800 500 ms ns ns ms s s ms s s ms ms ms s Linear regulator output 0 < Io < 50mA 7.5V < VCC < 13.5V voltage -5% 3.3 +5% V
Watch-dog pulse width See Figure 23 Minimum value. See Figure 23 Maximum value. See Figure 23 See Figure 23 Control register bit 7 and bit 8 Figure 22
TWM
RxTx 0->1 vs. time out Figure 22 delay Carrier detection time selectable by register CD_PD Propagation delay Master clock output selectable by register Control register bit 9 and bit10 Figure 14 Figure 14 Control register bit 15 and bit 16 See Table 12 Control register bit 3 and bit 4 See Table 12
TCD
TDCD
MCLK
MHz
BAUD
Baud rate
Baud
13/44
Electrical characteristics Table 5. Electrical characteristics (continued) ( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40C TA 85C, TJ < 125C, unless otherwise specified)
Symbol Serial Interface Control register bit 3 and bit 4 (See Figure 13) see Figures 8, 9, 10, 11 & 12 see Figures 8, 9, 10, 11 & 12 see Figures 8, 9, 10, 11 & 12 see Figures 8, 9, 10, 11 & 12 see Figures 8, 9, 10, 11 & 12 see Figures 8, 9, 10, 11 & 12 TB TB/4 TB/4 TH 1667 833 417 208 Parameter Test condition Min. Typ. Max.
ST7540
Unit
TB
Setup time Hold time CLR/T vs. REG_DATA or RxTx CLR/T vs. CLR/T Setup time Hold time
ns ns
Figure 3.
PA_OUT
1uF
Measurement point
14/44
ST7540
SVss
Figure 5. Crystal Resonator
X1
X2
32 pF
32 pF
D03IN1425A
External ClockOFFSET
X2
External ClockSWING
15/44
Functional description
ST7540
6
6.1
Functional description
Carrier frequencies
ST7540 is a multi frequency device: eight programmable Carrier Frequencies are available (see Table 6). Only one Carrier can be used a time. The communication channel could be varied during the normal working Mode to realize a multi frequency communication. Selecting the desired frequency in the Control Register the Transmission and Reception filters are accordingly tuned. Table 6. Channels List
FCarrier F0 F1 F2 F3 F4 F5 F6 F7 (1)
1. Default value
6.2
Baud rates
ST7540 is a multi Baud rate device: four Baud Rate are available (See Table 8). Table 7. ST7540 mark and space tones frequency distance Vs. baud rate and deviation
Baud Rate [Baud] 600 1200 2400 (4) 4800
1. Frequency deviation 2. Deviation = F / (Baud Rate) 3. Deviation 0.5 not allowed 4. Default value
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ST7540
Functional description
6.3
Deviation
Deviation
17/44
ST7540
6.4
The choice between the two types of access can be performed by means of Control Register bit 14(see Table 12) and affects the ST7540 data flow in Transmission Mode as in Reception Mode (for how to set the communication Mode, see Section 6.5).
Synchronous Mains access: on clock signal provided by ST7540 (CLR/T line) rising edge, data transmission line (TxD line) value is read and sent to the FSK Modulator. ST7540 manages the Transmission timing according to the BaudRate Selected. Asynchronous Mains access: data transmission line (TxD line) value enters directly to the FSK Modulator. The Host Controller manages the Transmission timing (CLR/T line should be neglected).
Synchronous Mains access: on clock signal recovered by a PLL from ST7540 (CLR/T line) rising edge, value on FSK Demodulator is read and put to the data reception line (RxD line). ST7540 recovers the bit timing timing according to the BaudRate Selected. Asynchronous Mains access: Value on FSK Demodulator is sent directly to the data reception line (RxD line). The Host Controller recovers the communication timing (CLR/T line should be neglected).
18/44
ST7540
Functional description
6.5
Data Reception Data Transmission Control Register Read Control Register Write
REG_DATA and RxTx lines are level sensitive inputs. Table 9. Data and Control register access bits configuration
REG_DATA Data Transmission Data Reception Control Register Read Control Register Write 0 0 1 1 RxTx 0 1 1 0
SPI UART
The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to 0 SPI interface is selected while if UART/SPI pin is forced to 1 UART interface is selected. The type of interface affects the Data Reception by setting the idle state of RxD line. When ST7540 is in Receiving mode (REG_DATA=0 and RxTx =1) and no data are available on mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the RxD line is forced to 0 when UART/SPI pin is forced to 0 or it is forced to 1 when UART/SPI pin is forced to 1. The UART interface allows to connect an UART compatible device while SPI interface allows to connect an SPI compatible device. The allowed combinations of Host Interface/ST7540 Mains Access are: Table 10. Host interface / ST7540 mains access combinations
Host device interface type UART UART SPI SPI 1 1 0 0 UART/SPI pin Communication mode Transmission Reception Transmission Reception Mains access Asynchronous X X X X Synchronous
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Host Controller
ST7540
Host Controller
D03IN1415
ST7540
ST7540 allows to interface the Host Controller using a five line interface (RxD,TxD,RxTx, CLR/T, & REG_DATA) in case of Synchronous mains access or using a 3 line interface (RxD,TxD & RxTx) in Asynchronous mains access. Since Control Register is not accessible in Asynchronous mode, in this case REG_DATA pin must be tied to GND.
6.5.1
Asynchronous mode: In Asynchronous Mode, data are exchanged without any data Clock reference. The host controller has to recover the clock reference in receiving Mode and control the Bit time in transmission mode. If RxTx line is set to 1 & REG_DATA=0 (Data Reception), ST7540 enters in an Idle State. After Tcc time the modem starts providing received data on RxD line. If RxTx line is set to 0 & REG_DATA=0 (Data Transmission), ST7540 enters in an Idle State and transmission circuitry is switched on. After Tcc time the modem starts transmitting data present on TxD line.
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ST7540
Functional description
Synchronous mode: In Synchronous Mode ST7540 is always the master of the communication and provides the clock reference on CLR/T line. When ST7540 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge. When ST7540 is in transmitting mode the clock reference is internally generated and TxD line is sampled on CLR/T rising Edge. If RxTx line is set to 1 & REG_DATA=0 (Data Reception), ST7540 enters in an Idle State and CLR/T line is forced Low. After Tcc time the modem starts providing received data on RxD line. If RxTx line is set to 0 & REG_DATA=0 (Data Transmission), ST7540 enters in an Idle State and transmission circuitry is switched on. After Tcc time the modem starts transmitting data present on TxD line (Figure 8) .
Figure 7.
CLR/T
CLR/T
RxD
TxD
D03IN1416
TS TH
Figure 8.
CLR_T TDS RxD REG_DATA
TCR
TxD
D03IN1402
21/44
Functional description
ST7540
6.5.2
BIT23
REG_DATA
RxTx
D03IN1404
Figure 10. data reception control register write data reception timing diagram
TCC CLR_T TDS RxD TCR REG_DATA TCR RxTx TSTH TxD BIT23 BIT22
D03IN1403
TCC TB
TDH
TCR
TCR
22/44
ST7540
Functional description Figure 11. Data transmission control register read data reception timing diagram
TCC CLR_T TB RxD BIT23 TDS TDH TDS TDH TCC
BIT22
REG_DATA
TCR
TCR
Figure 12. Data transmission control register write data reception timing diagram
TCC CLR_T TB TxD TSTH BIT23 BIT22 TCR TSTH REG_DATA TCR TCR RxTx TDS RxD
D03IN1401
TCC
TDH
6.6
Receiving mode
The receive section is active when RxTx Pin =1 and REG_DATA=0. The input signal is read on RX_IN Pin using SVSS as ground reference and then pre-filtered by a Band pass Filter (62kHz max bandwidth at -3dB). The Pre-Filter can be inserted setting one bit in the Control Register. The Input Stage features a wide dynamic range to receive Signal with a Very Low Signal to Noise Ratio. The Amplitude of the applied waveform is automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (14kHz max at -3dB). The resulting signal is down-converted by a mixer using a sinewave generated by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter) improves the Signal to Noise ration before sending the signal to the FSK demodulator. The FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal Jitter. RxD Line is forced to 0 or 1 (according the UART/SPI pin level) when neither mark or space frequencies are detected on RX_IN Pin. Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct demodulation. While ST7540 is in Receiving Mode (RxTx pin =1), the transmit circuitry, Power Line Interface included, is turned off. This allows the device to achieve a very low current consumption (5mA typ).
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Functional description
ST7540
Receiving Sensitivity Level Selection It is possible to select the ST7540 Receiving Sensitivity Level by Control Register (see Table 12) or setting to 1 the TxD pin during reception phase (this condition overcomes the control register setting the sensitivity equal to BU threshold). Increasing the device sensitivity allows to improve the communication reliability when the ST7540 sensitivity is the limiting factor. Synchronization Recovery System (PLL) ST7540 embeds a Clock Recovery System to feature a Synchronous data exchange with the Host Controller. The clock recovery system is realized by means of a second order PLL. In Synchronous mode, data on the data line (RxD) are stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions LOCK-IN Range). The PLL Lock-in and Lock-out Range is /2. When the PLL is in the unlock condition RxD line is forced to 0 or 1 according to the UART/SPI pin level and CLR/T is forced to 0 only if the Detection Method Preamble Detection With Conditioning is selected.When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the CLR/T Jitter. ST7540 PLL is forced in the un-lock condition, when more than 32 equal symbols are received.Due to the fact that the PLL, in lock-in condition, is sensitive only to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL into the un-lock condition.
CLR/T
RxD
D03IN1417
LOCK-IN RANGE
Carrier/Preamble Detection The Carrier/Preamble Block is a digital Frequency detector Circuit. It can be used to manage the MAINS access and to detect an incoming signal. Two are the possible setting: Carrier Detection Preamble Detection
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ST7540
Functional description
Carrier Detection The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RX_IN Input a signal with an harmonic component close to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode). When the device sensitivity is set by the TxD line (Sensitivity level equal to BU threshold) the CD_PD signal is conditioned to the BU signal. The CD_PD line is forced to a logic level low when a Carrier is detected. Preamble Detection The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols (1010 or 0101 are the symbols sequences detected). CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range. To reinforce the effectiveness of the information given by CD_PD Block, a digital filtering is applied on Carrier or Preamble notification signal (see Section 6.8: Control register). The Detection Time Bits in the Control Register define the filter performance. Increasing the Detection Time reduced the false notifications caused by noise on main line. The Digital filter adds a delay to CD_PD notification equal to the programmed Detection Time. When the carrier frequency disappears, CD_PD line is held low for a period equal to the detection time and then forced high. During this time, some spurious data caused by noise can be demodulated and sent over RxD line.
Header Recognition In Control Register Extended Mode (Control Register bit 21=1, see Table 12) the CD_PD line can be used to recognize if an header has been sent during the transmission. With Header Recognition function enable (Control Register bit 18=1, see Table 12), CD_PD line is forced low when a Frame Header is detected. If Frame Length Count function is enabled, CD_PD is held low and a number of 16 bit word equal to the Frame Length selected is sent to the host controller. In this case, CLR/T is forced to 0 and RxD is forced to 0 or 1 (according the UART/SPI pin level) when Header has not been detected or after the Frame Length has been reached. If Frame Length Count function is disabled, an header recognition is signaled by forcing CD_PD low for one period of CLR/T line. In this case, CLR/T and RxD signal are always present, even if no header has been recognized.
25/44
ST7540
CD_PD
RX_IN
RxD (UART/SPI="0")
noise demodulated
D03IN1418
Bits 9-10
BAND IN USE
D03IN1419
6.7
Transmission mode
The transmission mode is set when RxTx Pin =0 and REG_DATA Pin =0. In transmitting mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data (TxD) enter synchronously or asynchronously to the FSK modulator.
Synchronous Mains access: on CLR/T rising edge, TxD Line Value is read and sent to the FSK Modulator. ST7540 manages the Transmission timing according to the BaudRate Selected Asynchronous Mains access: TxD data enter directly to the FSK Modulator.The Host Controller manages the Transmission timing
In both conditions no Protocol Bits are added by ST7540. The FSK frequencies are synthesized in the FSK modulator from a 16 MHz crystal oscillator by direct digital synthesis technique. The frequencies Table in different Configuration is reported in Table 8. The frequencies precision is same as external crystal ones.
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ST7540
Functional description In the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. The transition between a symbol and the following is done at the end of the on-going half FSK sinewave cycle. Figure 16. Transmitting path block diagram
Bits 7-8 Bits 17 & 21 VOLTAGE LOOP THERMAL SENSOR TIMER CURRENT LOOP Bit 14 TxD 6 DAC Band Pass D-TYPE FLIP FLOP CLR/T 8 FSK MODULATOR TRANSMISSION FILTER 14 18 19 PA_INPA_IN+ TX_OUT ALC Bits 0-5 Bits 0-2 24 CL 23 Vsense
BU/THERM
+ PA
15
PA_OUT
CLR/T GENERATOR
D03IN1420
Automatic Level Control (ALC) The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ). Two are the control loops acting to define the ALC gain: A Voltage Control loop A Current Control Loop
The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense. The gain adjustment is related to the result of a peak detection between the Voltage waveform on Vsense and two internal Voltage references. It is possible to protect the Voltage Control Loop against noise by freezing the output level (see Section 7.5: Output voltage level freeze). If Vsense < VsenseTH - VsenseHYST If Vsense > VsenseTH + VsenseHYST The next gain level is increased by 1 step The next gain level is decreased by 1 step
27/44
Functional description
ST7540
The Current control loop acts to limit the maximum Peak Output current inside PA_OUT. The current control loop acts through the voltage control loop decreasing the Output Peak-to-Peak Amplitude to reduce the Current inside the Power Line Interface. The current sensing is done by mirroring the current in the High side MOS of the Power Amplifier (not dissipating current Sensing). The Output Current Limit (up to 500mrms), is set by means of an external resistor (RCL) connected between CL and VSS. The resistor converts the current sensed into a voltage signal. The Peak current sensing block works as the Output Voltage sensing Block: If V(CL) < CLTH - CLHYSTVoltage Control Loop Acting If CLTH - CLHYST < V(CL) < CLTH + CLHYSTNo Gain Change If V(CL) > CLTH + CLHYSTThe next gain level is decreased by 1 step
Figure 17 shows the typical connection of Current anVoltage control loops. Figure 17. Voltage and current feedback external interconnection example
ALC
PA_OUT/TX_OUT
Vout
VoutPK
R1 VOLTAGE LOOP Vsense 10nF R2 VsenseHYST VsenseTH CURRENT LOOP 80pF typ. CL RCL AVss VCLHYST VCLTH 1.865V (Typ)
D03IN1421
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Functional description
R2 (K) 7.5 5.1 3.6 3.3 3.3 2.7 2.0 1.6 1.6 1.6
R1 (K) 1.0 3.9 5.6 8.2 11.0 12.0 11.0 10.0 13.0 15.0
Note:
Notes: The rate of R2 takes in account the input resistance on the VSENSE pin (36K). 10nF capacitor effect has been neglected. Figure 18. Typical output current vs RCL
Irms (mA)
1220 1120 1020 920 820 720 620 520 420 320 220 120 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1
D01IN1311
Rcl(k)
Integrated Power Line Interface (PLI) The Power Amplifier (PA) is a CMOS AB Class Power Amplifier. The PA requires, to ensure a proper operation, a regulated and well filtered Supply Voltage. Vcc Voltage and PA_OUT Voltage must fulfil the following formulas to work without clipping phenomena:
( AC ) V CC VPAOUT --------------------------------------- + VPOUT ( DC ) + 3V 2
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Functional description
ST7540
V
Vcc
3V
VPA_OUT(AC)
1.5V
VPA_OUT(DC)
Vss
t
D03IN1425
Inputs and outputs of PA are available on pins PA_IN-,PA_IN+ and PA_OUT. User can easily select an appropriate active filtering topology to filter the signal present on TX_OUT pin. TX_OUT output has a current capability much lower than PA_OUT.
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Functional description
PA_IN-
Z2 Z1
PA_OUT PA_IN+
AC LINE R3 TX_OUT ALC R4 Vss R1 VOLTAGE LOOP Vsense R2 CURRENT LOOP 80pF typ. CL RCL
D03IN1422
TX_OUT
0V STEP NUMBER 16 17 18 31
D03IN1408
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Functional description
ST7540
6.8
Control register
The ST7540 is a multi-channel and multifunction transceiver. An internal 24 or 48 Bits (in Extended mode) Control Register allows to manage all the programmable parameters (Table 12). The programmable functions are:
Channel Frequency Baud Rate Deviation Watchdog Transmission Timeout Frequency Detection Time Detection Method Mains Interfacing Mode Output Clock Sensitivity Mode Input Pre-Filter
In addition to these functions the Extended mode provides 24 additional bits and others functions:
Output Level Freeze Frame Header Recognizes (one 16 bits header of or two 8 bits headers) with support to Frame Length Bit count
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ST7540
Functional description
0 to 2
Frequencies
132.5 kHz
2400
1 sec
1 ms
11
Reserved
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ST7540
Default
Bit 14 14 Mains Interfacing Mode Synchronous Asynchronous Bit 16 16 MHz 8 MHz 4 MHz Clock OFF 0 0 1 1 Bit 17 17 Output Voltage Level Freeze Enabled Disabled 0 1 Bit 18 18 Header Recognition Disabled Enabled 0 1 Bit 19 19 Frame Length Count Disabled Enabled 0 1 Active only if extended control register is enable (Bit 21=1) Active only if header recognition function (Bit 18=1) and extended control register (Bit 21=1) are enable Disabled Active only if extended control register is enable (Bit 21=1) Disabled 0 1 Bit 15 0 1 0 1 Asynchronous
15 to 16
Output Clock
4 MHz
Disabled
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Functional description
Default
Active only if Extended Control Register is enable (Bit 21=1) Extended Register enables Functions on Bit 17, 18,19 and 20
16 bits
Normal
Disabled One 16 bits Header or two 8 bits Headers (MSB first) depending on Bit 20 Number of 16 bits words expected
24 to 39
9B58h
40 to 47 Frame Length
08h
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ST7540
7
7.1
7.2
Time out
Time Out Function is a protection against a too long data transmission. When Time Out function is enabled after 1 or 3 second of continuos transmission the transceiver is forced in receiving mode. This function allows ST7540 to automatically manage the CENELEC Medium Access specification. When a time-out event occur, the transmission section is disabled for at least 125 ms. To Unlock the Time Out condition RxTx should be forced High. During the time out period only register access or reception mode are enabled. During Reset sequence if RxTx line =0 & REG_DATA line =0, Time Out protection is suddenly enabled and ST7540 must be configured in data reception after the reset event before starting a new data transmission. Time Out time is programmable using Control Register bits 7 and 8 (Table 12). Figure 22. Time-out timing and unlock sequence
RxTx TOUT Time Out function
D03IN1409
TOFF TOFFD
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ST7540
7.3
RSTO TWD WD
TWM
D03IN1410
7.4
Output clock
MCLK is the master clock output. The clock frequency sourced can be programmed through the Control Register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4). The transition between one frequency and another is done only at the end of the ongoing cycle. The oscillator can be disabled using Control Register bits 15 and 16 (Table 12).
7.5
7.6
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ST7540
7.7
7.8
Thermal shutdown
The ST7540 is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170C 10% . Hysteresis is around 30C. When shutdown threshold is overcome, PLI interface is switched OFF. Thermal Shutdown event is notified to the HOST controller using BU/THERM line. When BU/THERM line is High, ST7540 junction temperature exceed the shutdown threshold (Not Latched). This function is enabled only in Transmission mode (in Receiving mode the BU/THERM pin is used for Band in Use signaling, see Band in Use function Section 7.1: Band in use).
7.9
5V Voltage regulator
ST7540 has an embedded 5V linear regulator externally available (on pin VDC) to supply the application circuitry. The 5V linear regulator has a very low quiescent current (50A) and a current capability of 50mA. The regulator is protected against short circuitry events.
7.10
7.11
Power-up procedure
To ensure ST7540 proper power-Up sequence, VCC and VDD Supply has to fulfil the following rules: 1. 2. VCC rising slope must not exceed 100V/ms. When VDD is below 5V/3.3V: VCC-VDD < 1.2V.
When VDD supply is connected to VDC (5V Digital Supply) the above mentioned relation can be ignored if VDC load < 50mA and if the filtering capacitor on VDC < 100uF. If VDD is not forced to 5V, the Digital I/Os are internally supplied at 3.3 V and if VDD load < 50mA and the filtering capacitor on VDD < 100uF the second relation can be ignored .
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VCC
5V/3.3V
VDD
VCC-VDD
D03IN1424
Time
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VDC 26 17 Z2 Z1 15 PA_IN+ 28 27 25 13 TX_OUT 19 R4 R3 AC LINE RX_IN 18 PA_OUT No External Components for POWER LINE DRIVER VCC AC/DC Converter SINGLE SUPPY 20 SVss 14 VDD 9 PA_INWD
TEST2
TEST1
BU/THERM 7
ST7540
16
VSS R1 C1
CD/PD
CLR/T
R2
REG/DATA
MCLK
RSTO
X1_OSCIN
ST7540
D03IN1412A
ST7540
Mechanical data
Mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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ST7540
1.0
0.039
9.7
9.8
0.382
0.385
6.4 4.4
6.6 4.5
0.244 0.169
0.252 0.173
0.260 0.177
0.004
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ST7540
Revision history
Revision history
Table 14. Revision history
Date 15-Mar-2006 25-Sep-2006 Revision 1 2 Initial release. Updated Electrical Characteristics and Power Amplifier description Changes
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ST7540
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