A complete basic tutorial of 555 Timer IC.

This article covers every basic aspect of 555 Timer IC. You may already know that SE !E 555 is a Timer IC introduced by Si"netics corporation in #$%&'s. In this article we cover the followin" information about 555 Timer IC.

#. Introduction to 555 Timer IC (. 555 Timer IC )in Confi"uration *. +asics of 555 Timer ,. +lock -ia"ram 5. .orkin" )rinciple

#. Introduction
555 timer IC /ne of the most versatile linear ICs is the 555 timer which was first introduced in early #$%& by Si"netic Corporation "ivin" the name as SE !E 555 timer. This IC is a monolithic timin" circuit that can produce accurate and hi"hly stable time delays or oscillation. 0ike other commonly used op1amps2 this IC is also very much reliable2 easy to use and cheaper in cost. It has a variety of applications includin" monostable and astable multivibrators2 dc1dc converters2 di"ital lo"ic probes2 waveform "enerators2 analo" fre3uency meters and tachometers2 temperature measurement and control devices2 volta"e re"ulators etc. The timer basically operates in one of the two modes either as a monostable 4one1shot5 multivibrator or as an astable 4free1runnin"5 multivibrator.The SE 555 is desi"ned for the operatin" temperature ran"e from 6 557C to #(57 while the !E 555 operates over a temperature ran"e of &7 to %&7C.

The important features of the 555 timer are 8

It operates from a wide ran"e of power supplies ran"in" from 9 5 :olts to 9 #; :olts supply volta"e. Sinkin" or sourcin" (&& mA of load current. The e<ternal components should be selected properly so that the timin" intervals can be made into several minutes )roper selection of only a few e<ternal components allows timin" intervals of several minutes alon" with the fre3uencies e<ceedin" several hundred kilo hert=. It has a hi"h current output> the output can drive TT0. It has a temperature stability of 5& parts per million 4ppm5 per de"ree Celsius chan"e in temperature2 or e3uivalently &.&&5 ? 7C. The duty cycle of the timer is ad@ustable with the ma<imum power dissipation per packa"e is A&& m. and its tri""er and reset inputs are lo"ic compatible.

(. IC )in Confi"uration
The 555 Timer IC is available as an ;1pin metal can2 an ;1pin mini -I) 4dual1in1packa"e5 or a #,1pin -I). This IC consists of (* transistors2 ( diodes and #A resistors. The e<planation of terminals comin" out of the 555 timer IC is as follows. The pin number used in the followin" discussion refers to the ;1pin -I) and ;1pin metal can packa"es. )in #8 Brounded Terminal8 All the volta"es are meas ured with respect to this terminal. )in (8 Tri""er Terminal8 This pin is an invertin" input to a comparator that is responsible for transition of flip1 flop from set to reset. The output of the timer depends on the amplitude of the e<ternal tri""er pulse applied to this pin.

)in *8 /utput Terminal8 /utput of the timer is avail able at this pin. There are two ways in which a load can be connected to the output terminal either between pin * and "round pin 4pin #5 or between pin * and supply pin 4pin ;5. The load connected between pin * and "round supply pin is called the normally on load and that connected between pin * and "round pin is called the normally off load. )in ,8 Ceset Terminal8 To disable or reset the timer a ne"ative pulse is applied to this pin due to which it is referred to as reset terminal. .hen this pin is not to be used for reset purpose2 it should be connected to 9 : CC to avoid any possibility of false tri""erin". )in 58 Control :olta"e Terminal8 The function of this terminal is to control the threshold and tri""er levels. Thus either the e<ternal volta"e or a pot connected to this pin determines the pulse width of the output waveform. The e<ternal volta"e applied to this pin can also be used to modulate the output waveform. .hen this pin is not used2 it should be connected to "round throu"h a &.&# micro Darad to avoid any noise problem. )in A8 Threshold Terminal8 This is the non1invertin" input terminal of comparator #2 which compares the volta"e applied to the terminal with a reference volta"e of ( * :CC. The amplitude of volta"e applied to this terminal is responsible for the set state of flip1flop. )in % 8 -ischar"e Terminal8 This pin is connected internally to the collector of transistor and mostly a capacitor is connected between this terminal and "round. It is called dischar"e terminal because when transistor saturates2 capacitor dischar"es throu"h the transistor. .hen the transistor is cut1off2 the capacitor char"es at a rate determined by the e<ternal resistor and capacitor. )in ;8 Supply Terminal8 A supply volta"e of 9 5 : to 9 #; : is applied to this terminal with respect to "round 4pin #5.

*. 555 Timer +asics

The 555 timer combines a rela<ation oscillator2 two comparators2 an C1S flip1flop2 and a dischar"e capacitor. C1S Dlip1Dlop8 6 A pair of cross1coupled transistors is shown in fi"ure. Each collector drives the opposite base throu"h resistance C+. In such circuit one transistor is saturated while the other is cut1off. Dor instance2 if transistor E # is saturated2 its collector volta"e is almost =ero. So there is no base drive for transistor E( and it "oes into cut1off and its collector volta"e approaches 9 :CC. This hi"h volta"e produces enou"h base current to keep transistor E# in saturation. /n the other hand if transistor E# is cut1off2 its collector volta"e2 which is appro<imately e3ual to 9 :CC2 drives the transistor E( into saturation. The low collector volta"e 4which is appro<imately to =ero5 of this transistor then keeps the transistor E( in cut1off.-ependin" on which transistor is saturated2 the E output is either low or hi"h . +y addin" more components to the circuit2 an C1S flip1flop is obtained. C1S flip1flop is a circuit that can set the E output to hi"h or reset it low. Incidentally2 a complementary 4opposite5 output E is available from the collector of the other transistor. Di"ure shows the schematic symbol for an C1S flip1flop of any desi"n. The circuit latches in either two states. A hi"h S input sets E to hi"h> a hi"h C input resets E to low. /utput E remains in a "iven state until it is tri""ered into the opposite state.

+asic Timin" Concept

Di"ure illustrates some basic ideas that will prove useful in comin" blo" posts of the 555 timer. Assumin" output E hi"h2 the transistor is saturated and the capacitor volta"e is clamped at "round i.e. the capacitor C is shorted and cannot char"e. The non1invertin" input volta"e of the comparator is referred to as the threshold voltage while the invertin" input volta"e is referred to as the control voltage. .ith C1S flip flop set2 the saturated transistor holds the threshold volta"e at =ero. The control volta"e2 however2 is fi<ed at ( * :CC 4i.e. at #& :5 because of the volta"e divider. Suppose that a hi"h volta"e is applied to the C input. This resets the flip1flop C1/utput E "oes low and the transistor is cut1off. Capacitor C is now free to char"e. As this capacitor C char"es2 the threshold volta"e rises. Eventually2 the threshold volta"e becomes sli"htly "reater than 49 #& :5. The output of the comparator then "oes hi"h, forcin" the C S flip1flop to set. The hi"h E output saturates the transistor2 and this 3uickly dischar"es the capacitor. The two waveforms are depicted in fi"ure . An e<ponential rise is across the capacitor C2 and a positive "oin" pulse appears at the output E. Thus capacitor volta"e : C is e<ponential while the output is rectan"ular2 as illustrated in fi"ure.

,. +lock -ia"ram
+lock -ia"ram 1555 Timer The block dia"ram of a 555 timer is shown in the above fi"ure. A 555 timer has two comparators2 which are basically ( op1amps52 an C1S flip1flop2 two transistors and a resistive network. Cesistive network consists of three e3ual resistors and acts as a volta"e divider. Comparator # compares threshold volta"e with a reference volta"e 9 ( * :CC volts. Comparator ( compares the tri""er volta"e with a reference volta"e 9 # * :CC volts. /utput of both the comparators is supplied to the flip1flop. Dlip1flop assumes its state accordin" to the output of the two compa rators. /ne of the two transistors is a dischar"e transis tor of which collector is connected to pin %. This tran sistor saturates or cuts1off accordin" to the output state of the flip1flop. The saturated transis tor provides a dischar"e path to a capacitor con nected e<ternally. +ase of another transistor is connected to a reset terminal. A pulse applied to this terminal resets the whole timer irrespective of any input.

5. .orkin" )rinciple
Cefer +lock -ia"ram of 555 timer IC "iven above8 Comparator # has a threshold input 4pin A5 and a control input 4pin 55. In most applications2 the control input is not used2 so that the control volta"e e3uals 9( * :CC. /utput of this comparator is applied to set 4S5 input of the flip1flop. .henever the threshold volta"e e<ceeds the control volta"e2 comparator # will set the flip1flop and its output is hi"h . A hi"h output from the flip1flop saturates the dischar"e transistor and dischar"e the capacitor connected e<ternally to pin %. The complementary si"nal out of the flip1flop "oes to pin *2 the output. The output available at pin * is low. These conditions will prevail until comparator ( tri""ers the flip1flop. Even if the volta"e at the threshold input falls below ( * :CC2that is comparator # cannot cause the flip1flop to chan"e a"ain. It means that the

comparator # can only force the flip1flopFs output hi"h. To chan"e the output of flip1flop to low, the volta"e at the tri""er input must fall below 9 # * :cc. .hen this occurs2 comparator ( tri""ers the flip1flop2 forcin" its output low. The low output from the flip1flop turns the dischar"e transistor off and forces the power amplifier to output a hi"h. These conditions will continue independent of the volta"e on the tri""er input. Comparator ( can only cause the flip1flop to output low. Drom the above discussion it is concluded that for the havin" low output from the timer 5552 the volta"e on the threshold input must e<ceed the control volta"e or 9 ( * :CC. They also turn the dischar"e transistor on. To force the output from the timer hi"h2 the volta"e on the tri""er input must drop below 9# * :CC. This also turns the dischar"e transistor off. A volta"e may be applied to the control input to chan"e the levels at which the switchin" occurs. .hen not in use2 a &.&# nano Darad capacitor should be connected between pin 5 and "round to prevent noise coupled onto this pin from causin" false tri""erin". Connectin" the reset 4pin ,5 to a lo"ic low will place a hi"h on the output of flip1flop. The dischar"e transistor will "o on and the power amplifier will output a low. This condition will continue until reset is taken hi"h. This allows synchroni=ation or resettin" of the circuitFs operation. .hen not in use2 reset should be tied to 9:CC.