International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: [email protected] Volume 3, Issue 3, March 2014 ISSN 2319 - 4847

Implementation of 2.4 GHz Phase Locked Loop using Sigma Delta Modulator
Chaitali P.Charjan1, Asso.Prof.Atul S.Joshi2
1

PG student, Department of Electronics & Telecommunication, Sipnas college of Engineering & Technology, Amravati, Maharashtra, India

Associate Professor, Department of Electronics & Telecommunication, Sipnas college of Engineering & Technology, Amravati, Maharashtra, India

Abstract
Phase locked loops are widely used now a days in digital frequency synthesis for most RF transceivers. So, there is great need of fine resolution and low power consumption PLLs. Therefore a modified version of PLL i.e. a fractional-N phase locked loop frequency synthesizer is discussed in this paper which achieves fine resolution and large loop bandwidth .This paper presents the design and simulation of a fractional-N phase locked loop frequency synthesizer by making the use of sigma-delta modulator for bluetooth systems with a frequency range from 2402 to 2480 MHz .The most important factors in improving the performance of fractional-N phase locked loop are loop filter and Sigma-Delta modulator. Phase noise is introduced by fractional division operation which is removed by noise shaping done by the digital Sigma-Delta modulator, while the loop filter bandwidth limits the speed of switching time between the synthesized frequencies. Simulation results show that the system is stable even if the voltage is varied and the fractional spurs in the output spectrum of the fractional-N phase locked loop are absent.

Keywords: Phase locked loop (PLL), voltage-controlled oscillator (VCO), 45nm technology, VLSI technology, sigma delta modulator, low power.

1. INTRODUCTION
1.1 Phase Locked Loop- A phase locked loop (PLL) is widely applied for different purposes in various domains such as communication and instrumentation. In the microwave range they have been applied in frequency synthesis and phase recovering among others. Phase-locked loop can be used to maintain a well-defined phase, and hence frequency relation between two independent signal sources A phase locked loop (PLL) is used for different purposes in various sectors such as communication and instrumentation. In the microwave range they are used in frequency synthesis and phase recovering among others. A phase-locked loop can be used to maintain a well-defined phase and hence frequency relation between two independent signal sources, Basic PLL consists of three elements: a phase detector, a loop filter and a voltage controlled oscillator (VCO) as shown in figure.

Figure 1. Block diagram of PLL A phase locked loop is divided into two architectures namely, an integer-N Phase Locked Loop and a fractional-N Phase Locked Loop. The basic problem with the integer-N PLL is the trade-off between the channel spacing and the loop bandwidth. A small reference frequency (Fref) is desirable for small channel spacing or high frequency resolution, but using a small reference frequency leads to two main problems. First, reduction in reference frequency causes an increase in the phase noise because of the high division ratio. Second, the loop bandwidth must be smaller than the reference frequency (fB.W0.1 Fref) , for the requirement of stability, so, a low reference frequency means a small loop bandwidth. This in turn results in slow switching time. The trade-off problems found in the integer-N PLL is removed by the fractional N-PLL, thus, offering a higher frequency resolution, lower phase noise, and a larger loop bandwidth. A large loop bandwidth means a faster switching time. The output frequency of the fractional-N PLL is given by the formula fout = (N.)* Fref, where N is an integer, and is the fractional part. A dual modulus divider is used to average many integer divider cycles over time to obtain the desired fractional division ratio. A simple digital accumulator with an overflow controlling the dual modulus divider can be used to get the fractional ratio. The main problem associated with this method is that, the periodic operation of the dual modulus divider generates fractional spurs. The first fractional spur is located at (. Fref); if these spurs appear inside the loop bandwidth, this

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International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: [email protected] Volume 3, Issue 3, March 2014 ISSN 2319 - 4847

problem can be solved by reducing the loop bandwidth, but this will in turn increase the switching time. The best method to remove the fractional spurs is by breaking the periodicity of the dual modulus operation without affecting the loop bandwidth, which is realized by using a Sigma-Delta Modulator as the Sigma-Delta modulator changes the division ratio between more than two values, so the spurs will spread over the spectrum. The Sigma-Delta modulator generates a random integer number with an average equal to the desired fractional ratio while shaping the quantization noise and pushes the spurious contents to the higher frequencies and then the spurious contents are removed by the loop filter action. 1.2Sigma-Delta Fractional-N PLL Frequency Synthesizer The PLL consist of Low pass filter, charge pump, voltage controlled oscillator and sigma delta modulator. Phase detector is a comparator that compares the input frequency with output frequency of VCO and generates a d.c voltage that is proportional to the phase difference between the two frequencies. The low pass filter removes the high frequency components from the output of the phase detector. This low pass filter controls other characteristics of the PLL including bandwidth, capture range, lock range and transient response. The VCO is commonly used to generate clock in phase locked loop circuits. This work consists of additional sigma delta modulator block with fractional input. The input of sigma-delta modulator is the desired fractional division number (), where the output consists of a DC component y[n] that is proportional to the input () plus the quantization noise introduced due to using integer divider instead of ideal fractional divider. The frequency divider divides the output frequency of the VCO by Nint +y[n], where Nint is an integer value and y[n] is the output sequence of the modulator.

Figure2. Fractional N-PLL using Sigma Delta Modulator

2. Methodology:
2.1 VLSI Technology Phase locked loop is an electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e. lock) on the frequency of an input or reference signal. It is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. PLL is an electronic circuit consisting of a phase detector and variable frequency oscillator. This circuit makes the comparison between the phase of the input signal and the phase of the signal derived from its output oscillator and adjusts the frequency of its oscillator for keeping the phases matched. The basic PLL can be analog or digital. A good review of PLLs from a control engineering perspective can be found in various references. Thus the work describes the basic component of the PLL and how to build and analyze the proposed PLL using 45 nm VLSI technology. 2.2 45 nm VLSI Technology VLSI is dominated by the CMOS technology and much like other logic families, this too has its limitations which have been battled and improved over past years. Taking the example of a processor, the process or technology has rapidly shrunk from 180 nm in 1999 to 60nm in 2008 and now it stands at 45nm and attempts are being made to reduce it further. As the transistors increase in number, the power dissipation is increased and also the noise. If heat generated per unit area is to be considered, the chip heat dissipation has already reached to the nozzle of a jet engine. At the same time, the voltage scaling of threshold voltages beyond a certain point poses serious limitations in providing low dynamic power dissipation with increased complexity. The number of metal layers and the interconnects be it global and local also tend to get messy at such nano levels. More simplified view of the VLSI technology consists of various representations, abstractions of design, logic circuits, CMOS circuits and physical layout. Here for the design using VLSI technology microwind 3.1 VLSI backend software is used.

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The proposed PLL is designed using 45 nm CMOS/VLSI technology in microwind 3.1. The main novelties related to the 45 nm technology are very low-k interconnect dielectric, the high-k gate oxide and metal gate. The effective gate length required for 45 nm technology is 25nm. The microwind 3.1 software allows designing and simulating at physical description level. Low leakage transistors will be used for low power and will Compromise on little bit frequency. Table1. Key Features of 45 nm Technology Sr. No. Parameter Value VDD (V) 0.40 -1.2 V. 1 Ioff N (nA/m) 5-100 (nA/m) 2 Ioff P (nA/m) 5-100 (nA/m) 3 Gate dielectric SiON, HfO2 4 No. of metal layers 6-8 5 Compared to 65-nm technology, 45 nm technology must offer: 30% increases in switching performance 30 % reduction in Power consumption 2 times higher density 2 times reduction of the leakage between source and drain and through the gate oxide. Considering the advantage of 45 nm technologies over 90 nm & 65 nm technologies, the proposed work is implemented using 45 nm technology. 2.3: Design Steps and Flowchart Following steps are involved to obtain this design. Step 1:- Design of phase detector & filter using 45 nm VLSI technology. Step 2:- Design of voltage controlled oscillator using 45 nm VLSI technology. Step 3:- Design of phase locked loop using 45 nm VLSI technology. Step 4:- Design of High performance voltage controlled oscillator (VCO) using 45 nm VLSI technology. Step 5:- Design of phase locked loop with high performance VCO using 45 nm VLSI technology. Step 6:- Design of Low power PLL with sigma delta modulator using 45 nm VLSI technology. Step 7:- Simulation & Analysis of proposed design. Every step of design follows the design flow of microwind 3.1 software as mentioned in figure 2.3.1 the design methodology will be according to VLSI backend design flow. The main target is to design and analyze the fractional-N phase locked loop frequency synthesizer which could be implemented by adding divided /network along with sigma delta modulator into basic PLL-block circuit. To achieve the proposed target following steps are included in the design and analysis of proposed phase-locked loop. i. Schematic design of proposed PLL using CMOS transistors (BSIM4). ii. CMOS layout for the proposed PLL using VLSI backend. iii. Schematic design of proposed sigma-delta modulator with divided /network using CMOS transistors (BSIM4). iv. Performance verification of the above for different parameters. v. CMOS layout for the proposed-delta modulator with divided /network using VLSI backend. vi. Verification of CMOS layout and parameter testing. vii. If the goal is achieved for all proposed parameter including detail verification, sign off for the design analysis and design will be ready for IC making. viii. If detail verification of parameters could not be completed then again fallow the first step with different methodology. To achieve the fractional-N phase-locked loop, different methodology and techniques can be used. To obtain the layout of proposed fractional-N PLL, CMOS circuit of each element of proposed fractional-N PLL is converted into physical layout using Lambda based rules of microwind 3.1 software. After cascading the layout of each element, final layout is obtained. The MICROWIND3.1 software allows designing and simulation of an integrated circuit at physical description level. Its package contains analog ICs and a library of common logic to view and simulate. It includes all the commands for a mask editor as well as original tools never gathered before in a single module (2D and 3D process view, tutorial on MOS devices and verilog compiler). By pressing a single key we can perform circuit simulation.

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International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: [email protected] Volume 3, Issue 3, March 2014 ISSN 2319 - 4847

Figure 3. Design Flow Chart

3. RESULT
3.1 Simulation Setup: This paper describes the use of CMOS 45nm technology and the implementation of this technology in Microwind 3.1. In 45nm technology, required effective gate length is 25nm with metal gate and SiON gate dielectric. This technology is called High speed technology as it is devoted to applications for which the highest speed is the primary objective: fast microprocessors, fast DSP, etc. The use of Software Microwind 3.1 is done in this paper which allows us to design and simulate an integrated circuit at physical description level. We can gain access to the Circuit Simulation by pressing one single key in this software .The electric extraction of the circuit is performed automatically and the voltage and current curves are produced by the analog simulator immediately. Figure 4 ,shows the layout of Fractional N-Phase Locked Loop using Sigma Delta Modulator with the help of 45nm VLSI technology .

Figure4. Layout of Fractional N-Phase Locked Loop using Sigma Delta Modulator

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The simulation of a low power Fractional N-Phase Locked Loop using Sigma Delta Modulator is shown in following figure 5 .This shows the simulation of a high performance N- PLL circuit, frequency versus time .The frequency is 2.4GHz. for which power consumed is 0.223 mw.

Figure5. Simulation result of Fractional N-PLL using sigma delta modulator,(Frequency vs Time)

4. CONCLUSION
From the above simulation result it is concluded that the frequency of Fractional N-PLL using Sigma Delta Modulator is locked at 2.5GHz which can be used for bluetooth standard systems for the current applications. It provided with fast switching time and high noise reduction. Also, it is concluded that this system is highly stable i.e. even if the voltage is varied the frequency remains constant and also this system consume low power.

REFERENCES
[1] T.Bourdi, A.Borjak, and I.Kale, A Delta-Sigma frequency synthesizer with enhanced phase noise performance, Instrumentation and Measurement Technology Conference, Proceedings of 19th IEEE, 2002, pp.247-250 [2] Erkan Bilhan, Feng Ying, Jason M. Meiners, and Liming Xiu, Spur free fractional-N PLL utilizing precision frequency and phase selection, IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software, 2006. [3] N. Fatahi, and H. Nabovati, Sigma-Delta Modulation technique for low noise fractional-N frequency synthesizer, Proceedings of the 4th International Symposium on Communications, Control and Signal Processing, ISCCSP 2010, Limassol, cyprus, 3-5 March 2010. [4] Kaveh Hosseini and Michael Petter Kennedy, " Minimizing spurious tones in digital Delta Sigma modulators, Analog Circuits And Signal Processing, pp. 30-31 [5] Wong Man Chun, A 1.8-V 2.4-GHz Monolithic CMOS Inductor-less frequency synthesizer for bluetooth application, thesis master, Hong Kong University of Science and Technology, August, 2002. [6] N.Fatahi, and H.Nabovati, Design of low noise fractional-N frequency synthesizer using Sigma-Delta Modulation technique, 27th International Conference of Microelectronics, IEEE, 2010. [7] Richard Gu, and Sridhar Ramaswamy, Fractional-N phase locked loop design and application, 7th International Conference on ASIC Proc. October 26-29, 2007, pp. 327-332. [8] Sangil Park, Principles of Sigma-Delta Modulation for analog-to-digital converters, Chapter 6, pp.8 [9] Dean Banerjee, PLL performance, simulation, and design, 4th Edition, pp.186-197. [10] Shiwei Cheng, Ke Zhang, Shengguo Cao, Xiao fang Zhou, and Dian Zhou, 2.4 GHz ISM band Delta-Sigma fractional-N frequency synthesizer with automatic calibration, WSEAS Transactions on Circuits and Systems, Volume 7 Issue 10, October 2008, pp. 859-868. [11] Yi-Da Wu, Chang-Ming Lai, Chao-Cheng Lee, and Po-Chiun Huang Error minimization method using DDS-DAC for wideband fractional-N frequency synthesizer, IEEE Journal of Solid-State Circuits, 2010, pp.2283-2291 [12] Xiao Pu, Axel Thomsen, and Jacob Abraham, Improving bandwidth while managing phase noise and spurs in fractional-N PLL, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Washington, DC, USA, 2008, pp.168-172. [13] Kevin J.Wang, Ashok Swaminathan, Ian Galton, Spurious tones suppression techniques applied to a widebandwidth 2.4 GHz fractional-N PLL, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008, pp.2787-2797.

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Web Site: www.ijaiem.org Email: [email protected] Volume 3, Issue 3, March 2014 AUTHORS
Chaitali P.Charjan1 received the bachelors degree in Electronics and Telecommunication Engineering from Prof. Prof. Ram Meghe College of Technology & Research, Amravati, Maharashtra, India and currently pursuing M.E M.E in Electronics &Telecommunication from Sipna College of Engineering & Technology, Amravati, Maharashtra, India. Asso.Prof.Atul S.Joshi2 is currently working as an Associate Professor in Electronics and Telecommunication Engineering Department, Sipna College of Engineering & Technology, Amravati, Maharashtra, India.

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