SaberRD Electrical Student Guide v1.7

SaberRD Electrical Systems 1
1 2013 Synopsys, Inc. All Rights Reserved

Synopsys Customer Education Services
2013 Synopsys, Inc. All Rights Reserved
Introduction to
SaberRD
Physical Modeling, Simulation, and Analysis
for Multi-Domain Power Systems
Introductions
Name
Company
Job Responsibilities
EDA Experience
Main Goal(s) and Expectations for this Course
Facilities
Building Hours
Restrooms
Meals
Messages
Smoking
Recycling
Phones
Emergency EXIT
Please turn off cell phones and pagers
Facilities
Agenda
Tool Flow and Time Domain Analysis 1
Schematic Capture & Parts Gallery 2
Small-Signal Frequency Analysis 3
Operating Point Analysis 4
Introduction 0 DAY DAY
1
Agenda
DC Transfer Analysis 5 DAY DAY
1
FFT 6
Design Optimization 8
Mixed-signal Analysis 7
Agenda
Modeling: Import Spice Model 10
Modeling: TLU 11
Modeling: StateAMS 12
Modeling: Characterization 13
Introduction to Robust Design 14
Introduction to Modeling 9 DAY DAY
2
Worst Case Analysis 15
Agenda
1
Serves Expert and Casual Users
Proven technology, broad application
coverage
Easy to Use
Intuitive UI guides the flow
Embeds Methodology
Test-driven results for electro-*
system design & verification: system
performance, robustness, reliability
Deployable throughout Enterprises
Standards-based, compatible with CAE
environments & flows, supply chains
Desktop Simulation for Electro-* Systems
Quick Methods
SaberRD: Serving All Levels of Users
SaberRD supports any level of users
Quick and easy entry point
Basic analysis up through fully customized verification flow
User selects method based on need, experience & available time
Seamless transition between levels guarantees easy learning curve
Advanced Customized
Ive heard of Saber, what is SaberRD?
Saber
Classic
SaberRD
Saber
Simulator
SaberHDL
Interface
Simulation
Kernel
SaberHDL
MAST
only
MAST +
VHDL-AMS
MAST +
VHDL-AMS
Ive heard of Saber, what is SaberRD?
If my company uses Saber
Classic or Saber through a
Frameway, will this class
still be useful?
Definitely. The menu
selections / buttons may be
different, but the
functionality is the same
and the concepts of
simulation are whats
important here
The two environments co-
exist nicely: schematic,
symbol, results, library
compatibility
Saber Classic SaberRD
Saber
Simulator SaberHDL SaberHDL
S
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Base Set:
Time-Domain
Performance
Freq-Domain
Performance
Scripting /
Automation
Embedded SW
Connections
Base Set:
Time-Domain
Performance
Freq-Domain
Performance
Scripting /
Automation
Embedded SW
Connections
Advanced Beyond the Competition
Physical Modeling & Simulation for Real Systems
+ Saber:
Desi gn for
Rel i ability
Gri d / Parallel
Computi ng
Desi gn for
Robustness
Desi gn
Opti mizati on
M
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Base Set:
Behavioral
Language(s)
Multi-Domain
Modeling
Generic Model
Libraries
Modeling
Assistants
+ Saber:
Component
Characterization
FE / Field Solver
Extraction
Input Format
Compatibility
Component
Li braries
E
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Base Set:
Windows-
based IDE
Documentation
& Examples
Support &
Community
Industry
Standards
+ Saber:
Leadi ng
Robustness
Suppl y Chai n
Success
Leadi ng
Performance
Li nux, Uni x
Support
Base Set:
Behavioral
Language(s)
Multi-Domain
Modeling
Generic Model
Libraries
Modeling
Assistants
Base Set:
Windows-
based IDE
Documentation
& Examples
Support &
Community
Industry
Standards
Agenda
1
Getting Started
Design
Modeling
Simulation
Analysis
Reporting
Quick access to examples,
documentation, and user resources
Full-f eatured schematic design f or power
electronic and multi-domain systems
Create & manage MAST and VHDL-
AMS models
Intuitive controls f or test-driven
simulation
Measurements, calculations, and
transf orms
Flexible output options
SaberRD: An Intuitive User Flow
Easy Design
Access
Help System
Jump Start
Designs
Support
Resources
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Getting Started Welcome
Online Resources from previous
User Groups
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Online Help/Support Integrated Browser
Integrated Access to Synopsys
Online Support System
Finding Documentation
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
?
Intuitively organized controls through Tabbed Ribbon
Structured by flow as opposed to features
Customizable Quick Access toolbar for frequently
used features
Tabbed Ribbon Where to Find?
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Dialog box launcher
Provides access to advanced
configuration
Easy navigation through tabs
Help through QuickHelp
Tool Tips
Dialog Box Launchers
QuickHelp field
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Intuitive schematic-based modeling
Tabbed MDI (multi-document interface) for handling multiple schematics
Tight integration with model library
Design hierarchy browsing & easy archiving
Modeling Schematic-Based Design Creation
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Symbol properties evaluated for correctness of syntax
Enforces data type consistency with underlying model
Design Correct-by-Construction
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Quick model access through model library
Easy model creation through modeling tools
Library management
Modeling: Creating and Managing Libraries
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Intuitive controls
Optimized to require minimum input from user
Single & looping analyses
Advanced configuration options for finer control
Simulation Quick Simulation Controls
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Advanced
Simulation
Configuration
Post processing & simulation in a single environment
Tabbed documents to switch between design and results
Waveform Calculator for results manipulation
Seamless Integration: Simulation & Analysis
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Easy export to standard formats
Quick creation of images for reports
& presentations
Customizable and scriptable
Reporting: Export to Standard Formats
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Getting
Started
Design
Modeling
Simulation
Analysis
Reporting
Documentation: Archiving/Exporting Results
Time Domain (Transient) Analysis
General Description
Transient analysis calculates the behavior of a system as a
function of time.
Each calculated data point in time is called a time step.
Required Parameters
Other Features/Comments
To allow for file comparison you can specify plot file names.
Transient analyses can start from zero (no Operating Point
analysis required).
Advanced simulation controls are available to calibrate
accuracy.
End Time - specifies the
end time of the analysis.
Time Step - specifies the initial
time step of the analysis.
Time Domain Response - Example
Setting the Time Step Field
Typically, set this to 1/100
th
or 1/1000
th
of end time
Rule of Thumb
Set the value of tstep to the smallest of:
1/10
th
of the smallest relevant time constant in the design
Shortest rise or fall time of a square/pulse wave driving source
1/100
th
of the input period of a sinusoidal driving source
SaberRD uses the value in the Time Step field to
determine an initial guess at the next solution point in
the simulation.
Prefix Abbreviations
a atto 10
-18
f femto 10
-15
p pico 10
-12
n nano 10
-9
u (or mu) micro 10
-6
m milli 10
-3
k kilo 10
3
meg (or me) mega 10
6
g giga 10
9
t tera 10
12
You can express a number as a constant immediately followed by an
appropriate abbreviation (do not include units).
Prefix Abbreviations - Examples
For example, the following are equivalent:
x = 3p x = 3e-12
The following are illegal specifications for numbers:
x = 3 p (space not allowed between number and
abbreviation)
x = 1mA (units not allowed)
NOTE: VHDL-AMS models require scientific notation:
x = 3p x = 3e-12
Time Domain Measures
Falltime
Risetime
Slew Rate
Period
Frequency
Duty Cycle
Pulse Width
Delay
Overshoot
Undershoot
Settle Time
Advanced Simulation Controls
Accessed with the Dialog
Box Launcher at the
bottom right of the Quick
Simulation controls
Provides access to
customization of file
names and advanced
simulation controls
Changing solver options
is typically not needed and
is covered in advanced
training
15 minutes
Lab 1: Time Domain
In this lab exercise, you will
perform a time domain
(transient) analysis on the
RLC circuit.
Perform the steps beginning
on the page titled
Lab #1 in your exercise
manual.
Open Design
Perform Transient
Analysis
View Results
Perform Measurement
Close Design
Lab #1 Review
Time domain analyses are characterized by having time
as the independent axis (X-axis)
The results appear similar to how they would look on an
oscilloscope
Measurements specifically designed for Transient
analysis can be found using the Measurement Tool
under Time Domain.
References: SaberRD Users Guide
Agenda
1
Schematic-Based Design Creation
Intuitive, flexible, schematic-based modeling
Tabbed MDI for handling multiple schematics
Tight integration with model library
Design hierarchy browsing & easy archiving
Describe (model) system behavior using parts,
connections, and annotations
Home tab
Hierarchical
Model
Symbol / Model
Multiple
Sheets
Conserved
node
Ground node
Signal flow node
Mixed
Domains
Selected part
Attributes of selected property
Properties of selected part
Parts Gallery
Parts Gallery tool accessible on
left side of SaberRD
30,000+ models for multi-domain
applications
Includes generic models to fully
characterized parts
Browse or Search to find models
you need
Extensive Libraries for Physical Modeling
Machines
&
Generators
Switches
& Relays
Power
Devices
Thermal
Elements
Passive
Elements
Logical
Gates
Transmission
Lines
Electromagnetics
Transformers
Behavioral
Blocks
Fluidic
Elements
Mechanical
Elements
Signal Flow
Blocks
Batteries
&
Storage
Comparators
& Op-Amps
Bridges
& Drives
Generic Parts
Extensive Libraries for Physical Modeling
Saber Component Library
Characterized Parts
BJTs
Philips, TI, Fairchild, Harris, etc.
MOSFETs
IRF, Philips, Harris, Toshiba, etc.
IGBTs
IRF, Harris, Mitsubishi Electric, etc.
Fuses
Littelfuse, Autofuse, Microfuse, etc.
PWMs
Fairchild, Linear, Intersil, TI, Motorola, etc.
Regulators
Analog Devices, National, TI, Motorola, etc.
Op-amps
Analog Devices, Motorola, National, Philips, etc.
Motor Controllers
TI, ON Semi, Fairchild, etc.
IVN Components
Transceivers (CAN, LIN, FlexRay), Chokes, Ferrites
More
Off-the-Shelf Parts
Searching libraries
Intelligent search capabilities
Search for generics or
components
Blue icon indicates a MAST-
based model, red indicates a
VHDL-AMS-based model
Click the search tab
Open the documentation on the part
Type in a part name, number, or key word
Other part and library information
displays once you select a part
Place
part
Parametric Search
You can also locate
parts via parametric
search.
Define performance
ranges and ratings to
find the specific part
you need.
Must select Components to activate
Parametric Search
Important parts of a part on a schematic
Parts come either from a
distribution (Saber)
library, site library, user
library, or local
workspace
Symbols are just
graphics, graphics have
attributes
Models are connected to
symbols through
properties
Important parts of a part on a schematic
Parts come either from a
distribution (Saber)
library, site library, user
library, or local
workspace
Symbols are just
graphics, graphics have
attributes
Models are connected to
symbols through
properties
schematic property indicates
hierarchical model
Design Browser
The Design Browser provides an efficient
way to navigate your design
Design Browser
The Design Browser also
provides a design
archivingtool
Right-click menu
Includes needed files in a
directory
Great for storing, sharing,
sending to support
Customizable Hot-keys
Customizable Quick Access Toolbar
Easy access to frequently used features
Build-up quick flows aligned with your specific needs
Optimizing Workflow Quick Access Toolbar
Tips for success
Always ground your design. Why?
Tips for success
Parts Gallery includes multiple
grounds for different domains
Mainly for aesthetics
All reference parts = node 0
Tips for success
Always fill in required properties
Tips for success
Connection Notes
Electrical Digital
User can connect directly.
Hypermodels (D-Aor A-D) are
automatically inserted.
Domain A Domain B
User must insert one or more
converter blocks.
Signal flow Conserved
User must insert converter blocks.
Domain converter blocks included in Parts Gallery
Tips for success
Open circle = no connection
Solid dot = connection
Not connected
Connected
Tips for success
Same page
connectors make
schematics more
readable
15 minutes
Lab 2: Schematic Circuit
In this lab, you will
complete the schematic
diagram shown on the
following slide.
Perform the steps
beginning on the page
titled Lab #2 in your
exercise manual.
Open Design
Place Parts
Define Properties
Inspect the Design
Save the Design
Differential Amplifier Schematic
Agenda
1
Small-Signal AC Analysis
General Description
Frequency (or small-signal AC) analysis calculates the behavior of a
system as a function of frequency.
This is a linear analysis about a specified operating point. The default
operating point is the output of the DC analysis.
Required Parameters
You must have an AC voltage or current source specified in the circuit.
To allow for file comparison, you can specify plot file names.
You can specify number of frequency points calculated, as well as
linear or logarithmic spacing of those points.
Start Frequency - specifies the
beginning frequency for the analysis.
End Frequency - specifies the
end frequency for the analysis.
Why AC Analysis?
AC analyses are useful in several areas, including:
Filter design
Open and closed loop control design
Stability analysis
In general, any time you need to know how something
behaves as a function of frequency
Small-Signal AC Analysis
Small-signal AC analyses characterize non-linear
systems in the frequency domain by frequency-
sweeping a small sinusoidal signal at the input.
This small sinusoid keeps the system running in the
linear region of operation around a previously
calculated operating point.
Typical AC analysis signals are shown on the following
slide. The slide shows a systems gain (magnitude) and
phase as a function of frequency.
Small-Signal AC Response Example
Frequency Domain Measures
Lowpass (3dB point)
Highpass (3dB point)
Bandpass (Q, ripple, etc.)
Stopband
Phase Margin
Gain Margin
Slope
Magnitude
Phase
Real
Imaginary
Nyquist Plot Frequency
THD / SNR / SINAD
Notes on Waveforms
The availability of signals in the Plot File window is controlled
by the Signal List. Below are some examples:
:*:*
Include all signals in current instance
:...:*
Include all signals within or below the top level design
:...:foo.*:* Include all signals in all instances of any foo component
:...:foo.u12:* Include all signals in the foo.u12 instance
sig1 sig2
Include each signal listed. Separate the names with spaces
You can also Browse for signals
to include in the Signal List. A
Signal List can be configured for
each analysis and is available
under File Control in the
Advanced Simulation form.
20 minutes
Lab 3: Small-Signal AC
perform frequency domain
(small-signal AC) analysis on
the RLC circuit.
You will perform a standard
transfer function analysis and
display it in Bode form.
on the page titled Lab #3 in
your exercise manual.
Open Design
Perform AC Analysis
View Results
Close Design
Lab #3 Review
Small-Signal AC Analysis is linear about an operating
point
Useful whenever you want to understand something as
a function of frequency
Measurements specifically designed for AC analysis
can be found using the Measurement Tool under
Frequency Domain
Lab #3 Review - Continued
Looping can be used to sweep various component
values
Batch measurements are possible (measurements on
multi-membered waveforms)
Agenda
1
Operating Point (DC) Analysis
General Description
The DC operating point analysis calculates the state of
the system at time=0.
This is used as an initial point for subsequent analyses.
Required Parameters
None. You can simply select OK to run a DC operating
point analysis.
Input and output files can be specified.
Different algorithms are available for difficult circuits.
Operating Point Analysis (continued)
In essence, for an operating point analysis:
All dynamic elements are effectively removed from the
circuit
Inductors are shorted
Capacitors are opened
Time-dependent sources are removed
Noise sources set to 0
AC sources set to 0
An operating point is a set of values that define the
steady state of a nonlinear system at time=0, with all
time-varying parameters and their derivatives set to 0.
Operating Point - Initial Point File
It contains the operating point used in other SaberRD
analyses
SaberRD uses it as the first data point for time domain
analysis.
For small signal frequency analysis, SaberRD applies a
small sinusoidal signal around the operating point.
It provides a quick check to determine possible incorrect
part parameters
Gives you an idea if components have correct values, etc.
The results of an operating point analysis are stored in
the initial point file (named design_name.dc.ai_ipby
default). This file serves two purposes:
15 minutes
Lab 4: Operating Point
In this lab exercise, you
will perform an operating
point analysis on an RLC
circuit.
Perform the steps
exercise manual.
Open Design
Perform Operating
Point Analysis
Change Input Voltage
and Rerun Analysis
Close Design
Lab #4 Review
With vin = 0 at time = 0, all circuit nodes are 0 for DC
analysis
With vin = 1 at time = 0, vout = 0.909V
Inductor is shorted for DC analysis
Capacitor is opened for DC analysis
vout is the input voltage across a simple voltage divider
1V*(1k/1.1k)
Component values can be dynamically altered in
SaberRD
Agenda
2011 Synopsys, Inc. All Rights Reserved
1
FFT 6
DC Transfer Analysis
General Description
Sweeps an independent DC voltage or current source
over a user-defined range of value and computes the DC
operating point for each sweep value.
Required Parameters
Independent Source (e.g. v_dc.v1).
Sweep Range
Requires DC Operating Point analysis to be run first (or
run from zero)
Input and output files can be specified
DC Transfer Analysis
Useful for finding the transfer function of an amplifier,
component thresholds, etc.
Nested DC Transfer
You can also vary other design parameters while
sweeping the source
DC Transfer - Loudspeaker Circuit
15 minutes
Lab 5: Operating Point with Looping
In this lab, you will find the
DC Transfer function of
the Loudspeaker circuit
Perform the steps
exercise manual.
Open Design
Point Analysis
Perform Operating
Point Analysis
Find Transfer Find Transfer
Function
Plot Results
Lab #5 Review
DC Transfer analysis allows you to study a circuit with
the x-axis (independent variable) chosen as something
other than time. (Great for transfer function analysis)
Agenda
1
FFT 6
Fourier Analysis
Transforms time-domain waveforms into a frequency spectrum
Fouriers Theorem
According to Fouriers theorem, any periodic waveform can be
represented by the sum of its average and a series of sine waves.
The sine waves have frequencies of integer multiples of the
frequency of the periodic function, and varying magnitudes and
phases.
f(t) = a
0
+ a
1
cos w
0
t + a
2
cos 2w
0
t + + b
1
sin w
0
t + b
2
sin 2w
0
t
The discrete Fourier transform allows the magnitudes and phases
of the sine waves to be determined from data points along a
period of the function.
The range of the data points is from the end of the analysis to one
period before the end of the analysis.
Fourier Analysis
The main advantage of doing this is to allow easy
discrimination between large and small sinusoids of
different frequencies in a given waveform
For example, if you want to test the purity of an
oscillator:
Time Domain: the ripple you want to measure
may be buried in the larger signal its super-
imposed upon.
Frequency Domain: all signals of varying
frequency are represented on their own spot on
the frequency axis, distinct and separate from
the other signals.
Fast Fourier Transform (FFT)
The Fast Fourier Transform is a
post-processing command that
calculates the frequency
components of a section of
time.
Because this analysis requires
time domain data, you must run
a transient analysis prior to
executing this analysis.
Because non-periodic functions
cannot be represented by a
Fourier series, it is no longer
sufficient to find the Fourier
coefficients at a set of harmonic
frequencies.
Instead, a continuous range of
frequencies is calculated
showing the value of each FFT
data point.
FFT analysis is used to
transform time-domain
data into frequency-
domain data.
Input values must be real-
valued, and the generated
output values will be
complex.
Windowing functions may
be applied to the input
data before being
transformed.
Discontinuities cause spectral leakage
Blurring of the frequency spectrum output
Extra harmonics appearing
Solutions
Apply a window function to the original data,
Serves to smooth out discontinuities in the
sampled data
Dont Forget to choose a truly periodic part of the
signal
Waveform Calculator
In the next lab, you will use the Waveform Calculator. This
is a very powerful tool, and an extensive reference for it
can be found toward the end of this manual.
The following slide highlights some of the calculators
features.
Waveform Calculator
Entry Field (Register)
Icon Bar
Pulldown Menus
Programmable Buttons
Stack Display
Extended Operation Buttons
Keypad
Using the Calculator
To get a waveform into the Register, select the
waveform name on the graph window and middle-click
in the Register.
You can also use Edit > Copy, then Edit > Paste to
accomplish this task
Either RPN or Algebraic input modes can be selected.
To plot results from the calculator, click on the Graph X
button in the Icon Bar:
15 minutes
Lab 6: Fast Fourier Transform (FFT)
In this lab, you will
perform an FFT on the
Audio loudspeakers
transient simulation
results. You will determine
the large-signal frequency
response of this non-
linear block.
Perform the steps
exercise manual.
Open Design
Perform Alter Perform Alter
Parameter
Perform AC/TR/FFT Perform AC/TR/FFT
Analyses
Compare Results
Close Design
Agenda
1
FFT 6
Mixed Signal Analysis
Mixed-signal is often needed in order to add control
into a design
D(s) G(s)
H(s)
Controller Plant
+
_
Methods of adding control
Control blocks in SaberRDlibrary
StateAMS
Co-simulation with Simulink
Abstract VHDL digital part
C foreign function
Co-simulation with a digital chip simulator
D(s) G(s)
H(s)
Controller Plant
+
_
Control blocks in SaberRD
Many control blocks
in Parts Gallery
StateAMS
Easily / graphically
model control for
your design
Simulink Models
Saber Simulink
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Take advantage of existing
Simulink models
Co-simulate
Import into Saber via
Simulink Real Time
Workshop
Abstract VHDL Digital Part
As a VHDL-AMS simulator, SaberRDcan natively
simulate VHDL digital parts
C Foreign Function
Mixed-Signal Analysis
Mixed-signal analysis involves both analog and
digital components/models.
Mixed-Signal Simulation Approaches
Glued Simulators
Native Mixed-Signal
Cosimulation
A/D Interface Models - Hypermodels
Mixed-signal parts
are complicated and
fall a little into each bin.
Digital
Simulator
Digital Library
Analog
Simulator
Analog Library
Glued Simulators
Simulators coupled via a backplane
No mixed-signal modeling language
0 1 X Z
Coupling Algorithm Coupling Algorithm
Summary of Glued Approach
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Analog Models Digital Models
Analog Solver Digital Solver
Back Plane
No mixed-signal models
Boundary Algorithm Boundary Algorithm
One shared library of Analog,
Digital, and Mixed-Signal Parts
SaberRD
Analog Digital
Calaveras
Native Mixed-Signal (Single-Kernel)
Tight analog/digital integration (not working with two foreign
simulators)
Only one mixed-signal language needed, and one design
Summary of Native Mixed-Signal
SaberRD
Digital Models
Digital Solver
Mixed-Signal Models Analog Models
Analog Solver Boundary Algorithm
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Digital Cosimulation
Cosimulation achieved by merging event-queues of simulators
Analog/digital interface still resides with native (single-kernel)
simulator
One shared library of Analog,
Digital, and Mixed-Signal Parts
SaberRD
Analog Digital
Calaveras
Digital
Simulator
Digital Library
0 1 X Z
IPC Link
Summary Cosimulation Approach
SaberRD
Co-Simulation
Analog Models Mixed-Signal Models
Analog Solver Boundary Algorithm
0,1,X,Z
Verilog
VHDL
Digital Models
Digital Solver
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What to Use When?
If you have big A (Analog), little D (Digital) then you can
use SaberRDs native mixed simulation environment.
SaberRDcan simulate digital VHDL natively.
If you have big Dfor example, a multi-million gate
ASIC or FPGAthen leave the digital to a high-
performance digital simulator like Synopsys VCS.
If the design lies somewhere in-between, then it is very
design dependent as to which approach will work best.
A/d A/d
a/D a/D
Hypermodels
Hypermodels inserted automatically by SaberRD
Hypermodels are associated with digital components
3,500 parts already characterized by Synopsys
Templates to customize to specific requirements
P P
N N
P P
N N
a2d
d2a
Analog-to-digital and digital-to-analog boundaries
must be traversed
Hypermodel I/O
A Hypermodel template can be considered as a single-
bit, digital-to-analog or analog-to-digital converter that
models the following:
Transition characteristics
Terminal (loading) characteristics
Hypermodels do not model digital delays. This is
done within the digital components.
Hypermodel Logic Levels
Hypermodel templates recognize only the following logic
levels: 0, 1, X, Z. These logic levels are represented by
digital states that use logic_4 values shown below.
These values are defined in the units.sin file that is
automatically loaded when running SaberRD.
l4_0 0 (LOW)
l4_1 1 (HIGH)
l4_x X (uncertain not treated as "don't care")
l4_z Z (high impedance)
Preparation for Lab #7
10 minutes
Lab 7: Time Domain
In this lab, you will perform
mixed-signal simulation on a
counter circuit. You will
netlist the circuit with various
hypermodels and observe
simulation results of each.
Open Design
Perform DC/TR
Analysis
Analyze Results
Close Design
Lab #7 Review
Hypermodels are automatically inserted at the
boundary between analog and digital pins.
Hypermodels do not exist at the schematic level:
they are inserted during netlist generation
The inserted hypermodels can be viewed by looking
directly at the netlist
References: SaberRD Book; Co-simulation User
Guides; Introduction to MAST Workshop; Advanced
Saber/MAST Workshop
Agenda
1
FFT 6
Why Design Optimization?
Useful for
Filter design
Impedance matching
Minimizing power consumption
PID Controller optimization
or anytime youre trading off multiple
input values to try to achieve some
optimal design result
Design Optimization in SaberRD
Leverages Worst-Case Analysis Tool
WCA is also just an optimization challenge
WCA covered in subsequent sections
Design Optimization Flow
Objective
Start with the goal in mind, for example
Minimize power consumption
Obtainclosest matchto a value or a
waveform
typically thought of in terms of
minimums or maximums
Objective
Measure
What do you need to measure? For
example
Power consumed
Closeness to a value or waveform
Objective
Measure
Analysis
What analysis will produce that
measure? For example
Operating Point
Time Domain
AC
Objective
Measure
Analysis
Variation
What design parameters will be allowed
to vary?
Add tolerances to those components
Design Optimization in SaberRD
WCA Tool
Intuitive drag & drop
solution
Analysis Definition
Measurements &
objectives
Multi objective definition
Library of powerful
algorithms
Workflow for Optimization in SaberRD
Objective
Measure
Analysis
Variation
Objective
Measure
Analysis
Variation
Objective
Measure
Analysis
Variation
Objective
Measure
Analysis
Variation
Algorithms the key to success
Search Algorithms
Local & global algorithms
Combined search possible to
leverage synergy of different
methods
Customized calibration
possible
Lab 8: Design Optimization
60 minutes
In this lab, you will use
design optimization to design
a bandpass filter
If using SaberRDStudent
Edition for the training, skip
this entire lab. Optimization
is not enabled in the Student
Edition.
Extract Stochastic Extract Stochastic
Parameters
Perform Optimization
Analyze Results
Close Design
Open Design
Agenda
Modeling: TLU 11
2
Why is modeling important?
Certain model effects are important
A model without the right effects could delay discovery of
design flaws until prototyping
However, a model with too many effects slows simulation
time
Robust Design processes demand efficiency
Many iterations to observe statistical information
Often analyzing large or complex systems
Models that simulate fast decrease simulation times
Model Effects
Basic first order behaviors
Steady State & Logic behaviors
Dynamic transfer function behaviors
Averaged effects
Complex behaviors such as over-value
protection and self-heating effects
Switching effects
Actual system architecture
Device physics
Least
Complex
Most
Complex
Architectural
Behavioral
Functional
Component
Modeling Approaches
Architectural and Functional
Architectural: Steady State & Logic
behaviors
Functional: Transient behaviors,
Averaged model (no switching)
Model the effects of the complete block
Dynamic transfer function behaviors
Averaged effects
Evaluate and Ensure stability
Test topology concepts without
worrying about implementation
D(s) G(s)
H(s)
Controller Plant
+
_
Architectural
Behavioral
Component
Functional
130 .
s
2
+1250s+130
Plant
Architectural and Functional
Advantages
Simple to create a model
No need for modeling language
knowledge
No building blocks required
Accommodates multiple abstraction
levels
Very fast simulations possible
Only consider important model
characteristics
Disadvantage
Only as detailed as
characteristics considered
Modeling Approaches
D(s) G(s)
H(s)
Controller Plant
+
_
130 .
s
2
+1250s+130
Plant
Architectural
Behavioral
Component
Functional
Modeling Approaches
Behavioral
Model the effects individual
components contribute
Complex behaviors such as
over-value protection and self-
heating effects
Switching effects
Component implementation is
not considered
Model represents actual dynamic
waveforms
Evaluate signal quality
D(s) G(s)
H(s)
Controller Plant
+
_
Architectural
Behavioral
Component
Functional
Plant
Modeling Approaches
Behavioral
Advantages
Easy to Model
Use existing building blocks
No need for modeling language
knowledge
Fast Simulation Times
Can use either control system
models or conserved models
Disadvantage
Lower fidelity than component level
Architectural
Behavioral
Component
Functional
D(s) G(s)
H(s)
Controller Plant
+
_
Plant
Two common approaches to modeling
Control System
Also referred to as signal flow
Has a direction
No units
Input is independent of output
Conserved
Based on conservation of
energy
Ports have no direction
Considers physical units
through and across
variables depend on each other
input output
H(s)
across
through
across=f(through)
In power systems design, the focus is on the
hardware.
The choice of approaches matters because
the hardware matters.
Why does this choice matter?
Conserved
Physical Model
Control
System Model
Use physics equations directly
i = C( i = C( i = C( i = C(dv dv dv dv/ // /dt dt dt dt) ) ) )
i = v/R i = v/R i = v/R i = v/R
Its about accuracy:
in power systems
the physics
equations more
readily model the
behavior than a
transformation
Conserved
Physical Model
Control
System Model
Reuse block ?
No! Because its
equivalent to
something else.
Equivalent
Equations
Reuse block ?
Yes!
Re-use sub-models
Model complex, real world hardware easily
Feedback is
explicitly defined.
This model is not bi-
directional. What
happens if its back-
driven (as a
generator)?
Control System Model of a DC Motor
Equations:
vin = vres + vgen + d_by_dt(flux)
tq_Nm(shaft) = tgen - d_by_dt(mom) - visc
Same equations apply
when back-driven
as a generator
Sides of the equations here
means obeying the laws of
conservation of energy
Loading effects are
critical to modeling
power systems
Example: modeling an IGBT
It would be extremely difficult to
capture non-linear effects in a
signal flow model:
Timing behavior, that is,
switching behavior as a
function of frequency,
temperature, and bias
Switching losses as a function
of frequency and bias
conditions
Tail current
Thermal behavior as a function
of frequency and bias
Model non-linearities / interdependencies
Ideal Control Signals Ideal Sensor Signals
Physical System:
Conserved Models
Algorithms:
Control System
Models
Mix signal flow and conserved
Mix signal flow and conserved
Control System Modeling Conserved Modeling
Behaviors with no loading effects
Sensor output signals
Ideal measurement of signals
Performance maps (table look-up
type performance data)
Systems with loading effects
Vehicle chassis acting to load the
vehicle powertrain
Powertrain motor acting to load the
electrical power system
Algorithmmodeling Description of physical hardware
Electronic circuits
Hydraulic circuits
Mechanical systems
Thermal systems
Systems with greater than 1
st
or 2
nd
order effects
Modeling Approaches
Component
Model the detailed physical behavior
of the components
Device physics
Model behavior matches hardware
behavior
Evaluate regions of operation
Define component tolerances
Aid in selection of manufacturer
components
Architectural
Behavioral
Component
Functional
D(s) G(s)
H(s)
Controller Plant
+
_
Plant
Modeling Approaches
Component
Advantage
Very high fidelity
Disadvantages
Slower simulation times
Can require more modeling effort
Requires knowledge of a
modeling language
Requires manufacturers data
Plant
Architectural
Behavioral
Component
Functional
D(s) G(s)
H(s)
Controller Plant
+
_
Model Effects
Architectural
Behavioral
Functional
Component
Faster
Simulation
Slower
Simulation
Less Effort
to Create
More Effort
to Create
Lower
Fidelity
Higher
Fidelity
Steady State & Logic
behaviors
Dynamic transfer function
behaviors
Averaged effects
Complex behaviors such
as over-value protection
and self-heating effects
Switching effects
Device physics
Modeling: Automatic Symbol Creation
Automatically create symbols from
Source code
MAST
VHDL-AMS
Spice
Hierarchical Models
Needed properties are added to the symbol automatically
Symbol editor lets you customize the graphics
Shape
Port alignment
Flip / Rotate Graphics
Symbol Generation from Schematic
Add hierarchical pins
to schematic
Symbol Generation from Source Code
Our goal is to enable an author to protect their
Intellectual Property while allowing a user to
execute the IP with any trusted tool.
SaberRD can encrypt MAST and VHDL-AMS model
source.
For VHDL-AMS, SaberRD follows IEEEs P1076-
2008 which defines encryption for VHDL-AMS
model portability.
Modeling: Encryption
Modeling: Encryption
Encryption Tool
GUI
Graphically specify
region to be
encrypted in MAST
or VHDL-AMS
model
Recommend you
leave variable
names, etc.
exposed where
possible
60 minutes
Lab 9: Hierarchical Models & Encryption
In this lab, you will complete
a schematic and encrypt this
as a hierarchical model.
Edition for training, skip only
the Encryption part of lab.
Encryption is not enabled in
the Student Edition.
Add Hierarchical Pins
Create Symbol
Encrypt Model and Attach
to Symbol
Test Model
Create Schematic Create Schematic
Model
Agenda
Modeling: TLU 11
2
30,000+ parts in Saber Library
Generic Models
Characterized Parts
SaberRD: Flexible Modeling Options
Electronic
Electro-Mechanical
Electrical
Magnetic
Mechanical
Thermal
Hydraulic
Controls
Pneumatic
Optical
Digital
Generic Models
Characterized Parts
Modeling Tools
State Diagrams
Characterization
Multi-dimensional TLU
Hierarchical Schematic
Transformers
MOSFETs
IGBTs
More
Characterize
Diodes
Create
MAST
VHDL-AMS
Generic Models
Characterized Parts
Modeling Tools
State Diagrams
Characterization
Multi-dimensional TLU
Hierarchical Schematics
Languages
Industry Standard VHDL-AMS
MAST
HSPICE, PSpice
IBIS
S-parameters
C/C++, Fortran
Accept
PSpice HSPICE
Simulink
SaberRD
Importing Spice Models
Spice Import Wizard
Helps build symbol
automatically
With options for a
default box symbol,
OpAmp,
Comparator
Spice Import Wizard
Helps build symbol
automatically
With options for a
default box symbol,
OpAmp,
Comparator
Easy access to
Spice source, pin
names, etc.
Select Import Spice from a
user library in Parts Gallery
Create symbol with Spice Wizard
Compile Library
Use the new part
10 minutes
Lab 10: Modeling
In this lab, you will import
and use a Spice model.
Edition for training, stop after
Task #2. This model exceeds
the node limits of the Student
Edition.
Open Design
Import Spice model
Analyze Results
Close Design
Agenda
Modeling: TLU 11
2
Generic & Specific Modeling Capabilities
Modeling Tools Palette
Shortens the development time to produce both generic
and specific models
Graphical interface enables model creation without having
to know a modeling language
Imports measured data or data sheets
Optimizer calculates model parameters to match simulation
results with imported data
Table Look-Up Tool allows modeling of a behavior that is
dependent on up to 5 variables
StateAMS allows modeling of complex state dependent
equations for conservative systems using graphical state
diagrams
Table Look-Up Tool
Quick and easy creation of
generic and specific models
from:
Measured Data (ASCII Files,
Scanned Waveforms, etc)
Datasheets
SaberRD Plot Files
Automatic symbol creation
Advanced interpolation
and extrapolation options
Support for up to 5
independent variables
No need to know any modeling language
Model Architect - Scanned Data Utility
How to import PDF, BMP, GIF, JPG or other
scanned formats into Model Architect?
Answer: ScannedData Utility
Import Image
Export ASCII
30 minutes
Lab 11: Table Look-Up
In this lab, you will use the
TLU tool to develop a
Thermistor for a system.
You will then use SaberRD to
analyze the system.
Open Design
Create TLU model
Compare expected vs.
model results
Close Design
Agenda
Modeling: TLU 11
2
Generic & Specific Modeling Capabilities
StateAMS
State-dependent modeling
of continuous behavior
Easy to create very
complex models
Advanced modeling
features
Tightly integrated with
SaberRD environment
No need to know any
modeling language
StateAMS Example: Model Interface
Define the interface of
the model by adding
ports and terminals
StateAMS Example: Model Interface
Terminals are
associated with a
physical domain and
have "across" and
"through" variables
Ports may be
continuous or state-
driven
StateAMS Example: Model Quantities
Variables are used to
construct equations
that describe the
behavior of the model
Variables may be
continuous or static
StateAMS Example: Model Quantities
Constants can be
used to parameterize
model behavior
Appear as properties
on the generated
symbol
StateAMS Example: States
States are used to
describe different
modes of model
behavior
Each concurrent
group of states must
have one initial state
The equations that
govern variables are
defined in each state
Governing equations
may also be defined
by editing a variable
directly
StateAMS Example: Blocks
Blocks are used to
group states that
share transitions and
actions
StateAMS Example: Transitions
Transitions define the
conditions for moving
from one state to
another
StateAMS Example: Code Generation
View the generated
MAST or VHDL-AMS
code for the model
Directly place the
symbol in a SaberRD
design and simulate
30 minutes
Lab 12: StateAMS
StateAMS tool to develop a
controller for a system.
You will then use SaberRD to
analyze the systems.
Open Design
Create StateAMS
model
Check Results
Close Design
Agenda
Modeling: TLU 11
2
Device Characterization
Characterization
through Datasheet
Information
Support for Power
Electronics and
Multidomain (MOSFETs,
IGBTs, Diodes, and
more...)
Thermal
Charaterization
IGBT
Characterization
Magnetics
Characterization
MOSFET
Characterization
Saber
Modeling
Solutions
DCPM Motor
Charaterization
Diode
Charaterization
Scanned Data Utility
Import image
Drag axis box to match image boundaries
Define axis range and scale
Define parameters for multiple curves
Click mouse button along curve to create data points
Data Sheet Image
Optimize & Use
Before Optimization
After Optimization
Automatic Symbol Generation
Place Part
Simulate
45 minutes
Lab 13: Characterization
Diode tool to characterize a
power diode.
Open Datasheet
Characterize diode
model
Agenda
Modeling: TLU 11
2
Robust Design Objective
Implement the simplest, most cost effective design
that meets performance specifications and
promises the highest reliability
Most economical life-cycle costs
Meet performance:
Despite variationin manufacturing processes
Despite variationdue to environmental conditions
Despite variationdue to aging
Costs of deviating from optimal design show up as:
Poor quality
Overdesign
Designing for Quality
Methodologies
Screen out defective units
Test or rework all failing parts
Remove causes of variation
Remove causes external to the system
Replace causes internal to the system
Adopt Robust Design principles
Make system performance insensitive to variation
Costly!
Robust Design Focus
Determine the important characteristic(s) of component, sub-system,
or system
Robust Design concentrates on this Design Performance
Measurement
Target
Performance
Distribution Y
Distribution X
Cost ($) Quality
Loss
Function
Poor Quality Overdesign
Units
Shipped
Goal is to reduce effect of variability on that characteristic
Units
Shipped
Inductance
-10% +10%
Time Delay
-2% +2%
Current
-15% +5%
-30%
Capacitance
+30%
Why Statistical Analysis?
System Performance =? Solution: Statistical Analysis
Goal: Analyze the behavior of the system when
variation is introduced
Design Requirements
Component tolerances are included
External variation/noise is added to the system
Analysis Requirements
Multiple variations considered simultaneously
Design variations determined by statistical tolerance
Number of permutations large enough to provide useful
statistical information
Physical prototyping cannot meet all the requirements
Simulation-based Robust Design Flow
performance
measure(s)
model(s)
nominal
design &
optimization
sensitivity
analysis
robust
design
parameters /
tolerances
monte carlo
simulations
pareto
analysis
Does this work?
Observations
Vehicles were being brought in for
service due to poor performance
Diagnostics determined that all parts
were operating within specifications
Randomly replacing parts eventually
caused vehicle to have proper
performance
Possible Causes
Tolerance stack-up caused the vehicle to
have poor performance
Explicitly defined tolerances for system
performance metrics do not exist
Case Study
Customer Example The Problem
Ti me Ti me Ti me Ti me
Out put Out put Out put Out put
Cus t omer Cus t omer Cus t omer Cus t omer
Ma x Acceptable Ma x Acceptable Ma x Acceptable Ma x Acceptable
Te s t Boundary Te s t Boundary Te s t Boundary Te s t Boundary
16 16 16 16 Target Response Target Response Target Response Target Response
Cus t omer Cus t omer Cus t omer Cus t omer
Mi n Acceptable Mi n Acceptable Mi n Acceptable Mi n Acceptable
? ?? ?
? ?? ?
Considerable overshoot was observed for the measured
output
Maximum acceptable overshoot was not defined during the
design of the system
Customer Example The Solution
1. 1. 1. 1. Model system in Model system in Model system in Model system in Saber Saber Saber Saber
2. 2. 2. 2. Use Robust Design to identify where system can be improved Use Robust Design to identify where system can be improved Use Robust Design to identify where system can be improved Use Robust Design to identify where system can be improved
3. 3. 3. 3. Modify design to reduce variation in Modify design to reduce variation in Modify design to reduce variation in Modify design to reduce variation in system system system system performance metric due to variation in performance metric due to variation in performance metric due to variation in performance metric due to variation in
individual individual individual individual components components components components
Ti me Ti me Ti me Ti me
Out put Out put Out put Out put
Ma x Acceptable Ma x Acceptable Ma x Acceptable Ma x Acceptable
16 16 16 16
Target Target Target Target
Mi n Acceptable Mi n Acceptable Mi n Acceptable Mi n Acceptable
? ?? ?
? ?? ?
Customer Example Conclusions
Robust design improved the signal response
Robust design techniques improved the design to handle
the statistical variation of the components and reduce the
variation of the system
Saber simulation results were later validated in the
vehicle and matched the measured response
Quantified Return On Investment (ROI) in warranty cost
savings
Simulation-based Robust Design Flow
performance
measure(s)
model(s)
nominal
design &
optimization
sensitivity
analysis
robust
design
parameters /
tolerances
monte carlo
simulations
pareto
analysis
Define Tolerances
In Saber, tolerances are defined by
assigning a probability density
functions (PDF) to parameters
Models should have meaningful
parameters
Allowable probability density functions
Uniform:
uniform(nominal_value,tolerance)
Normal:
normal(nominal_value,tolerance)
Piecewise Linear:
pwl(nominal_value,tolerance)
Example of a 10k resistor with 10%
tolerance
rnom=normal(10k,0.1)
Monte Carlo vs. Sensitivity
Sensitivity Monte Carlo -> Pareto
Deterministic Method Statistical Method
Does not use
tolerances
Uses Tolerances
Perturb one parameter
at a time, by a small
fixed amount
Allow all parameters to randomly vary in
their tolerance band
Run a sample set of simulations
Compute correlation between variations in
performance and the variations of each of
the independent parameters
Ratio
Percent performance
change to the percent
parameter change
Statistical sensitivity
Percent change in performance correlated
with percent change in each parameter
Monte Carlo Analysis
SaberRDs Monte Carlo Analysis
Randomly varies component parameters, and executes
the specified Saber analysis at each set of parameter
values.
Random selection based on tolerance data in models
Saber changes component values every time the loop is
executed
Large or small-signal analyses allowed
Inductance
-10% +10%
Time Delay
-2% +2%
Current
-15% +5%
-30%
Capacitance
+30%
!
Which source of variation
most affects overall variation?
MC Analysis results are
useful for spotting trends
or correlation between a
given measure and a
component parameter
Data can also be
represented in histogram
format
Statistical information such
as circuit mins, maxs,
std dev, etc. are available
Apply Multiple Variations Simultaneously
Min Sensor Voltage vs. Damping (good correlation)
0.6
0.65
0.7
0.75
0.8
0.85
0.9
d(damper_t.visc)()
5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0
(V) : d(damper_t.visc)()
LocMin(sens_point)
_run(-)
0.0
20.0
40.0
rnom(r.pbias)()
8.5k 9.0k 9.5k 10.0k 10.5k 11.0k
Mean: 10022.0
std_dev: 334.25
(1)
count
Tools for Optimizing for Robustness
Pareto Analysis
Monte Carlo simulations produce large amounts of data
How do we turn that data into information?
Pareto analysis rank orders the parameters that have the
biggest effect on the variance of the design performance
measure
results analysis
simulation
Pareto Analysis
Monte Carlo results show
the effect of tolerances
Including parametric
interdependency
Pareto results provide
correlation data about the
impact of tolerances on the
design performance
measure
monte carlo simulation
plot signal
of interest
plot measurement
of interest
pareto analysis on measurement
parameter
file
Pareto Analysis (cont.)
Results provide information
on the impact of parameter
interaction
Example
Parameter B has an effect
on performance, but only
when parameter A is at a
higher-than-nominal level
This will show up in the
correlation analysis
results because some of
the random runs are likely
to be performed with a
high value assigned to A
A
B
Performance
Random runs
Pareto Scatter Plots
Least-Squares
fit lines generated
automatically by
Pareto
Pareto Sensitivity and R
2
Histograms
(-)
(-)
Over(vout)
0.0
2.0
par(-)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-2.0
0.0
2.0
(-) : par(-)
R**2
(-) : par(-)
Sensitivity
c(c.c1)
c(c.c1)
l (l .l1)
l (l .l1)
rnom(r.r1)
rnom(r.r1)
rnom(r.r2)
rnom(r.r2)
Over(vout)
Over(vout)
Sensitivity or Main Effect Histograms
indicate magnitude and direction of
least-squared fit line though correlation
scatter plots
R
2
Correlation histograms
indicate the tightness of the
scatter points around the least-
squared fit line
Histograms can be created
for any measurement
Interpreting Pareto
Sensitivity or Main Effect can be thought of as the slope of best fit line
R
2
can be thought of as tightness of scatter points around best fit line
Summarizing this example we see:
l(l.l1) has weak, positive correlation (Sensitivity) and little relative
contribution (R
2
) to changes in the overshoot of vout
rnom(r.r1) has stronger, negative correlation (Sensitivity) and
greater relative contribution (R
2
) to changes in the overshoot of vout
(-)
(-)
Over(vout)
0.0
2.0
par(-)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-2.0
0.0
2.0
(-): par(-)
R**2
(-): par(-)
Sensitivity
c(c.c1)
c(c.c1)
l(l.l1)
l(l.l1)
rnom(r.r1)
rnom(r.r1)
rnom(r.r2)
rnom(r.r2)
Over(vout)
Over(vout)
Example Results
Example Results
Review: Robust Design Flow
performance
measure(s)
model(s)
nominal
design &
optimization
sensitivity
analysis
robust
design
parameters /
tolerances
monte carlo
simulations
pareto
analysis
Observations
Observations:
Statistical analyses
1. Yield valuable data
2. Are very important in analyzing the robustness of a
system
3. Are computationally intensive by nature
Statistical analyses are a good candidate for using
parallel computing
SaberRDallows this through a feature called Distributed
Iterative Analysis (DIA)
Distribute iterative analyses of a design
across a compute network to reduce
overall analysis time
Enables more iterations (of design and
variations) to meet quality goals
Typically 1000 runs per design
Example with 24 CPUs: Reduced turn
around time from 48 hours to 2+ hours
(~24x)
Simulation sent to the Grid
Results gathered from the Grid
Grid Computing with Saber
45 minutes
Lab 14: Monte Carlo and Pareto Analysis
perform a Monte Carlo
analysis on the RLC circuit
then use Pareto Analysis to
determine sensitivity.
Edition for the training, follow
the extra Student Edition
instructions in the lab guide.
The Student Edition limits
Monte Carlo runs to 10.
Open Design
Perform Monte Carlo
Analysis
Perform Pareto
Analysis
Generate Scatter Plot
Close Design
Lab 14: Review
1. Design Quality
Does Tolerance Stack-up affect your ability to meet design
specifications?
Work with suppliers to improve tolerances on those components
or more specifically, parametersthat will give you the best ROI
Increase design confidence without prototyping
2. Design Optimization
Where are the areas of over-design?
Trade-off tight tolerances in favor of cost savings in areas that do
not affect overall performance
Agenda
Modeling: TLU 11
2
WCA is essential in fault-intolerant and safety-
critical systems.
Also, sub-systems are complex, how do you
determine the minimums and maximums of
important parameter values?
Motivation
Traditional Approaches: Variation Analysis
Deterministic approach
Discrete set of parameter values (defined by the user)
to analyze the parameter space
Benefit
Easy to set up & quick overview of influences thru
variations
Drawbacks
May not uncover the worst case (no search-based
method)
Requires the definition of a search grid (overwhelming
for a large parameter space)
Traditional Approaches: Monte Carlo Analysis
Statistical approach
Discrete analysis of parameter space using a random based
algorithm
Uses distribution functions to define tolerances and
associated probability behavior
Benefit
Overview of behavior across the entire parameter space
Drawbacks
May not uncover the worst case (no search-based method)
Requires implicit definition of a search grid (distribution
functions + number of runs)
Computationally expensive
Traditional Approaches: EVA
Extreme Value Analysis
Deterministic approach
Discrete analysis investigating the extremes/corners of
the parameter space
Benefit
Easy to set up
Drawbacks
Parameter space between extremes/corners is not
considered
Worst case may be missed
Traditional Approaches: RSS
Root Sum Square
Statistical approach
Based on Central Limit Theorem
Combination of overall parameter statstics into a single
normal (Gaussian) statistical distribution
Worst Case defined as the 3 value of combined distribution
Benefit
More realistic results than EVA
Drawbacks
Assume linearity between parameter and behavior (constant
sensitivity)
Worst case may be missed for more complex circuits
Traditional Methods Conclusion
No guarantee to uncover worst case behavior
All methods are lacking a target-oriented
algorithm
Can even fail for very simple designs (eg. voltage
divider)
No confident results to finally qualify the
robustness of an implementation for sign-off
Saber WCA Overview
Purpose is to overcome the limitations of
traditional methods
Confident uncoverage of worst case
Easy to use
Technical requirements
Search-based algorithms
Flexible definition of WCA objectives (e.g. Min, Max)
Re-use of existing design set up (e.g. MC tolerances)
Intuitive graphical user interface
Sabers WCA Solution
Saber WCA
Solution
Design Parameter
Tolerance Values
Design Unit under
Test
WCA Objectives
WC Parameter Values
WC Behavior
Workflow
Design
Creation
Design
Creation
Definition
Test
Definition
WCA WCA
Execution
Results
Evaluation
Results
Evaluation
- Sabers modeling library
- Customized HDL models
- Models from suppliers
- WCA objectives
- Constraints definitions
- Algorithm selection
- 1-click solution
- Analysis monitoring
- In-Analysis adjustment
- WCA Parameter export
- Robustness verification
- Design decision
Test Definition Made Easy
Test definition
Intuitive drag & drop solution
Analysis Definition
Measurements & objectives
Multi objective definition
Library of powerful algorithms
Algorithms the key to success with WCA
Search Algorithms
Local & global algorithms
Combined search possible to
leverage synergy of different
methods
Customized calibration
possible
Example
AC Source Rectifier
DC/DC Converter
Variable Load
Supply Voltages
Feedback Loop
The Challenge
Steady state level of output voltage across load varies
due to design tolerances
What are the Worst Case values (upper & lower limit)?
Output Voltage
Steady State
?
?
The Solution
WCA tool calculates WC limits
Significant deviation from
nominal behavior (27.9V)
Lower Limit
Upper Limit
Comparison with Monte Carlo
Voltage values within boundaries of WCA results
Monte Carlo does not uncover the Worst Case
Does this mean that Monte Carlo is not necessary?
Goal Method
Identify parameters to
reduce variation
Monte Carlo
and Pareto
Goal Method
reduce variation
Monte Carlo
and Pareto
Identify +/- 3- Monte Carlo
Goal Method
reduce variation
Monte Carlo
and Pareto
Identify +/- 3- Monte Carlo
Identify conditions that
lead to worst-case
WCA
45 minutes
Lab 15: WCA
run a worst-case analysis on
a voltage divider circuit
on the page titled
Lab #15 in your exercise
manual.
Edition for the training, skip
this entire lab. WCA is not
enabled in the Student
Edition.
Open Design
Run a Range Search
Run a Corner Search
Compare Results
Agenda
1
Agenda
1
FFT 6
Agenda
Modeling: TLU 11
2
Serves Experts and Casual Users
Proven technology, broad application
coverage
Easy to Use
Intuitive UI guides the flow
Embeds Methodology
Test-driven results for electro-* systems
design & verification: system performance,
robustness, reliability
Deployable throughout Enterprises
Standards-based, compatible with CAE
environments & flows, supply chains
Desktop Simulation for Electro-* Systems
Thank you!
Appendices
Appendix A: SaberRD Applications
Appendix B: SaberRD Measurements
Appendix C: MAST Preview & Netlists
Appendix D: More About SaberRD
SaberRD Features
SaberRD Applications
SaberRD Algorithms
SPICE Import
Appendix E: SaberRD Simulation Controls
Appendix A
General Purpose Non-Linear Ordinary Algebraic Differential
equation solver integrated with an event scheduler
Primary function is to optimize mixed-signal and mixed physical
domain systems and circuits
Used for top down or bottom up design methodology. System
(Control system) abstraction to hardware implementation.
Examples of Specific Applications:
Linear and mixed-signal ASICs (Regulators, Multiplexers, PWMs,
Oscillators, etc.)
Linear and mixed-signal Boards (Sensor interface circuits, micro-
processor (software algorithms), motor drivers, etc.)
Switching Power Supplies both full implementation and
State average (Buck, Boost, Inverters etc.)
Servo Mechanisms (Disk controllers, Satellite
positioning, Throttle actuators etc.)
Mechatronic Systems (Doorlock Assemblies,
Windshield wipers, Sun Roof, Soft Start on
compressors etc.)
Electro-Hydraulic (Fuel Injection, Automotive
Transmission Controller, Sprayer Mechanisms)
Sampled Data System (Digital Filters, Data acquisition
systems etc.)
SaberRD Measurements
Appendix B
SaberRD Measurements
Measurements are the key to design analysis
Over 60 built-in measurements at your fingertips
You can add custom measurements
Measurements transform simulation data into design
information
Measurements
Time Domain:
duty cycle, frequency, period, pulsewidth, risetime, falltime, slew
rate, delay, overshoot, undershoot, settle time, slope
Frequency Domain:
lowpass, highpass, bandpass (Q, ripple, etc.), stopband, phase
margin, gain margin, group delay, slope
Reference or level measurements:
max, min, X at max, X at min, peak to peak, topline, baseline,
amplitude, average, RMS, AC-coupled RMS
General Measurements:
at X, at Y, delta X, delta Y, length, slope, local min/max, crossing,
horiz. level, vert. level, point marker
Statistics:
Max, min, range, mean, median, std. deviation, mean (+/- 3 std
dev), histogram, yield, Dpu, Cpk
MAST Preview
Appendix C
Mixed-Signal Hardware Description Language
MAST is a fully functional Mixed-signal Hardware
Description Language (MSHDL)
The simulator accepts an ASCII file
The model development procedure is as follows:
Write your model in MAST and put file in your working
directory.
Existing models can be included with the equations of a new
model (i.e. netlist entries can be put into model)
General Template Syntax and Structure
template header
unit and pin_type definitions
header declarations
{
local declarations
parameters {
parameter assignments
}
netlist statements
when {
state assignments
}
values {
value assignments
}
control_section {
simulator-dependent control statements
}
equations {
equations describing behavior
}
}
Resistor Template (Equations)
MAST Template
template resistor p m = res
electrical p, m
number res
{
equations {
i(p->m) += v(p,m)/res
}
}
p m
res
i
r
+ v
r
-
Characteristic Equation:
i
r
= v
r
/ res
Resistor with Power (Values)
template resistor p m = res
electrical p, m
number res
{
val p power
val i ires
values {
ires = v(p,m)/res
power = v(p,m)*ires
}
equations {
i(p->m) += ires
}
}
Resistor with Temperature (Parameters)
element template r_temp p m = rnom, tc1, tc2, tnom
electrical p,m
number rnom, tc1=0, tc2=0, tnom = 27
external number temp
{
number r_tmp
parameters {
r_tmp = rnom*(1+tc1*(temp-tnom)+tc2*(temp-tnom)**2)
}
equations {
i(p->m) += v(p,m)/r_tmp
}
}
Constant Current Source Template
MAST Template
template isource p m = cur
electrical p, m
number cur
{
equations {
i(p->m) += cur
}
}
p m
cur
cur = constant
Capacitor Template
MAST Template
template capacitor p m = cap
electrical p, m
number cap
{
equations {
i(p->m) += d_by_dt(cap * v(p,m))
}
}
p m
i
c
cap
+ v
c
d(cap*v
c
)
dt
i
c
=
Inductor Template
MAST Template
template inductor p m = ind
electrical p, m
number ind
{
var i il
equations {
i(p->m) += il
il: v(p,m) = d_by_dt(ind*il)
}
}
iL
ind
+ vL -
p m
v
L
=
d(ind*i
L
)
dt
VCVS Template
MAST Template
template vcvs vp vm p m = gain
electrical vp, vm, p, m
number gain
{
var i iout
equations {
i(p->m) += iout
iout: v(p,m) = gain*v(vp, vm)
}
}
VCVS
vp
vm
p
m
vin vout
vout = gain*vin
Choose iout such that Kirchoffs Voltage Law is satisfied
Digital Inverter
MAST Template
template inverter in out
state logic_4 in, out
{
when (event_on(in)) {
if (in == l4_0) schedule_event(time, out, l4_1)
else if (in == l4_1) schedule_event(time, out, l4_0)
else if (in == l4_x) schedule_event(time, out, l4_x)
}
}
Theres no l4_z here since the output is unchanged (dont do anything)
out in
Truth Table
IN OUT
l4_0 l4_1
l4_1 l4_0
l4_X l4_X
l4_Z unchanged
Mechanical Mass Template (translational)
MAST Template
template mass pos = mass
translational_pos pos # Position connection.
number mass # Mass constant.
{
var vel_mps vel # Differential velocity.
equations {
frc_N(pos) += d_by_dt(-mass * vel)
vel: vel = d_by_dt(pos_m(pos))
}
}
force = -1 * mass * acceleration(pos)
Mechanical Spring Template (translational)
force = -1 * k * [(pos1 - pos2) - delta0]
MAST Template
template spring_t pos1 pos2 = k, delta0
translational_pos pos1, pos2 # Position connections.
number k, # Spring constant.
delta0 = 0 # Equilibrium position of spring (where force =0).
{
val frc_N force_mks
val pos_m posn_mks # Differential position (meters).
values {
posn_mks = pos_m(pos1) - pos_m(pos2) # Distance between the inputs.
force_mks = -1*k*(posn_mks - delta0) # Restraining force (N).
}
equations {
frc_N(pos1->pos2) += force_mks
}
}
2-bit ADC Converter
element template adc2_l4 in refin clk ena q2 q1 gnd = td
electrical refin, gnd, in
state logic_4 q2,q1,clk,ena
number td = 1n # delay time
{
state v vin, vref, ref1, ref2
state time outtime
when (event_on(clk) & (clk == l4_1) & (ena == l4_1)) {
vin = v(in) - v(gnd)
vref = (v(refin) - v(gnd))*0.5 # Set MSB
ref2 = vref
ref1 = vref*0.5
outtime = time + td
# MSB
if (vin >= ref2) {
vin = vin - ref2
if (q2 ~= l4_1) schedule_event(outtime,q2,l4_1)
}
else if (q2 ~= l4_0) schedule_event(outtime,q2,l4_0)
# Next bit
if (vin >= ref1) {
vin = vin - ref1
if (q1 ~= l4_1) schedule_event(outtime,q1,l4_1)
}
else if (q1 ~= l4_0) schedule_event(outtime,q1,l4_0)
MAST References
SaberRD Help
Guide to Writing MAST Templates
MAST Reference Manual
Introduction to MAST Workshop
Advanced Saber/MAST Workshop
Modeling with An Analog Hardware Description
Language (Mantooth and Fiegenbaum; Kluwer
Academic publishers)
Netlists
A netlist is an ASCII description of a circuit/system
SaberRD performs simulations on netlists
Netlists can be generated as follows:
Automatically from SaberRD as needed (if the schematic has
been updated and saved, SaberRD will generate a netlist prior
to simulating)
By hand
Why Should You Understand Netlists?
In the labs you have just completed, the instructions you were given should have
allowed you to progress through without many difficulties. But what do you do when
you DO encounter a problem?
Often, the best way to identify schematic entry or syntax problems in your design is
to go to the netlist. There are some good reasons to do this:
Often, SaberRD will give you a warning or error message that
directly references the line number in a netlist.
The netlist (not the schematic) is what is actually read in and
used by the simulator. It is your direct link to SaberRD
Sometimes you will want to see the actual template argument
syntax as it appears in the netlist, rather than the way you may
add it at the schematic level (these are often different to
simplify schematic entry).
Netlists
Squares represent component pins (p and m are pin names),
and dots represent connection pointscircuit nodes (in, out, x
are net names). The netlist, or description of this symbolic
circuit representation would be:
Constants do not have units in SaberRD.
p m
capacitor.c1
inductor.l1 resistor.r1
x
m
m
p
p
in out
1m
1k
1u
Netlists
p m
capacitor.c1
inductor.l1 resistor.r1
x
m
m
p
p
in out
1m
1k
1u
inductor.l1 p:in m:x = l = 1m
resistor.r1 p:x m:out = rnom = 1k
capacitor.c1 p:in m:out = c = 1u
Netlists - Pin Connections
Example: r.load out 0 = 47
template_name is the name of the template.
instance_name (also known as refdes (reference designator))
is an identifier which for this template is unique in this netlist.
connection_point_assignments assign the templates
connection points to the netlists nodes. If the
connection_point_assignments are in the same order that the
connection points appear in the template header, then only the
nodes need be named; otherwise, use explicit assignments:
connection_point_name:node_name
Example: r.load p:out m:0 = 47
Netlists - Argument Assignments
Arguments are assigned as a comma (,) separated list of
expressions which assigns values to the templates
arguments. Any legal MAST expression of parameters and
constants may be used. If the argument assignments are in
the same order that the arguments appear in the template
header, then only the expressions need be named.
Otherwise, use explicit assignments:
argument_name = expression
Example: r.load out 0 = rnom = 47
Example: r.1 a b = rnom = res * sin(math_pi/3)
Netlist - Example
Netlist - Example
r.r1 p:vcc m:top_base = rnom=1k
r.r2 p:top_base m:n_1 = rnom=3.3k
r.r3 p:n_2 m:bot_base = rnom=3.3k
r.r4 p:bot_base m:vee = rnom=1k
r.r5 p:vin m:in_base = rnom=27k
q2n3904.q3 b:in_base c:n_1 e:0
q2n3906.q4 b:in_base c:n_2 e:0
q2n2907a.q1 b:top_base c:out e:vcc
q2n3227.q2 b:bot_base c:out e:vee
v_dc.vcc p:vcc m:0 = dc_value=15
v_dc.vee p:0 m:vee = dc_value=15
v_pulse.in p:vin m:0 = initial=5, pulse=5, \
width=200u, period=1m, \
tr=1u, tf=1u, ac_mag=1, ac_phase=0
Netlist Review
Netlists are the text files that SaberRD actually uses for
simulation
Certain simulation problems are best to troubleshoot at
the netlist level
References: Introduction to MAST Modeling Workshop
More About SaberRD
Appendix D
Appendix D: More About SaberRD
This section covers:
SaberRD Features
SaberRD Algorithms
SPICE to SaberRD Conversion
SaberRD Features
Mixed-signal and multi-technology simulator
Fully supported mixed-signal hardware description languages (MAST and
VHDL-AMS)
Large library of models. New models can be added through the hardware
description language. (i.e. motors, gears, cavitation, flexible lines,
A to Ds, D-flip flops, Z-domain rational polynomials, State Averaged Power
Supply models etc.)
Large Component Library (i.e. same as Spice plus fuses, motors,
magnetic cores, switches, A to Ds, PWMs, Schmitt triggers, etc.)
Engineering units are maintained by the simulator
Can simulate signal flow diagrams and perform classical control analysis
Can cosimulate with digital and signal-flow simulators
Can extract any signal or variable in the simulation that was not specified
when the simulation was run
SaberRD Features
No circuit/system size limitations as well no limitation on simulation
size
Piecewise linear algorithm yields superior convergence
Post Processing including a waveform calculator and over 60 built-
in measurements (i.e. rms, 3 db, Cpk, risetime, period, phase
margin)
Can link C/C++ and FORTRAN code as well as write functions in
MAST and VHDL-AMS
Can stop, change parameters, and restart the simulator
Has a scripting language (AIM) that controls the simulator,
analyses and post-processing
SaberRD Algorithms
Trapezoidal, Euler and Gear integration algorithms
The Calaveras algorithm for handling mixed mode and
mixed signal simulations
Variable time step algorithm
Newton-Raphson:
Where F(x) = xs
F(x) = d F(x)
d x
F(x) and F(x) must be explicitly
known and coded into the simulator. This gives
an approximate solution to the exact problem.
x
F(x)
(x
0
,F(x
0
),F(x
0
))
(x
1
,F(x
1
),F(x
1
))
(x
2
,F(x
2
),F(x
2
))
(x
3
,F(x
3
),F(x
3
))
error
Newton-Raphson Algorithm
Piecewise Linear Newton-Raphson:
F
a
(x)
x
(x
0
,F
a
(x
0
))
(x
1
,F
a
(x
1
))
(x
2
,F
a
(x
2
))
(x
3
,F
a
(x
3
))
Fa(x) is the piecewise linear approximation of F(x). All that is needed for this
solution is F(x). SaberRD gives the exact solution to an approximate problem.
Because the problem is made piecewise linear, there is a higher likelihood of
convergence.
SaberRDs N-R Algorithm
SaberRD Macro Modeling
Can use the approximately hundreds of primitive
models and thousands of component models to create
a model of a non-existing part or function
Can create macro models in any physical domain
Can mix macro modeling with behavioral modeling in
MAST or VHDL-AMS
Example of Macro Modeling:
(-)
(+)
Vcc
Vee
Vout
uA741 Macro-Model
Macro Modeling
Example of Macro Modeling:
H(s) =
Lag
k
(s/w) + 1
Electrical
to
Control
Interface
p
m
Control
to
Electrical
Interface
p
m
Pressure
to Var
Interface
p1
p2
pres_out
Pressure Input
Supply Voltage
Sensor Output
Hydraulic Pressure Sensor
Macro Modeling
Example of Spice Import:
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* [email protected]
*//////////////////////////////////////////////////////////
*LM6262 High Speed OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | pos. power supply
* | | | neg. power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LM6262/NS 1 2 99 50 28
*
*Features:
*Low supply current = 5mA
*High bandwidth = 100MHz
*High slew rate = 300V/uS
*
****************INPUTSTAGE**************
*
Spice Model of a LM6262
SPICE Import Example
IOS 2 1 150N
*^Input offset current
CI1 1 0 2P
CI2 2 0 2P
R1 1 3 90K
R2 3 2 90K
I1 4 50 1M
R3 99 5 351.7
R4 99 6 351.7
Q1 5 2 45 QX
Q2 6 7 46 QX
R43 45 4 300
R44 46 4 300
*Fp2=230 MHz
C4 5 6 9.8376E-13
*
***********COMMON MODE EFFECT***********
*
I2 99 50 4M
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 3E-3 1
*Input offset voltage.^
R8 99 49 80K
R9 49 50 80K
*
*********OUTPUTVOLTAGE LIMITING********
V2 99 8 1.43
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.23
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
F1 9 98 POLY(1) VA1 0 0 0 .85
G1 98 9 POLY(1) 5 6 0 6.5E-3 0 8.646E-3
*Fp1=17.935 KHz
R5 98 9 1MEG
C3 98 9 8.874P
*
***************POLESTAGE***************
*
*Fp=230 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 6.9198E-16
*
***************POLESTAGE***************
*
*Fp=250 MHz
G5 98 18 15 49 1E-6
R15 98 18 1MEG
C6 98 18 6.3662E-16
*
*********COMMON-MODEZERO STAGE*********
*
*Fpcm=10 KHz
G4 98 16 3 49 1E-8
L2 98 17 15.915E-3
R13 17 16 1K
*
**************OUTPUTSTAGE**************
*
F6 50 99 POLY(1) V6 200U 1
VA1 99 93 0
E1 93 23 99 18 1
R16 24 23 10
D5 26 24 DX
V6 26 22 .63V
R17 23 25 10
D6 25 27 DX
C9 23 22 200P
V7 22 27 .63V
V5 22 21 .23V
D4 21 18 DX
V4 20 22 .23V
D3 18 20 DX
L3 22 28 100P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DXD(IS=1E-15)
.MODEL QXNPN(BF=227.3)
*
.ENDS
SaberRD Model of the LM6262
#//////////////////////////////////////////////////////////////////////
# (C) National Semiconductor,Inc.
# Models developed and under copyright by:
# National Semiconductor,Inc.
#
#/////////////////////////////////////////////////////////////////////
# Legal Notice: This material is intended for free software support.
# The file may be copied,and distributed
# material is illegal
#
#////////////////////////////////////////////////////////////////////
# For ordering or technical information on these models,contact:
# National Semiconductor's Customer Response Center
# 7:00 A.M.--7:00 P.M. U.S. Central Time
# (800) 272-9959
# For Applications support,contact the Internet address:
# [email protected]
#
#//////////////////////////////////////////////////////////
#LM6262 High Speed OP-AMP MACRO-MODEL
#//////////////////////////////////////////////////////////
#
# connections: non-inverting input
# | inverting input
# | | positive power supply
# | | | negative power supply
# | | | | output
# | | | | |
# | | | | |
template lm6262_sns 1 2 99 50 28
{
d..model dx = (is=1.00e-15)
spq..model qx = (type=_n,bf=2.27e+02)
#
#Features:
#Low supply current = 5mA
#High bandwidth = 100MHz
#High slew rate = 300V/uS
#
################INPUTSTAGE##############
#
spi.os 2 1 = dc=150n
#^Input offset current
c.i1 1 0 = 2p
c.i2 2 0 = 2p
res.1 1 3 = 90k
res.2 3 2 = 90k
spi.1 4 50 = dc=1m
res.3 99 5 = 3.52e+02
res.4 99 6 = 3.52e+02
spq.1 5 2 45 0 = model=qx
spq.2 6 7 46 0 = model=qx
res.43 45 4 = 300
res.44 46 4 = 300
#Fp2=230 MHz
c.4 5 6 = 9.84e-13
#
###########COMMON MODE EFFECT###########
#
spi.2 99 50 = dc=4m
#^Quiescent supply current
spe1.os 7 1 16 49 = [3e-3,1]
#Input offset voltage.^
res.8 99 49 = 80k
res.9 49 50 = 80k
#
#########OUTPUTVOLTAGE LIMITING########
spv.2 99 8 = dc=1.43
d.1 9 8 = model=dx
d.2 10 9 = model=dx
spv.3 10 50 = dc=2.23
#
##############SECOND STAGE##############
#
spe.h 99 98 99 49 = 1
spf1.1 9 98 i(spv.a1) = [0,0,0,.85]
spg1.1 98 9 5 6 = [0,6.50e-03,0,8.65e-03]
#Fp1=17.935 KHz
res.5 98 9 = 1meg
c.3 98 9 = 8.874p
#
###############POLESTAGE###############
#
#Fp=230 MHz
spg.3 98 15 9 49 = 1e-6
res.12 98 15 = 1meg
c.5 98 15 = 6.92e-16
#
SaberRD Simulation Controls
Appendix E
Appendix E: SaberRD Simulation Controls
The following slides give an overview of the simulation
controls available with SaberRD (the vast majority of
these do not typically need to be adjusted).
SaberRD Simulator Controls
SaberRD has automatic algorithm stepping to aid in
arriving at a DC solution. They are:
No ramping
Gmin ramping
Static ramping (source ramping)
Dynamic ramping
There are >50 control parameters for these algorithms
There are a large number of control parameters for
transient analysis
DC Simulation Controls
Parameter Default Notes
algstart NO_Ramp Specifies the initial algorithm of the pre-defined sequence to start
with or
the single algorithm to be used for the analysis
debug No Display debug information during analysis
holdnodes undefined List nodes that are to be held at specific values during the
operating point analysis
relholdnodes Yes Controls the release of the nodes during final solution of
operating point
monitor 0 Specifies amount of information to display while the simulator if
doing computations
density 1 Specifies the density of the sample points
nsdensity 1 Specifies a global newton step factor
fniter 100 Specifies the maximum number of Newton-Raphson iterations.
Mixed-Signal Simulation Controls
tresolution 1p Specifies the time resolution for the discrete time
simulation.
aditer 3 Specifies the maximum number of Synopsys/digital
iterations.
eviter 5000 Specifies maximum number of event iterations in a
mixed-mode analysis.
Dynamic Supply Ramping Controls
dr_tstep 10n Specif ies the time step f or dy namic ramping
dr_trise 200n Specif ies the ramp rise time f or dy namic ramping.
dr_tsettle 200u Specif ies the settling time f or dy namic ramping
dr_order 2 Specif ies the order of the Gear integration method used in dy namic ramping
dr_terror 0.05 Specif ies the truncation error f or the dy namic ramping
dr_terrnorm dy namic Specif ies the ty pe of norm used f or dy namic ramping truncation error calculations
dr_tniter 10 Specif ies the number Newton-Raphson iterations at each time step in dy namic ramping
dr_samestep 1 Specif ies how many steps are taken of a giv en step size bef ore a longer step size id used f or
dy namic ramping
dr_stepsize v ariable Specif ies the step size control f or dy namic ramping as Fixed or Variable
dr_tsmin 1f Specif ies the minimum time step used f or dy namic ramping
dr_tsmax 0.1 Specif ies the maximum time step used f or dy namic ramping
GMIN Ramping
gbegin 1 Specifies the starting value for gmin ramping
gstep 1000 Specifies the logarithmic step value (divisor) for gmin and ramping
gend 1e-12 Final value of conductance for gmin ramping
gmiter 10 Specifies the maximum number of Newton- Raphson iterations for
each gmin ramping iteration
Static Ramping
Parameter Default
SR_SStep 1e-3
SR_ORDer 2
SR_TERror 0.005
SR_TERRType 6
SR_TNiter 10
SR_SAMEStep 1
SR_STEPsize VARiable
SR_SSMIN 1e-10
SR_SSMAX 1e4
Transient Analysis Controls
tend required Specifies the end time for the simulation.
tstep required Specifies the step size of the first time step and it, by default,
controls the time steps during the simulation. 10
-5
ts < h < 10
7
ts
tbegin undefined Specifies the begin time of the simulation. If undefined the simulation
starts with the values in the IP file. If specified it shifts the values in
the IP file by the specified value.
terror 0.005 Specifies the value which the LTE is compared to.
terrtype dynamic Specifies how the truncation error is calculated. Dynamic uses the
elements which have derivatives. Static uses non derivative elements.
All uses both types.
terrnorm 6 Specifies how the LTE is calculated for comparison to terr. See
SaberRD Book.
density 1 Specifies the multiplier which increases the number of sample points
tresolution 1p Specifies the time resolution for discrete time simulation.
aditer 3 Specifies the number of analog/digital iterations for mixed
signal simulations.
zditer 100 Specifies the maximum number of Newton-Raphson
iterations used at a scheduled time step.
stepsize Variable Determines how the step size (h) is determined. Fixed will cause
fixed time steps to be taken (h=ts) and no LTE checking will be
performed. Variable will cause h to be calculated.
samestep 1 Defines the number of same size time steps (h) when the variable
time step is employed
tsmax undefined If specified it determines the upper limit for h for the variable time
step algorithm.
tsmin undefined If specified it determines the lower limit for h for the variable time
step algorithm.
order 2 Order of the Gear algorithm
method gear Can select either Gear 1, Gear 2 and Trapezoidal
algorithm Newton- Raphson Selects the iteration algorithm. Newton-Raphson should be
used on 99% of the circuit. There is a small class of the
circuits where the other algorithm (Katzenelson) will converge
and Newton-Raphson will not.
tniter 3 Maximum number of Newton-Raphson iterations at each time
step.
fniter 100 Maximum number of iterations of the Newton-Raphson
algorithm when it is selected
fkiter 50 Maximum number of Katzenelson iterations when that
algorithm is selected.
nsdensity 1 Specifies the number Newton Step points relative to the
amount specified in templates of the circuit.
nslimit yes Specifies whether Newton step will be limited at each time
point.
Calaveras Mixed-signal
algorithm
Appendix F
Calaveras Algorithm: Synching A & D
Under-the-hood, SaberRD uses the patented Calaveras
algorithm
for optimal performance
No lost digital events and no lost time resolution most accurate
results.
Unlimited feedback between analog and digital simulators for
complex circuitry.
Calaveras is the fastest, most accurate algorithm.
Digital
Events
Analog
time steps
Roll-back
Simulating with Calaveras
Number indicates sequence of simulation time points
No analog time step at digital step 6. Interpolation is used to find
the crossing point.
Analog time step 7 is ignored and Calaveras rolls-back to analog
time step 9 to syncronize analog and digital. Necessary when
driving an output.
1
2
4
3
5
6
7
8
9
A
Ba
Bd
gate input
threshold
C
11 10
A B C D
SaberRD Mixed-Signal Analysis Summary
The Calaveras Algorithm synchronizes the
analog and digital simulators within the
SaberRD simulator
Optimizes both accuracy and speed
Hypermodels handle signal flow between
analog and digital systems

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