Arm Tm4c123

Tiva
TM4C123AH6PM Microcontroller
(identical to LM4F211H5QR)
DATA SHEET
Copyr i ght 2007- 2013
Texas I nst r ument s I ncor por at ed
DS- TM4C123AH6PM- 14602. 2648
SPMS364
TEXAS I NSTRUMENTS- PRODUCTI ON DATA
Copyright
Copyright 2007-2013 Texas Instruments Incorporated All rights reserved. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM
and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specifcations per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/tm4c
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Texas Instruments-Production Data
Table of Contents
About This Document .................................................................................................................... 33
Audience .............................................................................................................................................. 33
About This Manual ................................................................................................................................ 33
Related Documents ............................................................................................................................... 33
Documentation Conventions .................................................................................................................. 34
1 Architectural Overview .......................................................................................... 36
1.1 Tiva C Series Overview .............................................................................................. 36
1.2 TM4C123AH6PM Microcontroller Overview .................................................................... 37
1.3 TM4C123AH6PM Microcontroller Features ..................................................................... 40
1.3.1 ARM Cortex-M4F Processor Core .................................................................................. 40
1.3.2 On-Chip Memory ........................................................................................................... 42
1.3.3 Serial Communications Peripherals ................................................................................ 44
1.3.4 System Integration ........................................................................................................ 47
1.3.5 Advanced Motion Control ............................................................................................... 52
1.3.6 Analog .......................................................................................................................... 55
1.3.7 JTAG and ARM Serial Wire Debug ................................................................................ 56
1.3.8 Packaging and Temperature .......................................................................................... 57
1.4 TM4C123AH6PM Microcontroller Hardware Details ......................................................... 57
1.5 Kits .............................................................................................................................. 57
1.6 Support Information ....................................................................................................... 57
2 The Cortex-M4F Processor ................................................................................... 58
2.1 Block Diagram .............................................................................................................. 59
2.2 Overview ...................................................................................................................... 60
2.2.1 System-Level Interface .................................................................................................. 60
2.2.2 Integrated Configurable Debug ...................................................................................... 60
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 61
2.2.4 Cortex-M4F System Component Details ......................................................................... 61
2.3 Programming Model ...................................................................................................... 62
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 62
2.3.2 Stacks .......................................................................................................................... 63
2.3.3 Register Map ................................................................................................................ 63
2.3.4 Register Descriptions .................................................................................................... 65
2.3.5 Exceptions and Interrupts .............................................................................................. 81
2.3.6 Data Types ................................................................................................................... 81
2.4 Memory Model .............................................................................................................. 81
2.4.1 Memory Regions, Types and Attributes ........................................................................... 84
2.4.2 Memory System Ordering of Memory Accesses .............................................................. 84
2.4.3 Behavior of Memory Accesses ....................................................................................... 84
2.4.4 Software Ordering of Memory Accesses ......................................................................... 85
2.4.5 Bit-Banding ................................................................................................................... 86
2.4.6 Data Storage ................................................................................................................ 88
2.4.7 Synchronization Primitives ............................................................................................. 89
2.5 Exception Model ........................................................................................................... 90
2.5.1 Exception States ........................................................................................................... 91
2.5.2 Exception Types ............................................................................................................ 91
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2.5.3 Exception Handlers ....................................................................................................... 95
2.5.4 Vector Table .................................................................................................................. 95
2.5.5 Exception Priorities ....................................................................................................... 96
2.5.6 Interrupt Priority Grouping .............................................................................................. 97
2.5.7 Exception Entry and Return ........................................................................................... 97
2.6 Fault Handling ............................................................................................................. 100
2.6.1 Fault Types ................................................................................................................. 101
2.6.2 Fault Escalation and Hard Faults .................................................................................. 101
2.6.3 Fault Status Registers and Fault Address Registers ...................................................... 102
2.6.4 Lockup ....................................................................................................................... 102
2.7 Power Management .................................................................................................... 103
2.7.1 Entering Sleep Modes ................................................................................................. 103
2.7.2 Wake Up from Sleep Mode .......................................................................................... 103
2.8 Instruction Set Summary .............................................................................................. 104
3 Cortex-M4 Peripherals ......................................................................................... 111
3.1 Functional Description ................................................................................................. 111
3.1.1 System Timer (SysTick) ............................................................................................... 112
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 113
3.1.3 System Control Block (SCB) ........................................................................................ 114
3.1.4 Memory Protection Unit (MPU) ..................................................................................... 114
3.1.5 Floating-Point Unit (FPU) ............................................................................................. 119
3.2 Register Map .............................................................................................................. 123
3.3 System Timer (SysTick) Register Descriptions .............................................................. 126
3.4 NVIC Register Descriptions .......................................................................................... 130
3.5 System Control Block (SCB) Register Descriptions ........................................................ 145
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 174
3.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 183
4 JTAG Interface ...................................................................................................... 189
4.1 Block Diagram ............................................................................................................ 190
4.2 Signal Description ....................................................................................................... 190
4.3.1 JTAG Interface Pins ..................................................................................................... 191
4.3.2 JTAG TAP Controller ................................................................................................... 193
4.3.3 Shift Registers ............................................................................................................ 193
4.3.4 Operational Considerations .......................................................................................... 194
4.4 Initialization and Configuration ..................................................................................... 196
4.5 Register Descriptions .................................................................................................. 197
4.5.1 Instruction Register (IR) ............................................................................................... 197
4.5.2 Data Registers ............................................................................................................ 199
5 System Control ..................................................................................................... 201
5.2.1 Device Identification .................................................................................................... 201
5.2.2 Reset Control .............................................................................................................. 202
5.2.3 Non-Maskable Interrupt ............................................................................................... 207
5.2.4 Power Control ............................................................................................................. 207
5.2.5 Clock Control .............................................................................................................. 208
5.2.6 System Control ........................................................................................................... 214
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5.4 Register Map .............................................................................................................. 219
5.5 System Control Register Descriptions ........................................................................... 224
5.6 System Control Legacy Register Descriptions ............................................................... 398
6 System Exception Module ................................................................................... 459
6.2 Register Map .............................................................................................................. 459
7 Internal Memory ................................................................................................... 467
7.1 Block Diagram ............................................................................................................ 467
7.2.1 SRAM ........................................................................................................................ 468
7.2.2 ROM .......................................................................................................................... 469
7.2.3 Flash Memory ............................................................................................................. 471
7.2.4 EEPROM .................................................................................................................... 477
7.3 Register Map .............................................................................................................. 482
7.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 483
7.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 501
7.6 Memory Register Descriptions (System Control Offset) .................................................. 518
8 Micro Direct Memory Access (DMA) ................................................................ 527
8.1 Block Diagram ............................................................................................................ 528
8.2.1 Channel Assignments .................................................................................................. 529
8.2.2 Priority ........................................................................................................................ 530
8.2.3 Arbitration Size ............................................................................................................ 530
8.2.4 Request Types ............................................................................................................ 530
8.2.5 Channel Configuration ................................................................................................. 531
8.2.6 Transfer Modes ........................................................................................................... 533
8.2.7 Transfer Size and Increment ........................................................................................ 541
8.2.8 Peripheral Interface ..................................................................................................... 541
8.2.9 Software Request ........................................................................................................ 541
8.2.10 Interrupts and Errors .................................................................................................... 542
8.3.1 Module Initialization ..................................................................................................... 542
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 543
8.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 544
8.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 546
8.3.5 Configuring Channel Assignments ................................................................................ 548
8.4 Register Map .............................................................................................................. 548
8.5 DMA Channel Control Structure ................................................................................. 550
8.6 DMA Register Descriptions ........................................................................................ 557
9 General-Purpose Input/Outputs (GPIOs) ........................................................... 591
9.2.1 Data Control ............................................................................................................... 595
9.2.2 Interrupt Control .......................................................................................................... 596
9.2.3 Mode Control .............................................................................................................. 597
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9.2.4 Commit Control ........................................................................................................... 598
9.2.5 Pad Control ................................................................................................................. 598
9.2.6 Identification ............................................................................................................... 598
9.4 Register Map .............................................................................................................. 600
10 General-Purpose Timers ...................................................................................... 645
10.1 Block Diagram ............................................................................................................ 646
10.3.1 GPTM Reset Conditions .............................................................................................. 649
10.3.2 Timer Modes ............................................................................................................... 650
10.3.3 Wait-for-Trigger Mode .................................................................................................. 659
10.3.4 Synchronizing GP Timer Blocks ................................................................................... 660
10.3.5 DMA Operation ........................................................................................................... 660
10.3.6 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 661
10.3.7 Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 661
10.4.1 One-Shot/Periodic Timer Mode .................................................................................... 663
10.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 664
10.4.3 Input Edge-Count Mode ............................................................................................... 664
10.4.4 Input Edge Timing Mode .............................................................................................. 665
10.4.5 PWM Mode ................................................................................................................. 665
10.5 Register Map .............................................................................................................. 666
11 Watchdog Timers ................................................................................................. 715
11.1 Block Diagram ............................................................................................................ 716
11.2.1 Register Access Timing ............................................................................................... 717
11.4 Register Map .............................................................................................................. 717
12 Analog-to-Digital Converter (ADC) ..................................................................... 740
12.1 Block Diagram ............................................................................................................ 741
12.3.1 Sample Sequencers .................................................................................................... 743
12.3.2 Module Control ............................................................................................................ 744
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 747
12.3.4 Analog-to-Digital Converter .......................................................................................... 748
12.3.5 Differential Sampling ................................................................................................... 751
12.3.6 Internal Temperature Sensor ........................................................................................ 753
12.3.7 Digital Comparator Unit ............................................................................................... 754
12.4.1 Module Initialization ..................................................................................................... 758
12.4.2 Sample Sequencer Configuration ................................................................................. 759
12.5 Register Map .............................................................................................................. 759
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13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 834
13.1 Block Diagram ............................................................................................................ 835
13.3.1 Transmit/Receive Logic ............................................................................................... 836
13.3.2 Baud-Rate Generation ................................................................................................. 837
13.3.3 Data Transmission ...................................................................................................... 838
13.3.4 Serial IR (SIR) ............................................................................................................. 838
13.3.5 ISO 7816 Support ....................................................................................................... 839
13.3.6 Modem Handshake Support ......................................................................................... 840
13.3.7 9-Bit UART Mode ........................................................................................................ 841
13.3.8 FIFO Operation ........................................................................................................... 841
13.3.9 Interrupts .................................................................................................................... 841
13.3.10 Loopback Operation .................................................................................................... 842
13.3.11 DMA Operation ........................................................................................................... 843
13.5 Register Map .............................................................................................................. 844
14 Synchronous Serial Interface (SSI) .................................................................... 893
14.1 Block Diagram ............................................................................................................ 894
14.3.1 Bit Rate Generation ..................................................................................................... 895
14.3.2 FIFO Operation ........................................................................................................... 896
14.3.3 Interrupts .................................................................................................................... 896
14.3.4 Frame Formats ........................................................................................................... 897
14.3.5 DMA Operation ........................................................................................................... 904
14.5 Register Map .............................................................................................................. 906
15 Inter-Integrated Circuit (I
2
C) Interface ................................................................ 936
15.1 Block Diagram ............................................................................................................ 937
15.3.1 I
2
C Bus Functional Overview ........................................................................................ 938
15.3.2 Available Speed Modes ............................................................................................... 943
15.3.3 Interrupts .................................................................................................................... 945
15.3.4 Loopback Operation .................................................................................................... 946
15.3.5 Command Sequence Flow Charts ................................................................................ 946
15.5 Register Map .............................................................................................................. 956
15.6 Register Descriptions (I
2
C Master) ............................................................................... 957
2
C Slave) ................................................................................. 974
2
C Status and Control) .............................................................. 984
16 Controller Area Network (CAN) Module ............................................................. 987
16.1 Block Diagram ............................................................................................................ 988
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16.3.1 Initialization ................................................................................................................. 990
16.3.2 Operation ................................................................................................................... 990
16.3.3 Transmitting Message Objects ..................................................................................... 991
16.3.4 Configuring a Transmit Message Object ........................................................................ 992
16.3.5 Updating a Transmit Message Object ........................................................................... 993
16.3.6 Accepting Received Message Objects .......................................................................... 993
16.3.7 Receiving a Data Frame .............................................................................................. 994
16.3.8 Receiving a Remote Frame .......................................................................................... 994
16.3.9 Receive/Transmit Priority ............................................................................................. 995
16.3.10 Configuring a Receive Message Object ........................................................................ 995
16.3.11 Handling of Received Message Objects ........................................................................ 996
16.3.12 Handling of Interrupts .................................................................................................. 998
16.3.13 Test Mode ................................................................................................................... 999
16.3.14 Bit Timing Configuration Error Considerations ............................................................. 1001
16.3.15 Bit Time and Bit Rate ................................................................................................. 1001
16.3.16 Calculating the Bit Timing Parameters ........................................................................ 1003
16.4 Register Map ............................................................................................................ 1006
16.5 CAN Register Descriptions ......................................................................................... 1007
17 Analog Comparators .......................................................................................... 1038
17.1 Block Diagram ........................................................................................................... 1039
17.2 Signal Description ..................................................................................................... 1039
17.3 Functional Description ............................................................................................... 1040
17.3.1 Internal Reference Programming ................................................................................ 1041
17.4 Initialization and Configuration .................................................................................... 1043
17.5 Register Map ............................................................................................................ 1043
17.6 Register Descriptions ................................................................................................. 1044
18 Pulse Width Modulator (PWM) .......................................................................... 1053
18.1 Block Diagram ........................................................................................................... 1054
18.3.1 PWM Timer ............................................................................................................... 1057
18.3.2 PWM Comparators .................................................................................................... 1057
18.3.3 PWM Signal Generator .............................................................................................. 1058
18.3.4 Dead-Band Generator ............................................................................................... 1059
18.3.5 Interrupt/ADC-Trigger Selector ................................................................................... 1060
18.3.6 Synchronization Methods .......................................................................................... 1060
18.3.7 Fault Conditions ........................................................................................................ 1061
18.3.8 Output Control Block .................................................................................................. 1062
18.5 Register Map ............................................................................................................ 1063
19 Quadrature Encoder Interface (QEI) ................................................................. 1131
19.1 Block Diagram ........................................................................................................... 1131
19.5 Register Map ............................................................................................................ 1136
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20 Pin Diagram ........................................................................................................ 1154
21 Signal Tables ...................................................................................................... 1155
21.1 Signals by Pin Number .............................................................................................. 1156
21.2 Signals by Signal Name ............................................................................................. 1163
21.3 Signals by Function, Except for GPIO ......................................................................... 1170
21.4 GPIO Pins and Alternate Functions ............................................................................ 1176
21.5 Possible Pin Assignments for Alternate Functions ....................................................... 1178
21.6 Connections for Unused Signals ................................................................................. 1182
22 Electrical Characteristics .................................................................................. 1183
22.1 Operating Characteristics ........................................................................................... 1183
22.2 Maximum Ratings ...................................................................................................... 1184
22.3 Recommended Operating Conditions ......................................................................... 1185
22.4 Load Conditions ........................................................................................................ 1187
22.5 JTAG and Boundary Scan .......................................................................................... 1188
22.6 Power and Brown-Out ............................................................................................... 1190
22.6.1 VDDA Levels ............................................................................................................ 1190
22.6.2 VDD Levels ............................................................................................................... 1191
22.6.3 VDDC Levels ............................................................................................................ 1192
22.6.4 VDD Glitches ............................................................................................................ 1193
22.6.5 VDD Droop Response ............................................................................................... 1193
22.7 Reset ........................................................................................................................ 1195
22.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1197
22.9 Clocks ...................................................................................................................... 1198
22.9.1 PLL Specifications ..................................................................................................... 1198
22.9.2 PIOSC Specifications ................................................................................................ 1199
22.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 1199
22.9.4 Main Oscillator Specifications ..................................................................................... 1199
22.9.5 System Clock Specification with ADC Operation .......................................................... 1202
22.10 Sleep Modes ............................................................................................................. 1203
22.11 Flash Memory and EEPROM ..................................................................................... 1205
22.12 Input/Output Pin Characteristics ................................................................................. 1206
22.12.1 GPIO Module Characteristics ..................................................................................... 1206
22.12.2 Types of I/O Pins and ESD Protection ......................................................................... 1206
22.13 Analog-to-Digital Converter (ADC) .............................................................................. 1210
22.14 Synchronous Serial Interface (SSI) ............................................................................. 1213
22.15 Inter-Integrated Circuit (I
2
C) Interface ......................................................................... 1215
22.16 Analog Comparator ................................................................................................... 1216
22.17 Current Consumption ................................................................................................. 1218
22.17.1 Current Consumption ................................................................................................. 1218
A Package Information .......................................................................................... 1220
A.1 Orderable Devices ..................................................................................................... 1220
A.2 Part Markings ............................................................................................................ 1220
A.3 Packaging Diagram ................................................................................................... 1220
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List of Figures
Figure 1-1. Tiva
TM4C123x Block Diagram .......................................................................... 37

Figure 1-2. Tiva TM4C123AH6PM Microcontroller High-Level Block Diagram ........................... 39
Figure 2-1. CPU Block Diagram ............................................................................................. 60
Figure 2-2. TPIU Block Diagram ............................................................................................ 61
Figure 2-3. Cortex-M4F Register Set ...................................................................................... 64
Figure 2-4. Bit-Band Mapping ................................................................................................ 88
Figure 2-5. Data Storage ....................................................................................................... 89
Figure 2-6. Vector Table ........................................................................................................ 96
Figure 2-7. Exception Stack Frame ........................................................................................ 99
Figure 3-1. SRD Use Example ............................................................................................. 117
Figure 3-2. FPU Register Bank ............................................................................................ 120
Figure 4-1. JTAG Module Block Diagram .............................................................................. 190
Figure 4-2. Test Access Port State Machine ......................................................................... 193
Figure 4-3. IDCODE Register Format ................................................................................... 199
Figure 4-4. BYPASS Register Format ................................................................................... 199
Figure 4-5. Boundary Scan Register Format ......................................................................... 200
Figure 5-1. Basic RST Configuration .................................................................................... 204
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 204
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 205
Figure 5-4. Power Architecture ............................................................................................ 208
Figure 5-5. Main Clock Tree ................................................................................................ 210
Figure 5-6. Module Clock Selection ...................................................................................... 217
Figure 7-1. Internal Memory Block Diagram .......................................................................... 467
Figure 7-2. EEPROM Block Diagram ................................................................................... 468
Figure 8-1. DMA Block Diagram ......................................................................................... 528
Figure 8-2. Example of Ping-Pong DMA Transaction ........................................................... 534
Figure 8-3. Memory Scatter-Gather, Setup and Configuration ................................................ 536
Figure 8-4. Memory Scatter-Gather, DMA Copy Sequence .................................................. 537
Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 539
Figure 8-6. Peripheral Scatter-Gather, DMA Copy Sequence ............................................... 540
Figure 9-1. Digital I/O Pads ................................................................................................. 594
Figure 9-2. Analog/Digital I/O Pads ...................................................................................... 595
Figure 9-3. GPIODATA Write Example ................................................................................. 596
Figure 9-4. GPIODATA Read Example ................................................................................. 596
Figure 10-1. GPTM Module Block Diagram ............................................................................ 646
Figure 10-2. Reading the RTC Value ...................................................................................... 653
Figure 10-3. Input Edge-Count Mode Example, Counting Down ............................................... 655
Figure 10-4. 16-Bit Input Edge-Time Mode Example ............................................................... 656
Figure 10-5. 16-Bit PWM Mode Example ................................................................................ 658
Figure 10-6. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 658
Figure 10-7. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 659
Figure 10-8. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 659
Figure 10-9. Timer Daisy Chain ............................................................................................. 660
Figure 11-1. WDT Module Block Diagram .............................................................................. 716
Figure 12-1. Implementation of Two ADC Blocks .................................................................... 741
Figure 12-2. ADC Module Block Diagram ............................................................................... 742
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Figure 12-3. ADC Sample Phases ......................................................................................... 745
Figure 12-4. Doubling the ADC Sample Rate .......................................................................... 746
Figure 12-5. Skewed Sampling .............................................................................................. 746
Figure 12-6. Sample Averaging Example ............................................................................... 748
Figure 12-7. ADC Input Equivalency Diagram ......................................................................... 749
Figure 12-8. ADC Voltage Reference ..................................................................................... 750
Figure 12-9. ADC Conversion Result ..................................................................................... 751
Figure 12-10. Differential Voltage Representation ..................................................................... 753
Figure 12-11. Internal Temperature Sensor Characteristic ......................................................... 754
Figure 12-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 756
Figure 12-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 757
Figure 12-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 758
Figure 13-1. UART Module Block Diagram ............................................................................. 835
Figure 13-2. UART Character Frame ..................................................................................... 837
Figure 13-3. IrDA Data Modulation ......................................................................................... 839
Figure 14-1. SSI Module Block Diagram ................................................................................. 894
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 898
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 898
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 899
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 899
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 900
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 901
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 901
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 902
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 903
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 904
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 904
Figure 15-1. I
2
C Block Diagram ............................................................................................. 937
Figure 15-2. I
2
C Bus Configuration ........................................................................................ 938
Figure 15-3. START and STOP Conditions ............................................................................. 939
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 939
Figure 15-5. R/S Bit in First Byte ............................................................................................ 940
Figure 15-6. Data Validity During Bit Transfer on the I
2
C Bus ................................................... 940
Figure 15-7. High-Speed Data Format ................................................................................... 945
Figure 15-8. Master Single TRANSMIT .................................................................................. 947
Figure 15-9. Master Single RECEIVE ..................................................................................... 948
Figure 15-10. Master TRANSMIT of Multiple Data Bytes ........................................................... 949
Figure 15-11. Master RECEIVE of Multiple Data Bytes ............................................................. 950
Figure 15-12. Master RECEIVE with Repeated START after Master TRANSMIT ........................ 951
Figure 15-13. Master TRANSMIT with Repeated START after Master RECEIVE ........................ 952
Figure 15-14. Standard High Speed Mode Master Transmit ....................................................... 953
Figure 15-15. Slave Command Sequence ................................................................................ 954
Figure 16-1. CAN Controller Block Diagram ............................................................................ 988
Figure 16-2. CAN Data/Remote Frame .................................................................................. 989
Figure 16-3. Message Objects in a FIFO Buffer ...................................................................... 998
Figure 16-4. CAN Bit Time ................................................................................................... 1002
Figure 17-1. Analog Comparator Module Block Diagram ....................................................... 1039
Figure 17-2. Structure of Comparator Unit ............................................................................ 1040
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Figure 17-3. Comparator Internal Reference Structure .......................................................... 1041
Figure 18-1. PWM Module Diagram ..................................................................................... 1055
Figure 18-2. PWM Generator Block Diagram ........................................................................ 1055
Figure 18-3. PWM Count-Down Mode .................................................................................. 1058
Figure 18-4. PWM Count-Up/Down Mode ............................................................................. 1058
Figure 18-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1059
Figure 18-6. PWM Dead-Band Generator ............................................................................. 1059
Figure 19-1. QEI Block Diagram .......................................................................................... 1132
Figure 19-2. QEI Input Signal Logic ...................................................................................... 1133
Figure 19-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1135
Figure 20-1. 64-Pin LQFP Package Pin Diagram .................................................................. 1154
Figure 22-1. Load Conditions ............................................................................................... 1187
Figure 22-2. JTAG Test Clock Input Timing ........................................................................... 1188
Figure 22-3. JTAG Test Access Port (TAP) Timing ................................................................ 1189
Figure 22-4. Power Assertions versus VDDA Levels ............................................................. 1191
Figure 22-5. Power and Brown-Out Assertions versus VDD Levels ........................................ 1192
Figure 22-6. POK assertion vs VDDC ................................................................................... 1193
Figure 22-7. POR-BOR0-BOR1 VDD Glitch Response .......................................................... 1193
Figure 22-8. POR-BOR0-BOR1 VDD Droop Response ......................................................... 1194
Figure 22-9. Digital Power-On Reset Timing ......................................................................... 1195
Figure 22-10. Brown-Out Reset Timing .................................................................................. 1195
Figure 22-11. External Reset Timing (RST) ............................................................................ 1196
Figure 22-12. Software Reset Timing ..................................................................................... 1196
Figure 22-13. Watchdog Reset Timing ................................................................................... 1196
Figure 22-14. MOSC Failure Reset Timing ............................................................................. 1196
Figure 22-15. ESD Protection on Fail-Safe Pins ...................................................................... 1207
Figure 22-16. ESD Protection on Non-Fail-Safe Pins .............................................................. 1208
Figure 22-17. ADC Input Equivalency Diagram ....................................................................... 1212
Figure 22-18. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1213
Figure 22-19. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1214
Figure 22-20. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1214
Figure 22-21. I
2
C Timing ....................................................................................................... 1215
Figure A-1. Key to Part Numbers ........................................................................................ 1220
April 10, 2013 12
Table of Contents
List of Tables
Table 1. Documentation Conventions ................................................................................ 34
Table 1-1. TM4C123AH6PM Microcontroller Features ........................................................... 37
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 63
Table 2-2. Processor Register Map ....................................................................................... 64
Table 2-3. PSR Register Combinations ................................................................................. 70
Table 2-4. Memory Map ....................................................................................................... 81
Table 2-5. Memory Access Behavior ..................................................................................... 84
Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 86
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 87
Table 2-8. Exception Types .................................................................................................. 92
Table 2-9. Interrupts ............................................................................................................ 93
Table 2-10. Exception Return Behavior ................................................................................. 100
Table 2-11. Faults ............................................................................................................... 101
Table 2-12. Fault Status and Fault Address Registers ............................................................ 102
Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 104
Table 3-1. Core Peripheral Register Regions ....................................................................... 111
Table 3-2. Memory Attributes Summary .............................................................................. 115
Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 117
Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 118
Table 3-5. AP Bit Field Encoding ........................................................................................ 118
Table 3-6. Memory Region Attributes for Tiva C Series Microcontrollers ............................. 119
Table 3-7. QNaN and SNaN Handling ................................................................................. 122
Table 3-8. Peripherals Register Map ................................................................................... 123
Table 3-9. Interrupt Priority Levels ...................................................................................... 153
Table 3-10. Example SIZE Field Values ................................................................................ 181
Table 4-1. JTAG_SWD_SWO Signals (64LQFP) ................................................................. 190
Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 191
Table 4-3. JTAG Instruction Register Commands ................................................................. 197
Table 5-1. System Control & Clocks Signals (64LQFP) ........................................................ 201
Table 5-2. Reset Sources ................................................................................................... 202
Table 5-3. Clock Source Options ........................................................................................ 209
Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field ............................... 211
Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 212
Table 5-6. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 212
Table 5-7. System Control Register Map ............................................................................. 219
Table 5-8. RCC2 Fields that Override RCC Fields ............................................................... 246
Table 6-1. System Exception Register Map ......................................................................... 459
Table 7-1. Flash Memory Protection Policy Combinations .................................................... 472
Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 476
Table 7-3. Flash Register Map ............................................................................................ 482
Table 8-1. DMA Channel Assignments .............................................................................. 529
Table 8-2. Request Type Support ....................................................................................... 531
Table 8-3. Control Structure Memory Map ........................................................................... 532
Table 8-4. Channel Control Structure .................................................................................. 532
Table 8-5. DMA Read Example: 8-Bit Peripheral ................................................................ 541
Table 8-6. DMA Interrupt Assignments .............................................................................. 542
13 April 10, 2013
Tiva
Table 8-7. Channel Control Structure Offsets for Channel 30 ................................................ 543
Table 8-8. Channel Control Word Configuration for Memory Transfer Example ...................... 543
Table 8-9. Channel Control Structure Offsets for Channel 7 .................................................. 544
Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 545
Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 546
Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 547
Table 8-13. DMA Register Map .......................................................................................... 549
Table 9-1. GPIO Pins With Non-Zero Reset Values .............................................................. 592
Table 9-2. GPIO Pins and Alternate Functions (64LQFP) ..................................................... 592
Table 9-3. GPIO Pad Configuration Examples ..................................................................... 599
Table 9-4. GPIO Interrupt Configuration Example ................................................................ 600
Table 9-6. GPIO Register Map ........................................................................................... 601
Table 10-1. Available CCP Pins ............................................................................................ 647
Table 10-2. General-Purpose Timers Signals (64LQFP) ......................................................... 647
Table 10-3. General-Purpose Timer Capabilities .................................................................... 649
Table 10-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 650
Table 10-5. 16-Bit Timer With Prescaler Configurations ......................................................... 651
Table 10-6. 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 652
Table 10-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 652
Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 654
Table 10-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 655
Table 10-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 657
Table 10-11. Timeout Actions for GPTM Modes ...................................................................... 660
Table 10-12. Timers Register Map .......................................................................................... 667
Table 11-1. Watchdog Timers Register Map .......................................................................... 718
Table 12-1. ADC Signals (64LQFP) ...................................................................................... 742
Table 12-2. Samples and FIFO Depth of Sequencers ............................................................ 743
Table 12-3. Differential Sampling Pairs ................................................................................. 751
Table 12-4. ADC Register Map ............................................................................................. 759
Table 13-1. UART Signals (64LQFP) .................................................................................... 835
Table 13-2. Flow Control Mode ............................................................................................. 840
Table 13-3. UART Register Map ........................................................................................... 845
Table 14-1. SSI Signals (64LQFP) ........................................................................................ 895
Table 14-2. SSI Register Map .............................................................................................. 906
Table 15-1. I2C Signals (64LQFP) ........................................................................................ 937
Table 15-2. Examples of I
2
C Master Timer Period versus Speed Mode ................................... 943
2
C Master Timer Period in High-Speed Mode .................................. 944
Table 15-4. Inter-Integrated Circuit (I
2
C) Interface Register Map ............................................. 956
Table 15-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 962
Table 16-1. Controller Area Network Signals (64LQFP) .......................................................... 989
Table 16-2. Message Object Configurations .......................................................................... 994
April 10, 2013 14
Table of Contents
Table 16-3. CAN Protocol Ranges ...................................................................................... 1002
Table 16-4. CANBIT Register Values .................................................................................. 1002
Table 16-5. CAN Register Map ........................................................................................... 1006
Table 17-1. Analog Comparators Signals (64LQFP) ............................................................. 1039
Table 17-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1041
Table 17-3. Analog Comparator Voltage Reference Characteristics, V
DDA
= 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1042
DDA
= 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1042
Table 17-5. Analog Comparators Register Map ................................................................... 1043
Table 18-1. PWM Signals (64LQFP) ................................................................................... 1056
Table 18-2. PWM Register Map .......................................................................................... 1063
Table 19-1. QEI Signals (64LQFP) ...................................................................................... 1133
Table 19-2. QEI Register Map ............................................................................................ 1137
Table 21-1. GPIO Pins With Default Alternate Functions ...................................................... 1155
Table 21-2. Signals by Pin Number ..................................................................................... 1156
Table 21-3. Signals by Signal Name ................................................................................... 1163
Table 21-4. Signals by Function, Except for GPIO ............................................................... 1170
Table 21-5. GPIO Pins and Alternate Functions ................................................................... 1176
Table 21-6. Possible Pin Assignments for Alternate Functions .............................................. 1178
Table 21-7. Connections for Unused Signals (64-Pin LQFP) ................................................. 1182
Table 22-1. Temperature Characteristics ............................................................................. 1183
Table 22-2. Thermal Characteristics ................................................................................... 1183
Table 22-3. ESD Absolute Maximum Ratings ...................................................................... 1183
Table 22-4. Maximum Ratings ............................................................................................ 1184
Table 22-5. Recommended DC Operating Conditions .......................................................... 1185
Table 22-6. Recommended GPIO Pad Operating Conditions ................................................ 1185
Table 22-7. GPIO Current Restrictions ................................................................................ 1185
Table 22-8. GPIO Package Side Assignments ..................................................................... 1186
Table 22-9. JTAG Characteristics ....................................................................................... 1188
Table 22-10. Power-On and Brown-Out Levels ...................................................................... 1190
Table 22-11. Reset Characteristics ....................................................................................... 1195
Table 22-12. LDO Regulator Characteristics ......................................................................... 1197
Table 22-13. Phase Locked Loop (PLL) Characteristics ......................................................... 1198
Table 22-14. Actual PLL Frequency ...................................................................................... 1198
Table 22-15. PIOSC Clock Characteristics ............................................................................ 1199
Table 22-16. Low-Frequency internal Oscillator Characteristics .............................................. 1199
Table 22-17. Main Oscillator Input Characteristics ................................................................. 1199
Table 22-18. Crystal Parameters .......................................................................................... 1201
Table 22-19. Supported MOSC Crystal Frequencies .............................................................. 1202
Table 22-20. System Clock Characteristics with ADC Operation ............................................. 1202
Table 22-21. Sleep Modes AC Characteristics ....................................................................... 1203
Table 22-22. Time to Wake with Respect to Low-Power Modes .............................................. 1203
Table 22-23. Flash Memory Characteristics ........................................................................... 1205
Table 22-24. EEPROM Characteristics ................................................................................. 1205
Table 22-25. GPIO Module Characteristics ............................................................................ 1206
Table 22-26. Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1207
Table 22-27. Fail-Safe GPIOs that Require an External Pull-up .............................................. 1208
15 April 10, 2013
Tiva
Table 22-28. Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1208
Table 22-29. ADC Electrical Characteristics .......................................................................... 1210
Table 22-30. SSI Characteristics .......................................................................................... 1213
Table 22-31. I
2
C Characteristics ........................................................................................... 1215
Table 22-32. Analog Comparator Characteristics ................................................................... 1216
Table 22-33. Analog Comparator Voltage Reference Characteristics ...................................... 1216
DDA
= 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1216
DDA
= 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1217
Table 22-36. Current Consumption ....................................................................................... 1218
April 10, 2013 16
Table of Contents
List of Registers
The Cortex-M4F Processor ........................................................................................................... 58
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 66
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 66
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 66
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 66
Register 14: Stack Pointer (SP) ........................................................................................................... 67
Register 15: Link Register (LR) ............................................................................................................ 68
Register 16: Program Counter (PC) ..................................................................................................... 69
Register 17: Program Status Register (PSR) ........................................................................................ 70
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 74
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 75
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 76
Register 21: Control Register (CONTROL) ........................................................................................... 77
Register 22: Floating-Point Status Control (FPSC) ................................................................................ 79
Cortex-M4 Peripherals ................................................................................................................. 111
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 127
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 129
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 130
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 131
Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 131
Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 131
Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 131
Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 132
Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 133
Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 133
Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 133
Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 133
Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 134
Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 135
Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 135
Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 135
Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 135
Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 136
Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 137
Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 137
Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 137
17 April 10, 2013
Tiva
Register 22: Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C ............................................... 137
Register 23: Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 .............................................. 138
Register 24: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 139
Register 25: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 139
Register 26: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 139
Register 27: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 139
Register 28: Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 140
Register 29: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 141
Register 30: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 141
Register 31: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 141
Register 32: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 141
Register 33: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 141
Register 36: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 141
Register 39: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 141
Register 40: Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 141
Register 44: Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 141
Register 54: Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 143
Register 56: Interrupt 108-111 Priority (PRI27), offset 0x46C ............................................................... 143
Register 57: Interrupt 112-115 Priority (PRI28), offset 0x470 ................................................................ 143
Register 58: Interrupt 116-119 Priority (PRI29), offset 0x474 ................................................................ 143
Register 60: Interrupt 124-127 Priority (PRI31), offset 0x47C ............................................................... 143
Register 64: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 145
Register 65: Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 146
Register 66: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 148
Register 67: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 149
Register 68: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 152
Register 69: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 153
April 10, 2013 18
Table of Contents
Register 70: System Control (SYSCTRL), offset 0xD10 ....................................................................... 155
Register 71: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 157
Register 72: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 159
Register 73: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 160
Register 74: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 161
Register 75: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 162
Register 76: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 166
Register 77: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 172
Register 78: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 173
Register 79: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 174
Register 80: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 175
Register 81: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 176
Register 82: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 178
Register 83: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 179
Register 84: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 179
Register 85: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 179
Register 86: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 179
Register 87: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 181
Register 88: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 181
Register 89: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 181
Register 90: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 181
Register 91: Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 184
Register 92: Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 185
Register 93: Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 187
Register 94: Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 188
System Control ............................................................................................................................ 201
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 225
Register 2: Device Identification 1 (DID1), offset 0x004 ..................................................................... 227
Register 3: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 229
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 230
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 232
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 234
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 237
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 239
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 244
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 246
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 249
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 250
Register 13: System Properties (SYSPROP), offset 0x14C .................................................................. 252
Register 14: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 254
Register 15: PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 255
Register 16: PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 256
Register 17: PLL Status (PLLSTAT), offset 0x168 ............................................................................... 257
Register 18: Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 258
Register 19: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 260
Register 20: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 262
Register 21: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 264
Register 22: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC ........................................... 265
19 April 10, 2013
Tiva
Register 23: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 ...................................... 267
Register 24: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC .................................... 268
Register 25: Watchdog Timer Peripheral Present (PPWD), offset 0x300 ............................................... 271
Register 26: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304 ................. 272
Register 27: General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308 ........................ 274
Register 28: Micro Direct Memory Access Peripheral Present (PPDMA), offset 0x30C .......................... 277
Register 29: Hibernation Peripheral Present (PPHIB), offset 0x314 ...................................................... 278
Register 30: Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset
0x318 ........................................................................................................................... 279
Register 31: Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C ............................ 281
Register 32: Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320 ...................................... 283
Register 33: Universal Serial Bus Peripheral Present (PPUSB), offset 0x328 ........................................ 285
Register 34: Controller Area Network Peripheral Present (PPCAN), offset 0x334 .................................. 286
Register 35: Analog-to-Digital Converter Peripheral Present (PPADC), offset 0x338 ............................. 287
Register 36: Analog Comparator Peripheral Present (PPACMP), offset 0x33C ...................................... 288
Register 37: Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340 ................................... 289
Register 38: Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344 ........................... 290
Register 39: EEPROM Peripheral Present (PPEEPROM), offset 0x358 ................................................ 291
Register 40: 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), offset 0x35C ..... 292
Register 41: Watchdog Timer Software Reset (SRWD), offset 0x500 ................................................... 294
Register 42: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504 ...................... 296
Register 43: General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508 ............................ 298
Register 44: Micro Direct Memory Access Software Reset (SRDMA), offset 0x50C ............................... 300
Register 45: Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 .... 301
Register 46: Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C ................................ 303
Register 47: Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520 ........................................... 305
Register 48: Controller Area Network Software Reset (SRCAN), offset 0x534 ....................................... 307
Register 49: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 .................................. 309
Register 50: Analog Comparator Software Reset (SRACMP), offset 0x53C .......................................... 311
Register 51: Pulse Width Modulator Software Reset (SRPWM), offset 0x540 ....................................... 312
Register 52: Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 ............................... 314
Register 53: EEPROM Software Reset (SREEPROM), offset 0x558 .................................................... 316
Register 54: 32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER), offset 0x55C .......... 317
Register 55: Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 ...................... 319
Register 56: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset
0x604 ........................................................................................................................... 320
Register 57: General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset
0x608 ........................................................................................................................... 322
Register 58: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset
0x60C ........................................................................................................................... 324
Register 59: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART),
offset 0x618 .................................................................................................................. 325
Register 60: Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset
0x61C ........................................................................................................................... 327
Register 61: Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 ............. 329
Register 62: Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 ......... 331
Register 63: Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 .... 332
Register 64: Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C ............. 333
Register 65: Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), offset 0x640 .......... 334
April 10, 2013 20
Table of Contents
Register 66: Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset
0x644 ........................................................................................................................... 335
Register 67: EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 ....................... 336
Register 68: 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER),
offset 0x65C .................................................................................................................. 337
Register 69: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 .................... 339
Register 70: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset
0x704 ........................................................................................................................... 340
Register 71: General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset
0x708 ........................................................................................................................... 342
Register 72: Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset
0x70C ........................................................................................................................... 344
Register 73: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control
(SCGCUART), offset 0x718 ............................................................................................ 345
Register 74: Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset
0x71C ........................................................................................................................... 347
Register 75: Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 ........... 349
Register 76: Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 ....... 351
Register 77: Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset
0x738 ........................................................................................................................... 352
Register 78: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C .......... 353
Register 79: Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740 ........ 354
Register 80: Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset
0x744 ........................................................................................................................... 355
Register 81: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 ..................... 356
Register 82: 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER),
offset 0x75C .................................................................................................................. 357
Register 83: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 .......... 359
Register 84: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER),
offset 0x804 .................................................................................................................. 360
Register 85: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset
0x808 ........................................................................................................................... 362
Register 86: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset
0x80C ........................................................................................................................... 364
Register 87: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
(DCGCUART), offset 0x818 ............................................................................................ 365
Register 88: Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset
0x81C ........................................................................................................................... 367
Register 89: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset
0x820 ........................................................................................................................... 369
Register 90: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset
0x834 ........................................................................................................................... 371
Register 91: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset
0x838 ........................................................................................................................... 372
Register 92: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset
0x83C ........................................................................................................................... 373
Register 93: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset
0x840 ........................................................................................................................... 374
Register 94: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset
0x844 ........................................................................................................................... 375
21 April 10, 2013
Tiva
Register 95: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 ........... 376
Register 96: 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control
(DCGCWTIMER), offset 0x85C ...................................................................................... 377
Register 97: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00 ................................................ 379
Register 98: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04 ................... 380
Register 99: General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08 ......................... 382
Register 100: Micro Direct Memory Access Peripheral Ready (PRDMA), offset 0xA0C ........................... 384
Register 101: Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset
0xA18 ........................................................................................................................... 385
Register 102: Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C ............................. 387
Register 103: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20 ....................................... 389
Register 104: Controller Area Network Peripheral Ready (PRCAN), offset 0xA34 ................................... 391
Register 105: Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38 ............................... 392
Register 106: Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C ....................................... 393
Register 107: Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40 .................................... 394
Register 108: Quadrature Encoder Interface Peripheral Ready (PRQEI), offset 0xA44 ............................ 395
Register 109: EEPROM Peripheral Ready (PREEPROM), offset 0xA58 ................................................. 396
Register 110: 32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER), offset 0xA5C ...... 397
Register 111: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 399
Register 115: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 411
Register 119: Device Capabilities 8 (DC8), offset 0x02C ....................................................................... 420
Register 120: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 423
Register 123: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 430
Register 126: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 440
Register 129: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 448
Register 130: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 451
Register 131: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 454
Register 133: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 458
System Exception Module .......................................................................................................... 459
Register 1: System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000 ................................ 460
Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004 ........................................... 462
Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset 0x008 ........................... 464
Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C ........................................... 466
Internal Memory ........................................................................................................................... 467
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 484
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Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 485
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 486
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 488
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 491
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 493
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 496
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 497
Register 9: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 498
Register 10: Flash Size (FSIZE), offset 0xFC0 .................................................................................... 499
Register 11: SRAM Size (SSIZE), offset 0xFC4 .................................................................................. 500
Register 12: ROM Software Map (ROMSWMAP), offset 0xFCC ........................................................... 501
Register 13: EEPROM Size Information (EESIZE), offset 0x000 .......................................................... 502
Register 14: EEPROM Current Block (EEBLOCK), offset 0x004 .......................................................... 503
Register 15: EEPROM Current Offset (EEOFFSET), offset 0x008 ........................................................ 504
Register 16: EEPROM Read-Write (EERDWR), offset 0x010 .............................................................. 505
Register 17: EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 .................................. 506
Register 18: EEPROM Done Status (EEDONE), offset 0x018 .............................................................. 507
Register 19: EEPROM Support Control and Status (EESUPP), offset 0x01C ........................................ 509
Register 20: EEPROM Unlock (EEUNLOCK), offset 0x020 .................................................................. 511
Register 21: EEPROM Protection (EEPROT), offset 0x030 ................................................................. 512
Register 22: EEPROM Password (EEPASS0), offset 0x034 ................................................................. 514
Register 23: EEPROM Password (EEPASS1), offset 0x038 ................................................................. 514
Register 24: EEPROM Password (EEPASS2), offset 0x03C ................................................................ 514
Register 25: EEPROM Interrupt (EEINT), offset 0x040 ........................................................................ 515
Register 26: EEPROM Block Hide (EEHIDE), offset 0x050 .................................................................. 516
Register 27: EEPROM Debug Mass Erase (EEDBGME), offset 0x080 ................................................. 517
Register 28: EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0 ........................................... 518
Register 29: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 519
Register 30: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 520
Register 31: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 520
Register 32: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 520
Register 33: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 520
Register 34: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 521
Register 35: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 521
Register 36: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 521
Register 37: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 521
Register 38: Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 523
Register 39: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 526
Register 42: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 526
Micro Direct Memory Access (DMA) ........................................................................................ 527
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 551
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 552
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 553
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 558
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 560
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 561
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Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 562
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 563
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 564
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 565
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 566
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 567
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 568
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 569
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 570
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 571
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 572
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 573
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 574
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 575
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 576
Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 577
Register 23: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 ............................................... 578
Register 26: DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C .............................................. 581
Register 27: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 582
Register 30: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 585
Register 31: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 586
Register 32: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 587
Register 35: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 590
General-Purpose Input/Outputs (GPIOs) ................................................................................... 591
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 603
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 604
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 605
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 606
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 607
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 608
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 609
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 610
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 611
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 612
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 614
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 617
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 618
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 620
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 622
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 623
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Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 625
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 626
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 628
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 629
Register 23: GPIO ADC Control (GPIOADCCTL), offset 0x530 ............................................................ 631
Register 24: GPIO DMA Control (GPIODMACTL), offset 0x534 ........................................................... 632
Register 25: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 633
Register 28: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 636
Register 29: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 637
Register 32: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 640
Register 33: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 641
Register 36: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 644
General-Purpose Timers ............................................................................................................. 645
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 668
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 670
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 674
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 678
Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010 .............................................................. 682
Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 686
Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 689
Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 692
Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 695
Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 697
Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 698
Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 699
Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 700
Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 701
Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 702
Register 16: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 703
Register 17: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 704
Register 18: GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 705
Register 19: GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 706
Register 20: GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 707
Register 21: GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 708
Register 22: GPTM RTC Predivide (GPTMRTCPD), offset 0x058 ........................................................ 709
Register 23: GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C ........................................ 710
Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 ........................................ 711
Register 25: GPTM Timer A Prescale Value (GPTMTAPV), offset 0x064 .............................................. 712
Register 26: GPTM Timer B Prescale Value (GPTMTBPV), offset 0x068 .............................................. 713
Register 27: GPTM Peripheral Properties (GPTMPP), offset 0xFC0 ..................................................... 714
Watchdog Timers ......................................................................................................................... 715
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 719
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Tiva
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 720
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 721
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 723
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 724
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 725
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 726
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 727
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 728
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 731
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 732
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 735
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 736
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 739
Analog-to-Digital Converter (ADC) ............................................................................................. 740
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 762
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 764
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 766
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 769
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 772
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 774
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 779
Register 8: ADC Trigger Source Select (ADCTSSEL), offset 0x01C ................................................... 780
Register 9: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 782
Register 10: ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 784
Register 11: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 786
Register 12: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 788
Register 13: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 789
Register 14: ADC Control (ADCCTL), offset 0x038 ............................................................................. 791
Register 15: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 792
Register 16: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 794
Register 17: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 801
Register 20: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 801
Register 21: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 802
Register 22: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 802
Register 23: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 802
Register 24: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 802
Register 25: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 804
Register 26: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 806
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Register 31: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 813
Register 32: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 813
Register 35: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 816
Register 36: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 817
Register 37: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 819
Register 38: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 820
Register 39: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 821
Register 40: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 826
Register 43: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 826
Register 47: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 826
Register 48: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 829
Register 51: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 829
Register 55: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 829
Register 56: ADC Peripheral Properties (ADCPP), offset 0xFC0 .......................................................... 830
Register 57: ADC Peripheral Configuration (ADCPC), offset 0xFC4 ..................................................... 832
Register 58: ADC Clock Configuration (ADCCC), offset 0xFC8 ............................................................ 833
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 834
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 847
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 849
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 852
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 854
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 855
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 856
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 857
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 859
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 863
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 865
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 868
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 871
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 874
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 876
Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................... 877
Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................... 878
Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0 ...................................................... 879
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Register 18: UART Clock Configuration (UARTCC), offset 0xFC8 ........................................................ 880
Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 881
Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 884
Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 885
Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 888
Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 889
Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 892
Synchronous Serial Interface (SSI) ............................................................................................ 893
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 908
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 910
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 912
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 913
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 915
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 916
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 917
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 919
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 921
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 922
Register 11: SSI Clock Configuration (SSICC), offset 0xFC8 ............................................................... 923
Register 12: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 924
Register 15: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 927
Register 16: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 928
Register 19: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 931
Register 20: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 932
Register 23: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 935
Inter-Integrated Circuit (I
2
C) Interface ........................................................................................ 936
Register 1: I
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 958
Register 2: I
2
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 959
Register 3: I
2
C Master Data (I2CMDR), offset 0x008 ......................................................................... 964
Register 4: I
2
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 965
Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 966
Register 6: I
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 967
Register 7: I
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 968
Register 8: I
2
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 969
Register 9: I
2
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 970
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Register 10: I
2
C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 ............................... 972
Register 11: I
2
C Master Bus Monitor (I2CMBMON), offset 0x02C ........................................................ 973
Register 12: I
2
C Master Configuration 2 (I2CMCR2), offset 0x038 ....................................................... 974
Register 13: I
2
C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 975
Register 14: I
2
C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 976
Register 15: I
2
C Slave Data (I2CSDR), offset 0x808 ........................................................................... 978
Register 16: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 979
Register 17: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 980
Register 18: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 981
Register 19: I
2
C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 982
Register 20: I
2
C Slave Own Address 2 (I2CSOAR2), offset 0x81C ....................................................... 983
Register 21: I
2
C Slave ACK Control (I2CSACKCTL), offset 0x820 ....................................................... 984
Register 22: I
2
C Peripheral Properties (I2CPP), offset 0xFC0 .............................................................. 985
Register 23: I
2
C Peripheral Configuration (I2CPC), offset 0xFC4 ......................................................... 986
Controller Area Network (CAN) Module ..................................................................................... 987
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................ 1009
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................. 1011
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................. 1014
Register 4: CAN Bit Timing (CANBIT), offset 0x00C ........................................................................ 1015
Register 5: CAN Interrupt (CANINT), offset 0x010 ........................................................................... 1016
Register 6: CAN Test (CANTST), offset 0x014 ................................................................................ 1017
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ..................................... 1019
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 .............................................. 1020
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 .............................................. 1020
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 ................................................ 1021
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 ................................................ 1021
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 .............................................................. 1024
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 .............................................................. 1024
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C .............................................................. 1025
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C .............................................................. 1025
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ....................................................... 1027
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 ................................................ 1030
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 ................................................ 1030
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ............................................................... 1033
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................ 1033
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................ 1033
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................ 1033
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ............................................................... 1033
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ............................................................... 1033
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ............................................................... 1033
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ............................................................... 1033
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 .............................................. 1034
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 .............................................. 1034
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ............................................................... 1035
29 April 10, 2013
Tiva
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ............................................................... 1035
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ................................... 1036
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ................................... 1036
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ..................................................... 1037
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ..................................................... 1037
Analog Comparators ................................................................................................................. 1038
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1045
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1046
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1047
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... 1048
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... 1049
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... 1049
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... 1050
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1050
Register 9: Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0 ................................ 1052
Pulse Width Modulator (PWM) .................................................................................................. 1053
Register 1: PWM Master Control (PWMCTL), offset 0x000 .............................................................. 1067
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ......................................................... 1069
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 ........................................................ 1070
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ..................................................... 1072
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 .............................................................. 1074
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ......................................................... 1076
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ...................................................... 1078
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C .............................................. 1081
Register 9: PWM Status (PWMSTATUS), offset 0x020 .................................................................... 1084
Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ........................................... 1086
Register 11: PWM Enable Update (PWMENUPD), offset 0x028 ......................................................... 1088
Register 12: PWM0 Control (PWM0CTL), offset 0x040 ...................................................................... 1092
Register 14: PWM2 Control (PWM2CTL), offset 0x0C0 ..................................................................... 1092
Register 16: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 ................................... 1097
Register 18: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 ................................... 1097
Register 20: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 ................................................... 1100
Register 22: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 .................................................. 1100
Register 24: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C .......................................... 1102
Register 26: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC .......................................... 1102
Register 28: PWM0 Load (PWM0LOAD), offset 0x050 ...................................................................... 1104
Register 30: PWM2 Load (PWM2LOAD), offset 0x0D0 ...................................................................... 1104
Register 32: PWM0 Counter (PWM0COUNT), offset 0x054 ............................................................... 1105
April 10, 2013 30
Table of Contents
Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4 .............................................................. 1105
Register 36: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................ 1106
Register 37: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................ 1106
Register 38: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................ 1106
Register 39: PWM3 Compare A (PWM3CMPA), offset 0x118 ............................................................. 1106
Register 40: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................ 1107
Register 42: PWM2 Compare B (PWM2CMPB), offset 0x0DC ........................................................... 1107
Register 44: PWM0 Generator A Control (PWM0GENA), offset 0x060 ............................................... 1108
Register 45: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ............................................... 1108
Register 46: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ............................................... 1108
Register 47: PWM3 Generator A Control (PWM3GENA), offset 0x120 ............................................... 1108
Register 48: PWM0 Generator B Control (PWM0GENB), offset 0x064 ............................................... 1111
Register 49: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ............................................... 1111
Register 50: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ............................................... 1111
Register 51: PWM3 Generator B Control (PWM3GENB), offset 0x124 ............................................... 1111
Register 52: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ............................................... 1114
Register 53: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ............................................... 1114
Register 54: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ............................................... 1114
Register 55: PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128 ............................................... 1114
Register 56: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................ 1115
Register 57: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................ 1115
Register 58: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................ 1115
Register 59: PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C ............................ 1115
Register 60: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................ 1116
Register 61: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................ 1116
Register 62: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................ 1116
Register 63: PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130 ............................ 1116
Register 64: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 .................................................. 1117
Register 65: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 .................................................. 1117
Register 66: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 .................................................. 1117
Register 69: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 .................................................. 1119
Register 70: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 .................................................. 1119
Register 72: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C ................................... 1122
Register 73: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC ................................... 1122
Register 74: PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC ................................... 1122
Register 75: PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C ................................... 1122
Register 76: PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 .......................................... 1123
Register 80: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 ................................................... 1124
31 April 10, 2013
Tiva
Register 88: PWM Peripheral Properties (PWMPP), offset 0xFC0 ...................................................... 1129
Quadrature Encoder Interface (QEI) ........................................................................................ 1131
Register 1: QEI Control (QEICTL), offset 0x000 .............................................................................. 1138
Register 2: QEI Status (QEISTAT), offset 0x004 .............................................................................. 1141
Register 3: QEI Position (QEIPOS), offset 0x008 ............................................................................ 1142
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ..................................................... 1143
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ..................................................................... 1144
Register 6: QEI Timer (QEITIME), offset 0x014 ............................................................................... 1145
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ........................................................... 1146
Register 8: QEI Velocity (QEISPEED), offset 0x01C ........................................................................ 1147
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................. 1148
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ........................................................... 1150
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ................................................... 1152
April 10, 2013 32
Table of Contents
About This Document
This data sheet provides reference information for the TM4C123AH6PM microcontroller, describing
the functional blocks of the system-on-chip (SoC) device designed around the ARMCortex-M4F
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the Tiva C Series web site at
http://www.ti.com/tiva-c:
TM4C123AH6PM Errata
ARM Cortex-M4 Errata
Cortex-M3/M4 Instruction Set Technical User's Manual
TivaWare Boot Loader for C Series User's Guide
TivaWare Graphics Library for C Series User's Guide
TivaWare Peripheral Driver Library for C Series User's Guide
TivaWare USB Library for C Series User's Guide
TM4C123AH6PM ROM Users Guide
The following related documents are also referenced:
ARM Debug Interface V5 Architecture Specification
ARM Embedded Trace Macrocell Architecture Specification
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
33 April 10, 2013
Tiva
Documentation Conventions
This document uses the conventions shown in Table 1 on page 34.
Table 1. Documentation Conventions
Meaning Notation
General Register Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
REGISTER
A single bit in a register. bit
Two or more consecutive and related bits. bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 81.
offset 0xnnn
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register N
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
reserved
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
yy:xx
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Register Bit/Field
Types
Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RC
Software can read this field. Always write the chip reset value. RO
Software can read or write this field. R/W
Software can read or write this field. Writing to it with any value clears the register. R/WC
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1C
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
R/W1S
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
W1C
Only a write by software is valid; a read of the register returns no meaningful data. WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted. Register Bit/Field
Reset Value
Bit cleared to 0 on chip reset. 0
Bit set to 1 on chip reset. 1
Nondeterministic. -
Pin/Signal Notation
Pin alternate function; a pin defaults to the signal without the brackets. [ ]
Refers to the physical connection on the package. pin
Refers to the electrical signal encoding of a pin. signal
April 10, 2013 34
About This Document
Table 1. Documentation Conventions (continued)
Meaning Notation
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Lowsignals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
assert a signal
Change the value of the signal from the logically True state to the logically False state. deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
SIGNAL
Numbers
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
X
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
0x
35 April 10, 2013
Tiva
1 Architectural Overview
Texas Instrument's Tiva C Series microcontrollers provide designers a high-performance ARM
Cortex
-M-based architecture with a broad set of integration capabilities and a strong ecosystem
of software and development tools. Targeting performance and flexibility, the Tiva C Series
architecture offers a 80 MHz Cortex-M with FPU, a variety of integrated memories and multiple
programmable GPIO. Tiva C Series devices offer consumers compelling cost-effective solutions
by integrating application-specific peripherals and providing a comprehensive library of software
tools which minimize board costs and design-cycle time. Offering quicker time-to-market and cost
savings, the Tiva C Series microcontrollers are the leading choice in high-performance 32-bit
applications.
This chapter contains an overview of the Tiva C Series microcontrollers as well as details on the
TM4C123AH6PM microcontroller:
Tiva C Series Overview on page 36
TM4C123AH6PM Microcontroller Overview on page 37
TM4C123AH6PM Microcontroller Features on page 40
TM4C123AH6PM Microcontroller Hardware Details on page 57
1.1 Tiva C Series Overview
The Tiva C Series ARM Cortex-M4 microcontrollers provide top performance and advanced
integration. The product family is positioned for cost-conscious applications requiring significant
control processing and connectivity capabilities such as:
Low power, hand-held smart devices
Gaming equipment
Home and commercial site monitoring and control
Motion control
Medical instrumentation
Test and measurement equipment
Factory automation
Fire and security
Smart Energy/Smart Grid solutions
Intelligent lighting control
Transportation
In addition, the TM4C123AH6PM microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the TM4C123AH6PM microcontroller is
code-compatible to all members of the extensive Tiva C Series; providing flexibility to fit precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network.
April 10, 2013 36
Architectural Overview
Figure 1-1. Tiva
TM4C123x Block Diagram

TM
Tiva TM4C123x MCU
SWD/T
NVIC
JTAG
FPU
ETM
MPU
ARM
TM
Cortex M4F
80 MHz
ROM
2KB EEPROM
256 KB
Flash
32 KB
SRAM
Analog
LDO Voltage
Regulator
3 Analog
Comparators
2 x 12-bit ADC
Up to 24 Channel
1 MSPS
Temp Sensor
2 CAN
8 UARTs
4 SSI/SPI
USB Full Speed
Host/Device/OTG
2
6 I C
Serial Interfaces
Clocks, Reset
System Control
Systick Timer
12 Timer/PWM/CCP
6 each 32-bit or 2x16-bit
6 each 64-bit or 2x32-bit
2 Watchdog Timers
GPIOs
32ch DMA
Precision Oscillator
Battery-Backed
Hibernate
R
T
C
System
Comparators
Timer
2 Quadrature
Encoder Inputs
16 PWM Outputs
Motion Control
PWM
Generator
PWM
Generator
Dead-Band
Generator
1.2 TM4C123AH6PM Microcontroller Overview
The TM4C123AH6PMmicrocontroller combines complex integration and high performance with the
features shown in Table 1-1.
Table 1-1. TM4C123AH6PM Microcontroller Features
Description Feature
ARM Cortex-M4F processor core Core
80-MHz operation; 100 DMIPS performance Performance
256 KB single-cycle Flash memory Flash
32 KB single-cycle SRAM System SRAM
2KB of EEPROM EEPROM
Internal ROM loaded with TivaWare for C Series software Internal ROM
Communication Interfaces
Eight UARTs Universal Asynchronous Receivers/Transmitter
(UART)
Four SSI modules Synchronous Serial Interface (SSI)
Six I
2
C modules with four transmission speeds including high-speed
mode
2
C)
Two CAN 2.0 A/B controllers Controller Area Network (CAN)
System Integration
ARM PrimeCell 32-channel configurable DMA controller Micro Direct Memory Access (DMA)
Six 16/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocks General-Purpose Timer (GPTM)
37 April 10, 2013
Tiva
Table 1-1. TM4C123AH6PM Microcontroller Features (continued)
Description Feature
Two watchdog timers Watchdog Timer (WDT)
Seven physical GPIO blocks General-Purpose Input/Output (GPIO)
Advanced Motion Control
Two PWM modules, each with four PWM generator blocks and a
control block, for a total of 16 PWM outputs.
Pulse Width Modulator (PWM)
Two QEI modules Quadrature Encoder Interface (QEI)
Analog Support
Two 12-bit ADC modules with a maximum sample rate of one million
samples/second
Analog-to-Digital Converter (ADC)
Two independent integrated analog comparators Analog Comparator Controller
16 digital comparators Digital Comparator
One JTAG module with integrated ARM SWD JTAG and Serial Wire Debug (SWD)
64-pin LQFP Package
Industrial (-40C to 85C) temperature range Operating Range
Figure 1-2 on page 39 shows the features on the TM4C123AH6PM microcontroller. Note that there
are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB)
bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back
access performance than the APB bus.
April 10, 2013 38
Figure 1-2. Tiva TM4C123AH6PM Microcontroller High-Level Block Diagram
ARM
Cortex-M4F
(80MHz)
NVIC MPU
FPU ETM
Flash
(256KB)
Boot Loader
DriverLib
AES & CRC
ROM
DCodebus
ICodebus
JTAG/SWD
System
Controland
Clocks
(w/ Precis. Osc.)
Bus Matrix
System Bus
SRAM
(32KB)
SYSTEM PERIPHERALS
Watchdog
Timer
(2)
DMA
EEPROM
(2K)
General-
Purpose
Timer (12)
GPIOs
(49)
SERIAL PERIPHERALS
UART
(8)
I2C
(6)
SSI
(4)
CAN
Controller
(2)
ANALOG PERIPHERALS
12- BitADC
Channels
(12)
Analog
Comparator
(2)
MOTION CONTROL PERIPHERALS
QEI
(2)
PWM
(16)
A
d
v
a
n
c
e
d
P
e
r
i
p
h
e
r
a
l
B
u
s
(
A
P
B
)
A
d
v
a
n
c
e
d
H
i
g
h
-
P
e
r
f
o
r
m
a
n
c
e
B
u
s
(
A
H
B
)
TM4C123AH6PM
39 April 10, 2013
Tiva
1.3 TM4C123AH6PM Microcontroller Features
The TM4C123AH6PM microcontroller component features and general function are discussed in
more detail in the following section.
1.3.1 ARM Cortex-M4F Processor Core
All members of the Tiva C Series, including the TM4C123AH6PM microcontroller, are designed
around an ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a
high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
1.3.1.1 Processor Core (see page 58)
32-bit ARM Cortex-M4F architecture optimized for small-footprint embedded applications
80-MHz operation; 100 DMIPS performance
Outstanding processing performance combined with fast interrupt handling
Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
Single-cycle multiply instruction and hardware divide
Atomic bit manipulation (bit-banding), delivering maximummemory utilization and streamlined
peripheral control
Unaligned data access, enabling data to be efficiently packed into memory
IEEE754-compliant single-precision Floating-Point Unit (FPU)
16-bit SIMD vector processing unit
Fast code execution permits slower processor clock or increases sleep mode time
Harvard architecture characterized by separate buses for instruction and data
Efficient processor core, system and memories
Hardware division and fast digital-signal-processing orientated multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
Enhanced system debug with extensive breakpoint and trace capabilities
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
April 10, 2013 40
Migration from the ARM7
processor family for better performance and power efficiency

Optimized for single-cycle Flash memory usage up to specific frequencies; see Internal
Memory on page 467 for more information.
Ultra-low power consumption with integrated sleep modes
1.3.1.2 System Timer (SysTick) (see page 112)
ARM Cortex-M4F includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
A high-speed alarm timer using the system clock
A variable rate alarm or signal timerthe duration is range-dependent on the reference clock
used and the dynamic range of the counter
A simple counter used to measure time to completion and time used
An internal clock-source control based on missing/meeting durations
1.3.1.3 Nested Vectored Interrupt Controller (NVIC) (see page 113)
The TM4C123AH6PM controller includes the ARM Nested Vectored Interrupt Controller (NVIC).
The NVIC and Cortex-M4F prioritize and handle all exceptions in Handler Mode. The processor
state is automatically stored to the stack on an exception and automatically restored from the stack
at the end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the
state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 79 interrupts.
Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining (these
values reflect no FPU stacking)
External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
Dynamically reprioritizable interrupts
Exceptional interrupt handling via hardware implementation of required register manipulations
1.3.1.4 System Control Block (SCB) (see page 114)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
1.3.1.5 Memory Protection Unit (MPU) (see page 114)
The MPUsupports the standard ARM7 Protected Memory SystemArchitecture (PMSA) model. The
MPUprovides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
41 April 10, 2013
Tiva
1.3.1.6 Floating-Point Unit (FPU) (see page 119)
The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate,
and square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.
32-bit instructions for single-precision (C float) data-processing operations
Combined multiply and accumulate instructions for increased precision (Fused MAC)
Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
Hardware support for denormals and all IEEE rounding modes
32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
Decoupled three stage pipeline
1.3.2 On-Chip Memory
The TM4C123AH6PM microcontroller is integrated with the following set of on-chip memory and
features:
32 KB single-cycle SRAM
256 KB Flash memory
2KB EEPROM
Internal ROM loaded with TivaWare for C Series software:
TivaWare
Peripheral Driver Library

TivaWare Boot Loader
Advanced Encryption Standard (AES) cryptography tables
Cyclic Redundancy Check (CRC) error detection functionality
1.3.2.1 SRAM (see page 468)
The TM4C123AH6PM microcontroller provides 32 KB of single-cycle on-chip SRAM. The internal
SRAM of the device is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller
(DMA).
1.3.2.2 Flash Memory (see page 471)
The TM4C123AH6PM microcontroller provides 256 KB of single-cycle on-chip Flash memory. The
Flash memory is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of
2-KB blocks that can be individually protected. The blocks can be marked as read-only or
execute-only, providing different levels of code protection. Read-only blocks cannot be erased or
programmed, protecting the contents of those blocks from being modified. Execute-only blocks
April 10, 2013 42
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
1.3.2.3 ROM (see page 469)
The TM4C123AH6PM ROM is preprogrammed with the following software and programs:
TivaWare Peripheral Driver Library
TivaWare Boot Loader
Cyclic Redundancy Check (CRC) error-detection functionality
The TivaWare Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M4F core.
No special pragmas or custom assembly code prologue/epilogue functions are required. For
applications that require in-field programmability, the royalty-free TivaWare Boot Loader can act as
an application loader and support in-field firmware updates.
The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government. AES is a strong encryption method with reasonable performance and size. In
addition, it is fast in both hardware and software, is fairly easy to implement, and requires little
memory. The Texas Instruments encryption package is available with full source code, and is based
on lesser general public license (LGPL) source. An LGPL means that the code can be used within
an application without any copyleft implications for the application (the code does not automatically
become open source). Modifications to the package source, however, must be open source.
CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents
as when previously checked. This technique can be used to validate correct receipt of messages
(nothing lost or modified in transit), to validate data after decompression, to validate that Flash
memory contents have not been changed, and for other cases where the data needs to be validated.
A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more
readily.
1.3.2.4 EEPROM (see page 477)
The TM4C123AH6PM microcontroller includes an EEPROM with the following features:
2Kbytes of memory accessible as 512 32-bit words
32 blocks of 16 words (64 bytes) each
Built-in wear leveling
Access protection per block
Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock
codes (application selectable)
Interrupt support for write completion to avoid polling
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Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion)
to 15M operations (when cycling through two pages ) per each 2-page block.
1.3.3 Serial Communications Peripherals
The TM4C123AH6PMcontroller supports both asynchronous and synchronous serial communications
with:
Two CAN 2.0 A/B controllers
Eight UARTs with IrDA, 9-bit and ISO 7816 support.
UART1 (modem flow control)
Six I
2
C modules with four transmission speeds including high-speed mode
Four Synchronous Serial Interface modules (SSI)
The following sections provide more detail on each of these communications functions.
1.3.3.1 Controller Area Network (CAN) (see page 987)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally
created for automotive purposes, it is nowused in many embedded control applications (for example,
industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters.
Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information.
The TM4C123AH6PM microcontroller includes two CAN units with the following features:
CAN protocol version 2.0 part A/B
Bit rates up to 1 Mbps
32 message objects with individual identifier masks
Maskable interrupt
Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
Programmable loopback mode for self-test operation
Programmable FIFO mode enables storage of multiple message objects
Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
1.3.3.2 UART (see page 834)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
April 10, 2013 44
The TM4C123AH6PM microcontroller includes eight fully programmable 16C550-type UARTs.
Although the functionality is similar to a 16C550 UART, this UART design is not register compatible.
The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, and
error conditions. The module generates a single combined interrupt when any of the interrupts are
asserted and are unmasked.
The eight UARTs have the following features:
Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
Line-break generation and detection
Fully programmable serial interface characteristics
5, 6, 7, or 8 data bits
Even, odd, stick, or no-parity bit generation/detection
1 or 2 stop bit generation
IrDA serial-IR (SIR) encoder/decoder providing
Programmable use of IrDA Serial Infrared (SIR) or UART input/output
Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
Support of normal 3/16 and low-power (1.41-2.23 s) bit durations
Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
Support for communication with ISO 7816 smart cards
Modem flow control (on UART1)
EIA-485 9-bit support
Standard FIFO-level and End-of-Transmission interrupts
Efficient transfers using Micro Direct Memory Access Controller (DMA)
Separate channels for transmit and receive
Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
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Transmit single request asserted when there is space in the FIFO; burst request asserted at
1.3.3.3 I
2
C (see page 936)
The Inter-Integrated Circuit (I
2
C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I
2
C bus interfaces to external I
2
C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I
2
C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I
2
C bus can be designated as either a master or a slave. I
2
C module supports
both sending and receiving data as either a master or a slave and can operate simultaneously as
both a master and a slave. Both the I
2
C master and slave can generate interrupts.
The TM4C123AH6PM microcontroller includes six I
2
C modules with the following features:
Devices on the I
2
C bus can be designated as either a master or a slave
Supports both transmitting and receiving data as either a master or a slave
Supports simultaneous master and slave operation
Four I
2
C modes
Master transmit
Master receive
Slave transmit
Slave receive
Four transmission speeds:
Standard (100 Kbps)
Fast-mode (400 Kbps)
Fast-mode plus (1 Mbps)
High-speed mode (3.33 Mbps)
Clock low timeout interrupt
Dual slave address capability
Glitch suppression
Master and slave interrupt generation
Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
April 10, 2013 46
Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
1.3.3.4 SSI (see page 893)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts
data between parallel and serial. The SSI module performs serial-to-parallel conversion on data
received froma peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The SSI module can be configured as either a master or slave device. As a slave device,
the SSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
The TM4C123AH6PM microcontroller includes four SSI modules with the following features:
Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
Master or slave operation
Programmable clock bit rate and prescaler
Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
Programmable data frame size from 4 to 16 bits
Internal loopback test mode for diagnostic/debug testing
Standard FIFO-based interrupts and End-of-Transmission interrupt
Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
Transmit single request asserted when there is space in the FIFO; burst request asserted
when four or more entries are available to be written in the FIFO
1.3.4 System Integration
The TM4C123AH6PM microcontroller provides a variety of standard system functions integrated
into the device, including:
Direct Memory Access Controller (DMA)
System control and clocks including on-chip precision 16-MHz oscillator
Six 32-bit timers (up to twelve 16-bit), with real-time clock capability
Six wide 64-bit timers (up to twelve 32-bit), with real-time clock capability
Twelve 32/64-bit Capture Compare PWM (CCP) pins
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Two Watchdog Timers
One timer runs off the main oscillator
One timer runs off the precision internal oscillator
Up to 49 GPIOs, depending on configuration
Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
Independently configurable to 2-, 4- or 8-mA drive capability
Up to 4 GPIOs can have 18-mA drive capability
The following sections provide more detail on each of these functions.
1.3.4.1 Direct Memory Access (see page 527)
The TM4C123AH6PM microcontroller includes a Direct Memory Access (DMA) controller, known
as micro-DMA (DMA). The DMA controller provides a way to offload data transfer tasks from the
Cortex-M4F processor, allowing for more efficient use of the processor and the available bus
bandwidth. The DMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
performtransfers between peripherals and memory as the peripheral is ready to transfer more data.
The DMA controller provides the following features:
ARM PrimeCell
32-channel configurable DMA controller

Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
Basic for simple transfer scenarios
Ping-pong for continuous data flow
Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single
request
Highly flexible and configurable channel operation
Independently configured and operated channels
Dedicated channels for supported on-chip modules
Flexible channel assignments
One channel each for receive and transmit path for bidirectional modules
Dedicated channel for software-initiated transfers
Per-channel configurable priority scheme
Optional software-initiated requests for any channel
Two levels of priority
Design optimizations for improved bus access performance between DMA controller and the
processor core
DMA controller access is subordinate to core access
April 10, 2013 48
RAM striping
Peripheral bus segmentation
Data sizes of 8, 16, and 32 bits
Transfer size is programmable in binary steps from 1 to 1024
Source and destination address increment size of byte, half-word, word, or no increment
Maskable peripheral requests
Interrupt on transfer completion, with a separate interrupt per channel
1.3.4.2 System Control and Clocks (see page 201)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
Device identification information: version, part number, SRAM size, Flash memory size, and so
on
Power control
On-chip fixed Low Drop-Out (LDO) voltage regulator
Low-power options for microcontroller: Sleep and Deep-sleep modes with clock gating
Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory
3.3-V supply brown-out detection and reporting via interrupt or reset
Multiple clock sources for microcontroller system clock
Precision Oscillator (PIOSC): On-chip resource providing a 16 MHz 1% frequency at room
temperature
16 MHz 3% across temperature
Software power down control for low power modes
Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external
single-ended clock source is connected to the OSC0 input pin, or an external crystal is
connected across the OSC0 input and OSC1 output pins.
External crystal used with or without on-chip PLL: select supported frequencies from 4
MHz to 25 MHz.
External oscillator: from DC to maximum device speed
Low Frequency Internal Oscillator (LFIOSC): On-chip resource used during power-saving
modes
Flexible reset sources
Power-on reset (POR)
Reset pin assertion
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Brown-out reset (BOR) detector alerts to system power drops
Software reset
Watchdog timer reset
MOSC failure
1.3.4.3 Programmable Timers (see page 645)
Programmable timers can be used to count or time external events that drive the Timer input pins.
Each 16/32-bit GPTM block provides two 16-bit timers/counters that can be configured to operate
independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit
Real-Time Clock (RTC). Each 32/64-bit Wide GPTM block provides two 32-bit timers/counters that
can be configured to operate independently as timersor event counters, or configured to operate
as one 64-bit timer or one 64-bit Real-Time Clock (RTC). Timers can also be used to trigger
analog-to-digital (ADC) conversions and DMA transfers.
The General-Purpose Timer Module (GPTM) contains six 16/32-bit GPTM blocks and six 32/64-bit
Wide GPTM blocks with the following functional options:
16/32-bit operating modes:
16- or 32-bit programmable one-shot timer
16- or 32-bit programmable periodic timer
16-bit general-purpose timer with an 8-bit prescaler
32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
16-bit input-edge count- or time-capture modes with an 8-bit prescaler
16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the
PWM signal
32-bit general-purpose timer with a 16-bit prescaler
32-bit input-edge count- or time-capture modes with a16-bit prescaler
32-bit PWM mode with a 16-bit prescaler and software-programmable output inversion of the
PWM signal
Count up or down
Twelve 16/32-bit Capture Compare PWM pins (CCP)
April 10, 2013 50
Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
Timer synchronization allows selected timers to start counting on the same clock cycle
ADC event trigger
User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding
RTC mode)
Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine
Dedicated channel for each timer
Burst request generated on timer interrupt
1.3.4.4 CCP Pins (see page 653)
Capture Compare PWMpins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTMcan generate a simple PWM
output on the CCP pin.
The TM4C123AH6PM microcontroller includes twelve 16/32-bit CCP pins that can be programmed
to operate in the following modes:
Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
PWM: The GPTimer is incremented/decremented by the systemclock. APWMsignal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
1.3.4.5 Watchdog Timers (see page 715)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The TM4C123AH6PM Watchdog
Timer can generate an interrupt, a non-maskable interrupt, or a reset when a time-out value is
reached. In addition, the Watchdog Timer is ARMFiRM-compliant and can be configured to generate
an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second
timeout. Once the Watchdog Timer has been configured, the lock register can be written to prevent
the timer configuration from being inadvertently altered.
The TM4C123AH6PM microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses
the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The
Watchdog Timer module has the following features:
32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking and optional NMI function
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Lock register protection from runaway software
Reset generation logic with an enable/disable
User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
1.3.4.6 Programmable GPIOs (see page 591)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The
TM4C123AH6PM GPIO module is comprised of seven physical GPIO blocks, each corresponding
to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 0-49 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see Signal
Tables on page 1155 for the signals available to each GPIO pin).
5-V-tolerant in input configuration
Ports A-G accessed through the Advanced Peripheral Bus (APB)
Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for
ports on APB
Programmable control for GPIO interrupts
Interrupt generation masking
Edge-triggered on rising, falling, or both
Level-sensitive on High or Low values
Bit masking in both read and write operations through address lines
Can be used to initiate an ADC sample sequence or a DMA transfer
Pins configured as digital inputs are Schmitt-triggered
Programmable control for GPIO pad configuration
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA
for high-current applications
Slew rate control for 8-mA pad drive
Open drain enables
Digital input enables
1.3.5 Advanced Motion Control
The TM4C123AH6PM microcontroller provides motion control functions integrated into the device,
including:
April 10, 2013 52
Two PWMmodules, with a total of 16 advanced PWMoutputs for motion and energy applications
Six fault inputs to promote low-latency shutdown
Two Quadrature Encoder Inputs (QEI)
The following provides more detail on these motion control functions.
1.3.5.1 PWM (see page 1053)
The TM4C123AH6PM microcontroller contains two PWM modules, each with four PWM generator
blocks and a control block, for a total of 16 PWM outputs. Pulse width modulation (PWM) is a
powerful technique for digitally encoding analog signal levels. High-resolution counters are used to
generate a square wave, and the duty cycle of the square wave is modulated to encode an analog
signal. Typical applications include switching power supplies and motor control. Each
TM4C123AH6PM PWM module consists of four PWM generator block and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. Each PWM
generator block produces two PWM signals that can either be independent signals or a single pair
of complementary signals with dead-band delays inserted.
Each PWM generator has the following features:
Three fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage
to the motor being controlled, for a total of six inputs
One 16-bit counter
Runs in Down or Up/Down mode
Output frequency controlled by a 16-bit load value
Load value updates can be synchronized
Produces output signals at zero and load value
Two PWM comparators
Comparator value updates can be synchronized
Produces output signals on match
PWM signal generator
Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
Produces two independent PWM signals
Dead-band generator
Produces two PWMsignals with programmable dead-band delays suitable for driving a half-H
bridge
Can be bypassed, leaving input PWM signals unmodified
Can initiate an ADC sample sequence
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The control block determines the polarity of the PWM signals and which signals are passed through
to the pins. The output of the PWM generation blocks are managed by the output control block
before being passed to the device pins. The PWM control block has the following options:
PWM output enable of each PWM signal
Optional output inversion of each PWM signal (polarity control)
Optional fault handling for each PWM signal
Synchronization of timers in the PWM generator blocks
Synchronization of timer/comparator updates across the PWM generator blocks
Extended PWM synchronization of timer/comparator updates across the PWM generator blocks
Interrupt status summary of the PWM generator blocks
Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering
PWM generators can be operated independently or synchronized with other generators
1.3.5.2 QEI (see page 1131)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index
signal, can be used to reset the position counter. The TM4C123AH6PM quadrature encoder with
index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position
over time and determine direction of rotation. In addition, it can capture a running estimate of the
velocity of the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the
processor frequency (for example, 20 MHz for a 80-MHz system).
The TM4C123AH6PM microcontroller includes two QEI modules providing control of two motors at
the same time with the following features:
Position integrator that tracks the encoder position
Programmable noise filter on the inputs
Velocity capture using built-in timer
The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
Interrupt generation on:
Index pulse
Velocity-timer expiration
Direction change
Quadrature error detection
April 10, 2013 54
1.3.6 Analog
The TM4C123AH6PMmicrocontroller provides analog functions integrated into the device, including:
Two 12-bit Analog-to-Digital Converters (ADC) with 12 analog input channels and a sample rate
of one million samples/second
Two analog comparators
16 digital comparators
On-chip voltage regulator
The following provides more detail on these analog functions.
1.3.6.1 ADC (see page 740)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number. The TM4C123AH6PM ADC module features 12-bit conversion resolution
and supports 12 input channels plus an internal temperature sensor. Four buffered sample
sequencers allow rapid sampling of up to 12 analog input sources without controller intervention.
Each sample sequencer provides flexible programming with fully configurable input source, trigger
events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator
function that allows the conversion value to be diverted to a comparison unit that provides eight
digital comparators.
The TM4C123AH6PM microcontroller provides two ADC modules with the following features:
12 shared analog input channels
12-bit precision ADC
Single-ended and differential-input configurations
On-chip internal temperature sensor
Maximum sample rate of one million samples/second
Optional phase shift in sample time programmable from 22.5 to 337.5
Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
Flexible trigger control
Controller (software)
Timers
Analog Comparators
PWM
GPIO
Hardware averaging of up to 64 samples
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Digital comparison unit providing eight digital comparators
Converter uses VDDA and GNDA as the voltage reference
Power and ground for the analog circuitry is separate from the digital power and ground
Dedicated channel for each sample sequencer
ADC module uses burst requests for DMA
1.3.6.2 Analog Comparators (see page 1038)
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result. The TM4C123AH6PM microcontroller provides two
independent integrated analog comparators that can be configured to drive an output or generate
an interrupt or ADC event.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The TM4C123AH6PM microcontroller provides two independent integrated analog comparators
with the following functions:
Compare external pin input to external pin input or to internal programmable voltage reference
Compare a test voltage against any one of the following voltages:
An individual external reference voltage
A shared single external reference voltage
A shared internal reference voltage
1.3.7 JTAG and ARM Serial Wire Debug (see page 189)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/Opin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port
(SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one
module providing all the normal JTAG debug and test functionality plus real-time access to system
memory without halting the core or requiring any target resident code. The SWJ-DP interface has
the following features:
IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
Four-bit Instruction Register (IR) chain for storing JTAG instructions
IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST
April 10, 2013 56
ARM additional instructions: APACC, DPACC and ABORT
Integrated ARM Serial Wire Debug (SWD)
Serial Wire JTAG Debug Port (SWJ-DP)
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
Embedded Trace Macrocell (ETM) for instruction trace capture
Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
1.3.8 Packaging and Temperature
64-pin RoHS-compliant LQFP package
Industrial (-40C to 85C) temperature range
1.4 TM4C123AH6PM Microcontroller Hardware Details
Details on the pins and package can be found in the following sections:
Pin Diagram on page 1154
Signal Tables on page 1155
Electrical Characteristics on page 1183
Package Information on page 1220
1.5 Kits
The Tiva C Series provides the hardware and software tools that engineers need to begin
development quickly.
Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files
Evaluation Kits provide a low-cost and effective means of evaluating TM4C123AH6PM
microcontrollers before purchase
Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box
See the Tiva series website at http://www.ti.com/tiva-c for the latest tools available, or ask your
distributor.
1.6 Support Information
For support on Tiva C Series products, contact the TI Worldwide Product Information Center
nearest you.
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2 The Cortex-M4F Processor
The ARMCortex-M4F processor provides a high-performance, low-cost platformthat meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
32-bit ARM
Cortex
-M4F architecture optimized for small-footprint embedded applications

80-MHz operation; 100 DMIPS performance
Outstanding processing performance combined with fast interrupt handling
Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
Single-cycle multiply instruction and hardware divide
Atomic bit manipulation (bit-banding), delivering maximummemory utilization and streamlined
peripheral control
Unaligned data access, enabling data to be efficiently packed into memory
IEEE754-compliant single-precision Floating-Point Unit (FPU)
16-bit SIMD vector processing unit
Fast code execution permits slower processor clock or increases sleep mode time
Harvard architecture characterized by separate buses for instruction and data
Efficient processor core, system and memories
Hardware division and fast digital-signal-processing orientated multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
Enhanced system debug with extensive breakpoint and trace capabilities
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
Migration from the ARM7
processor family for better performance and power efficiency

Optimized for single-cycle Flash memory usage up to specific frequencies; see Internal
Memory on page 467 for more information.
Ultra-low power consumption with integrated sleep modes
April 10, 2013 58
The Cortex-M4F Processor
The TivaCSeries microcontrollers builds on this core to bring high-performance 32-bit computing
to
This chapter provides information on the Tiva C Series implementation of the Cortex-M4F
processor, including the programming model, the memory model, the exception model, fault handling,
and power management.
For technical details on the instruction set, see the Cortex-M3/M4 Instruction Set Technical User's
Manual.
2.1 Block Diagram
The Cortex-M4F processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including IEEE754-compliant single-precision floating-point
computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate
capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4F processor implements tightly
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M4F processor implements a version of the
Thumb instruction set based on Thumb-2 technology, ensuring high code density and reduced
programmemory requirements. The Cortex-M4F instruction set provides the exceptional performance
expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
The Cortex-M4F processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The TM4C123AH6PM NVIC includes a non-maskable
interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core
and NVICprovides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt
latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.
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Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM4 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Debug
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M4F
FPU
Embedded
Trace
Macrocell
2.2 Overview
2.2.1 System-Level Interface
The Cortex-M4F processor provides multiple interfaces using AMBA technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M4F processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.
2.2.2 Integrated Configurable Debug
The Cortex-M4F processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Tiva
C Series implementation replaces the ARM SW-DP and JTAG-DP with the ARM
CoreSight-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface
combines the SWD and JTAG debug ports into one module. See the ARM Debug Interface V5
Architecture Specification for details on SWJ-DP.
For systemtrace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.
April 10, 2013 60
The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area smaller
than traditional trace units, enabling full instruction trace. For more details on the ARM ETM, see
the ARM Embedded Trace Macrocell Architecture Specification.
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions of up to eight
words in the program code in the CODE memory region. This enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M4F debug capabilities, see theARM Debug Interface V5
Architecture Specification.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M4F trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 61.
Figure 2-2. TPIU Block Diagram
ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
2.2.4 Cortex-M4F System Component Details
The Cortex-M4F includes the following system components:
SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see System Timer (SysTick) on page 112).
Nested Vectored Interrupt Controller (NVIC)
An embedded interrupt controller that supports low latency interrupt processing (see Nested
Vectored Interrupt Controller (NVIC) on page 113).
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System Control Block (SCB)
The programming model interface to the processor. The SCB provides system implementation
information and systemcontrol, including configuration, control, and reporting of systemexceptions
(see System Control Block (SCB) on page 114).
Memory Protection Unit (MPU)
Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
Memory Protection Unit (MPU) on page 114).
Floating-Point Unit (FPU)
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square-root operations. It also provides conversions between fixed-point and floating-point data
2.3 Programming Model
This section describes the Cortex-M4F programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.
2.3.1 Processor Mode and Privilege Levels for Software Execution
The Cortex-M4F has two modes of operation:
Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.
In addition, the Cortex-M4F has two privilege levels:
Unprivileged
In this mode, software has the following restrictions:
Limited access to the MSR and MRS instructions and no use of the CPS instruction
No access to the system timer, NVIC, or system control block
Possibly restricted access to memory or peripherals
Privileged
In this mode, software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register (see page 77) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
April 10, 2013 62
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.
2.3.2 Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
itemon the memory. When the processor pushes a new itemonto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks:
the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 67).
In Thread mode, the CONTROL register (see page 77) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 63.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Stack Used Privilege Level Use Processor Mode
Main stack or process stack
a
Privileged or unprivileged
a
Applications Thread
Main stack Always privileged Exception handlers Handler
a. See CONTROL (page 77).
2.3.3 Register Map
Figure 2-3 on page 64 shows the Cortex-M4F register set. Table 2-2 on page 64 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
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Figure 2-3. Cortex-M4F Register Set
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP
PSP
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
Banked version of SP
Table 2-2. Processor Register Map
See
page
Description Reset Type Name Offset
66 Cortex General-Purpose Register 0 - R/W R0 -
April 10, 2013 64
Table 2-2. Processor Register Map (continued)
See
page
67 Stack Pointer - R/W SP -
68 Link Register 0xFFFF.FFFF R/W LR -
69 Program Counter - R/W PC -
70 Program Status Register 0x0100.0000 R/W PSR -
74 Priority Mask Register 0x0000.0000 R/W PRIMASK -
75 Fault Mask Register 0x0000.0000 R/W FAULTMASK -
76 Base Priority Mask Register 0x0000.0000 R/W BASEPRI -
77 Control Register 0x0000.0000 R/W CONTROL -
79 Floating-Point Status Control - R/W FPSC -
2.3.4 Register Descriptions
This section lists and describes the Cortex-M4F registers, in the order shown in Figure
2-3 on page 64. The core registers are not memory mapped and are accessed by register name
rather than offset.
Note: The register type shown in the register descriptions refers to type during programexecution
in Thread mode and Handler mode. Debug access can differ.
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Register 1: Cortex General-Purpose Register 0 (R0)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
Cortex General-Purpose Register 0 (R0)
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DATA
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA
- - - - - - - - - - - - - - - - Reset
Description Reset Type Name Bit/Field
Register data. - R/W DATA 31:0
April 10, 2013 66
Register 14: Stack Pointer (SP)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.
Stack Pointer (SP)
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SP
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SP
- - - - - - - - - - - - - - - - Reset
This field is the address of the stack pointer. - R/W SP 31:0
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Register 15: Link Register (LR)
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. LR can be accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 100 for the values and
description.
Link Register (LR)
Type R/W, reset 0xFFFF.FFFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LINK
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LINK
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
This field is the return address. 0xFFFF.FFFF R/W LINK 31:0
April 10, 2013 68
Register 16: Program Counter (PC)
The ProgramCounter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSRat reset and must be 1. The PCregister
can be accessed in either privileged or unprivileged mode.
Program Counter (PC)
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PC
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PC
- - - - - - - - - - - - - - - - Reset
This field is the current program address. - R/W PC 31:0
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Register 17: Program Status Register (PSR)
Note: This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
Application Program Status Register (APSR), bits 31:27, bits 19:16
Execution Program Status Register (EPSR), bits 26:24, 15:10
Interrupt Program Status Register (IPSR), bits 7:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSRdirectly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see Exception Entry and Return on page 97).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 70 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex-M3/M4 Instruction Set Technical User's
Manual for more information about how to access the program status registers.
Table 2-3. PSR Register Combinations
Combination Type Register
APSR, EPSR, and IPSR R/W
a
,
b
PSR
EPSR and IPSR RO IEPSR
APSR and IPSR R/W
a
IAPSR
APSR and EPSR R/W
b
EAPSR
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type R/W, reset 0x0100.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
GE reserved THUMB ICI / IT Q V C Z N
R/W R/W R/W R/W RO RO RO RO RO RO RO R/W R/W R/W R/W R/W Type
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ISRNUM reserved ICI / IT
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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APSR Negative or Less Flag
Description Value
The previous operation result was negative or less than. 1
The previous operation result was positive, zero, greater than,
or equal.
0
The value of this bit is only meaningful when accessing PSR or APSR.
0 R/W N 31
APSR Zero Flag
Description Value
The previous operation result was zero. 1
The previous operation result was non-zero. 0
0 R/W Z 30
APSR Carry or Borrow Flag
Description Value
The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
1
The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.
0
0 R/W C 29
APSR Overflow Flag
Description Value
The previous operation resulted in an overflow. 1
The previous operation did not result in an overflow. 0
0 R/W V 28
APSR DSP Overflow and Saturation Flag
Description Value
DSP Overflow or saturation has occurred. 1
DSP overflowor saturation has not occurred since reset or since
the bit was last cleared.
0
This bit is cleared by software using an MRS instruction.
0 R/W Q 27
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EPSR ICI / IT status
These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following an IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSRor EPSR.
0x0 RO ICI / IT 26:25
EPSR Thumb State
This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:
The BLX, BX and POP{PC} instructions
Restoration from the stacked xPSR value on an exception return
Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a fault
or lockup. See Lockup on page 102 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
1 RO THUMB 24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00 RO reserved 23:20
Greater Than or Equal Flags
See the description of the SEL instruction in the Cortex-M3/M4
Instruction Set Technical User's Manual for more information.
The value of this field is only meaningful when accessing PSRor APSR.
0x0 R/W GE 19:16
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor stops the
load multiple or store multiple instruction operation temporarily and
stores the next register operand in the multiple operation to bits 15:12.
After servicing the interrupt, the processor returns to the register pointed
to by bits 15:12 and resumes execution of the multiple load or store
instruction. When EPSR holds the ICI execution state, bits 11:10 are
zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSRor EPSR.
0x0 RO ICI / IT 15:10
0x0 RO reserved 9:8
April 10, 2013 72
IPSR ISR Number
This field contains the exception type number of the current Interrupt
Service Routine (ISR).
Description Value
Thread mode 0x00
Reserved 0x01
NMI 0x02
Hard fault 0x03
Memory management fault 0x04
Bus fault 0x05
Usage fault 0x06
Reserved 0x07-0x0A
SVCall 0x0B
Reserved for Debug 0x0C
Reserved 0x0D
PendSV 0x0E
SysTick 0x0F
Interrupt Vector 0 0x10
... ...
Interrupt Vector 138 0x9A
See Exception Types on page 91 for more information.
The value of this field is only meaningful when accessing PSR or IPSR.
0x00 RO ISRNUM 7:0
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Register 18: Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the
Cortex-M3/M4 Instruction Set Technical User's Manual for more information on these instructions.
For more information on exception priority levels, see Exception Types on page 91.
Priority Mask Register (PRIMASK)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PRIMASK reserved
R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0000.000 RO reserved 31:1
Priority Mask
Description Value
Prevents the activation of all exceptions with configurable
priority.
1
No effect. 0
0 R/W PRIMASK 0
April 10, 2013 74
Register 19: Fault Mask Register (FAULTMASK)
The FAULTMASKregister prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASKregister, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex-M3/M4 Instruction Set Technical User's Manual for more information on
these instructions. For more information on exception priority levels, see Exception
Types on page 91.
Fault Mask Register (FAULTMASK)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FAULTMASK reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Fault Mask
Description Value
Prevents the activation of all exceptions except for NMI. 1
No effect. 0
The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.
0 R/W FAULTMASK 0
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Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see Exception Types on page 91.
Base Priority Mask Register (BASEPRI)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved BASEPRI reserved
RO RO RO RO RO R/W R/W R/W RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASKregister
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
Description Value
All exceptions are unmasked. 0x0
All exceptions with priority level 1-7 are masked. 0x1
All exceptions with priority level 7 are masked. 0x7
0x0 R/W BASEPRI 7:5
0x0 RO reserved 4:0
April 10, 2013 76
Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode, and indicates whether the FPU state is active. This register is only
accessible in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 100).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch
the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as
detailed in the Cortex-M3/M4 Instruction Set Technical User's Manual, or perform an exception
return to Thread mode with the appropriate EXC_RETURNvalue, as shown in Table 2-10 on page 100.
Note: When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex-M3/M4 Instruction Set Technical User's Manual.
Control Register (CONTROL)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TMPL ASP FPCA reserved
R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Floating-Point Context Active
Description Value
Floating-point context active 1
No floating-point context active 0
The Cortex-M4F uses this bit to determine whether to preserve
floating-point state when processing an exception.
Important:
Two bits control when FPCA can be enabled: the ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the DISFPCA bit in the Auxiliary Control
(ACTLR) register.
0 R/W FPCA 2
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Active Stack Pointer
Description Value
PSP is the current stack pointer. 1
MSP is the current stack pointer 0
In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M4F updates this bit automatically on exception return.
0 R/W ASP 1
Thread Mode Privilege Level
Description Value
Unprivileged software can be executed in Thread mode. 1
Only privileged software can be executed in Thread mode. 0
0 R/W TMPL 0
April 10, 2013 78
Register 22: Floating-Point Status Control (FPSC)
The FPSC register provides all necessary user-level control of the floating-point system.
Floating-Point Status Control (FPSC)
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved RMODE FZ DN AHP reserved V C Z N
RO RO RO RO RO RO R/W R/W R/W R/W R/W RO R/W R/W R/W R/W Type
0 0 0 0 0 0 - - - - - 0 - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IOC DZC OFC UFC IXC reserved IDC reserved
R/W R/W R/W R/W R/W RO RO R/W RO RO RO RO RO RO RO RO Type
- - - - - 0 0 - 0 0 0 0 0 0 0 0 Reset
Negative Condition Code Flag
Floating-point comparison operations update this condition code flag.
- R/W N 31
Zero Condition Code Flag
- R/W Z 30
Carry Condition Code Flag
- R/W C 29
Overflow Condition Code Flag
- R/W V 28
0 RO reserved 27
Alternative Half-Precision
When set, alternative half-precision format is selected. When clear,
IEEE half-precision format is selected.
The AHP bit in the FPDSC register holds the default value for this bit.
- R/W AHP 26
Default NaN Mode
When set, any operation involving one or more NaNs returns the Default
NaN. When clear, NaN operands propagate through to the output of a
floating-point operation.
The DN bit in the FPDSC register holds the default value for this bit.
- R/W DN 25
Flush-to-Zero Mode
When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero
mode is disabled and the behavior of the floating-point system is fully
compliant with the IEEE 754 standard.
The FZ bit in the FPDSC register holds the default value for this bit.
- R/W FZ 24
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Rounding Mode
The specified rounding mode is used by almost all floating-point
instructions.
The RMODE bit in the FPDSC register holds the default value for this bit.
Description Value
Round to Nearest (RN) mode 0x0
Round towards Plus Infinity (RP) mode 0x1
Round towards Minus Infinity (RM) mode 0x2
Round towards Zero (RZ) mode 0x3
- R/W RMODE 23:22
Input Denormal Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
- R/W IDC 7
0x0 RO reserved 6:5
Inexact Cumulative Exception
to this bit.
- R/W IXC 4
Underflow Cumulative Exception
to this bit.
- R/W UFC 3
Overflow Cumulative Exception
to this bit.
- R/W OFC 2
Division by Zero Cumulative Exception
to this bit.
- R/W DZC 1
Invalid Operation Cumulative Exception
to this bit.
- R/W IOC 0
April 10, 2013 80
2.3.5 Exceptions and Interrupts
The Cortex-M4F processor supports interrupts and system exceptions. The processor and the
Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception
changes the normal flow of software control. The processor uses Handler mode to handle all
exceptions except for reset. See Exception Entry and Return on page 97 for more information.
The NVIC registers control interrupt handling. See Nested Vectored Interrupt Controller
(NVIC) on page 113 for more information.
2.3.6 Data Types
The Cortex-M4F supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
Memory Regions, Types and Attributes on page 84 for more information.
2.4 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the TM4C123AH6PM controller is provided in Table 2-4 on page 81. In this
manual, register addresses are given as a hexadecimal increment, relative to the modules base
address as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see Bit-Banding on page 86).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see Cortex-M4 Peripherals on page 111).
Note: Within the memory map, all reserved space returns a bus fault when read or written.
Table 2-4. Memory Map
For details,
see page ...
Description End Start
Memory
483 On-chip Flash 0x0003.FFFF 0x0000.0000
- Reserved 0x00FF.FFFF 0x0004.0000
469 Reserved for ROM 0x1FFF.FFFF 0x0100.0000
468 Bit-banded on-chip SRAM 0x2000.7FFF 0x2000.0000
468 Bit-band alias of bit-banded on-chip SRAM starting at
0x2000.0000
0x220F.FFFF 0x2200.0000
- Reserved 0x3FFF.FFFF 0x2210.0000
FiRM Peripherals
718 Watchdog timer 0 0x4000.0FFF 0x4000.0000
718 Watchdog timer 1 0x4000.1FFF 0x4000.1000
- Reserved 0x4000.3FFF 0x4000.2000
602 GPIO Port A 0x4000.4FFF 0x4000.4000
602 GPIO Port B 0x4000.5FFF 0x4000.5000
602 GPIO Port C 0x4000.6FFF 0x4000.6000
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Table 2-4. Memory Map (continued)
For details,
see page ...
602 GPIO Port D 0x4000.7FFF 0x4000.7000
907 SSI0 0x4000.8FFF 0x4000.8000
907 SSI1 0x4000.9FFF 0x4000.9000
907 SSI2 0x4000.AFFF 0x4000.A000
907 SSI3 0x4000.BFFF 0x4000.B000
846 UART0 0x4000.CFFF 0x4000.C000
846 UART1 0x4000.DFFF 0x4000.D000
846 UART2 0x4000.EFFF 0x4000.E000
846 UART3 0x4000.FFFF 0x4000.F000
846 UART4 0x4001.0FFF 0x4001.0000
846 UART5 0x4001.1FFF 0x4001.1000
846 UART6 0x4001.2FFF 0x4001.2000
846 UART7 0x4001.3FFF 0x4001.3000
- Reserved 0x4001.FFFF 0x4001.4000
Peripherals
957 I
2
C 0 0x4002.0FFF 0x4002.0000
957 I
2
C 1 0x4002.1FFF 0x4002.1000
957 I
2
C 2 0x4002.2FFF 0x4002.2000
957 I
2
C 3 0x4002.3FFF 0x4002.3000
602 GPIO Port E 0x4002.4FFF 0x4002.4000
602 GPIO Port F 0x4002.5FFF 0x4002.5000
602 GPIO Port G 0x4002.6FFF 0x4002.6000
- Reserved 0x4002.7FFF 0x4002.7000
1066 PWM 0 0x4002.8FFF 0x4002.8000
1066 PWM 1 0x4002.9FFF 0x4002.9000
- Reserved 0x4002.BFFF 0x4002.A000
1137 QEI0 0x4002.CFFF 0x4002.C000
1137 QEI1 0x4002.DFFF 0x4002.D000
- Reserved 0x4002.FFFF 0x4002.E000
667 16/32-bit Timer 0 0x4003.0FFF 0x4003.0000
667 16/32-bit Timer 1 0x4003.1FFF 0x4003.1000
667 16/32-bit Timer 2 0x4003.2FFF 0x4003.2000
667 16/32-bit Timer 3 0x4003.3FFF 0x4003.3000
667 16/32-bit Timer 4 0x4003.4FFF 0x4003.4000
667 16/32-bit Timer 5 0x4003.5FFF 0x4003.5000
667 32/64-bit Timer 0 0x4003.6FFF 0x4003.6000
667 32/64-bit Timer 1 0x4003.7FFF 0x4003.7000
761 ADC0 0x4003.8FFF 0x4003.8000
761 ADC1 0x4003.9FFF 0x4003.9000
- Reserved 0x4003.BFFF 0x4003.A000
1038 Analog Comparators 0x4003.CFFF 0x4003.C000
April 10, 2013 82
Table 2-4. Memory Map (continued)
For details,
see page ...
- Reserved 0x4003.FFFF 0x4003.D000
1007 CAN0 Controller 0x4004.0FFF 0x4004.0000
1007 CAN1 Controller 0x4004.1FFF 0x4004.1000
- Reserved 0x4004.BFFF 0x4004.2000
667 32/64-bit Timer 2 0x4004.CFFF 0x4004.C000
667 32/64-bit Timer 3 0x4004.DFFF 0x4004.D000
667 32/64-bit Timer 4 0x4004.EFFF 0x4004.E000
667 32/64-bit Timer 5 0x4004.FFFF 0x4004.F000
- Reserved 0x4005.7FFF 0x4005.0000
602 GPIO Port A (AHB aperture) 0x4005.8FFF 0x4005.8000
602 GPIO Port B (AHB aperture) 0x4005.9FFF 0x4005.9000
602 GPIO Port C (AHB aperture) 0x4005.AFFF 0x4005.A000
602 GPIO Port D (AHB aperture) 0x4005.BFFF 0x4005.B000
602 GPIO Port E (AHB aperture) 0x4005.CFFF 0x4005.C000
602 GPIO Port F (AHB aperture) 0x4005.DFFF 0x4005.D000
602 GPIO Port G (AHB aperture) 0x4005.EFFF 0x4005.E000
- Reserved 0x400A.EFFF 0x4005.F000
501 EEPROM and Key Locker 0x400A.FFFF 0x400A.F000
- Reserved 0x400B.FFFF 0x400B.0000
957 I
2
C 4 0x400C.0FFF 0x400C.0000
957 I
2
C 5 0x400C.1FFF 0x400C.1000
- Reserved 0x400F.8FFF 0x400C.2000
459 System Exception Module 0x400F.9FFF 0x400F.9000
- Reserved 0x400F.CFFF 0x400F.A000
483 Flash memory control 0x400F.DFFF 0x400F.D000
224 System control 0x400F.EFFF 0x400F.E000
548 DMA 0x400F.FFFF 0x400F.F000
- Bit-banded alias of 0x4000.0000 through 0x400F.FFFF 0x43FF.FFFF 0x4200.0000
- Reserved 0xDFFF.FFFF 0x4400.0000
Private Peripheral Bus
60 Instrumentation Trace Macrocell (ITM) 0xE000.0FFF 0xE000.0000
60 Data Watchpoint and Trace (DWT) 0xE000.1FFF 0xE000.1000
60 Flash Patch and Breakpoint (FPB) 0xE000.2FFF 0xE000.2000
- Reserved 0xE000.DFFF 0xE000.3000
123 Cortex-M4F Peripherals (SysTick, NVIC, MPU, FPUand SCB) 0xE000.EFFF 0xE000.E000
- Reserved 0xE003.FFFF 0xE000.F000
61 Trace Port Interface Unit (TPIU) 0xE004.0FFF 0xE004.0000
60 Embedded Trace Macrocell (ETM) 0xE004.1FFF 0xE004.1000
- Reserved 0xFFFF.FFFF 0xE004.2000
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2.4.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
Normal: The processor can re-order transactions for efficiency and perform speculative reads.
Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
systemcan buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
Software Ordering of Memory Accesses on page 85).
However, the memory systemdoes guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3 Behavior of Memory Accesses
Table 2-5 on page 84 shows the behavior of accesses to each region in the memory map. See
Memory Regions, Types and Attributes on page 84 for more information on memory types and
the XN attribute. Tiva C Series devices may have reserved memory areas within the address
ranges shown below (refer to Table 2-4 on page 81 for more information).
Table 2-5. Memory Access Behavior
Description Execute
Never
(XN)
Memory Type Memory Region Address Range
This executable region is for programcode.
Data can also be stored here.
- Normal Code 0x0000.0000 - 0x1FFF.FFFF
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 86).
- Normal SRAM 0x2000.0000 - 0x3FFF.FFFF
This region includes bit band and bit band
alias areas (see Table 2-7 on page 87).
XN Device Peripheral 0x4000.0000 - 0x5FFF.FFFF
This executable region is for data. - Normal External RAM 0x6000.0000 - 0x9FFF.FFFF
April 10, 2013 84
Table 2-5. Memory Access Behavior (continued)
Description Execute
Never
(XN)
Memory Type Memory Region Address Range
This region is for external device memory. XN Device External device 0xA000.0000 - 0xDFFF.FFFF
This region includes the NVIC, system
timer, and system control block.
XN Strongly
Ordered
Private peripheral
bus
0xE000.0000- 0xE00F.FFFF
- - - Reserved 0xE010.0000- 0xFFFF.FFFF
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M4F has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see Memory Protection Unit (MPU) on page 114.
The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from
branch target addresses.
2.4.4 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
The processor has multiple bus interfaces.
Memory or devices in the memory map have different wait states.
Some memory accesses are buffered or speculative.
Memory SystemOrdering of Memory Accesses on page 84 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M4F
has the following memory barrier instructions:
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
MPU programming
If the MPUsettings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.
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Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.
Vector table
If the programchanges an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.
Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.
Memory map switching
If the systemcontains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.
Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex-M3/M4 Instruction Set
Technical User's Manual.
2.4.5 Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAMand peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 86. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 87. For the specific address range of the bit-band regions,
see Table 2-4 on page 81.
Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.
Table 2-6. SRAM Memory Bit-Banding Regions
Instruction and Data Accesses Memory Region
Address Range
End Start
Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
SRAM bit-band region 0x2000.7FFF 0x2000.0000
April 10, 2013 86
Table 2-6. SRAM Memory Bit-Banding Regions (continued)
Address Range
End Start
Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not remapped.
SRAM bit-band alias 0x220F.FFFF 0x2200.0000
Table 2-7. Peripheral Memory Bit-Banding Regions
Address Range
End Start
Direct accesses to this memory range behave as
peripheral memory accesses, but this region is also bit
addressable through bit-band alias.
Peripheral bit-band
region
0x400F.FFFF 0x4000.0000
Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not permitted.
Peripheral bit-band alias 0x43FF.FFFF 0x4200.0000
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
bit_word_offset
The position of the target bit in the bit-band memory region.
bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.
bit_band_base
The starting address of the alias region.
byte_offset
The number of the byte in the bit-band region that contains the targeted bit.
bit_number
The bit position, 0-7, of the targeted bit.
Figure 2-4 on page 88 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:
The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)
The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)
The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:
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0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)
The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:
0x2200.001C = 0x2200.0000+ (0*32) + (7*4)
Figure 2-4. Bit-Band Mapping
0x23FF.FFE4
0x2200.0004
0x23FF.FFE0 0x23FF.FFE8 0x23FF.FFEC 0x23FF.FFF0 0x23FF.FFF4 0x23FF.FFF8 0x23FF.FFFC
0x2200.0000 0x2200.0014 0x2200.0018 0x2200.001C 0x2200.0008 0x2200.0010 0x2200.000C
32-MB Alias Region
0
7 0
0 7
0x2000.0000 0x2000.0001 0x2000.0002 0x2000.0003
6 5 4 3 2 1 0 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 7 6 5 4 3 2 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0x200F.FFFC 0x200F.FFFD 0x200F.FFFE 0x200F.FFFF
1-MB SRAM Bit-Band Region
2.4.5.1 Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
2.4.5.2 Directly Accessing a Bit-Band Region
Behavior of Memory Accesses on page 84 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
2.4.6 Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order fromzero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 89 illustrates how data is stored.
April 10, 2013 88
Figure 2-5. Data Storage
Memory Register
Address A
A+1
lsbyte
msbyte
A+2
A+3
0 7
B0 B1 B3 B2
31 2423 1615 8 7 0
B0
B1
B2
B3
2.4.7 Synchronization Primitives
The Cortex-M4F instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
The word instructions LDREX and STREX
The halfword instructions LDREXH and STREXH
The byte instructions LDREXB and STREXB
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Modify the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the newvalue back to the memory location.
4. Test the returned status bit.
If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no
write was performed, which indicates that the value returned at step 1 might be out of date. The
software must retry the entire read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
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1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.
The Cortex-M4F includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:
It executes a CLREX instruction.
It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.
For more information about the synchronization primitive instructions, see the Cortex-M3/M4
Instruction Set Technical User's Manual.
2.5 Exception Model
The ARM Cortex-M4F processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 92 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 79 interrupts (listed in Table 2-9 on page 93).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
Nested Vectored Interrupt Controller (NVIC) on page 113.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See Nested Vectored Interrupt Controller (NVIC) on page 113 for more information on exceptions
and interrupts.
April 10, 2013 90
2.5.1 Exception States
Each exception is in one of the following states:
Inactive. The exception is not active and not pending.
Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
Active. An exception that is being serviced by the processor but has not completed.
Note: An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2 Exception Types
The exception types are:
Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special formof exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.
Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.
Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.
Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
An undefined instruction
An illegal unaligned access
Invalid state on instruction execution
91 April 10, 2013
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An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVCinstructions to access OS kernel functions and device
drivers.
Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 93 lists the interrupts on the TM4C123AH6PM controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 92 shows as having
configurable priority (see the SYSHNDCTRL register on page 162 and the DIS0 register on page 133).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see Fault Handling on page 100.
Table 2-8. Exception Types
Activation Vector Address or
Offset
b
Priority
a
Vector
Number
Exception Type
Stack top is loaded fromthe first
entry of the vector table on reset.
0x0000.0000 - 0 -
Asynchronous 0x0000.0004 -3 (highest) 1 Reset
Asynchronous 0x0000.0008 -2 2 Non-Maskable Interrupt
(NMI)
- 0x0000.000C -1 3 Hard Fault
Synchronous 0x0000.0010 programmable
c
4 Memory Management
Synchronous when precise and
asynchronous when imprecise
0x0000.0014 programmable
c
5 Bus Fault
c
6 Usage Fault
Reserved - - 7-10 -
Synchronous 0x0000.002C programmable
c
11 SVCall
c
12 Debug Monitor
Reserved - - 13 -
April 10, 2013 92
Table 2-8. Exception Types (continued)
Activation Vector Address or
Offset
b
Priority
a
Vector
Number
Exception Type
Asynchronous 0x0000.0038 programmable
c
14 PendSV
Asynchronous 0x0000.003C programmable
c
15 SysTick
Asynchronous 0x0000.0040 and above programmable
d
16 and above Interrupts
a. 0 is the default priority for all the programmable priorities.
b. See Vector Table on page 95.
c. See SYSPRI1 on page 159.
d. See PRIn registers on page 141.
Table 2-9. Interrupts
Description Vector Address or
Offset
Interrupt Number (Bit
in Interrupt Registers)
Vector Number
Processor exceptions 0x0000.0000 -
0x0000.003C
- 0-15
GPIO Port A 0x0000.0040 0 16
GPIO Port B 0x0000.0044 1 17
GPIO Port C 0x0000.0048 2 18
GPIO Port D 0x0000.004C 3 19
GPIO Port E 0x0000.0050 4 20
UART0 0x0000.0054 5 21
UART1 0x0000.0058 6 22
SSI0 0x0000.005C 7 23
I
2
C0 0x0000.0060 8 24
PWM0 Fault 0x0000.0064 9 25
PWM0 Generator 0 0x0000.0068 10 26
PWM0 Generator 1 0x0000.006C 11 27
PWM0 Generator 2 0x0000.0070 12 28
QEI0 0x0000.0074 13 29
ADC0 Sequence 0 0x0000.0078 14 30
ADC0 Sequence 1 0x0000.007C 15 31
ADC0 Sequence 2 0x0000.0080 16 32
ADC0 Sequence 3 0x0000.0084 17 33
Watchdog Timers 0 and 1 0x0000.0088 18 34
16/32-Bit Timer 0A 0x0000.008C 19 35
16/32-Bit Timer 0B 0x0000.0090 20 36
16/32-Bit Timer 1A 0x0000.0094 21 37
16/32-Bit Timer 1B 0x0000.0098 22 38
16/32-Bit Timer 2A 0x0000.009C 23 39
16/32-Bit Timer 2B 0x0000.00A0 24 40
Analog Comparator 0 0x0000.00A4 25 41
Analog Comparator 1 0x0000.00A8 26 42
Reserved - 27 43
System Control 0x0000.00B0 28 44
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Table 2-9. Interrupts (continued)
Offset
Vector Number
Flash Memory Control and EEPROM Control 0x0000.00B4 29 45
GPIO Port F 0x0000.00B8 30 46
GPIO Port G 0x0000.00BC 31 47
Reserved - 32 48
UART2 0x0000.00C4 33 49
SSI1 0x0000.00C8 34 50
16/32-Bit Timer 3A 0x0000.00CC 35 51
16/32-Bit Timer 3B 0x0000.00D0 36 52
I
2
C1 0x0000.00D4 37 53
QEI1 0x0000.00D8 38 54
CAN0 0x0000.00DC 39 55
CAN1 0x0000.00E0 40 56
Reserved - 41-44 57-60
PWM Generator 3 0x0000.00F4 45 61
DMA Software 0x0000.00F8 46 62
DMA Error 0x0000.00FC 47 63
ADC1 Sequence 0 0x0000.0100 48 64
ADC1 Sequence 1 0x0000.0104 49 65
ADC1 Sequence 2 0x0000.0108 50 66
ADC1 Sequence 3 0x0000.010C 51 67
Reserved - 52-56 68-72
SSI2 0x0000.0124 57 73
SSI3 0x0000.0128 58 74
UART3 0x0000.012C 59 75
UART4 0x0000.0130 60 76
UART5 0x0000.0134 61 77
UART6 0x0000.0138 62 78
UART7 0x0000.013C 63 79
Reserved 0x0000.0140 -
0x0000.014C
64-67 80-83
I
2
C2 0x0000.0150 68 84
I
2
C3 0x0000.0154 69 85
16/32-Bit Timer 4A 0x0000.0158 70 86
16/32-Bit Timer 4B 0x0000.015C 71 87
Reserved 0x0000.0160 -
0x0000.01AC
72-91 88-107
16/32-Bit Timer 5A 0x0000.01B0 92 108
16/32-Bit Timer 5B 0x0000.01B4 93 109
32/64-Bit Timer 0A 0x0000.01B8 94 110
32/64-Bit Timer 0B 0x0000.01BC 95 111
32/64-Bit Timer 1A 0x0000.01C0 96 112
32/64-Bit Timer 1B 0x0000.01C4 97 113
April 10, 2013 94
Table 2-9. Interrupts (continued)
Offset
Vector Number
32/64-Bit Timer 2A 0x0000.01C8 98 114
32/64-Bit Timer 2B 0x0000.01CC 99 115
32/64-Bit Timer 3A 0x0000.01D0 100 116
32/64-Bit Timer 3B 0x0000.01D4 101 117
32/64-Bit Timer 4A 0x0000.01D8 102 118
32/64-Bit Timer 4B 0x0000.01DC 103 119
32/64-Bit Timer 5A 0x0000.01E0 104 120
32/64-Bit Timer 5B 0x0000.01E4 105 121
System Exception (imprecise) 0x0000.01E8 106 122
Reserved - 107-108 123-124
I
2
C4 0x0000.01F4 109 125
I
2
C5 0x0000.01F8 110 126
Reserved - 111-133 127-149
PWM1 Generator 0 0x0000.0258 134 150
PWM1 Generator 1 0x0000.025C 135 151
PWM1 Generator 2 0x0000.0260 136 152
PWM1 Generator 3 0x0000.0264 137 153
PWM1 Fault 0x0000.0268 138 154
2.5.3 Exception Handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4 Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 92. Figure 2-6 on page 96 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
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Figure 2-6. Vector Table
Initial SP value
Reset
Hard fault
NMI
Memory management fault
Usage fault
Bus fault
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
Reserved
SVCall
PendSV
Reserved for Debug
Systick
IRQ0
Reserved
0x002C
0x0038
0x003C
0x0040
Offset Exception number
2
3
4
5
6
11
12
14
15
16
18
13
7
10
1
Vector
.
.
.
8
9
IRQ1
IRQ2
0x0044
IRQ131
17
0x0048
0x004C
154
.
.
.
.
.
.
0x0268
IRQ number
-14
-13
-12
-11
-10
-5
-2
-1
0
2
1
138
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0400 to 0x3FFF.FC00 (see Vector Table on page 95). Note
that when configuring the VTABLE register, the offset must be aligned on a 1024-byte boundary.
2.5.5 Exception Priorities
As Table 2-8 on page 92 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 159 and
page 141.
Note: Configurable priority values for the Tiva C Series implementation are in the range 0-7.
This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority
values, always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
April 10, 2013 96
If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.
2.5.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:
An upper field that defines the group priority
A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 153.
2.5.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
Interrupt Priority Grouping on page 97 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
Exception Entry on page 98 more information.
Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See Exception Return on page 99 for
more information.
Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.
Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
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return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.
2.5.7.1 Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 74, FAULTMASK on page 75, and BASEPRI on page 76). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
When using floating-point routines, the Cortex-M4F processor automatically stacks the architected
floating-point state on exception entry. Figure 2-7 on page 99 shows the Cortex-M4F stack frame
layout when floating-point state is preserved on the stack as the result of an interrupt or an exception.
Note: Where stack space for floating-point state is not allocated, the stack frame is the same as
that of ARMv7-M implementations without an FPU. Figure 2-7 on page 99 shows this stack
frame also.
April 10, 2013 98
Figure 2-7. Exception Stack Frame
Pre-IRQ top of stack
xPSR
PC
LR
R12
R3
R2
R1
R0
{aligner}
IRQ top of stack
Decreasing
memory
address
xPSR
PC
LR
R12
R3
R2
R1
R0
S7
S6
S5
S4
S3
S2
S1
S0
S9
S8
FPSCR
S15
S14
S13
S12
S11
S10
{aligner}
IRQ top of stack
...
Exception frame with
floating-point storage
Exception frame without
floating-point storage
Pre-IRQ top of stack
...
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address fromthe vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.
2.5.7.2 Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
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An LDM or POP instruction that loads the PC
A BX instruction using any register
An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest five
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 100
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURNbits 31:5 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
Description EXC_RETURN[31:0]
Reserved 0xFFFF.FFE0
Return to Handler mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFE1
Reserved 0xFFFF.FFE2 - 0xFFFF.FFE8
Return to Thread mode.
Exception return uses floating-point state from MSP.
0xFFFF.FFE9
Reserved 0xFFFF.FFEA - 0xFFFF.FFEC
Exception return uses floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFED
Reserved 0xFFFF.FFEE - 0xFFFF.FFF0
Return to Handler mode.
Exception return uses non-floating-point state from MSP.
0xFFFF.FFF1
Reserved 0xFFFF.FFF2 - 0xFFFF.FFF8
Exception return uses non-floating-point state from MSP.
0xFFFF.FFF9
Reserved 0xFFFF.FFFA - 0xFFFF.FFFC
Exception return uses non-floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFFD
Reserved 0xFFFF.FFFE - 0xFFFF.FFFF
2.6 Fault Handling
Faults are a subset of the exceptions (see Exception Model on page 90). The following conditions
generate a fault:
A bus error on an instruction fetch or vector table load or a data access.
April 10, 2013 100
An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.
Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
An MPU fault because of a privilege violation or an attempt to access an unmanaged region.
2.6.1 Fault Types
Table 2-11 on page 101 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 166 for more
information about the fault status registers.
Table 2-11. Faults
Bit Name Fault Status Register Handler Fault
VECT Hard Fault Status (HFAULTSTAT) Hard fault Bus error on a vector read
FORCED Hard Fault Status (HFAULTSTAT) Hard fault Fault escalated to a hard fault
IERR
a
Memory Management Fault Status
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch on
instruction access
DERR Memory Management Fault Status
(MFAULTSTAT)
Memory management
fault
data access
MSTKE Memory Management Fault Status
(MFAULTSTAT)
Memory management
fault
exception stacking
MUSTKE Memory Management Fault Status
(MFAULTSTAT)
Memory management
fault
exception unstacking
MLSPERR Memory Management Fault Status
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch
during lazy floating-point state
preservation
BSTKE Bus Fault Status (BFAULTSTAT) Bus fault Bus error during exception stacking
BUSTKE Bus Fault Status (BFAULTSTAT) Bus fault Bus error during exception unstacking
IBUS Bus Fault Status (BFAULTSTAT) Bus fault Bus error during instruction prefetch
BLSPE Bus Fault Status (BFAULTSTAT) Bus fault Bus error during lazy floating-point state
preservation
PRECISE Bus Fault Status (BFAULTSTAT) Bus fault Precise data bus error
IMPRE Bus Fault Status (BFAULTSTAT) Bus fault Imprecise data bus error
NOCP Usage Fault Status (UFAULTSTAT) Usage fault Attempt to access a coprocessor
UNDEF Usage Fault Status (UFAULTSTAT) Usage fault Undefined instruction
INVSTAT Usage Fault Status (UFAULTSTAT) Usage fault Attempt to enter an invalid instruction
set state
b
INVPC Usage Fault Status (UFAULTSTAT) Usage fault Invalid EXC_RETURN value
UNALIGN Usage Fault Status (UFAULTSTAT) Usage fault Illegal unaligned load or store
DIV0 Usage Fault Status (UFAULTSTAT) Usage fault Divide by 0
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction
with ICI continuation.
2.6.2 Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 159). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 162).
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Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in Exception Model on page 90.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
2.6.3 Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 102.
Table 2-12. Fault Status and Fault Address Registers
Register Description Address Register Name Status Register Name Handler
page 172 - Hard Fault Status (HFAULTSTAT) Hard fault
page 166
page 173
Memory Management Fault
Address (MMADDR)
Memory Management Fault Status
(MFAULTSTAT)
Memory management
fault
page 166
page 174
Bus Fault Address
(FAULTADDR)
Bus Fault Status (BFAULTSTAT) Bus fault
page 166 - Usage Fault Status (UFAULTSTAT) Usage fault
2.6.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
April 10, 2013 102
2.7 Power Management
The Cortex-M4F processor sleep modes reduce power consumption:
Sleep mode stops the processor clock.
Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 155). For more information about the behavior of the sleep modes, see System
Control on page 214.
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.
2.7.1 Entering Sleep Modes
This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.
2.7.1.1 Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see Wake Up from WFI or Sleep-on-Exit on page 104). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex-M3/M4 Instruction Set Technical User's Manual for more information.
2.7.1.2 Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex-M3/M4 Instruction Set Technical User's Manual for more information.
2.7.1.3 Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.
2.7.2 Wake Up from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep
mode.
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2.7.2.1 Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 74 and page 75.
2.7.2.2 Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 155.
2.8 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 104 lists the
supported instructions.
Note: In Table 2-13 on page 104:
Angle brackets, <>, enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the ARM Cortex-M4 Technical Reference Manual.
Table 2-13. Cortex-M4F Instruction Summary
Flags Brief Description Operands Mnemonic
N,Z,C,V Add with carry {Rd,} Rn, Op2 ADC, ADCS
N,Z,C,V Add {Rd,} Rn, Op2 ADD, ADDS
- Add {Rd,} Rn , #imm12 ADD, ADDW
- Load PC-relative address Rd, label ADR
N,Z,C Logical AND {Rd,} Rn, Op2 AND, ANDS
N,Z,C Arithmetic shift right Rd, Rm, <Rs|#n> ASR, ASRS
- Branch label B
- Bit field clear Rd, #lsb, #width BFC
- Bit field insert Rd, Rn, #lsb, #width BFI
N,Z,C Bit clear {Rd,} Rn, Op2 BIC, BICS
- Breakpoint #imm BKPT
- Branch with link label BL
- Branch indirect with link Rm BLX
- Branch indirect Rm BX
- Compare and branch if non-zero Rn, label CBNZ
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Table 2-13. Cortex-M4F Instruction Summary (continued)
- Compare and branch if zero Rn, label CBZ
- Clear exclusive - CLREX
- Count leading zeros Rd, Rm CLZ
N,Z,C,V Compare negative Rn, Op2 CMN
N,Z,C,V Compare Rn, Op2 CMP
- Change processor state, disable
interrupts
i CPSID
- Change processor state, enable
interrupts
i CPSIE
- Data memory barrier - DMB
- Data synchronization barrier - DSB
N,Z,C Exclusive OR {Rd,} Rn, Op2 EOR, EORS
- Instruction synchronization barrier - ISB
- If-Then condition block - IT
- Load multiple registers, increment after Rn{!}, reglist LDM
- Load multiple registers, decrement
before
Rn{!}, reglist LDMDB, LDMEA
- Load multiple registers, increment after Rn{!}, reglist LDMFD, LDMIA
- Load register with word Rt, [Rn, #offset] LDR
- Load register with byte Rt, [Rn, #offset] LDRB, LDRBT
- Load register with two bytes Rt, Rt2, [Rn, #offset] LDRD
- Load register exclusive Rt, [Rn, #offset] LDREX
- Load register exclusive with byte Rt, [Rn] LDREXB
- Load register exclusive with halfword Rt, [Rn] LDREXH
- Load register with halfword Rt, [Rn, #offset] LDRH, LDRHT
- Load register with signed byte Rt, [Rn, #offset] LDRSB, LDRSBT
- Load register with signed halfword Rt, [Rn, #offset] LDRSH, LDRSHT
- Load register with word Rt, [Rn, #offset] LDRT
N,Z,C Logical shift left Rd, Rm, <Rs|#n> LSL, LSLS
N,Z,C Logical shift right Rd, Rm, <Rs|#n> LSR, LSRS
- Multiply with accumulate, 32-bit result Rd, Rn, Rm, Ra MLA
- Multiply and subtract, 32-bit result Rd, Rn, Rm, Ra MLS
N,Z,C Move Rd, Op2 MOV, MOVS
N,Z,C Move 16-bit constant Rd, #imm16 MOV, MOVW
- Move top Rd, #imm16 MOVT
- Move from special register to general
register
Rd, spec_reg MRS
N,Z,C,V Move from general register to special
register
spec_reg, Rm MSR
N,Z Multiply, 32-bit result {Rd,} Rn, Rm MUL, MULS
N,Z,C Move NOT Rd, Op2 MVN, MVNS
- No operation - NOP
N,Z,C Logical OR NOT {Rd,} Rn, Op2 ORN, ORNS
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N,Z,C Logical OR {Rd,} Rn, Op2 ORR, ORRS
- Pack halfword {Rd,} Rn, Rm, Op2 PKHTB, PKHBT
- Pop registers from stack reglist POP
- Push registers onto stack reglist PUSH
Q Saturating add {Rd,} Rn, Rm QADD
- Saturating add 16 {Rd,} Rn, Rm QADD16
- Saturating add 8 {Rd,} Rn, Rm QADD8
- Saturating add and subtract with
exchange
{Rd,} Rn, Rm QASX
Q Saturating double and add {Rd,} Rn, Rm QDADD
Q Saturating double and subtract {Rd,} Rn, Rm QDSUB
- Saturating subtract and add with
exchange
{Rd,} Rn, Rm QSAX
Q Saturating subtract {Rd,} Rn, Rm QSUB
- Saturating subtract 16 {Rd,} Rn, Rm QSUB16
- Saturating subtract 8 {Rd,} Rn, Rm QSUB8
- Reverse bits Rd, Rn RBIT
- Reverse byte order in a word Rd, Rn REV
- Reverse byte order in each halfword Rd, Rn REV16
- Reverse byte order in bottom halfword
and sign extend
Rd, Rn REVSH
N,Z,C Rotate right Rd, Rm, <Rs|#n> ROR, RORS
N,Z,C Rotate right with extend Rd, Rm RRX, RRXS
N,Z,C,V Reverse subtract {Rd,} Rn, Op2 RSB, RSBS
GE Signed add 16 {Rd,} Rn, Rm SADD16
GE Signed add 8 {Rd,} Rn, Rm SADD8
GE Signed add and subtract with exchange {Rd,} Rn, Rm SASX
N,Z,C,V Subtract with carry {Rd,} Rn, Op2 SBC, SBCS
- Signed bit field extract Rd, Rn, #lsb, #width SBFX
- Signed divide {Rd,} Rn, Rm SDIV
- Select bytes {Rd,} Rn, Rm SEL
- Send event - SEV
- Signed halving add 16 {Rd,} Rn, Rm SHADD16
- Signed halving add 8 {Rd,} Rn, Rm SHADD8
- Signed halving add and subtract with
exchange
{Rd,} Rn, Rm SHASX
- Signed halving add and subtract with
exchange
{Rd,} Rn, Rm SHSAX
- Signed halving subtract 16 {Rd,} Rn, Rm SHSUB16
- Signed halving subtract 8 {Rd,} Rn, Rm SHSUB8
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Q Signed multiply accumulate long
(halfwords)
Rd, Rn, Rm, Ra SMLABB,
SMLABT,
SMLATB,
SMLATT
Q Signed multiply accumulate dual Rd, Rn, Rm, Ra SMLAD,
SMLADX
- Signed multiply with accumulate
(32x32+64), 64-bit result
RdLo, RdHi, Rn, Rm SMLAL
- Signed multiply accumulate long
(halfwords)
RdLo, RdHi, Rn, Rm SMLALBB,
SMLALBT,
SMLALTB,
SMLALTT
- Signed multiply accumulate long dual RdLo, RdHi, Rn, Rm SMLALD, SMLALDX
Q Signed multiply accumulate, word by
halfword
Rd, Rn, Rm, Ra SMLAWB,SMLAWT
Q Signed multiply subtract dual Rd, Rn, Rm, Ra SMLSD
SMLSDX
Signed multiply subtract long dual RdLo, RdHi, Rn, Rm SMLSLD
SMLSLDX
- Signed most significant word multiply
accumulate
Rd, Rn, Rm, Ra SMMLA
- Signed most significant word multiply
subtract
Rd, Rn, Rm, Ra SMMLS,
SMMLR
- Signed most significant word multiply {Rd,} Rn, Rm SMMUL,
SMMULR
Q Signed dual multiply add {Rd,} Rn, Rm SMUAD
SMUADX
- Signed multiply halfwords {Rd,} Rn, Rm SMULBB,
SMULBT,
SMULTB,
SMULTT
- Signed multiply (32x32), 64-bit result RdLo, RdHi, Rn, Rm SMULL
- Signed multiply by halfword {Rd,} Rn, Rm SMULWB,
SMULWT
- Signed dual multiply subtract {Rd,} Rn, Rm SMUSD,
SMUSDX
Q Signed saturate Rd, #n, Rm {,shift #s} SSAT
Q Signed saturate 16 Rd, #n, Rm SSAT16
GE Saturating subtract and add with
exchange
{Rd,} Rn, Rm SSAX
- Signed subtract 16 {Rd,} Rn, Rm SSUB16
- Signed subtract 8 {Rd,} Rn, Rm SSUB8
- Store multiple registers, increment after Rn{!}, reglist STM
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- Store multiple registers, decrement
before
Rn{!}, reglist STMDB, STMEA
- Store multiple registers, increment after Rn{!}, reglist STMFD, STMIA
- Store register word Rt, [Rn {, #offset}] STR
- Store register byte Rt, [Rn {, #offset}] STRB, STRBT
- Store register two words Rt, Rt2, [Rn {, #offset}] STRD
- Store register exclusive Rt, Rt, [Rn {, #offset}] STREX
- Store register exclusive byte Rd, Rt, [Rn] STREXB
- Store register exclusive halfword Rd, Rt, [Rn] STREXH
- Store register halfword Rt, [Rn {, #offset}] STRH, STRHT
- Store register signed byte Rt, [Rn {, #offset}] STRSB, STRSBT
- Store register signed halfword Rt, [Rn {, #offset}] STRSH, STRSHT
- Store register word Rt, [Rn {, #offset}] STRT
N,Z,C,V Subtract {Rd,} Rn, Op2 SUB, SUBS
N,Z,C,V Subtract 12-bit constant {Rd,} Rn, #imm12 SUB, SUBW
- Supervisor call #imm SVC
- Extend 8 bits to 32 and add {Rd,} Rn, Rm, {,ROR #} SXTAB
- Dual extend 8 bits to 16 and add {Rd,} Rn, Rm,{,ROR #} SXTAB16
- Extend 16 bits to 32 and add {Rd,} Rn, Rm,{,ROR #} SXTAH
- Signed extend byte 16 {Rd,} Rm {,ROR #n} SXTB16
- Sign extend a byte {Rd,} Rm {,ROR #n} SXTB
- Sign extend a halfword {Rd,} Rm {,ROR #n} SXTH
- Table branch byte [Rn, Rm] TBB
- Table branch halfword [Rn, Rm, LSL #1] TBH
N,Z,C Test equivalence Rn, Op2 TEQ
N,Z,C Test Rn, Op2 TST
GE Unsigned add 16 {Rd,} Rn, Rm UADD16
GE Unsigned add 8 {Rd,} Rn, Rm UADD8
GE Unsigned add and subtract with
exchange
{Rd,} Rn, Rm UASX
- Unsigned halving add 16 {Rd,} Rn, Rm UHADD16
- Unsigned halving add 8 {Rd,} Rn, Rm UHADD8
- Unsigned halving add and subtract with
exchange
{Rd,} Rn, Rm UHASX
- Unsigned halving subtract and add with
exchange
{Rd,} Rn, Rm UHSAX
- Unsigned halving subtract 16 {Rd,} Rn, Rm UHSUB16
- Unsigned halving subtract 8 {Rd,} Rn, Rm UHSUB8
- Unsigned bit field extract Rd, Rn, #lsb, #width UBFX
- Unsigned divide {Rd,} Rn, Rm UDIV
- Unsigned multiply accumulate
accumulate long (32x32+64), 64-bit
result
RdLo, RdHi, Rn, Rm UMAAL
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- Unsigned multiply with accumulate
(32x32+32+32), 64-bit result
RdLo, RdHi, Rn, Rm UMLAL
- Unsigned multiply (32x 2), 64-bit result RdLo, RdHi, Rn, Rm UMULL
- Unsigned Saturating Add 16 {Rd,} Rn, Rm UQADD16
- Unsigned Saturating Add 8 {Rd,} Rn, Rm UQADD8
- Unsigned Saturating Add and Subtract
with Exchange
{Rd,} Rn, Rm UQASX
- Unsigned Saturating Subtract and Add
with Exchange
{Rd,} Rn, Rm UQSAX
- Unsigned Saturating Subtract 16 {Rd,} Rn, Rm UQSUB16
- Unsigned Saturating Subtract 8 {Rd,} Rn, Rm UQSUB8
- Unsigned Sum of Absolute Differences {Rd,} Rn, Rm USAD8
- Unsigned Sum of Absolute Differences
and Accumulate
{Rd,} Rn, Rm, Ra USADA8
Q Unsigned Saturate Rd, #n, Rm {,shift #s} USAT
Q Unsigned Saturate 16 Rd, #n, Rm USAT16
GE Unsigned Subtract and add with
Exchange
{Rd,} Rn, Rm USAX
GE Unsigned Subtract 16 {Rd,} Rn, Rm USUB16
GE Unsigned Subtract 8 {Rd,} Rn, Rm USUB8
- Rotate, extend 8 bits to 32 and Add {Rd,} Rn, Rm, {,ROR #} UXTAB
- Rotate, dual extend 8 bits to 16 and Add {Rd,} Rn, Rm, {,ROR #} UXTAB16
- Rotate, unsigned extend and Add
Halfword
{Rd,} Rn, Rm, {,ROR #} UXTAH
- Zero extend a Byte {Rd,} Rm, {,ROR #n} UXTB
- Unsigned Extend Byte 16 {Rd,} Rm, {,ROR #n} UXTB16
- Zero extend a Halfword {Rd,} Rm, {,ROR #n} UXTH
- Floating-point Absolute Sd, Sm VABS.F32
- Floating-point Add {Sd,} Sn, Sm VADD.F32
FPSCR Compare two floating-point registers, or
one floating-point register and zero
Sd, <Sm | #0.0> VCMP.F32
FPSCR Compare two floating-point registers, or
one floating-point register and zero with
Invalid Operation check
Sd, <Sm | #0.0> VCMPE.F32
- Convert between floating-point and
integer
Sd, Sm VCVT.S32.F32
- Convert between floating-point and fixed
point
Sd, Sd, #fbits VCVT.S16.F32
- Convert between floating-point and
integer with rounding
Sd, Sm VCVTR.S32.F32
- Converts half-precision value to
single-precision
Sd, Sm VCVT<B|H>.F32.F16
- Converts single-precision register to
half-precision
Sd, Sm VCVTT<B|T>.F32.F16
- Floating-point Divide {Sd,} Sn, Sm VDIV.F32
- Floating-point Fused Multiply Accumulate {Sd,} Sn, Sm VFMA.F32
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- Floating-point Fused Negate Multiply
Accumulate
{Sd,} Sn, Sm VFNMA.F32
- Floating-point Fused Multiply Subtract {Sd,} Sn, Sm VFMS.F32
- Floating-point Fused Negate Multiply
Subtract
{Sd,} Sn, Sm VFNMS.F32
- Load Multiple extension registers Rn{!}, list VLDM.F<32|64>
- Load an extension register frommemory <Dd|Sd>, [Rn] VLDR.F<32|64>
- Floating-point Multiply Accumulate {Sd,} Sn, Sm VLMA.F32
- Floating-point Multiply Subtract {Sd,} Sn, Sm VLMS.F32
- Floating-point Move immediate Sd, #imm VMOV.F32
- Floating-point Move register Sd, Sm VMOV
- Copy ARM core register to single
precision
Sn, Rt VMOV
- Copy 2 ARM core registers to 2 single
precision
Sm, Sm1, Rt, Rt2 VMOV
- Copy ARM core register to scalar Dd[x], Rt VMOV
- Copy scalar to ARM core register Rt, Dn[x] VMOV
N,Z,C,V Move FPSCR to ARM core register or
APSR
Rt, FPSCR VMRS
FPSCR Move to FPSCRfromARMCore register FPSCR, Rt VMSR
- Floating-point Multiply {Sd,} Sn, Sm VMUL.F32
- Floating-point Negate Sd, Sm VNEG.F32
- Floating-point Multiply and Add {Sd,} Sn, Sm VNMLA.F32
- Floating-point Multiply and Subtract {Sd,} Sn, Sm VNMLS.F32
- Floating-point Multiply {Sd,} Sn, Sm VNMUL
- Pop extension registers list VPOP
- Push extension registers list VPUSH
- Calculates floating-point Square Root Sd, Sm VSQRT.F32
- Floating-point register Store Multiple Rn{!}, list VSTM
- Stores an extension register to memory Sd, [Rn] VSTR.F3<32|64>
- Floating-point Subtract {Sd,} Sn, Sm VSUB.F<32|64>
- Wait for event - WFE
- Wait for interrupt - WFI
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3 Cortex-M4 Peripherals
This chapter provides information on the TivaCSeries implementation of the Cortex-M4 processor
peripherals, including:
SysTick (see page 112)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
Nested Vectored Interrupt Controller (NVIC) (see page 113)
Facilitates low-latency exception and interrupt handling
Controls power management
Implements system control registers
System Control Block (SCB) (see page 114)
Provides systemimplementation information and systemcontrol, including configuration, control,
and reporting of system exceptions.
Memory Protection Unit (MPU) (see page 114)
Supports the standard ARMv7 Protected Memory SystemArchitecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
Floating-Point Unit (FPU) (see page 119)
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square root operations. It also provides conversions between fixed-point and floating-point data
Table 3-1 on page 111 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Description (see page ...) Core Peripheral Address
112 System Timer 0xE000.E010-0xE000.E01F
113 Nested Vectored Interrupt Controller 0xE000.E100-0xE000.E4EF
0xE000.EF00-0xE000.EF03
114 System Control Block 0xE000.E008-0xE000.E00F
0xE000.ED00-0xE000.ED3F
114 Memory Protection Unit 0xE000.ED90-0xE000.EDB8
119 Floating Point Unit 0xE000.EF30-0xE000.EF44
3.1 Functional Description
This chapter provides information on the TivaCSeries implementation of the Cortex-M4 processor
peripherals: SysTick, NVIC, SCB and MPU.
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3.1.1 System Timer (SysTick)
Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
A high-speed alarm timer using the system clock.
A variable rate alarm or signal timerthe duration is range-dependent on the reference clock
used and the dynamic range of the counter.
A simple counter used to measure time to completion and time used.
An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.
SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on either the system clock or the precision internal oscillator (PIOSC)
divided by 4. If this clock signal is stopped for low power mode, the SysTick counter stops. SysTick
can be kept running during Deep-sleep mode by setting the CLK_SRC bit in the SysTick Control
and Status Register (STCTRL) register and ensuring that the PIOSCPD bit in the Deep Sleep
Clock Configuration (DSLPCLKCFG) register is clear. Ensure software uses aligned word accesses
to access the SysTick registers.
The SysTick counter reload and current value are undefined at reset; the correct initialization
sequence for the SysTick counter is:
1. Program the value in the STRELOAD register.
2. Clear the STCURRENT register by writing to it with any value.
3. Configure the STCTRL register for the required operation.
Note: When the processor is halted for debugging, the counter does not decrement.
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Cortex-M4 Peripherals
3.1.2 Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
79 interrupts.
A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
Low-latency exception and interrupt handling.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non-maskable interrupt (NMI).
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
3.1.2.1 Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see Hardware and Software Control of Interrupts on page 113 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.1.2.2 Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
The NVIC detects that the interrupt signal is High and the interrupt is not active.
The NVIC detects a rising edge on the interrupt signal.
Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 135 or SWTRIG on page 145.
A pending interrupt remains pending until one of the following:
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The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.
For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
Software writes to the corresponding interrupt clear-pending register bit
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
3.1.3 System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.1.4 Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPUsupports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPUregion setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see Memory Regions, Types and
Attributes on page 84 for more information).
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Table 3-2 on page 115 shows the possible MPU region attributes. See the section called MPU
Configuration for a Tiva C Series Microcontroller on page 119 for guidelines for programming a
microcontroller implementation.
Table 3-2. Memory Attributes Summary
Description Memory Type
All accesses to Strongly Ordered memory occur in program order. Strongly Ordered
Memory-mapped peripherals Device
Normal memory Normal
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.
The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPUhas previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.
3.1.4.1 Updating an MPU Region
To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.
Updating an MPU Region Using Separate Words
This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute
Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
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BIC R2, R2, #1 ; Disable
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
Software must use memory barrier instructions:
Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.
After MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.
Updating an MPU Region Using Multi-Word Writes
The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region number, address, attribute, size and enable
This operation can be done in two words for pre-packed information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 179) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:
April 10, 2013 116
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 181) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.
Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 117 shows.
Figure 3-1. SRD Use Example
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
Base address of both regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
3.1.4.2 MPU Access Permission Attributes
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 117 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M4 does
not support the concept of cacheability or shareability. Refer to the section called MPUConfiguration
for a Tiva C Series Microcontroller on page 119 for information on programming the MPU for
TM4C123AH6PM implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
Other Attributes Shareability Memory Type B C S TEX
- Shareable Strongly Ordered 0 0 x
a
000b
- Shareable Device 1 0 x
a
000
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Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)
Other Attributes Shareability Memory Type B C S TEX
Outer and inner
write-through. No write
allocate.
Not shareable Normal 0 1 0 000
Shareable Normal 0 1 1 000
Outer and inner
noncacheable.
- - Reserved encoding 1 0 x
a
001
a
001
Outer and inner
write-back. Write and
read allocate.
Nonshared Device. Not shareable Device 0 0 x
a
010
a
010
- - Reserved encoding x
a
1 x
a
010
Cached memory (BB =
outer policy, AA = inner
policy).
See Table 3-4 for the
encoding of the AA and
BB bits.
Not shareable Normal A A 0 1BB
Shareable Normal A A 1 1BB
a. The MPU ignores the value of this bit.
Table 3-4 on page 118 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.
Table 3-4. Cache Policy for Memory Attribute Encoding
Corresponding Cache Policy Encoding, AA or BB
Non-cacheable 00
Write back, write and read allocate 01
Write through, no write allocate 10
Write back, no write allocate 11
Table 3-5 on page 118 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
Description Unprivileged
Permissions
Privileged
Permissions
AP Bit Field
All accesses generate a permission fault. No access No access 000
Access from privileged software only. No access R/W 001
Writes by unprivileged software generate a
permission fault.
RO R/W 010
Full access. R/W R/W 011
Reserved. Unpredictable Unpredictable 100
Reads by privileged software only. No access RO 101
April 10, 2013 118
Table 3-5. AP Bit Field Encoding (continued)
Description Unprivileged
Permissions
Privileged
Permissions
AP Bit Field
Read-only, by privileged or unprivileged software. RO RO 110
Read-only, by privileged or unprivileged software. RO RO 111
MPU Configuration for a Tiva C Series Microcontroller
Tiva C Series microcontrollers have only a single processor and no caches. As a result, the MPU
should be programmed as shown in Table 3-6 on page 119.
Table 3-6. Memory Region Attributes for Tiva C Series Microcontrollers
Memory Type and Attributes B C S TEX Memory Region
Normal memory, non-shareable, write-through 0 1 0 000b Flash memory
Normal memory, shareable, write-through 0 1 1 000b Internal SRAM
Normal memory, shareable, write-back,
write-allocate
1 1 1 000b External SRAM
Device memory, shareable 1 0 1 000b Peripherals
In current Tiva C Series microcontroller implementations, the shareability and cache policy
attributes do not affect the system behavior. However, using these settings for the MPU regions
can make the application code more portable. The values given are for typical situations.
3.1.4.3 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see Exceptions and Interrupts on page 81 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 166 for more information.
3.1.5 Floating-Point Unit (FPU)
This section describes the Floating-Point Unit (FPU) and the registers it uses. The FPU provides:
32-bit instructions for single-precision (C float) data-processing operations
Combined multiply and accumulate instructions for increased precision (Fused MAC)
Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
Hardware support for denormals and all IEEE rounding modes
32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
Decoupled three stage pipeline
The Cortex-M4F FPU fully supports single-precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between fixed-point and
floating-point data formats, and floating-point constant instructions. The FPU provides floating-point
computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for
Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU's single-precision
extension registers can also be accessed as 16 doubleword registers for load, store, and move
operations.
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3.1.5.1 FPU Views of the Register Bank
The FPU provides an extension register file containing 32 single-precision registers. These can be
viewed as:
Sixteen 64-bit doubleword registers, D0-D15
Thirty-two 32-bit single-word registers, S0-S31
A combination of registers from the above views
Figure 3-2. FPU Register Bank
...
D0
D1
D2
D3
D14
D15
S0
S1
S2
S3
S4
S5
S6
S7
S28
S29
S30
S31
...
The mapping between the registers is as follows:
S<2n> maps to the least significant half of D<n>
S<2n+1> maps to the most significant half of D<n>
For example, you can access the least significant half of the value in D6 by accessing S12, and the
most significant half of the elements by accessing S13.
3.1.5.2 Modes of Operation
The FPU provides three modes of operation to accommodate a variety of applications.
Full-Compliance mode. In Full-Compliance mode, the FPU processes all operations according to
the IEEE 754 standard in hardware.
Flush-to-Zero mode. Setting the FZ bit of the Floating-Point Status and Control (FPSC) register
enables Flush-to-Zero mode. In this mode, the FPUtreats all subnormal input operands of arithmetic
CDP operations as zeros in the operation. Exceptions that result from a zero operand are signalled
appropriately. VABS, VNEG, and VMOV are not considered arithmetic CDP operations and are not
affected by Flush-to-Zero mode. A result that is tiny, as described in the IEEE 754 standard, where
the destination precision is smaller in magnitude than the minimum normal value before rounding,
is replaced with a zero. The IDC bit in FPSC indicates when an input flush occurs. The UFC bit in
FPSC indicates when a result flush occurs.
Default NaNmode. Setting the DN bit in the FPSCregister enables default NaNmode. In this mode,
the result of any arithmetic data processing operation that involves an input NaN, or that generates
a NaN result, returns the default NaN. Propagation of the fraction bits is maintained only by VABS,
April 10, 2013 120
VNEG, and VMOV operations. All other CDP operations ignore any information in the fraction bits
of an input NaN.
3.1.5.3 Compliance with the IEEE 754 standard
When Default NaN(DN) and Flush-to-Zero (FZ) modes are disabled, FPv4 functionality is compliant
with the IEEE 754 standard in hardware. No support code is required to achieve this compliance.
3.1.5.4 Complete Implementation of the IEEE 754 standard
The Cortex-M4F floating point instruction set does not support all operations defined in the IEEE
754-2008 standard. Unsupported operations include, but are not limited to the following:
Remainder
Round floating-point number to integer-valued floating-point number
Binary-to-decimal conversions
Decimal-to-binary conversions
Direct comparison of single-precision and double-precision values
The Cortex-M4 FPUsupports fused MACoperations as described in the IEEEstandard. For complete
implementation of the IEEE 754-2008 standard, floating-point functionality must be augmented with
library functions.
3.1.5.5 IEEE 754 standard implementation choices
NaN handling
All single-precision values with the maximum exponent field value and a nonzero fraction field are
valid NaNs. A most-significant fraction bit of zero indicates a Signaling NaN(SNaN). A one indicates
a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. The
below table shows the default NaN values.
Fraction Fraction Sign
bit [22] = 1, bits [21:0] are all zeros 0xFF 0
Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows:
In full-compliance mode, NaNs are handled as described in the ARM Architecture Reference
Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For data
transfer operations, NaNs are transferred without raising the Invalid Operation exception. For
the non-arithmetic CDP instructions, VABS, VNEG, and VMOV, NaNs are copied, with a change
of sign if specified in the instructions, without causing the Invalid Operation exception.
In default NaN mode, arithmetic CDP instructions involving NaN operands return the default
NaN regardless of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation
set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions
is the same as in full-compliance mode.
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Table 3-7. QNaN and SNaN Handling
With SNaN Operand With QNaN Operand Default NaN
Mode
Instruction Type
IOC
a
set. The SNaN is quieted and the
result NaN is determined by the rules
given in the ARM Architecture Reference
Manual.
The QNaN or one of the QNaN operands,
if there is more than one, is returned
according to the rules given in the ARM
Architecture Reference Manual.
Off
Arithmetic CDP
IOCa set. Default NaN returns. Default NaN returns. On
NaN passes to destination with sign changed as appropriate. Off/On Non-arithmetic CDP
IOC set. Unordered compare. Unordered compare. - FCMP(Z)
IOC set. Unordered compare. IOC set. Unordered compare. - FCMPE(Z)
All NaNs transferred. Off/On Load/store
a. IOC is the Invalid Operation exception flag, FPSCR[0].
Comparisons
Comparison results modify the flags in the FPSCR. You can use the MVRS APSR_nzcv instruction
(formerly FMSTAT) to transfer the current flags from the FPSCR to the APSR. See the ARM
Architecture Reference Manual for mapping of IEEE754-2008 standard predicates to ARMconditions.
The flags used are chosen so that subsequent conditional execution of ARM instructions can test
the predicates defined in the IEEE standard.
Underflow
The Cortex-M4F FPU uses the before rounding form of tininess and the inexact result form of loss
of accuracy as described in the IEEE 754-2008 standard to generate Underflow exceptions.
In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE standard, are
flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual
for information on flush-to-zero mode.
When the FPU is not in flush-to-zero mode, operations are performed on subnormal operands. If
the operation does not produce a tiny result, it returns the computed result, and the UFC flag,
FPSCR[3], is not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation
produces a tiny result, the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set
if the result was also inexact.
3.1.5.6 Exceptions
The FPU sets the cumulative exception status flag in the FPSCR register as required for each
instruction, in accordance with the FPv4 architecture. The FPU does not support user-mode traps.
The exception enable bits in the FPSCR read-as-zero, and writes are ignored. The processor also
has six output pins, FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect the
status of one of the cumulative exception flags. For a description of these outputs, see the ARM
Cortex-M4 Integration and Implementation Manual (ARM DII 0239, available from ARM).
The processor can reduce the exception latency by using lazy stacking. See Auxiliary Control
Register, ACTLR on page 4-5. This means that the processor reserves space on the stack for the
FP state, but does not save that state information to the stack. See the ARMv7-M Architecture
Reference Manual (available from ARM) for more information.
3.1.5.7 Enabling the FPU
The FPUis disabled fromreset. You must enable it before you can use any floating-point instructions.
The processor must be in privileged mode to read from and write to the Coprocessor Access
April 10, 2013 122
Control (CPAC) register. The below example code sequence enables the FPU in both privileged
and user modes.
; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
STR R1, [R0]; wait for store to complete
DSB
;reset pipeline now the FPU is enabled
ISB
3.2 Register Map
Table 3-8 on page 123 lists the Cortex-M4 Peripheral SysTick, NVIC, MPU, FPU and SCB registers.
The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-8. Peripherals Register Map
See
page
System Timer (SysTick) Registers
127 SysTick Control and Status Register 0x0000.0004 R/W STCTRL 0x010
129 SysTick Reload Value Register - R/W STRELOAD 0x014
130 SysTick Current Value Register - R/WC STCURRENT 0x018
Nested Vectored Interrupt Controller (NVIC) Registers
131 Interrupt 0-31 Set Enable 0x0000.0000 R/W EN0 0x100
131 Interrupt 96-127 Set Enable 0x0000.0000 R/W EN3 0x10C
133 Interrupt 0-31 Clear Enable 0x0000.0000 R/W DIS0 0x180
133 Interrupt 96-127 Clear Enable 0x0000.0000 R/W DIS3 0x18C
135 Interrupt 0-31 Set Pending 0x0000.0000 R/W PEND0 0x200
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Table 3-8. Peripherals Register Map (continued)
See
page
135 Interrupt 96-127 Set Pending 0x0000.0000 R/W PEND3 0x20C
137 Interrupt 0-31 Clear Pending 0x0000.0000 R/W UNPEND0 0x280
137 Interrupt 96-127 Clear Pending 0x0000.0000 R/W UNPEND3 0x28C
139 Interrupt 0-31 Active Bit 0x0000.0000 RO ACTIVE0 0x300
139 Interrupt 96-127 Active Bit 0x0000.0000 RO ACTIVE3 0x30C
141 Interrupt 0-3 Priority 0x0000.0000 R/W PRI0 0x400
141 Interrupt 12-15 Priority 0x0000.0000 R/W PRI3 0x40C
April 10, 2013 124
See
page
145 Software Trigger Interrupt 0x0000.0000 WO SWTRIG 0xF00
System Control Block (SCB) Registers
146 Auxiliary Control 0x0000.0000 R/W ACTLR 0x008
148 CPU ID Base 0x410F.C241 RO CPUID 0xD00
149 Interrupt Control and State 0x0000.0000 R/W INTCTRL 0xD04
152 Vector Table Offset 0x0000.0000 R/W VTABLE 0xD08
153 Application Interrupt and Reset Control 0xFA05.0000 R/W APINT 0xD0C
155 System Control 0x0000.0000 R/W SYSCTRL 0xD10
157 Configuration and Control 0x0000.0200 R/W CFGCTRL 0xD14
159 System Handler Priority 1 0x0000.0000 R/W SYSPRI1 0xD18
160 System Handler Priority 2 0x0000.0000 R/W SYSPRI2 0xD1C
161 System Handler Priority 3 0x0000.0000 R/W SYSPRI3 0xD20
162 System Handler Control and State 0x0000.0000 R/W SYSHNDCTRL 0xD24
166 Configurable Fault Status 0x0000.0000 R/W1C FAULTSTAT 0xD28
172 Hard Fault Status 0x0000.0000 R/W1C HFAULTSTAT 0xD2C
173 Memory Management Fault Address - R/W MMADDR 0xD34
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See
page
174 Bus Fault Address - R/W FAULTADDR 0xD38
Memory Protection Unit (MPU) Registers
175 MPU Type 0x0000.0800 RO MPUTYPE 0xD90
176 MPU Control 0x0000.0000 R/W MPUCTRL 0xD94
178 MPU Region Number 0x0000.0000 R/W MPUNUMBER 0xD98
179 MPU Region Base Address 0x0000.0000 R/W MPUBASE 0xD9C
181 MPU Region Attribute and Size 0x0000.0000 R/W MPUATTR 0xDA0
179 MPU Region Base Address Alias 1 0x0000.0000 R/W MPUBASE1 0xDA4
181 MPU Region Attribute and Size Alias 1 0x0000.0000 R/W MPUATTR1 0xDA8
179 MPU Region Base Address Alias 2 0x0000.0000 R/W MPUBASE2 0xDAC
181 MPU Region Attribute and Size Alias 2 0x0000.0000 R/W MPUATTR2 0xDB0
179 MPU Region Base Address Alias 3 0x0000.0000 R/W MPUBASE3 0xDB4
181 MPU Region Attribute and Size Alias 3 0x0000.0000 R/W MPUATTR3 0xDB8
Floating-Point Unit (FPU) Registers
184 Coprocessor Access Control 0x0000.0000 R/W CPAC 0xD88
185 Floating-Point Context Control 0xC000.0000 R/W FPCC 0xF34
187 Floating-Point Context Address - R/W FPCA 0xF38
188 Floating-Point Default Status Control 0x0000.0000 R/W FPDSC 0xF3C
3.3 System Timer (SysTick) Register Descriptions
This section lists and describes the System Timer registers, in numerical order by address offset.
April 10, 2013 126
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010
Note: This register can only be accessed from privileged mode.
The SysTick STCTRL register enables the SysTick features.
SysTick Control and Status Register (STCTRL)
Base 0xE000.E000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
COUNT reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ENABLE INTEN CLK_SRC reserved
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Count Flag
Description Value
The SysTick timer has not counted to 0 since the last time
this bit was read.
0
The SysTick timer has counted to 0 since the last time
this bit was read.
1
This bit is cleared by a read of the register or if the STCURRENT register
is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise,
the COUNT bit is not changed by the debugger read. See the ARM
Debug Interface V5 Architecture Specification for more information on
MasterType.
0 RO COUNT 16
Clock Source
Description Value
Precision internal oscillator (PIOSC) divided by 4 0
System clock 1
1 R/W CLK_SRC 2
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Interrupt Enable
Description Value
Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached 0.
0
An interrupt is generated to the NVICwhen SysTick counts
to 0.
1
0 R/W INTEN 1
Enable
Description Value
The counter is disabled. 0
Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down.
On reaching 0, the COUNT bit is set and an interrupt is
generated if enabled by INTEN. The counter then loads the
RELOAD value again and begins counting.
1
0 R/W ENABLE 0
April 10, 2013 128
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014
The STRELOAD register specifies the start value to load into the SysTick Current Value
(STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and
0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the
COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
Note that in order to access this register correctly, the system clock must be faster than 8 MHz.
SysTick Reload Value Register (STRELOAD)
Base 0xE000.E000
Offset 0x014
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RELOAD reserved
R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RELOAD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Reload Value
Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.
0x00.0000 R/W RELOAD 23:0
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Register 3: SysTick Current Value Register (STCURRENT), offset 0x018
The STCURRENT register contains the current value of the SysTick counter.
SysTick Current Value Register (STCURRENT)
Base 0xE000.E000
Offset 0x018
Type R/WC, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CURRENT reserved
R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CURRENT
R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.
0x00.0000 R/WC CURRENT 23:0
3.4 NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 152.
April 10, 2013 130
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100
Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C
The ENn registers enable interrupts and showwhich interrupts are enabled. Bit 0 of EN0 corresponds
to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31
corresponds to Interrupt 63. Bit 0 of EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt
95. Bit 0 of EN3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of EN4 (see
page 132) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138.
See Table 2-9 on page 93 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 0-31 Set Enable (EN0)
Base 0xE000.E000
Offset 0x100
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Enable
Description Value
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
1
A bit can only be cleared by setting the corresponding INT[n] bit in
the DISn register.
0x0000.0000 R/W INT 31:0
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The EN4 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 93 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 128-138 Set Enable (EN4)
Base 0xE000.E000
Offset 0x110
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT reserved
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0000.000 RO reserved 31:11
Interrupt Enable
Description Value
0
On a write, enables the interrupt.
1
the DIS4 register.
0x0 R/W INT 10:0
April 10, 2013 132
Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C
The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds
to Interrupt 31. Bit 0 of DIS1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of
DIS2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of DIS3 corresponds to
Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of DIS4 (see page 134) corresponds to Interrupt
128; bit 10 corresponds to Interrupt 138.
Interrupt 0-31 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Disable
Description Value
0
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
1
0x0000.0000 R/W INT 31:0
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The DIS4 register disables interrupts. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to
Interrupt 138. See Table 2-9 on page 93 for interrupt assignments.
Interrupt 128-138 Clear Enable (DIS4)
Base 0xE000.E000
Offset 0x190
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0000.000 RO reserved 31:11
Interrupt Disable
Description Value
0
On a write, clears the corresponding INT[n] bit in the EN4
register, disabling interrupt [n].
1
0x0 R/W INT 10:0
April 10, 2013 134
Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200
Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C
The PENDn registers force interrupts into the pending state and show which interrupts are pending.
Bit 0 of PEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of PEND1
corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of PEND2 corresponds to
Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of PEND3 corresponds to Interrupt 96; bit 31
corresponds to Interrupt 127. Bit 0 of PEND4 (see page 136) corresponds to Interrupt 128; bit 10
corresponds to Interrupt 138.
Interrupt 0-31 Set Pending (PEND0)
Base 0xE000.E000
Offset 0x200
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Set Pending
Description Value
On a read, indicates that the interrupt is not pending.
0
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
1
If the corresponding interrupt is already pending, setting a bit has no
effect.
the UNPEND0 register.
0x0000.0000 R/W INT 31:0
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The PEND4 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 93
for interrupt assignments.
Interrupt 128-138 Set Pending (PEND4)
Base 0xE000.E000
Offset 0x210
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0000.000 RO reserved 31:11
Interrupt Set Pending
Description Value
0
On a write, the corresponding interrupt is set to pending
even if it is disabled.
1
If the corresponding interrupt is already pending, setting a bit has no
effect.
the UNPEND4 register.
0x0 R/W INT 10:0
April 10, 2013 136
Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
Register 22: Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C
The UNPENDn registers show which interrupts are pending and remove the pending state from
interrupts. Bit 0 of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of
UNPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2
corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to
Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of UNPEND4 (see page 138) corresponds to
Interrupt 128; bit 10 corresponds to Interrupt 138.
Interrupt 0-31 Clear Pending (UNPEND0)
Base 0xE000.E000
Offset 0x280
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Clear Pending
Description Value
0
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
1
0x0000.0000 R/W INT 31:0
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The UNPEND4 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table
2-9 on page 93 for interrupt assignments.
Interrupt 128-138 Clear Pending (UNPEND4)
Base 0xE000.E000
Offset 0x290
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0000.000 RO reserved 31:11
Interrupt Clear Pending
Description Value
0
On a write, clears the corresponding INT[n] bit in the PEND4
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
1
0x0 R/W INT 10:0
April 10, 2013 138
Register 24: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300
Register 27: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C
The UNPENDn registers indicate which interrupts are active. Bit 0 of ACTIVE0 corresponds to
Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of ACTIVE1 corresponds to Interrupt 32; bit 31
corresponds to Interrupt 63. Bit 0 of ACTIVE2 corresponds to Interrupt 64; bit 31 corresponds to
Interrupt 95. Bit 0 of ACTIVE3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit
0 of ACTIVE4 (see page 140) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138.
Caution Do not manually set or clear the bits in this register.
Interrupt 0-31 Active Bit (ACTIVE0)
Base 0xE000.E000
Offset 0x300
Type RO, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Active
Description Value
The corresponding interrupt is not active. 0
The corresponding interrupt is active, or active and pending. 1
0x0000.0000 RO INT 31:0
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The ACTIVE4 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 128; bit
10 corresponds to Interrupt 131. See Table 2-9 on page 93 for interrupt assignments.
Caution Do not manually set or clear the bits in this register.
Interrupt 128-138 Active Bit (ACTIVE4)
Base 0xE000.E000
Offset 0x310
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0000.000 RO reserved 31:11
Interrupt Active
Description Value
The corresponding interrupt is not active. 0
The corresponding interrupt is active, or active and pending. 1
0x0 RO INT 10:0
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Register 29: Interrupt 0-3 Priority (PRI0), offset 0x400
Register 32: Interrupt 12-15 Priority (PRI3), offset 0x40C
The PRIn registers (see also page 143) provide 3-bit priority fields for each interrupt. These registers
are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows:
Interrupt PRIn Register Bit Field
Interrupt [4n+3] Bits 31:29
Interrupt [4n] Bits 7:5
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 153) indicates the
position of the binary point that splits the priority and subpriority fields.
These registers can only be accessed from privileged mode.
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Interrupt 0-3 Priority (PRI0)
Base 0xE000.E000
Offset 0x400
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved INTC reserved INTD
RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved INTA reserved INTB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
0x0 R/W INTD 31:29
0x0 R/W INTC 23:21
0x0 R/W INTB 15:13
Interrupt Priority for Interrupt [4n]
[4n], where n is the number of the Interrupt Priority register (n=0 for
0x0 R/W INTA 7:5
0x0 RO reserved 4:0
April 10, 2013 142
The PRIn registers (see also page 141) provide 3-bit priority fields for each interrupt. These registers
are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows:
Interrupt PRIn Register Bit Field
Interrupt [4n] Bits 7:5
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 153) indicates the
position of the binary point that splits the priority and subpriority fields .
These registers can only be accessed from privileged mode.
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Interrupt 64-67 Priority (PRI16)
Base 0xE000.E000
Offset 0x440
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved INTC reserved INTD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved INTA reserved INTB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0 R/W INTD 31:29
0x0 R/W INTC 23:21
0x0 R/W INTB 15:13
Interrupt Priority for Interrupt [4n]
[4n], where n is the number of the Interrupt Priority register (n=0 for
0x0 R/W INTA 7:5
0x0 RO reserved 4:0
April 10, 2013 144
Register 64: Software Trigger Interrupt (SWTRIG), offset 0xF00
Note: Only privileged software can enable unprivileged access to the SWTRIG register.
Writing an interrupt number to the SWTRIGregister generates a Software Generated Interrupt (SGI).
When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 157) is
set, unprivileged software can access the SWTRIG register.
Software Trigger Interrupt (SWTRIG)
Base 0xE000.E000
Offset 0xF00
Type WO, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTID reserved
WO WO WO WO WO WO WO WO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt ID
This field holds the interrupt IDof the required SGI. For example, a value
of 0x3 generates an interrupt on IRQ3.
0x00 WO INTID 7:0
3.5 System Control Block (SCB) Register Descriptions
This section lists and describes the System Control Block (SCB) registers, in numerical order by
address offset. The SCB registers can only be accessed from privileged mode.
All registers must be accessed with aligned word accesses except for the FAULTSTAT and
SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to system control block registers.
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Register 65: Auxiliary Control (ACTLR), offset 0x008
The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default
memory map, and interruption of multi-cycle instructions. By default, this register is set to provide
optimum performance from the Cortex-M4 processor and does not normally require modification.
Auxiliary Control (ACTLR)
Base 0xE000.E000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DISMCYC DISWBUF DISFOLD reserved DISFPCA DISOOFP reserved
R/W R/W R/W RO RO RO RO RO R/W R/W RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Disable Out-Of-Order Floating Point
Disables floating-point instructions completing out of order with respect
to integer instructions.
0 R/W DISOOFP 9
Disable CONTROL.FPCA
Disable automatic update of the FPCA bit in the CONTROL register.
Important:
(ACTLR) register.
0 R/W DISFPCA 8
Disable IT Folding
Description Value
No effect. 0
Disables IT folding. 1
In some situations, the processor can start executing the first instruction
in an IT block while it is still executing the IT instruction. This behavior
is called IT folding, and improves performance, However, IT folding can
cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit
before executing the task, to disable IT folding.
0 R/W DISFOLD 2
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Disable Write Buffer
Description Value
No effect. 0
Disables write buffer use during default memory map accesses.
In this situation, all bus faults are precise bus faults but
performance is decreased because any store to memory must
complete before the processor can execute the next instruction.
1
Note: This bit only affects write buffers implemented in the
Cortex-M4 processor.
0 R/W DISWBUF 1
Disable Interrupts of Multiple Cycle Instructions
Description Value
No effect. 0
Disables interruption of load multiple and store multiple
instructions. In this situation, the interrupt latency of the
processor is increased because any LDM or STM must complete
before the processor can stack the current state and enter the
interrupt handler.
1
0 R/W DISMCYC 0
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Register 66: CPU ID Base (CPUID), offset 0xD00
The CPUID register contains the ARM Cortex-M4 processor part number, version, and
implementation information.
CPU ID Base (CPUID)
Base 0xE000.E000
Offset 0xD00
Type RO, reset 0x410F.C241
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CON VAR IMP
1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
REV PARTNO
1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 Reset
Implementer Code
Description Value
ARM 0x41
0x41 RO IMP 31:24
Variant Number
Description Value
The rn value in the rnpn product revision identifier, for example,
the 0 in r0p0.
0x0
0x0 RO VAR 23:20
Constant
Description Value
Always reads as 0xF. 0xF
0xF RO CON 19:16
Part Number
Description Value
Cortex-M4 processor. 0xC24
0xC24 RO PARTNO 15:4
Revision Number
Description Value
The pn value in the rnpn product revision identifier, for example,
the 1 in r0p1.
0x1
0x1 RO REV 3:0
April 10, 2013 148
Register 67: Interrupt Control and State (INTCTRL), offset 0xD04
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.
Interrupt Control and State (INTCTRL)
Base 0xE000.E000
Offset 0xD04
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VECPEND reserved ISRPEND ISRPRE reserved PENDSTCLR PENDSTSET UNPENDSV PENDSV reserved NMISET
RO RO RO RO RO RO RO RO RO WO R/W WO R/W RO RO R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VECACT reserved RETBASE VECPEND
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
NMI Set Pending
Description Value
On a read, indicates an NMI exception is not pending.
0
On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.
1
Because NMI is the highest-priority exception, normally the processor
enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
0 R/W NMISET 31
PendSV Set Pending
Description Value
On a read, indicates a PendSV exception is not pending.
0
On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.
1
Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.
0 R/W PENDSV 28
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PendSV Clear Pending
Description Value
On a write, no effect. 0
On a write, removes the pending state from the PendSV
exception.
1
This bit is write only; on a register read, its value is unknown.
0 WO UNPENDSV 27
SysTick Set Pending
Description Value
On a read, indicates a SysTick exception is not pending.
0
On a read, indicates a SysTick exception is pending.
On a write, changes the SysTick exception state to pending.
1
This bit is cleared by writing a 1 to the PENDSTCLR bit.
0 R/W PENDSTSET 26
SysTick Clear Pending
Description Value
On a write, no effect. 0
On a write, removes the pending state from the SysTick
exception.
1
This bit is write only; on a register read, its value is unknown.
0 WO PENDSTCLR 25
0 RO reserved 24
Debug Interrupt Handling
Description Value
The release from halt does not take an interrupt. 0
The release from halt takes an interrupt. 1
This bit is only meaningful in Debug mode and reads as zero when the
processor is not in Debug mode.
0 RO ISRPRE 23
Interrupt Pending
Description Value
No interrupt is pending. 0
An interrupt is pending. 1
This bit provides status for all interrupts excluding NMI and Faults.
0 RO ISRPEND 22
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Interrupt Pending Vector Number
This field contains the exception number of the highest priority pending
enabled exception. The value indicated by this field includes the effect
of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
Description Value
No exceptions are pending 0x00
Reserved 0x01
NMI 0x02
Hard fault 0x03
Memory management fault 0x04
Bus fault 0x05
Usage fault 0x06
Reserved 0x07-0x0A
SVCall 0x0B
Reserved for Debug 0x0C
Reserved 0x0D
PendSV 0x0E
SysTick 0x0F
... ...
Interrupt Vector 138 0x9A
0x00 RO VECPEND 19:12
Return to Base
Description Value
There are preempted active exceptions to execute. 0
There are no active exceptions, or the currently executing
exception is the only active exception.
1
This bit provides status for all interrupts excluding NMI and Faults. This
bit only has meaning if the processor is currently executing an ISR (the
Interrupt Program Status (IPSR) register is non-zero).
0 RO RETBASE 11
Interrupt Pending Vector Number
This field contains the active exception number. The exception numbers
can be found in the description for the VECPEND field. If this field is clear,
the processor is in Thread mode. This field contains the same value as
the ISRNUM field in the IPSR register.
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn),
Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn),
and Interrupt Priority (PRIn) registers (see page 70).
0x00 RO VECACT 7:0
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Register 68: Vector Table Offset (VTABLE), offset 0xD08
The VTABLE register indicates the offset of the vector table base address from memory address
0x0000.0000.
Vector Table Offset (VTABLE)
Base 0xE000.E000
Offset 0xD08
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
OFFSET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved OFFSET
RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Vector Table Offset
When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 138
interrupts, the offset must be aligned on a 1024-byte boundary.
0x000.00 R/W OFFSET 31:10
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Register 69: Application Interrupt and Reset Control (APINT), offset 0xD0C
The APINT register provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. To write to this register, 0x05FA must be written to
the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the
Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table
3-9 on page 153 shows how the PRIGROUP value controls this split. The bit numbers in the Group
Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the
INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note: Determining preemption of an exception uses only the group priority field.
Table 3-9. Interrupt Priority Levels
Subpriorities Group
Priorities
Subpriority Field Group Priority Field Binary Point
a
PRIGROUP Bit Field
1 8 None [7:5] bxxx. 0x0 - 0x4
2 4 [5] [7:6] bxx.y 0x5
4 2 [6:5] [7] bx.yy 0x6
8 1 [7:5] None b.yyy 0x7
a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.
Application Interrupt and Reset Control (APINT)
Base 0xE000.E000
Offset 0xD0C
Type R/W, reset 0xFA05.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VECTKEY
1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VECTRESET VECTCLRACT SYSRESREQ reserved PRIGROUP reserved ENDIANESS
WO WO WO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Register Key
This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this
register. On a read, 0xFA05 is returned.
0xFA05 R/W VECTKEY 31:16
Data Endianess
The Tiva C Series implementation uses only little-endian mode so
this is cleared to 0.
0 RO ENDIANESS 15
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Interrupt Priority Grouping
This field determines the split of group priority from subpriority (see
Table 3-9 on page 153 for more information).
0x0 R/W PRIGROUP 10:8
0x0 RO reserved 7:3
System Reset Request
Description Value
No effect. 0
Resets the core and all on-chip peripherals except the Debug
interface.
1
This bit is automatically cleared during the reset of the core and reads
as 0.
0 WO SYSRESREQ 2
Clear Active NMI / Fault
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
0 WO VECTCLRACT 1
System Reset
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
0 WO VECTRESET 0
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Register 70: System Control (SYSCTRL), offset 0xD10
The SYSCTRL register controls features of entry to and exit from low-power state.
System Control (SYSCTRL)
Base 0xE000.E000
Offset 0xD10
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved SLEEPEXIT SLEEPDEEP reserved SEVONPEND reserved
RO R/W R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Wake Up on Pending
Description Value
Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
0
Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
1
When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.
0 R/W SEVONPEND 4
0 RO reserved 3
Deep Sleep Enable
Description Value
Use Sleep mode as the low power mode. 0
Use Deep-sleep mode as the low power mode. 1
0 R/W SLEEPDEEP 2
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Sleep on ISR Exit
Description Value
When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode.
0
When returning fromHandler mode to Thread mode, enter sleep
or deep sleep on return from an ISR.
1
Setting this bit enables an interrupt-driven application to avoid returning
to an empty main application.
0 R/W SLEEPEXIT 1
0 RO reserved 0
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Register 71: Configuration and Control (CFGCTRL), offset 0xD14
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIGregister by unprivileged software (see page 145).
Configuration and Control (CFGCTRL)
Base 0xE000.E000
Offset 0xD14
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BASETHR MAINPEND reserved UNALIGNED DIV0 reserved BFHFNMIGN STKALIGN reserved
R/W R/W RO R/W R/W RO RO RO R/W R/W RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Reset
Stack Alignment on Exception Entry
Description Value
The stack is 4-byte aligned. 0
The stack is 8-byte aligned. 1
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
1 R/W STKALIGN 9
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
Description Value
Data bus faults caused by load and store instructions cause a
lock-up.
0
Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
1
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
0 R/W BFHFNMIGN 8
0x0 RO reserved 7:5
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Trap on Divide by 0
This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.
Description Value
Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
0
Trap on divide by 0. 1
0 R/W DIV0 4
Trap on Unaligned Access
Description Value
Do not trap on unaligned halfword and word accesses. 0
Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
1
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
0 R/W UNALIGNED 3
0 RO reserved 2
Allow Main Interrupt Trigger
Description Value
Disables unprivileged software access to the SWTRIGregister. 0
Enables unprivileged software access to the SWTRIG register
(see page 145).
1
0 R/W MAINPEND 1
Thread State Control
Description Value
The processor can enter Thread mode only when no exception
is active.
0
The processor can enter Thread mode fromany level under the
control of an EXC_RETURN value (see Exception
Return on page 99 for more information).
1
0 R/W BASETHR 0
April 10, 2013 158
Register 72: System Handler Priority 1 (SYSPRI1), offset 0xD18
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory
management fault exception handlers. This register is byte-accessible.
System Handler Priority 1 (SYSPRI1)
Base 0xE000.E000
Offset 0xD18
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved USAGE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved MEM reserved BUS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Usage Fault Priority
This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
0x0 R/W USAGE 23:21
Bus Fault Priority
This field configures the priority level of the bus fault. Configurable priority
values are in the range 0-7, with lower values having higher priority.
0x0 R/W BUS 15:13
Memory Management Fault Priority
This field configures the priority level of the memory management fault.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
0x0 R/W MEM 7:5
0x0 RO reserved 4:0
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Register 73: System Handler Priority 2 (SYSPRI2), offset 0xD1C
The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is
byte-accessible.
Base 0xE000.E000
Offset 0xD1C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved SVC
RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SVCall Priority
This field configures the priority level of SVCall. Configurable priority
0x0 R/W SVC 31:29
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Register 74: System Handler Priority 3 (SYSPRI3), offset 0xD20
The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV
handlers. This register is byte-accessible.
Base 0xE000.E000
Offset 0xD20
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved PENDSV reserved TICK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved DEBUG reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SysTick Exception Priority
This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
0x0 R/W TICK 31:29
PendSV Priority
This field configures the priority level of PendSV. Configurable priority
0x0 R/W PENDSV 23:21
Debug Priority
This field configures the priority level of Debug. Configurable priority
0x0 R/W DEBUG 7:5
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Register 75: SystemHandler Control and State (SYSHNDCTRL), offset 0xD24
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the
usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status
of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as
a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS
kernel can write to the active bits to perform a context switch that changes the current exception
type.
Caution Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure software that writes
to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modifed after enabling the system handlers, a
read-modify-write procedure must be used to ensure that only the required bit is modifed.
System Handler Control and State (SYSHNDCTRL)
Base 0xE000.E000
Offset 0xD24
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MEM BUS USAGE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MEMA BUSA reserved USGA reserved SVCA MON reserved PNDSV TICK USAGEP MEMP BUSP SVC
R/W R/W RO R/W RO RO RO R/W R/W RO R/W R/W R/W R/W R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Usage Fault Enable
Description Value
Disables the usage fault exception. 0
Enables the usage fault exception. 1
0 R/W USAGE 18
Bus Fault Enable
Description Value
Disables the bus fault exception. 0
Enables the bus fault exception. 1
0 R/W BUS 17
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Memory Management Fault Enable
Description Value
Disables the memory management fault exception. 0
Enables the memory management fault exception. 1
0 R/W MEM 16
SVC Call Pending
Description Value
An SVC call exception is not pending. 0
An SVC call exception is pending. 1
This bit can be modified to change the pending status of the SVC call
exception.
0 R/W SVC 15
Bus Fault Pending
Description Value
A bus fault exception is not pending. 0
A bus fault exception is pending. 1
This bit can be modified to change the pending status of the bus fault
exception.
0 R/W BUSP 14
Memory Management Fault Pending
Description Value
A memory management fault exception is not pending. 0
A memory management fault exception is pending. 1
This bit can be modified to change the pending status of the memory
management fault exception.
0 R/W MEMP 13
Usage Fault Pending
Description Value
A usage fault exception is not pending. 0
A usage fault exception is pending. 1
This bit can be modified to change the pending status of the usage fault
exception.
0 R/W USAGEP 12
SysTick Exception Active
Description Value
A SysTick exception is not active. 0
A SysTick exception is active. 1
This bit can be modified to change the active status of the SysTick
exception, however, see the Caution above before setting this bit.
0 R/W TICK 11
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PendSV Exception Active
Description Value
A PendSV exception is not active. 0
A PendSV exception is active. 1
This bit can be modified to change the active status of the PendSV
0 R/W PNDSV 10
0 RO reserved 9
Debug Monitor Active
Description Value
The Debug monitor is not active. 0
The Debug monitor is active. 1
0 R/W MON 8
SVC Call Active
Description Value
SVC call is not active. 0
SVC call is active. 1
This bit can be modified to change the active status of the SVC call
0 R/W SVCA 7
0x0 RO reserved 6:4
Usage Fault Active
Description Value
Usage fault is not active. 0
Usage fault is active. 1
This bit can be modified to change the active status of the usage fault
0 R/W USGA 3
0 RO reserved 2
Bus Fault Active
Description Value
Bus fault is not active. 0
Bus fault is active. 1
This bit can be modified to change the active status of the bus fault
0 R/W BUSA 1
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Memory Management Fault Active
Description Value
Memory management fault is not active. 0
Memory management fault is active. 1
This bit can be modified to change the active status of the memory
management fault exception, however, see the Caution above before
setting this bit.
0 R/W MEMA 0
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Register 76: Configurable Fault Status (FAULTSTAT), offset 0xD28
The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage
fault. Each of these functions is assigned to a subregister as follows:
Usage Fault Status (UFAULTSTAT), bits 31:16
Bus Fault Status (BFAULTSTAT), bits 15:8
Memory Management Fault Status (MFAULTSTAT), bits 7:0
FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:
The complete FAULTSTAT register, with a word access to offset 0xD28
The MFAULTSTAT, with a byte access to offset 0xD28
The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
The BFAULTSTAT, with a byte access to offset 0xD29
The UFAULTSTAT, with a halfword access to offset 0xD2A
Bits are cleared by writing a 1 to them.
In a fault handler, the true faulting address can be determined by:
1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.
2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.
Software must follow this sequence because another higher priority exception might change the
MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMADDR or FAULTADDR value.
Configurable Fault Status (FAULTSTAT)
Base 0xE000.E000
Offset 0xD28
Type R/W1C, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UNDEF INVSTAT INVPC NOCP reserved UNALIGN DIV0 reserved
R/W1C R/W1C R/W1C R/W1C RO RO RO RO R/W1C R/W1C RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IERR DERR reserved MUSTKE MSTKE MLSPERR reserved MMARV IBUS PRECISE IMPRE BUSTKE BSTKE BLSPERR reserved BFARV
R/W1C R/W1C RO R/W1C R/W1C R/W1C RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C RO R/W1C Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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Divide-by-Zero Usage Fault
Description Value
No divide-by-zero fault has occurred, or divide-by-zero trapping
is not enabled.
0
The processor has executed an SDIV or UDIV instruction with
a divisor of 0.
1
When this bit is set, the PCvalue stacked for the exception return points
to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register (see page 157).
This bit is cleared by writing a 1 to it.
0 R/W1C DIV0 25
Unaligned Access Usage Fault
Description Value
No unaligned access fault has occurred, or unaligned access
trapping is not enabled.
0
The processor has made an unaligned memory access. 1
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting the UNALIGNED bit
in the CFGCTRL register (see page 157).
0 R/W1C UNALIGN 24
No Coprocessor Usage Fault
Description Value
A usage fault has not been caused by attempting to access a
coprocessor.
0
The processor has attempted to access a coprocessor. 1
0 R/W1C NOCP 19
Invalid PC Load Usage Fault
Description Value
A usage fault has not been caused by attempting to load an
invalid PC value.
0
The processor has attempted an illegal load of EXC_RETURN
to the PC as a result of an invalid context or an invalid
EXC_RETURN value.
1
to the instruction that tried to perform the illegal load of the PC.
0 R/W1C INVPC 18
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Invalid State Usage Fault
Description Value
A usage fault has not been caused by an invalid state. 0
The processor has attempted to execute an instruction that
makes illegal use of the EPSR register.
1
to the instruction that attempted the illegal use of the Execution
Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
0 R/W1C INVSTAT 17
Undefined Instruction Usage Fault
Description Value
A usage fault has not been caused by an undefined instruction. 0
The processor has attempted to execute an undefined
instruction.
1
to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
0 R/W1C UNDEF 16
Bus Fault Address Register Valid
Description Value
The value in the Bus Fault Address (FAULTADDR) register
is not a valid fault address.
0
The FAULTADDR register is holding a valid fault address. 1
This bit is set after a bus fault, where the address is known. Other faults
can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority,
the hard fault handler must clear this bit. This action prevents problems
if returning to a stacked active bus fault handler whose FAULTADDR
register value has been overwritten.
0 R/W1C BFARV 15
0 RO reserved 14
Bus Fault on Floating-Point Lazy State Preservation
Description Value
No bus fault has occurred during floating-point lazy state
preservation.
0
A bus fault has occurred during floating-point lazy state
preservation.
1
0 R/W1C BLSPERR 13
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Stack Bus Fault
Description Value
No bus fault has occurred on stacking for exception entry. 0
Stacking for an exception entry has caused one or more bus
faults.
1
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the FAULTADDR register.
0 R/W1C BSTKE 12
Unstack Bus Fault
Description Value
No bus fault has occurred on unstacking for a return from
exception.
0
Unstacking for a return fromexception has caused one or more
bus faults.
1
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted fromthe failing return,
a new save is not performed, and a fault address is not written to the
FAULTADDR register.
0 R/W1C BUSTKE 11
Imprecise Data Bus Error
Description Value
An imprecise data bus error has not occurred. 0
A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.
1
When this bit is set, a fault address is not written to the FAULTADDR
register.
This fault is asynchronous. Therefore, if the fault is detected when the
priority of the current process is higher than the bus fault priority, the
bus fault becomes pending and becomes active only when the processor
returns fromall higher-priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects that both the IMPRE bit is set and one of the precise fault status
bits is set.
0 R/W1C IMPRE 10
Precise Data Bus Error
Description Value
A precise data bus error has not occurred. 0
A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the
fault.
1
When this bit is set, the fault address is written to the FAULTADDR
register.
0 R/W1C PRECISE 9
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Instruction Bus Error
Description Value
An instruction bus error has not occurred. 0
An instruction bus error has occurred. 1
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
0 R/W1C IBUS 8
Memory Management Fault Address Register Valid
Description Value
The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
0
The MMADDR register is holding a valid fault address. 1
If a memory management fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
0 R/W1C MMARV 7
0 RO reserved 6
Memory Management Fault on Floating-Point Lazy State Preservation
Description Value
No memory management fault has occurred during floating-point
lazy state preservation.
0
No memory management fault has occurred during floating-point
lazy state preservation.
1
0 R/W1C MLSPERR 5
Stack Access Violation
Description Value
No memory management fault has occurred on stacking for
exception entry.
0
Stacking for an exception entry has caused one or more access
violations.
1
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
0 R/W1C MSTKE 4
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Unstack Access Violation
Description Value
No memory management fault has occurred on unstacking for
a return from exception.
0
Unstacking for a return fromexception has caused one or more
access violations.
1
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted fromthe failing return,
a new save is not performed, and a fault address is not written to the
MMADDR register.
0 R/W1C MUSTKE 3
0 RO reserved 2
Data Access Violation
Description Value
A data access violation has not occurred. 0
The processor attempted a load or store at a location that does
not permit the operation.
1
to the faulting instruction and the address of the attempted access is
written to the MMADDR register.
0 R/W1C DERR 1
Instruction Access Violation
Description Value
An instruction access violation has not occurred. 0
The processor attempted an instruction fetch from a location
that does not permit execution.
1
This fault occurs on any access to an XN region, even when the MPU
is disabled or not present.
to the faulting instruction and the address of the attempted access is
not written to the MMADDR register.
0 R/W1C IERR 0
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Register 77: Hard Fault Status (HFAULTSTAT), offset 0xD2C
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.
Hard Fault Status (HFAULTSTAT)
Base 0xE000.E000
Offset 0xD2C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved FORCED DBG
RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved VECT reserved
RO R/W1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.
0 R/W1C DBG 31
Forced Hard Fault
Description Value
No forced hard fault has occurred. 0
A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
1
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
0 R/W1C FORCED 30
Vector Table Read Fault
Description Value
No bus fault has occurred on a vector table read. 0
A bus fault occurred on a vector table read. 1
This error is always handled by the hard fault handler.
to the instruction that was preempted by the exception.
0 R/W1C VECT 1
0 RO reserved 0
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Register 78: Memory Management Fault Address (MMADDR), offset 0xD34
The MMADDR register contains the address of the location that generated a memory management
fault. When an unaligned access faults, the address in the MMADDR register is the actual address
that faulted. Because a single read or write instruction can be split into multiple aligned accesses,
the fault address can be any address in the range of the requested access size. Bits in the Memory
Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether
the value in the MMADDR register is valid (see page 166).
Memory Management Fault Address (MMADDR)
Base 0xE000.E000
Offset 0xD34
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADDR
- - - - - - - - - - - - - - - - Reset
Fault Address
When the MMARV bit of MFAULTSTAT is set, this field holds the address
of the location that generated the memory management fault.
- R/W ADDR 31:0
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Register 79: Bus Fault Address (FAULTADDR), offset 0xD38
The FAULTADDR register contains the address of the location that generated a bus fault. When
an unaligned access faults, the address in the FAULTADDR register is the one requested by the
instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid
(see page 166).
Bus Fault Address (FAULTADDR)
Base 0xE000.E000
Offset 0xD38
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADDR
- - - - - - - - - - - - - - - - Reset
Fault Address
When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the
address of the location that generated the bus fault.
- R/W ADDR 31:0
3.6 Memory Protection Unit (MPU) Register Descriptions
This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by
address offset.
The MPU registers can only be accessed from privileged mode.
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Register 80: MPU Type (MPUTYPE), offset 0xD90
The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it
supports.
MPU Type (MPUTYPE)
Base 0xE000.E000
Offset 0xD90
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
IREGION reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SEPARATE reserved DREGION
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset
Number of I Regions
This field indicates the number of supported MPU instruction regions.
This field always contains 0x00. The MPU memory map is unified and
is described by the DREGION field.
0x00 RO IREGION 23:16
Number of D Regions
Description Value
Indicates there are eight supported MPU data regions. 0x08
0x08 RO DREGION 15:8
Separate or Unified MPU
Description Value
Indicates the MPU is unified. 0
0 RO SEPARATE 0
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Register 81: MPU Control (MPUCTRL), offset 0xD94
The MPUCTRL register enables the MPU, enables the default memory map background region,
and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask
Register (FAULTMASK) escalated handlers.
When the ENABLE and PRIVDEFEN bits are both set:
For privileged accesses, the default memory map is as described in Memory Model on page 81.
Any access by privileged software that does not address an enabled memory region behaves
as defined by the default memory map.
Any access by unprivileged software that does not address an enabled memory region causes
a memory management fault.
Execute Never (XN) and Strongly Ordered rules always apply to the SystemControl Space regardless
of the value of the ENABLE bit.
When the ENABLE bit is set, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled,
then only privileged software can operate.
When the ENABLE bit is clear, the system uses the default memory map, which has the same
memory attributes as if the MPUis not implemented (see Table 2-5 on page 84 for more information).
The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always
permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set.
Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for
an exception with priority 1 or 2. These priorities are only possible when handling a hard fault or
NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when
operating with these two priorities.
MPU Control (MPUCTRL)
Base 0xE000.E000
Offset 0xD94
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ENABLE HFNMIENA PRIVDEFEN reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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MPU Default Region
This bit enables privileged software access to the default memory map.
Description Value
If the MPUis enabled, this bit disables use of the default memory
map. Any memory access to a location not covered by any
enabled region causes a fault.
0
If the MPUis enabled, this bit enables use of the default memory
map as a background region for privileged software accesses.
1
When this bit is set, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this default
map.
If the MPU is disabled, the processor ignores this bit.
0 R/W PRIVDEFEN 2
MPU Enabled During Faults
This bit controls the operation of the MPU during hard fault, NMI, and
FAULTMASK handlers.
Description Value
The MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit.
0
The MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.
1
When the MPU is disabled and this bit is set, the resulting behavior is
unpredictable.
0 R/W HFNMIENA 1
MPU Enable
Description Value
The MPU is disabled. 0
The MPU is enabled. 1
When the MPU is disabled and the HFNMIENA bit is set, the resulting
behavior is unpredictable.
0 R/W ENABLE 0
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Register 82: MPU Region Number (MPUNUMBER), offset 0xD98
The MPUNUMBER register selects which memory region is referenced by the MPU Region Base
Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the
required region number should be written to this register before accessing the MPUBASE or the
MPUATTR register. However, the region number can be changed by writing to the MPUBASE
register with the VALID bit set (see page 179). This write updates the value of the REGION field.
MPU Region Number (MPUNUMBER)
Base 0xE000.E000
Offset 0xD98
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NUMBER reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
MPU Region to Access
This field indicates the MPU region referenced by the MPUBASE and
MPUATTR registers. The MPU supports eight memory regions.
0x0 R/W NUMBER 2:0
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Register 83: MPU Region Base Address (MPUBASE), offset 0xD9C
Register 84: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4
Register 85: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC
Register 86: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4
The MPUBASE register defines the base address of the MPU region selected by the MPU Region
Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To
change the current region number and update the MPUNUMBER register, write the MPUBASE
register with the VALID bit set.
The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size,
as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines
the value of N where:
N = Log
2
(Region size in bytes)
If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In
this case, the region occupies the complete memory map, and the base address is 0x0000.0000.
The base address is aligned to the size of the region. For example, a 64-KB region must be aligned
on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000.
MPU Region Base Address (MPUBASE)
Base 0xE000.E000
Offset 0xD9C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
REGION reserved VALID ADDR
R/W R/W R/W RO WO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Base Address Mask
Bits 31:N in this field contain the region base address. The value of N
depends on the region size, as shown above. The remaining bits (N-1):5
are reserved.
0x0000.000 R/W ADDR 31:5
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Region Number Valid
Description Value
The MPUNUMBER register is not changed and the processor
updates the base address for the region specified in the
MPUNUMBER register and ignores the value of the REGION
field.
0
The MPUNUMBER register is updated with the value of the
REGION field and the base address is updated for the region
specified in the REGION field.
1
This bit is always read as 0.
0 WO VALID 4
0 RO reserved 3
Region Number
On a write, contains the value to be written to the MPUNUMBERregister.
On a read, returns the current region number in the MPUNUMBER
register.
0x0 R/W REGION 2:0
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Register 87: MPU Region Attribute and Size (MPUATTR), offset 0xDA0
Register 88: MPURegion Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
Register 89: MPURegion Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
Register 90: MPURegion Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
The MPUATTR register defines the region size and memory attributes of the MPU region specified
by the MPURegion Number (MPUNUMBER) register and enables that region and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant
halfword holding the region attributes and the least-significant halfword holds the region size and
the region and subregion enable bits.
The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register
as follows:
(Region size in bytes) = 2
(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table
3-10 on page 181 gives example SIZE values with the corresponding region size and value of N in
the MPU Region Base Address (MPUBASE) register.
Table 3-10. Example SIZE Field Values
Note Value of N
a
Region Size SIZE Encoding
Minimum permitted size 5 32 B 00100b (0x4)
- 10 1 KB 01001b (0x9)
- 20 1 MB 10011b (0x13)
- 30 1 GB 11101b (0x1D)
Maximum possible size No valid ADDR field in MPUBASE; the
region occupies the complete
memory map.
4 GB 11111b (0x1F)
a. Refers to the N parameter in the MPUBASE register (see page 179).
MPU Region Attribute and Size (MPUATTR)
Base 0xE000.E000
Offset 0xDA0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
B C S TEX reserved AP reserved XN reserved
R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W RO R/W RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ENABLE SIZE reserved SRD
R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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Instruction Access Disable
Description Value
Instruction fetches are enabled. 0
Instruction fetches are disabled. 1
0 R/W XN 28
0 RO reserved 27
Access Privilege
For information on using this bit field, see Table 3-5 on page 118.
0 R/W AP 26:24
Type Extension Mask
For information on using this bit field, see Table 3-3 on page 117.
0x0 R/W TEX 21:19
Shareable
For information on using this bit, see Table 3-3 on page 117.
0 R/W S 18
Cacheable
0 R/W C 17
Bufferable
0 R/W B 16
Subregion Disable Bits
Description Value
The corresponding subregion is enabled. 0
The corresponding subregion is disabled. 1
Region sizes of 128 bytes and less do not support subregions. When
writing the attributes for such a region, configure the SRD field as 0x00.
See the section called Subregions on page 117 for more information.
0x00 R/W SRD 15:8
0x0 RO reserved 7:6
Region Size Mask
The SIZE field defines the size of the MPU memory region specified by
the MPUNUMBER register. Refer to Table 3-10 on page 181 for more
information.
0x0 R/W SIZE 5:1
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Region Enable
Description Value
The region is disabled. 0
The region is enabled. 1
0 R/W ENABLE 0
3.7 Floating-Point Unit (FPU) Register Descriptions
This section lists and describes the Floating-Point Unit (FPU) registers, in numerical order by address
offset.
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Register 91: Coprocessor Access Control (CPAC), offset 0xD88
The CPAC register specifies the access privileges for coprocessors.
Coprocessor Access Control (CPAC)
Base 0xE000.E000
Offset 0xD88
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved CP10 CP11 reserved
RO RO RO RO R/W R/W R/W R/W RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CP11 Coprocessor Access Privilege
Description Value
Access Denied
Any attempted access generates a NOCP Usage Fault.
0x0
Privileged Access Only
An unprivileged access generates a NOCP fault.
0x1
Reserved
The result of any access is unpredictable.
0x2
Full Access 0x3
0x00 R/W CP11 23:22
CP10 Coprocessor Access Privilege
Description Value
Access Denied
Any attempted access generates a NOCP Usage Fault.
0x0
Privileged Access Only
An unprivileged access generates a NOCP fault.
0x1
Reserved
The result of any access is unpredictable.
0x2
Full Access 0x3
0x00 R/W CP10 21:20
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Register 92: Floating-Point Context Control (FPCC), offset 0xF34
The FPCC register sets or returns FPU control data.
Floating-Point Context Control (FPCC)
Base 0xE000.E000
Offset 0xF34
Type R/W, reset 0xC000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved LSPEN ASPEN
RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LSPACT USER reserved THREAD HFRDY MMRDY BFRDY reserved MONRDY reserved
R/W R/W RO R/W R/W R/W R/W RO R/W RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Automatic State Preservation Enable
When set, enables the use of the FRACTV bit in the CONTROL register
on execution of a floating-point instruction. This results in automatic
hardware state preservation and restoration, for floating-point context,
on exception entry and exit.
Important:
(ACTLR) register.
1 R/W ASPEN 31
Lazy State Preservation Enable
When set, enables automatic lazy state preservation for floating-point
context.
1 R/W LSPEN 30
Monitor Ready
When set, DebugMonitor is enabled and priority permits setting
MON_PEND when the floating-point stack frame was allocated.
0 R/W MONRDY 8
0 RO reserved 7
Bus Fault Ready
When set, BusFault is enabled and priority permitted setting the BusFault
handler to the pending state when the floating-point stack frame was
allocated.
0 R/W BFRDY 6
Memory Management Fault Ready
When set, MemManage is enabled and priority permitted setting the
MemManage handler to the pending state when the floating-point stack
frame was allocated.
0 R/W MMRDY 5
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Hard Fault Ready
When set, priority permitted setting the HardFault handler to the pending
state when the floating-point stack frame was allocated.
0 R/W HFRDY 4
Thread Mode
When set, mode was Thread Mode when the floating-point stack frame
was allocated.
0 R/W THREAD 3
0 RO reserved 2
User Privilege Level
When set, privilege level was user when the floating-point stack frame
was allocated.
0 R/W USER 1
Lazy State Preservation Active
When set, Lazy State preservation is active. Floating-point stack frame
has been allocated but saving state to it has been deferred.
0 R/W LSPACT 0
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Register 93: Floating-Point Context Address (FPCA), offset 0xF38
The FPCA register holds the location of the unpopulated floating-point register space allocated on
an exception stack frame.
Floating-Point Context Address (FPCA)
Base 0xE000.E000
Offset 0xF38
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDRESS
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved ADDRESS
RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type
0 0 0 - - - - - - - - - - - - - Reset
Address
The location of the unpopulated floating-point register space allocated
on an exception stack frame.
- R/W ADDRESS 31:3
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Register 94: Floating-Point Default Status Control (FPDSC), offset 0xF3C
The FPDSCregister holds the default values for the Floating-Point Status Control (FPSC) register.
Floating-Point Default Status Control (FPDSC)
Base 0xE000.E000
Offset 0xF3C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved RMODE FZ DN AHP reserved
RO RO RO RO RO RO R/W R/W R/W R/W R/W RO RO RO RO RO Type
0 0 0 0 0 0 - - - - - 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
AHP Bit Default
This bit holds the default value for the AHP bit in the FPSC register.
- R/W AHP 26
DN Bit Default
This bit holds the default value for the DN bit in the FPSC register.
- R/W DN 25
FZ Bit Default
This bit holds the default value for the FZ bit in the FPSC register.
- R/W FZ 24
RMODE Bit Default
This bit holds the default value for the RMODE bit field in the FPSC
register.
Description Value
Round to Nearest (RN) mode 0x0
Round towards Plus Infinity (RP) mode 0x1
Round towards Minus Infinity (RM) mode 0x2
Round towards Zero (RZ) mode 0x3
- R/W RMODE 23:22
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4 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into
the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The TM4C123AH6PMJTAGcontroller works with the ARMJTAGcontroller built into the Cortex-M4F
core by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the
ARM TDO output while JTAG instructions select the TDO output. The multiplexer is controlled by the
JTAG controller, which has comprehensive programming for the ARM, Tiva C Series
microcontroller, and unimplemented JTAG instructions.
The TM4C123AH6PM JTAG module has the following features:
IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
Four-bit Instruction Register (IR) chain for storing JTAG instructions
IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST
ARM additional instructions: APACC, DPACC and ABORT
Integrated ARM Serial Wire Debug (SWD)
Serial Wire JTAG Debug Port (SWJ-DP)
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
Embedded Trace Macrocell (ETM) for instruction trace capture
Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
See the ARM Debug Interface V5 Architecture Specification for more information on the ARM
JTAG controller.
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4.1 Block Diagram
Figure 4-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TCK
TMS
TDI
TDO
Cortex-M4F
Debug
Port
4.2 Signal Description
The following table lists the external signals of the JTAG/SWD controller and describes the function
of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however
note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals
are under commit protection and require a special process to be configured as GPIOs, see Commit
Control on page 598. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO
pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIOAlternate Function
Select (GPIOAFSEL) register (page 612) is set to choose the JTAG/SWD function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIOPort Control
(GPIOPCTL) register (page 629) to assign the JTAG/SWD controller signals to the specified GPIO
port pin. For more information on configuring GPIOs, see General-Purpose Input/Outputs
(GPIOs) on page 591.
Table 4-1. JTAG_SWD_SWO Signals (64LQFP)
Description Buffer Type
a
Pin Type Pin Mux / Pin
Assignment
Pin Number Pin Name
JTAG/SWD CLK. TTL I PC0 (1) 52 SWCLK
JTAG TMS and SWDIO. TTL I/O PC1 (1) 51 SWDIO
JTAG TDO and SWO. TTL O PC3 (1) 49 SWO
JTAG/SWD CLK. TTL I PC0 (1) 52 TCK
JTAG TDI. TTL I PC2 (1) 50 TDI
JTAG TDO and SWO. TTL O PC3 (1) 49 TDO
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Table 4-1. JTAG_SWD_SWO Signals (64LQFP) (continued)
a
Assignment
Pin Number Pin Name
JTAG TMS and SWDIO. TTL I PC1 (1) 51 TMS
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
A high-level conceptual drawing of the JTAGmodule is shown in Figure 4-1 on page 190. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
The current state of the TAP controller depends on the sequence of values captured on TMS at the
rising edge of TCK. The TAP controller determines when the serial shift chains capture new data,
shift data from TDI towards TDO, and update the parallel load registers. The current state of the
TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register
(DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST, operate on data currently in a DR chain and do not capture, shift,
or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction
to ensure that the serial path between TDI and TDO is always connected (see Table 4-3 on page 197
for a list of implemented instructions).
See JTAG and Boundary Scan on page 1188 for JTAG timing diagrams.
Note: Of all the possible reset sources, only Power-On reset (POR) and the assertion of the RST
input have any effect on the JTAG module. The pin configurations are reset by both the
RST input and POR, whereas the internal JTAG logic is only reset with POR. See Reset
Sources on page 202 for more information on reset.
4.3.1 JTAG Interface Pins
The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their
associated state after a power-on reset or reset caused by the RST input are given in Table 4-2.
Detailed information on each pin follows.
Note: The following pins are configured as JTAGport pins out of reset. Refer to General-Purpose
Input/Outputs (GPIOs) on page 591 for information on how to reprogram the configuration
of these pins.
Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion
Drive Value Drive Strength Internal Pull-Down Internal Pull-Up Data Direction Pin Name
N/A N/A Disabled Enabled Input TCK
N/A N/A Disabled Enabled Input TMS
N/A N/A Disabled Enabled Input TDI
High-Z 2-mA driver Disabled Enabled Output TDO
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4.3.1.1 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks and to ensure that multiple JTAG TAP controllers that
are daisy-chained together can synchronously communicate serial test data between components.
During normal operation, TCK is driven by a free-running clock with a nominal 50%duty cycle. When
necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0
or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data
Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset, assuring that no clocking
occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors
can be turned off to save internal power as long as the TCK pin is constantly being driven by an
external source (see page 618 and page 620).
4.3.1.2 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be
entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1
expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
module and associated registers are reset to their default values. This procedure should be performed
to initialize the JTAGcontroller. The JTAGTest Access Port state machine can be seen in its entirety
in Figure 4-2 on page 193.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost (see page 618).
4.3.1.3 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, may present this data to the proper shift register chain. Because the TDI pin is sampled
on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the
falling edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost (see page 618).
4.3.1.4 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset, assuring that the pin
remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
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JTAG Interface
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states (see page 618 and page 620).
4.3.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 4-2. The TAP controller state machine
is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset
the JTAG module after the microcontroller has been powered on, the TMS input must be held HIGH
for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting
the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in
data, or idle during extended testing sequences. For detailed information on the function of the TAP
controller and the operations that occur in each state, please refer to IEEE Standard 1149.1.
Figure 4-2. Test Access Port State Machine
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 1 1
1 1
1
1 1
1 1
1 1
1 1
1 1 0 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
4.3.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controllers CAPTURE states and allows
this information to be shifted out on TDO during the TAP controllers SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controllers UPDATE
states. Each of the shift registers is discussed in detail in Register Descriptions on page 197.
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4.3.4 Operational Considerations
Certain operational parameters must be considered when using the JTAG module. Because the
JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these
pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes is described below.
4.3.4.1 GPIO Functionality
When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWDconfigurations. The default configuration includes enabling digital functionality (DEN[3:0]
set in the Port CGPIODigital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0]
set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors
(PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the
alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select
(GPIOAFSEL) register) on the JTAG/SWDpins. See page 612, page 618, page 620, and page 623.
It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in
the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.
Caution It is possible to create a software sequence that prevents the debugger from connecting to
the TM4C123AH6PM microcontroller. If the program code loaded into fash immediately changes the
JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt
the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out
of the part. This issue can be avoided with a software routine that restores JTAG functionality based
on an external or software trigger. In the case that the software routine is not implemented and the
device is locked out of the part, this issue can be solved by using the TM4C123AH6PMFlash Programmer
"Unlock" feature. Please refer to LMFLASHPROGRAMMER on the TI web for more information.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four
JTAG/SWD pins (PC[3:0])and the NMI pin (PD7 and PF0). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 612), GPIOPull Up Select (GPIOPUR)
register (see page 618), GPIO Pull-Down Select (GPIOPDR) register (see page 620), and GPIO
Digital Enable (GPIODEN) register (see page 623) are not committed to storage unless the GPIO
Lock (GPIOLOCK) register (see page 625) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 626) have been set.
4.3.4.2 Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWDinterface. In the Capture-DRstate,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
4.3.4.3 Recovering a "Locked" Microcontroller
Note: Performing the sequence belowrestores the non-volatile registers discussed in Non-Volatile
Register Programming on page 475 to their factory default values. The mass erase of the
Flash memory caused by the sequence below occurs prior to the non-volatile registers
being restored.
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In addition, the EEPROM is erased and its wear-leveling counters are returned to factory
default values when performing the sequence below.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug port unlock sequence that can be used to recover the
microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while
holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence
is:
1. Assert and hold the RST signal.
2. Apply power to the device.
3. Performsteps 1 and 2 of the JTAG-to-SWDswitch sequence on the section called JTAG-to-SWD
Switching on page 196.
4. Performsteps 1 and 2 of the SWD-to-JTAGswitch sequence on the section called SWD-to-JTAG
Switching on page 196.
5. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
6. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
13. Release the RST signal.
14. Wait 400 ms.
15. Power-cycle the microcontroller.
4.3.4.4 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M4F core without having to perform, or have any
knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued
before the SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. Fromhere, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequence of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM
Debug Interface V5 Architecture Specification.
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Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This instance is the only one
where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to
the low probability of this sequence occurring during normal operation of the TAP controller, it should
not affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the microcontroller. The 16-bit
TMS/SWDIOcommand for switching to SWDmode is defined as b1110.0111.1001.1110, transmitted
LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The
complete switch sequence should consist of the following transactions on the TCK/SWCLK and
TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.
2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS/SWDIO.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in SWD mode before sending the switch sequence, the SWD goes into the line reset state.
To verify that the Debug Access Port (DAP) has switched to the Serial Wire Debug (SWD) operating
mode, perform a SWD READID operation. The ID value can be compared against the devices
known ID to verify the switch.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch command to the microcontroller. The 16-bit TMS/SWDIO
command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first.
This command can also be represented as 0xE73Cwhen transmitted LSB first. The complete switch
sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.
2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS/SWDIO.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in JTAG mode before sending the switch sequence, the JTAG goes into the Test Logic Reset
state.
To verify that the Debug Access Port (DAP) has switched to the JTAG operating mode, set the
JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The
DR value can be compared against the devices known IDCODE to verify the switch.
4.4 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAGcommunication can be restored. To return the pins to their JTAGfunctions,
enable the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register.
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JTAG Interface
In addition to enabling the alternate functions, any other changes to the GPIO pad configurations
on the four JTAG pins (PC[3:0]) should be returned to their default settings.
4.5 Register Descriptions
The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are
not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within
the JTAG controller are all accessed serially through the TAP Controller. These registers include
the Instruction Register and the six Data Registers.
4.5.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated,
they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-3. A
detailed explanation of each instruction, along with its associated Data Register, follows.
Table 4-3. JTAG Instruction Register Commands
Description Instruction IR[3:0]
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
EXTEST 0x0
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
SAMPLE / PRELOAD 0x2
Shifts data into the ARM Debug Port Abort Register. ABORT 0x8
Shifts data into and out of the ARM DP Access Register. DPACC 0xA
Shifts data into and out of the ARM AC Access Register. APACC 0xB
Loads manufacturing information defined by the IEEE Standard 1149.1 into
the IDCODE chain and shifts it out.
IDCODE 0xE
Connects TDI to TDO through a single Shift Register chain. BYPASS 0xF
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
Reserved All Others
4.5.1.1 EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOADinstruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. With tests
that drive known values out of the controller, this instruction can be used to verify connectivity. While
the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can
be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
4.5.1.2 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DRstate during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while
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the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST instruction
to drive data into or out of the controller. See Boundary Scan Data Register on page 199 for more
information.
4.5.1.3 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAPabort of a previous request. See the ABORT Data Register on page 200 for more information.
4.5.1.4 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. See DPACC Data
Register on page 200 for more information.
4.5.1.5 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
See APACC Data Register on page 200 for more information.
4.5.1.6 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure input and output data streams. IDCODE is the default instruction loaded into the JTAG
Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is
entered. See IDCODE Data Register on page 199 for more information.
4.5.1.7 BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimumlength serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. See BYPASS Data Register on page 199 for more
information.
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JTAG Interface
4.5.2 Data Registers
The JTAGmodule contains six Data Registers. These serial Data Register chains include: IDCODE,
BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections.
4.5.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-3. The standard requires that every JTAG-compliant microcontroller implement either the
IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically
configure themselves to work correctly with the Cortex-M4F during debug.
Figure 4-3. IDCODE Register Format
Version Part Number Manufacturer ID 1
31 28 27 12 11 1 0
TDO TDI
4.5.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-4. The standard requires that every JTAG-compliant microcontroller implement either the
BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
Figure 4-4. BYPASS Register Format
0
TDO TDI
0
4.5.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting
with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each
GPIOpin has three associated digital signals that are included in the chain. These signals are input,
output, and output enable, and are arranged in that order as shown in the figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST instruction. The EXTEST instruction forces data out of the controller.
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Figure 4-5. Boundary Scan Register Format
I
N
TDI
1
st
GPIO
TDO
...
O
U
T
O
E
I
N
m
th
GPIO
O
U
T
O
E
I
N
(m+1)
th
GPIO
O
U
T
O
E
...
I
N
GPIO n
th
O
U
T
O
E
4.5.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM Debug
Interface V5 Architecture Specification.
4.5.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM Debug
4.5.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM Debug
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JTAG Interface
5 System Control
System control configures the overall operation of the device and provides information about the
device. Configurable features include reset control, NMI operation, power control, clock control, and
low-power modes.
The following table lists the external signals of the SystemControl module and describes the function
of each. The NMI signal is the alternate function for two GPIO signals and functions as a GPIO after
reset. PD7 and PF0 are under commit protection and require a special process to be configured as
any alternate function or to subsequently return to the GPIO function, see Commit
Control on page 598. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO
pin placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 612) should be set to choose the NMI function. The number in
(GPIOPCTL) register (page 629) to assign the NMI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see General-Purpose Input/Outputs (GPIOs) on page 591. The
remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin
assignment and function.
Table 5-1. System Control & Clocks Signals (64LQFP)
a
Assignment
Pin Number Pin Name
Non-maskable interrupt. TTL I PD7 (8)
PF0 (8)
10
28
NMI
Main oscillator crystal input or an external clock
reference input.
Analog I fixed 40 OSC0
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
Analog O fixed 41 OSC1
System reset input. TTL I fixed 38 RST
The System Control module provides the following capabilities:
Device identification, see Device Identification on page 201
Local control, such as reset (see Reset Control on page 202), power (see Power
Control on page 207) and clock control (see Clock Control on page 208)
System control (Run, Sleep, and Deep-Sleep modes), see System Control on page 214
5.2.1 Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, memory sizes, and peripherals present on the device. The Device Identification 0
(DID0) (page 225) and Device Identification 1 (DID1) (page 227) registers provide details about the
device's version, package, temperature range, and so on. The Peripheral Present registers starting
at SystemControl offset 0x300, such as the Watchdog Timer Peripheral Present (PPWD) register,
provide information on how many of each type of module are included on the device. Finally,
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information about the capabilities of the on-chip peripherals are provided at offset 0xFC0 in each
peripheral's register space in the Peripheral Properties registers, such as the GPTM Peripheral
Properties (GPTMPP) register. Previous devices used the Device Capabilities (DC0-DC9) registers
for information about the peripherals and their capabilities. These registers are present on this device
for backward software capability, but provide no information about peripherals that were not available
on older devices.
5.2.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
5.2.2.1 Reset Sources
The TM4C123AH6PM microcontroller has six sources of reset:
1. Power-on reset (POR) (see page 203).
2. External reset input pin (RST) assertion (see page 203).
3. A brown-out detection that can be caused by any of the following events: (see page 205).
V
DD
under BOR0. The trigger value is the highest V
DD
voltage level for BOR0.
V
DD
under BOR1. The trigger value is the highest V
DD
4. Software-initiated reset (with the software reset registers) (see page 206).
5. A watchdog timer reset condition violation (see page 206).
6. MOSC failure (see page 207).
Table 5-2 provides a summary of results of the various reset operations.
Table 5-2. Reset Sources
On-Chip Peripherals Reset? JTAG Reset? Core Reset? Reset Source
Yes Yes Yes Power-On Reset
Yes Pin Config Only Yes RST
Yes Pin Config Only Yes Brown-Out Reset
Yes Pin Config Only Yes Software System Request
Reset using the SYSRESREQ
bit in the APINT register.
No Pin Config Only Yes Software System Request
Reset using the VECTRESET
bit in the APINT register.
Yes
a
Pin Config Only No Software Peripheral Reset
Yes Pin Config Only Yes Watchdog Reset
Yes Pin Config Only Yes MOSC Failure Reset
a. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
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System Control
is the cause, in which case, all the bits in the RESCregister are cleared except for the PORindicator.
A bit in the RESC register can be cleared by writing a 0.
At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM
Boot Loader or the application in Flash memory by using any GPIOsignal as configured in the Boot
Configuration (BOOTCFG) register.
At reset, the following sequence is performed:
1. The BOOTCFG register is read. If the EN bit is clear, the ROM Boot Loader is executed.
2. In the ROM Boot Loader, the status of the specified GPIO pin is compared with the specified
polarity. If the status matches the specified polarity, the ROMis mapped to address 0x0000.0000
and execution continues out of the ROM Boot Loader.
3. f then EN bit is set or the status doesn't match the specified polarity, the data at address
0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to
address 0x0000.0000 and execution continues out of the ROM Boot Loader.
4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded
from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from
address 0x0000.0004. The user application begins executing.
For example, if the BOOTCFG register is written and committed with the value of 0x0000.3C01,
then PB7 is examined at reset to determine if the ROM Boot Loader should be executed. If PB7 is
Low, the core unconditionally begins executing the ROM boot loader. If PB7 is High, then the
application in Flash memory is executed if the reset vector at location 0x0000.0004 is not
0xFFFF.FFFF. Otherwise, the ROM boot loader is executed.
5.2.2.2 Power-On Reset (POR)
Note: The JTAG controller can only be reset by the power-on reset.
The internal Power-On Reset (POR) circuit monitors the power supply voltage (V
DD
) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (V
VDD_POK
). The microcontroller must be operating within the specified operating
parameters when the on-chip power-on reset pulse is complete (see Power and
Brown-Out on page 1190). For applications that require the use of an external reset signal to hold
the microcontroller in reset longer than the internal POR, the RST input may be used as discussed
in External RST Pin on page 203.
The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in Power and Brown-Out on page 1190.
5.2.2.3 External RST Pin
Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
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If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (V
DD
) through an optional pull-up resistor (0 to 100K ) as shown in Figure 5-1 on page 204.
The RST input has filtering which requires a minimum pulse width in order for the reset pulse to be
recognized, see Table 22-11 on page 1195.
Figure 5-1. Basic RST Configuration
PU
RST
Tiva
Microcontroller
R
VDD
R
PU
= 0 to 100 k
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals. The external reset sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by T
MIN
and then de-asserted
(see Reset on page 1195).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 204.
Figure 5-2. External Circuitry to Extend Power-On Reset
PU
C
1
RST
R
VDD
Tiva
Microcontroller
R
PU
= 1 k to 100 k
C
1
= 1 nF to 10 F
If the application requires the use of an external reset switch, Figure 5-3 on page 205 shows the
proper circuitry to use.
April 10, 2013 204
System Control
Figure 5-3. Reset Circuit Controlled by Switch
PU
C
1
R
S
RST
R
VDD
Tiva
Microcontroller
Typical R
PU
= 10 k
Typical R
S
= 470
C
1
= 10 nF
The R
PU
and C
1
components define the power-on delay.
The external reset timing is shown in Figure 22-11 on page 1196.
5.2.2.4 Brown-Out Reset (BOR)
The microcontroller provides a brown-out detection circuit that triggers if any of the following occur:
V
DD
under BOR0. The external V
DD
supply voltage is below the specified V
DD
BOR0 value. The
trigger value is the highest V
DD
V
DD
under BOR1. The external V
DD
supply voltage is below the specified V
DD
BOR1 value. The
trigger value is the highest V
DD
The application can identify that a BOR event caused a reset by reading the Reset Cause (RESC)
register. When a brown-out condition is detected, the default condition is to generate a reset. The
BOR events can also be programmed to generate an interrupt by clearing the BOR0 bit or BOR1 bit
in the Power-On and Brown-Out Reset Control (PBORCTL) register.
The brown-out reset sequence is as follows:
1. When V
DD
drops below V
BORnTH
, an internal BOR condition is set. Please refer to Power and
Brown-Out on page 1190 for V
BORnTH
value.
2. If the BOR condition exists, an internal reset is asserted.
3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer,
the initial program counter, the first instruction designated by the program counter, and begins
execution.
The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and
the reset is held active until the proper V
DD
level is restored. The RESC register can be examined
in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus
allowing software to determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Power and Brown-Out on page 1190.
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5.2.2.5 Software Reset
Software can reset a specific peripheral or generate a reset to the entire microcontroller.
Peripherals can be individually reset by software via peripheral-specific reset registers available
beginning at System Control offset 0x500 (for example the Watchdog Timer Software Reset
(SRWD) register). If the bit position corresponding to a peripheral is set and subsequently cleared,
the peripheral is reset.
The entire microcontroller, including the core, can be reset by software by setting the SYSRESREQ
bit in the Application Interrupt and Reset Control (APINT) register. The software-initiated system
reset sequence is as follows:
1. A software microcontroller reset is initiated by setting the SYSRESREQ bit.
2. An internal reset is asserted.
3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.
The core only can be reset by software by setting the VECTRESET bit in the APINT register. The
software-initiated core reset sequence is as follows:
1. A core reset is initiated by setting the VECTRESET bit.
3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.
The software-initiated system reset timing is shown in Figure 22-12 on page 1196.
5.2.2.6 Watchdog Timer Reset
The Watchdog Timer module's function is to prevent system hangs. The TM4C123AH6PM
microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One
watchdog is run off the systemclock and the other is run off the Precision Internal Oscillator (PIOSC).
Each module operates in the same manner except that because the PIOSCwatchdog timer module
is in a different clock domain, register accesses must have a time delay between them. The watchdog
timer can be configured to generate an interrupt or a non-maskable interrupt to the microcontroller
on its first time-out and to generate a reset on its second time-out.
After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of
the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If
the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal
has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog
timer reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
3. The internal reset is released and the microcontroller loads frommemory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
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System Control
For more information on the Watchdog Timer module, see Watchdog Timers on page 715.
The watchdog reset timing is shown in Figure 22-13 on page 1196.
5.2.3 Non-Maskable Interrupt
The microcontroller has four sources of non-maskable interrupt (NMI):
The assertion of the NMI signal
A main oscillator verification error
The NMISET bit in the Interrupt Control and State (INTCTRL) register in the Cortex
-M4F (see
page 149).
The Watchdog module time-out interrupt when the INTTYPE bit in the Watchdog Control
(WDTCTL) register is set (see page 721).
Software must check the cause of the interrupt in order to distinguish among the sources.
5.2.3.1 NMI Pin
The NMI signal is an alternate function for either GPIO port pin PD7 or PF0. The alternate function
must be enabled in the GPIO for the signal to be used as an interrupt, as described in
General-Purpose Input/Outputs (GPIOs) on page 591. Note that enabling the NMI alternate function
requires the use of the GPIO lock and commit function just like the GPIO port pins associated with
JTAG/SWD functionality, see page 626. The active sense of the NMI signal is High; asserting the
enabled NMI signal above V
IH
initiates the NMI interrupt sequence.
5.2.3.2 Main Oscillator Verification Failure
The TM4C123AH6PM microcontroller provides a main oscillator verification circuit that generates
an error condition if the oscillator is running too fast or too slow. If the main oscillator verification
circuit is enabled and a failure occurs, either a power-on reset is generated and control is transferred
to the NMI handler, or an interrupt is generated. The MOSCIM bit in the MOSCCTL register determines
which action occurs. In either case, the systemclock source is automatically switched to the PIOSC.
If a MOSC failure reset occurs, the NMI handler is used to address the main oscillator verification
failure because the necessary code can be removed from the general reset handler, speeding up
reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator
Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator
fail status (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit
action is described in more detail in Main Oscillator Verification Circuit on page 214.
5.2.4 Power Control
The TM4C123AH6PM microcontroller provides an integrated LDO regulator that is used to provide
power to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture.
An external LDO may not be used.
Note: VDDA must be supplied with a voltage that meets the specification in Table 22-5 on page 1185,
or the microcontroller does not function properly. VDDA is the supply for all of the analog
circuitry on the device, including the clock circuitry.
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Figure 5-4. Power Architecture
Analog Circuits
I/O Buffers
LDO Voltage
Regulator
Internal
Logic and PLL
GND
GNDA
GNDA
VDDA
VDDA
VDDC
VDDC
+3.3V
GND
GND
GND VDD
VDD
5.2.5 Clock Control
System control determines the control of clocks in this part.
5.2.5.1 Fundamental Clock Sources
There are multiple clock sources for use in the microcontroller:
Precision Internal Oscillator (PIOSC). The precision internal oscillator is an on-chip clock
source that is the clock source the microcontroller uses during and following POR. It does not
require the use of any external components and provides a clock that is 16 MHz 1% at room
temperature and 3% across temperature. The PIOSC allows for a reduced system cost in
applications that require an accurate clock source. If the main oscillator is required, software
must enable the main oscillator following reset and allow the main oscillator to stabilize before
changing the clock reference. Regardless of whether or not the PIOSC is the source for the
system clock, the PIOSC can be configured to be the source for the ADC clock as well as the
baud clock for the UART and SSI, see System Control on page 214.
Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 5 MHz to 25 MHz
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(inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies
between 4 MHz to 25 MHz. The single-ended clock source range is as specified in Table
22-13 on page 1198. The supported crystals are listed in the XTAL bit field in the RCC register
(see page 239).
Low-Frequency Internal Oscillator (LFIOSC). The low-frequency internal oscillator is intended
for use during Deep-Sleep power-saving modes. The frequency can have wide variations; refer
to Low-Frequency Internal Oscillator (LFIOSC) Specifications on page 1199 for more details. This
power-savings mode benefits from reduced internal switching and also allows the MOSC to be
powered down. In addition, the PIOSC can be powered down while in Deep-Sleep mode.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL and the precision internal oscillator divided by four (4 MHz 1%).
The frequency of the PLL clock reference must be in the range of 5 MHz to 25 MHz (inclusive).
Table 5-3 on page 209 shows how the various clock sources can be used in a system.
Table 5-3. Clock Source Options
Used as SysClk? Drive PLL? Clock Source
BYPASS = 1, OSCSRC = 0x1 Yes BYPASS = 0, OSCSRC
= 0x1
Yes Precision Internal Oscillator
BYPASS = 1, OSCSRC = 0x2 Yes - No Precision Internal Oscillator divide by
4 (4 MHz 1%)
BYPASS = 1, OSCSRC = 0x0 Yes BYPASS = 0, OSCSRC
= 0x0
Yes Main Oscillator
BYPASS = 1, OSCSRC = 0x3 Yes - No Low-Frequency Internal Oscillator
(LFIOSC)
5.2.5.2 Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
Source of clocks in sleep and deep-sleep modes
System clock derived from PLL or other clock source
Enabling/disabling of oscillators and PLL
Clock divisors
Crystal input selection
Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the
RCC register is required, include another register access after writing the RCC register
and before writing the RCC2 register.
When transitioning the systemclock configuration to use the MOSCas the fundamental
clock source, the MOSCDIS bit must be set prior to reselecting the MOSCor an undefined
system clock configuration can sporadically occur.
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The configuration of the systemclock must not be changed while an EEPROMoperation
is in process. Software must wait until the WORKING bit in the EEPROM Done Status
(EEDONE) register is clear before making any changes to the system clock.
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. The ADC clock signal can be selected from
the PIOSC, the system clock if the PLL is disabled, or the PLL output divided down to 16 MHz if the
PLL is enabled. The PWM clock signal is a synchronous divide of the system clock to provide the
PWM circuit with more range (set with PWMDIV in RCC).
Note: If the ADC module is not using the PIOSC as the clock source, the system clock must be
at least 16 MHz.
Figure 5-5. Main Clock Tree
Main OSC
Precision
Internal OSC
(16 MHz)
Internal OSC
(30 kHz)
4
25
PWRDN
System Clock
MOSCDIS
a
IOSCDIS
a
e
USESYSDIV
a,d
PWMDW
a
USEPWMDIV
a
PWM Clock
OSCSRC
b,d
BYPASS
b,d
XTAL
a
PWRDN
b
2
PLL
(400 MHz)
DIV400
c
BYPASS
b,d
UART Baud Clock
CS
f
SSI Baud Clock
CS
f
ADC Clock
CS
f
SYSDIV
Note: a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit
USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2
bit, or [SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set.
f. Control provided by UARTCC, SSICC, and ADCCC register field.
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Communication Clock Sources
In addition to the main clock tree described above, the UART, and SSI modules all have a Clock
Control register in the peripheral's register map at offset 0xFC8 that can be used to select the clock
source for the module's baud clock. Users can choose between the system clock, which is the
default source for the baud clock, and the PIOSC. Note that there may be special considerations
when using the PIOSC as the baud clock. For more information, see the Clock Control register
description in the chapter describing the operation of the module.
Using the SYSDIV and SYSDIV2 Fields
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-4 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-3 on page 209.
Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field
TivaWare
Parameter
a
Frequency (BYPASS=1) Frequency(BYPASS=0) Divisor SYSDIV
SYSCTL_SYSDIV_1 Clock source frequency/1 reserved /1 0x0
SYSCTL_SYSDIV_3 Clock source frequency/3 66.67 MHz /3 0x2
SYSCTL_SYSDIV_4 Clock source frequency/4 50 MHz /4 0x3
SYSCTL_SYSDIV_11 Clock source frequency/11 18.18 MHz /11 0xA
SYSCTL_SYSDIV_12 Clock source frequency/12 16.67 MHz /12 0xB
SYSCTL_SYSDIV_13 Clock source frequency/13 15.38 MHz /13 0xC
SYSCTL_SYSDIV_14 Clock source frequency/14 14.29 MHz /14 0xD
SYSCTL_SYSDIV_15 Clock source frequency/15 13.33 MHz /15 0xE
SYSCTL_SYSDIV_16 Clock source frequency/16 12.5 MHz (default) /16 0xF
a. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library.
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 5-5 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 5-3 on page 209.
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Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
TivaWare Parameter
a
Frequency (BYPASS2=1) Frequency
(BYPASS2=0)
Divisor SYSDIV2
... ... ... ... ...
... ... ... ... ...
SYSCTL_SYSDIV_64 Clock source frequency/64 3.125 MHz /64 0x3F
a. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library.
To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along
with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In
this situation, the divisor is equivalent to the (SYSDIV2 encoding with SYSDIV2LSB appended) plus
one. Table 5-6 shows the frequency choices when DIV400 is set. When the DIV400 bit is clear,
SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table
5-5 on page 212.
Table 5-6. Examples of Possible System Clock Frequencies with DIV400=1
TivaWare Parameter
b
Frequency (BYPASS2=0)
a
Divisor SYSDIV2LSB SYSDIV2
- reserved /2 reserved 0x00
- reserved /3 0
0x01
- reserved /4 1
SYSCTL_SYSDIV_2_5 80 MHz /5 0
0x02
SYSCTL_SYSDIV_3 66.67 MHz /6 1
- reserved /7 0
0x03
SYSCTL_SYSDIV_4 50 MHz /8 1
SYSCTL_SYSDIV_4_5 44.44 MHz /9 0
0x04
SYSCTL_SYSDIV_5 40 MHz /10 1
... ... ... ... ...
SYSCTL_SYSDIV_63_5 3.15 MHz /127 0
0x3F
SYSCTL_SYSDIV_64 3.125 MHz /128 1
a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0.
b. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library.
5.2.5.3 Precision Internal Oscillator Operation (PIOSC)
The microcontroller powers up with the PIOSCrunning. If another clock source is desired, the PIOSC
must remain enabled as it is used for internal functions. The PIOSC can only be disabled during
Deep-Sleep mode. It can be powered down by setting the PIOSCPD bit in the DSLPCLKCFGregister.
The PIOSC generates a 16-MHz clock with a 1% accuracy at room temperatures. Across the
extended temperature range, the accuracy is 3%. At the factory, the PIOSC is set to 16 MHz at
roomtemperature, however, the frequency can be trimmed for other voltage or temperature conditions
using software in one of two ways:
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Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator
Calibration (PIOSCCAL) register.
User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As
the UT value increases, the generated period increases. To commit a new UT value, first set the
UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within
a few clock periods and is glitch free.
5.2.5.4 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals from 4 to 25 MHz.
The XTAL bit in the RCC register (see page 239) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
5.2.5.5 Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor, unless the DIV400 bit in the RCC2 register is set.
To configure the PIOSC to be the clock source for the main PLL, program the OSCRC2 field in the
Run-Mode Clock Configuration 2 (RCC2) register to be 0x1.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the PLL Frequency n
(PLLFREQn) registers (see page 255). The internal translation provides a translation within 1%of
the targeted PLL VCO frequency. Table 22-14 on page 1198 shows the actual PLL frequency and
error for a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 239)
describes the available crystal choices and default programming of the PLLFREQn registers. Any
time the XTAL field changes, the new settings are translated and the internal PLL settings are
updated.
5.2.5.6 PLL Modes
Normal: The PLL multiplies the input clock reference and drives the output.
Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 239 and page 246).
5.2.5.7 PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is T
READY
(see Table
22-13 on page 1198). During the relock time, the affected PLL is not usable as a clock reference.
Software can poll the LOCK bit in the PLL Status (PLLSTAT) register to determine when the PLL
has locked.
The PLL is changed by one of the following:
Change to the XTAL value in the RCC registerwrites of the same value do not cause a relock.
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Change in the PLL from Power-Down to Normal mode.
A counter clocked by the system clock is used to measure the T
READY
requirement. The down
counter is set to 0x200 if the PLL is powering up. If the M or N values in the PLLFREQn registers
are changed, the counter is set to 0xC0. Hardware is provided to keep the PLL from being used as
a system clock until the T
READY
condition is met after one of the two changes above. It is the user's
responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register
is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the microcontroller fromthe oscillator selected by the RCC/RCC2
register until the main PLL is stable (T
READY
time met), after which it changes to the PLL. Software
can use many methods to ensure that the systemis clocked fromthe main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
5.2.5.8 Main Oscillator Verification Circuit
The clock control includes circuitry to ensure that the main oscillator is running at the appropriate
frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside
of the allowable band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, and if the MOSCIM bit in the MOSCCTL register
is clear, then the following sequence is performed by the hardware:
1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.
2. The system clock is switched from the main oscillator to the PIOSC.
3. An internal power-on reset is initiated.
4. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence.
if the MOSCIM bit in the MOSCCTL register is set, then the following sequence is performed by the
hardware:
1. The system clock is switched from the main oscillator to the PIOSC.
2. The MOFRIS bit in the RIS register is set to indicate a MOSC failure.
5.2.6 System Control
For power-savings purposes, the peripheral-specific RCGCx, SCGCx, and DCGCx registers (for
example, RCGCWD) control the clock gating logic for that peripheral or block in the system while
the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. These registers are located
in the System Control register map starting at offsets 0x600, 0x700, and 0x800, respectively. There
must be a delay of 3 system clocks after a peripheral module clock is enabled in the RCGC register
before any module registers are accessed.
Important: To support legacy software, the RCGCn, SCGCn, and DCGCn registers are available
at offsets 0x100 - 0x128. A write to any of these legacy registers also writes the
corresponding bit in the peripheral-specific RCGCx, SCGCx, and DCGCx registers.
Software must use the peripheral-specific registers to support modules that are not
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System Control
present in the legacy registers. It is recommended that new software use the new
registers and not rely on legacy operation.
If software uses a peripheral-specific register to write a legacy peripheral (such as
TIMER0), the write causes proper operation, but the value of that bit is not reflected in
the legacy register. Any bits that are changed by writing to a legacy register can be
read back correctly with a read of the legacy register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
There are three levels of operation for the microcontroller defined as:
Run mode
Sleep mode
Deep-Sleep mode
The following sections describe the different modes in detail.
Caution If the Cortex-M4F Debug Access Port (DAP) has been enabled, and the device wakes from
a lowpower sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their Run mode confguration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or fash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
systemfroma WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
5.2.6.1 Run Mode
In Run mode, the microcontroller actively executes code. Run mode provides normal operation of
the processor and all of the peripherals that are currently enabled by the the peripheral-specific
RCGC registers. The system clock can be any of the available clock sources including the PLL.
5.2.6.2 Sleep Mode
In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and
the memory subsystemare not clocked and therefore no longer execute code. Sleep mode is entered
by the Cortex-M4F core executing a WFI (Wait for Interrupt) instruction. Any properly configured
interrupt event in the system brings the processor back into Run mode. See Power
Management on page 103 for more details.
Peripherals are clocked that are enabled in the peripheral-specific SCGC registers when auto-clock
gating is enabled (see the RCC register) or the the peripheral-specific RCGC registers when the
auto-clock gating is disabled. The system clock has the same source and frequency as that during
Run mode.
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Additional sleep modes are available that lower the power consumption of the SRAM and Flash
memory. However, the lower power consumption modes have slower sleep and wake-up times,
see Dynamic Power Management on page 217 for more information.
Important: Before executing the WFI instruction, software must confirm that the EEPROM is not
busy by checking to see that the WORKING bit in the EEPROMDone Status (EEDONE)
register is clear.
5.2.6.3 Deep-Sleep Mode
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered on
request fromthe code. Deep-Sleep mode is entered by first setting the SLEEPDEEP bit in the System
Control (SYSCTRL) register (see page 155) and then executing a WFI instruction. Any properly
configured interrupt event in the system brings the processor back into Run mode. See Power
Management on page 103 for more details.
The Cortex-M4F processor core and the memory subsystem are not clocked in Deep-Sleep mode.
Peripherals are clocked that are enabled in the the peripheral-specific DCGC registers when
auto-clock gating is enabled (see the RCC register) or the peripheral-specific RCGC registers when
auto-clock gating is disabled. The system clock source is specified in the DSLPCLKCFG register.
When the DSLPCLKCFGregister is used, the internal oscillator source is powered up, if necessary,
and other clocks are powered down. If the PLL is running at the time of the WFI instruction, hardware
powers the PLL down and overrides the SYSDIV field of the active RCC/RCC2 register, to be
determined by the DSDIVORIDE setting in the DSLPCLKCFGregister, up to /16 or /64 respectively.
USB PLL is not powered down by execution of WFI instruction. When the Deep-Sleep exit event
occurs, hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration.
If the PIOSC is used as the PLL reference clock source, it may continue to provide the clock during
Deep-Sleep. See page 250.
Important: Before executing the WFI instruction, software must confirm that the EEPROM is not
busy by checking to see that the WORKING bit in the EEPROMDone Status (EEDONE)
register is clear.
To provide the lowest possible Deep-Sleep power consumption as well the ability to wake the
processor from a peripheral without reconfiguring the peripheral for a change in clock, some of the
communications modules have a Clock Control register at offset 0xFC8 in the module register space.
The CS field in the Clock Control register allows the user to select the PIOSC as the clock source
for the module's baud clock. When the microcontroller enters Deep-Sleep mode, the PIOSCbecomes
the source for the module clock as well, which allows the transmit and receive FIFOs to continue
operation while the part is in Deep-Sleep. Figure 5-6 on page 217 shows howthe clocks are selected.
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System Control
Figure 5-6. Module Clock Selection
Deep Sleep
Module Clock
System Clock
Clock Control Register
PIOSC
Baud Clock
0
0
1
1
Additional deep-sleep modes are available that lower the power consumption of the SRAM and
Flash memory. However, the lower power consumption modes have slower deep-sleep and wake-up
times, see Dynamic Power Management on page 217 for more information.
5.2.6.4 Dynamic Power Management
In addition to the Sleep and Deep-Sleep modes and the clock gating for the on-chip modules, there
are several additional power mode options that allow the LDO, Flash memory, and SRAM into
different levels of power savings while in Sleep or Deep-Sleep modes. Note that these features may
not be available on all devices; the System Properties (SYSPROP) register provides information
on whether a mode is supported on a given MCU. The following registers provides these capabilities:
LDO Sleep Power Control (LDOSPCTL): controls the LDO value in Sleep mode
LDO Deep-Sleep Power Control (LDODPCTL): controls the LDO value in Deep-Sleep mode
LDO Sleep Power Calibration (LDOSPCAL): provides factory recommendations for the LDO
value in Sleep mode
LDO Deep-Sleep Power Calibration (LDODPCAL): provides factory recommendations for the
LDO value in Deep-Sleep mode
Sleep Power Configuration (SLPPWRCFG): controls the power saving modes for Flash memory
and SRAM in Sleep mode
Deep-Sleep Power Configuration (DSLPPWRCFG): controls the power saving modes for Flash
memory and SRAM in Deep-sleep mode
Deep-Sleep Clock Configuration (DSLPCLKCFG): controls the clocking in Deep-sleep mode
Sleep / Deep-Sleep Power Mode Status (SDPMST): provides status information on the various
power saving events
LDO Power Control
Note: While the device is connected through JTAG, the LDO control settings for Sleep or
Deep-Sleep are not available and will not be applied.
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The user can dynamically request to raise or lower the LDO voltage level to trade-off
power/performance using either the LDOSPCTL register (see page 262) or the LDODPCTL register
(see page 265). When lowering the LDOlevel, software must configure the systemclock for the lower
LDO value in RCC/RCC2 for Sleep mode and in DSLPCLKCFG for Deep-Sleep mode before
requesting the LDO to lower.
The LDO Power Calibration registers, LDOSPCAL and LDODPCAL, provide suggested values for
the LDO in the various modes. If software requests an LDO value that is too low or too high, the
value is not accepted and an error is reported in the SDPMST register.
The table below shows the maximum system clock frequency and PIOSC frequency with respect
to the configured LDO voltage.
PIOSC Maximum System Clock Frequency Operating Voltage (LDO)
16 MHz 80 MHz 1.2
16 MHz 20 MHz 0.9
Flash Memory and SRAM Power Control
During Sleep or Deep-Sleep mode, Flash memory can be in either the default active mode or the
low power mode; SRAM can be in the default active mode, the standby mode, or the low power
mode. The active mode in each case provides the fastest times to sleep and wake up, but consumes
more power. The lowpower mode provides the lowest power consumption, but takes longer to sleep
and wake up.
The available options for SRAM include no power configuration, which operates in the same way
that legacy devices operate, Retention mode, and Retention mode with lower SRAM voltage. The
no power configuration mode provides the fastest sleep and wake-up times, but consumes the most
power while in Sleep or Deep-Sleep mode. The SRAM Retention mode with lower SRAM voltage
provides the lowest power consumption, but has the longest sleep and wake-up times. These modes
can be independently configured for Flash memory and SRAM using the SLPPWRCFG and
DSLPPWRCFG registers.
The following power saving options are available in Sleep and Deep-Sleep modes:
The clocks can be gated according to the settings in the the peripheral-specific SCGC or DCGC
registers.
In Deep-Sleep mode, the clock source can be changed and the PIOSC can be powered off (if
no active peripheral requires it) using the DSLPCLKCFGregister. These options are not available
for Sleep mode.
The LDO voltage can be changed using the LDOSPCTL or LDODPCTL register.
The Flash memory can be put into low power mode.
The SRAM can be put into standby or low power mode.
The SDPMST register provides results on the Dynamic Power Management command issued. It
also has some real time status that can be viewed by a debugger or the core if it is running. These
events do not trigger an interrupt and are meant to provide information to help tune software for
power management. The status register gets written at the beginning of every Dynamic Power
Management event request that provides error checking. There is no mechanism to clear the bits;
they are overwritten on the next event. The real time data is real time and there is no event to register
that information.
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The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register, thereby configuring the microcontroller to run off a "raw" clock source
and allowing for the new PLL configuration to be validated before switching the system clock
to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
5.4 Register Map
Table 5-7 on page 219 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Additional Flash and ROM registers defined in the System Control register space are
described in the Internal Memory on page 467.
Table 5-7. System Control Register Map
See
page
System Control Registers
225 Device Identification 0 - RO DID0 0x000
227 Device Identification 1 - RO DID1 0x004
229 Brown-Out Reset Control 0x0000.7FFF R/W PBORCTL 0x030
230 Raw Interrupt Status 0x0000.0000 RO RIS 0x050
232 Interrupt Mask Control 0x0000.0000 R/W IMC 0x054
234 Masked Interrupt Status and Clear 0x0000.0000 R/W1C MISC 0x058
237 Reset Cause - R/W RESC 0x05C
239 Run-Mode Clock Configuration 0x078E.3AD1 R/W RCC 0x060
244 GPIO High-Performance Bus Control 0x0000.7E00 R/W GPIOHBCTL 0x06C
246 Run-Mode Clock Configuration 2 0x07C0.6810 R/W RCC2 0x070
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Table 5-7. System Control Register Map (continued)
See
page
249 Main Oscillator Control 0x0000.0000 R/W MOSCCTL 0x07C
250 Deep Sleep Clock Configuration 0x0780.0000 R/W DSLPCLKCFG 0x144
252 System Properties 0x0000.1D31 RO SYSPROP 0x14C
254 Precision Internal Oscillator Calibration 0x0000.0000 R/W PIOSCCAL 0x150
255 PLL Frequency 0 0x0000.0032 RO PLLFREQ0 0x160
256 PLL Frequency 1 0x0000.0001 RO PLLFREQ1 0x164
257 PLL Status 0x0000.0000 RO PLLSTAT 0x168
258 Sleep Power Configuration 0x0000.0000 R/W SLPPWRCFG 0x188
260 Deep-Sleep Power Configuration 0x0000.0000 R/W DSLPPWRCFG 0x18C
262 LDO Sleep Power Control 0x0000.0018 R/W LDOSPCTL 0x1B4
264 LDO Sleep Power Calibration 0x0000.1818 RO LDOSPCAL 0x1B8
265 LDO Deep-Sleep Power Control 0x0000.0012 R/W LDODPCTL 0x1BC
267 LDO Deep-Sleep Power Calibration 0x0000.1212 RO LDODPCAL 0x1C0
268 Sleep / Deep-Sleep Power Mode Status 0x0000.0000 RO SDPMST 0x1CC
271 Watchdog Timer Peripheral Present 0x0000.0003 RO PPWD 0x300
272 16/32-Bit General-Purpose Timer Peripheral Present 0x0000.003F RO PPTIMER 0x304
274 General-Purpose Input/Output Peripheral Present 0x0000.007F RO PPGPIO 0x308
277 Micro Direct Memory Access Peripheral Present 0x0000.0001 RO PPDMA 0x30C
278 Hibernation Peripheral Present 0x0000.0000 RO PPHIB 0x314
279
Universal Asynchronous Receiver/Transmitter Peripheral
Present
0x0000.00FF RO PPUART 0x318
281 Synchronous Serial Interface Peripheral Present 0x0000.000F RO PPSSI 0x31C
283 Inter-Integrated Circuit Peripheral Present 0x0000.003F RO PPI2C 0x320
285 Universal Serial Bus Peripheral Present 0x0000.0000 RO PPUSB 0x328
286 Controller Area Network Peripheral Present 0x0000.0003 RO PPCAN 0x334
287 Analog-to-Digital Converter Peripheral Present 0x0000.0003 RO PPADC 0x338
288 Analog Comparator Peripheral Present 0x0000.0001 RO PPACMP 0x33C
289 Pulse Width Modulator Peripheral Present 0x0000.0003 RO PPPWM 0x340
290 Quadrature Encoder Interface Peripheral Present 0x0000.0003 RO PPQEI 0x344
291 EEPROM Peripheral Present 0x0000.0001 RO PPEEPROM 0x358
292
32/64-Bit Wide General-Purpose Timer Peripheral
Present
0x0000.003F RO PPWTIMER 0x35C
294 Watchdog Timer Software Reset 0x0000.0000 R/W SRWD 0x500
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296 16/32-Bit General-Purpose Timer Software Reset 0x0000.0000 R/W SRTIMER 0x504
298 General-Purpose Input/Output Software Reset 0x0000.0000 R/W SRGPIO 0x508
300 Micro Direct Memory Access Software Reset 0x0000.0000 R/W SRDMA 0x50C
301
Universal Asynchronous Receiver/Transmitter Software
Reset
0x0000.0000 R/W SRUART 0x518
303 Synchronous Serial Interface Software Reset 0x0000.0000 R/W SRSSI 0x51C
305 Inter-Integrated Circuit Software Reset 0x0000.0000 R/W SRI2C 0x520
307 Controller Area Network Software Reset 0x0000.0000 R/W SRCAN 0x534
309 Analog-to-Digital Converter Software Reset 0x0000.0000 R/W SRADC 0x538
311 Analog Comparator Software Reset 0x0000.0000 R/W SRACMP 0x53C
312 Pulse Width Modulator Software Reset 0x0000.0000 R/W SRPWM 0x540
314 Quadrature Encoder Interface Software Reset 0x0000.0000 R/W SRQEI 0x544
316 EEPROM Software Reset 0x0000.0000 R/W SREEPROM 0x558
317 32/64-Bit Wide General-Purpose Timer Software Reset 0x0000.0000 R/W SRWTIMER 0x55C
319 Watchdog Timer Run Mode Clock Gating Control 0x0000.0000 R/W RCGCWD 0x600
320
16/32-Bit General-Purpose Timer Run Mode Clock Gating
Control
0x0000.0000 R/W RCGCTIMER 0x604
322
General-Purpose Input/Output Run Mode Clock Gating
Control
0x0000.0000 R/W RCGCGPIO 0x608
324
Micro Direct Memory Access Run Mode Clock Gating
Control
0x0000.0000 R/W RCGCDMA 0x60C
325
Universal Asynchronous Receiver/Transmitter Run Mode
Clock Gating Control
0x0000.0000 R/W RCGCUART 0x618
327
Synchronous Serial Interface Run Mode Clock Gating
Control
0x0000.0000 R/W RCGCSSI 0x61C
329 Inter-Integrated Circuit Run Mode Clock Gating Control 0x0000.0000 R/W RCGCI2C 0x620
331 Controller Area Network Run Mode Clock Gating Control 0x0000.0000 R/W RCGCCAN 0x634
332
Analog-to-Digital Converter Run Mode Clock Gating
Control
0x0000.0000 R/W RCGCADC 0x638
333 Analog Comparator Run Mode Clock Gating Control 0x0000.0000 R/W RCGCACMP 0x63C
334 Pulse Width Modulator Run Mode Clock Gating Control 0x0000.0000 R/W RCGCPWM 0x640
335
Quadrature Encoder Interface Run Mode Clock Gating
Control
0x0000.0000 R/W RCGCQEI 0x644
336 EEPROM Run Mode Clock Gating Control 0x0000.0000 R/W RCGCEEPROM 0x658
337
32/64-Bit Wide General-Purpose Timer Run Mode Clock
Gating Control
0x0000.0000 R/W RCGCWTIMER 0x65C
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See
page
339 Watchdog Timer Sleep Mode Clock Gating Control 0x0000.0000 R/W SCGCWD 0x700
340
16/32-Bit General-Purpose Timer Sleep Mode Clock
Gating Control
0x0000.0000 R/W SCGCTIMER 0x704
342
General-Purpose Input/Output Sleep Mode Clock Gating
Control
0x0000.0000 R/W SCGCGPIO 0x708
344
Micro Direct Memory Access Sleep Mode Clock Gating
Control
0x0000.0000 R/W SCGCDMA 0x70C
345
Universal Asynchronous Receiver/Transmitter Sleep
Mode Clock Gating Control
0x0000.0000 R/W SCGCUART 0x718
347
Synchronous Serial Interface Sleep Mode Clock Gating
Control
0x0000.0000 R/W SCGCSSI 0x71C
349 Inter-Integrated Circuit Sleep Mode Clock Gating Control 0x0000.0000 R/W SCGCI2C 0x720
351
Controller Area Network Sleep Mode Clock Gating
Control
0x0000.0000 R/W SCGCCAN 0x734
352
Analog-to-Digital Converter Sleep Mode Clock Gating
Control
0x0000.0000 R/W SCGCADC 0x738
353 Analog Comparator Sleep Mode Clock Gating Control 0x0000.0000 R/W SCGCACMP 0x73C
354 Pulse Width Modulator Sleep Mode Clock Gating Control 0x0000.0000 R/W SCGCPWM 0x740
355
Quadrature Encoder Interface Sleep Mode Clock Gating
Control
0x0000.0000 R/W SCGCQEI 0x744
356 EEPROM Sleep Mode Clock Gating Control 0x0000.0000 R/W SCGCEEPROM 0x758
357
32/64-Bit Wide General-Purpose Timer Sleep Mode Clock
Gating Control
0x0000.0000 R/W SCGCWTIMER 0x75C
359 Watchdog Timer Deep-Sleep Mode Clock Gating Control 0x0000.0000 R/W DCGCWD 0x800
360
16/32-Bit General-Purpose Timer Deep-Sleep Mode
0x0000.0000 R/W DCGCTIMER 0x804
362
General-Purpose Input/Output Deep-Sleep Mode Clock
Gating Control
0x0000.0000 R/W DCGCGPIO 0x808
364
Micro Direct Memory Access Deep-Sleep Mode Clock
Gating Control
0x0000.0000 R/W DCGCDMA 0x80C
365
Universal Asynchronous Receiver/Transmitter
Deep-Sleep Mode Clock Gating Control
0x0000.0000 R/W DCGCUART 0x818
367
Synchronous Serial Interface Deep-Sleep Mode Clock
Gating Control
0x0000.0000 R/W DCGCSSI 0x81C
369
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating
Control
0x0000.0000 R/W DCGCI2C 0x820
371
Controller Area Network Deep-Sleep Mode Clock Gating
Control
0x0000.0000 R/W DCGCCAN 0x834
372
Analog-to-Digital Converter Deep-Sleep Mode Clock
Gating Control
0x0000.0000 R/W DCGCADC 0x838
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373
Analog Comparator Deep-Sleep Mode Clock Gating
Control
0x0000.0000 R/W DCGCACMP 0x83C
374
Pulse Width Modulator Deep-Sleep Mode Clock Gating
Control
0x0000.0000 R/W DCGCPWM 0x840
375
Quadrature Encoder Interface Deep-Sleep Mode Clock
Gating Control
0x0000.0000 R/W DCGCQEI 0x844
376 EEPROM Deep-Sleep Mode Clock Gating Control 0x0000.0000 R/W DCGCEEPROM 0x858
377
32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode
0x0000.0000 R/W DCGCWTIMER 0x85C
379 Watchdog Timer Peripheral Ready 0x0000.0000 RO PRWD 0xA00
380 16/32-Bit General-Purpose Timer Peripheral Ready 0x0000.0000 RO PRTIMER 0xA04
382 General-Purpose Input/Output Peripheral Ready 0x0000.0000 RO PRGPIO 0xA08
384 Micro Direct Memory Access Peripheral Ready 0x0000.0000 RO PRDMA 0xA0C
385
Universal Asynchronous Receiver/Transmitter Peripheral
Ready
0x0000.0000 RO PRUART 0xA18
387 Synchronous Serial Interface Peripheral Ready 0x0000.0000 RO PRSSI 0xA1C
389 Inter-Integrated Circuit Peripheral Ready 0x0000.0000 RO PRI2C 0xA20
391 Controller Area Network Peripheral Ready 0x0000.0000 RO PRCAN 0xA34
392 Analog-to-Digital Converter Peripheral Ready 0x0000.0000 RO PRADC 0xA38
393 Analog Comparator Peripheral Ready 0x0000.0000 RO PRACMP 0xA3C
394 Pulse Width Modulator Peripheral Ready 0x0000.0000 RO PRPWM 0xA40
395 Quadrature Encoder Interface Peripheral Ready 0x0000.0000 RO PRQEI 0xA44
396 EEPROM Peripheral Ready 0x0000.0000 RO PREEPROM 0xA58
397 32/64-Bit Wide General-Purpose Timer Peripheral Ready 0x0000.0000 RO PRWTIMER 0xA5C
System Control Legacy Registers
399 Device Capabilities 0 0x007F.007F RO DC0 0x008
401 Device Capabilities 1 0x1333.2FBF RO DC1 0x010
404 Device Capabilities 2 0x030F.F337 RO DC2 0x014
407 Device Capabilities 3 0xBFFF.8FFF RO DC3 0x018
411 Device Capabilities 4 0x0004.F07F RO DC4 0x01C
414 Device Capabilities 5 0x0730.00FF RO DC5 0x020
416 Device Capabilities 6 0x0000.0000 RO DC6 0x024
417 Device Capabilities 7 0xFFFF.FFFF RO DC7 0x028
420 Device Capabilities 8 0x0FFF.0FFF RO DC8 0x02C
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423 Software Reset Control 0 0x0000.0000 RO SRCR0 0x040
430 Run Mode Clock Gating Control Register 0 0x0000.0040 RO RCGC0 0x100
440 Sleep Mode Clock Gating Control Register 0 0x0000.0040 RO SCGC0 0x110
448 Deep Sleep Mode Clock Gating Control Register 0 0x0000.0040 RO DCGC0 0x120
451 Deep-Sleep Mode Clock Gating Control Register 1 0x0000.0000 RO DCGC1 0x124
454 Deep Sleep Mode Clock Gating Control Register 2 0x0000.0000 RO DCGC2 0x128
456 Device Capabilities 9 0x00FF.00FF RO DC9 0x190
458 Non-Volatile Memory Information 0x0000.0001 RO NVMSTAT 0x1A0
5.5 System Control Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000. Registers
provided for legacy software support only are listed in System Control Legacy Register
Descriptions on page 398.
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System Control
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the microcontroller. Each microcontroller is uniquely identified
by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1
register. The MAJOR and MINOR bit fields indicate the die revision number. Combined, the MAJOR
and MINOR bit fields indicate the part revision number.
Part Revision Die Revision MINOR Bitfield Value MAJOR Bitfield Value
1 A0 0x0 0x0
2 A1 0x1 0x0
3 A2 0x2 0x0
4 A3 0x3 0x0
5 B0 0x0 0x1
6 B1 0x1 0x1
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLASS reserved VER reserved
1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MINOR MAJOR
- - - - - - - - - - - - - - - - Reset
0 RO reserved 31
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Description Value
Second version of the DID0 register format. 0x1
0x01 RO VER 30:28
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Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all microcontrollers in a particular product line.
The CLASS field value is changed for new product lines, for changes in
fab process (for example, a remap or shrink), or any case where the
MAJOR or MINOR fields require differentiation fromprior microcontrollers.
The value of the CLASS field is encoded as follows (all other encodings
are reserved):
Description Value
Tiva
TM4C123x microcontrollers 0x05

0x05 RO CLASS 23:16
Major Die Revision
This field specifies the major revision number of the microcontroller.
The major revision reflects changes to base layers of the design. This
field is encoded as follows:
Description Value
Revision A (initial device) 0x0
Revision B (first base layer revision) 0x1
Revision C (second base layer revision) 0x2
and so on.
- RO MAJOR 15:8
Minor Die Revision
This field specifies the minor revision number of the microcontroller.
The minor revision reflects changes to the metal layers of the design.
The MINOR field value is reset when the MAJOR field is changed. This
field is numeric and is encoded as follows:
Description Value
Initial device, or a major revision update. 0x0
First metal layer change. 0x1
Second metal layer change. 0x2
and so on.
- RO MINOR 7:0
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System Control
Register 2: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the
DID0 register and the PARTNO field in the DID1 register.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PARTNO FAM VER
- - - - - - - - 0 0 0 0 1 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
QUAL ROHS PKG TEMP reserved PINCOUNT
- - 1 - - - - - 0 0 0 0 0 - - - Reset
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Description Value
Initial DID1 register format definition, indicating a Stellaris
LM3Snnn device.
0x0
Second version of the DID1 register format. 0x1
0x1 RO VER 31:28
Family
This field provides the family identification of the device within the product
portfolio. The value is encoded as follows (all other encodings are
reserved):
Description Value
Tiva C Series microcontrollers and legacy Stellaris
microcontrollers, that is, all devices with external part numbers
starting with TM4C, LM4F or LM3S.
0x0
0x0 RO FAM 27:24
Part Number
This field provides the part number of the device within the family. The
reset value shown indicates the TM4C123AH6PM microcontroller.
- RO PARTNO 23:16
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Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Description Value
reserved 0x0
reserved 0x1
100-pin package 0x2
64-pin package 0x3
144-pin package 0x4
157-pin package 0x5
- RO PINCOUNT 15:13
0 RO reserved 12:8
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Description Value
Reserved 0x0
Industrial temperature range (-40C to 85C) 0x1
Extended temperature range (-40C to 105C) 0x2
- RO TEMP 7:5
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Description Value
Reserved 0x0
LQFP package 0x1
BGA package 0x2
- RO PKG 4:3
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
1 RO ROHS 2
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Description Value
Engineering Sample (unqualified) 0x0
Pilot Production (unqualified) 0x1
Fully Qualified 0x2
- RO QUAL 1:0
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System Control
Register 3: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Note: The BOR voltage values and center points are based on simulation only. These values are
yet to be characterized and are subject to change.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved BOR1 BOR0 reserved
RO R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:3
VDD under BOR0 Event Action
The VDD BOR0 trip value is 3.02V +/- 90mv.
Description Value
A BOR0 event causes an interrupt to be generated in the
interrupt controller.
0
A BOR0 event causes a reset of the microcontroller. 1
1 R/W BOR0 2
VDD under BOR1 Event Action
The VDD BOR1 trip value is 2.88V +/- 90mv.
Description Value
A BOR1 event causes an interrupt to be generated to the
0
A BOR1 event causes a reset of the microcontroller. 1
1 R/W BOR1 1
0 RO reserved 0
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Register 4: Raw Interrupt Status (RIS), offset 0x050
This register indicates the status for systemcontrol raw interrupts. An interrupt is sent to the interrupt
controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1
to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt
status bit.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved BOR1RIS reserved MOFRIS reserved PLLLRIS reserved MOSCPUPRIS reserved VDDARIS BOR0RIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
VDD under BOR0 Raw Interrupt Status
Description Value
A VDD BOR0 condition is currently active. 1
A VDD BOR0 condition is not currently active. 0
Note the BOR0 bit in the PBORCTL register must be cleared to cause
an interrupt due to a BOR0 Event.
This bit is cleared by writing a 1 to the BOR0MIS bit in the MISC register.
0 RO BOR0RIS 11
VDDA Power OK Event Raw Interrupt Status
Description Value
VDDA is at an appropriate functional voltage. 1
VDDA power is not at its appropriate functional voltage. 0
This bit is cleared by writing a 1 to the VDDAMIS bit in the MISC register.
0 RO VDDARIS 10
0 RO reserved 9
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System Control
MOSC Power Up Raw Interrupt Status
Description Value
Sufficient time has passed for the MOSC to reach the expected
frequency. The value for this power-up time is indicated by
T
MOSC_START
.
1
Sufficient time has not passed for the MOSC to reach the
expected frequency.
0
This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC
register.
0 RO MOSCPUPRIS 8
0 RO reserved 7
PLL Lock Raw Interrupt Status
Description Value
The PLL timer has reached T
READY
indicating that sufficient time
has passed for the PLL to lock.
1
The PLL timer has not reached T
READY
. 0
This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register.
0 RO PLLLRIS 6
0x0 RO reserved 5:4
Main Oscillator Failure Raw Interrupt Status
Description Value
The MOSCIM bit in the MOSCCTL register is set and the main
oscillator has failed.
1
The main oscillator has not failed. 0
This bit is cleared by writing a 1 to the MOFMIS bit in the MISC register.
0 RO MOFRIS 3
0 RO reserved 2
VDD under BOR1 Raw Interrupt Status
Description Value
A VDDS BOR1 condition is currently active. 1
A VDDS BOR1 condition is not currently active. 0
Note the BOR1 bit in the PBORCTL register must be cleared to cause
an interrupt due to a BOR1 Event.
This bit is cleared by writing a 1 to the BOR1MIS bit in the MISC register.
0 RO BOR1RIS 1
0 RO reserved 0
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Register 5: Interrupt Mask Control (IMC), offset 0x054
This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by
a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the
corresponding bit in this register is set.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved BOR1IM reserved MOFIM reserved PLLLIM reserved MOSCPUPIM reserved VDDAIM BOR0IM reserved
RO R/W RO R/W RO RO R/W RO R/W RO R/W R/W RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
VDD under BOR0 Interrupt Mask
Description Value
An interrupt is sent to the interrupt controller when the BOR0RIS
bit in the RIS register is set.
1
The BOR0RIS interrupt is suppressed and not sent to the
0
0 R/W BOR0IM 11
VDDA Power OK Interrupt Mask
Description Value
An interrupt is sent to the interrupt controller when the VDDARIS
1
The VDDARIS interrupt is suppressed and not sent to the
0
0 R/W VDDAIM 10
0 RO reserved 9
MOSC Power Up Interrupt Mask
Description Value
An interrupt is sent to the interrupt controller when the
MOSCPUPRIS bit in the RIS register is set.
1
The MOSCPUPRIS interrupt is suppressed and not sent to the
0
0 R/W MOSCPUPIM 8
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System Control
0 RO reserved 7
PLL Lock Interrupt Mask
Description Value
An interrupt is sent to the interrupt controller when the PLLLRIS
1
The PLLLRIS interrupt is suppressed and not sent to the
0
0 R/W PLLLIM 6
0x0 RO reserved 5:4
Main Oscillator Failure Interrupt Mask
Description Value
An interrupt is sent to the interrupt controller when the MOFRIS
1
The MOFRIS interrupt is suppressed and not sent to the interrupt
controller.
0
0 R/W MOFIM 3
0 RO reserved 2
VDD under BOR1 Interrupt Mask
Description Value
An interrupt is sent to the interrupt controller when the BOR1RIS
1
The BOR1RIS interrupt is suppressed and not sent to the
0
0 R/W BOR1IM 1
0 RO reserved 0
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Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt in the
Raw Interrupt Status (RIS) register. All of the bits are R/W1C, thus writing a 1 to a bit clears the
corresponding raw interrupt bit in the RIS register (see page 230).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved BOR1MIS reserved MOFMIS reserved PLLLMIS reserved MOSCPUPMIS reserved VDDAMIS BOR0MIS reserved
RO R/W1C RO RO RO RO R/W1C RO R/W1C RO R/W1C R/W1C RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
VDD under BOR0 Masked Interrupt Status
Description Value
When read, a 1 indicates that an unmasked interrupt was
signaled because of a BOR0 condition.
Writing a 1 to this bit clears it and also the BOR0RIS bit in the
RIS register.
1
When read, a 0 indicates that a BOR0 condition has not
occurred.
A write of 0 has no effect on the state of this bit.
0
0 R/W1C BOR0MIS 11
VDDA Power OK Masked Interrupt Status
Description Value
signaled because VDDA was below the proper functioning
voltage.
Writing a 1 to this bit clears it and also the VDDARIS bit in the
RIS register.
1
When read, a 0 indicates that VDDA power is good.
0
0 R/W1C VDDAMIS 10
0 RO reserved 9
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System Control
MOSC Power Up Masked Interrupt Status
Description Value
signaled because sufficient time has passed for the MOSCPLL
to lock.
Writing a 1 to this bit clears it and also the MOSCPUPRIS bit in
the RIS register.
1
When read, a 0 indicates that sufficient time has not passed for
the MOSC PLL to lock.
0
0 R/W1C MOSCPUPMIS 8
0 RO reserved 7
PLL Lock Masked Interrupt Status
Description Value
signaled because sufficient time has passed for the PLL to lock.
Writing a 1 to this bit clears it and also the PLLLRIS bit in the
RIS register.
1
When read, a 0 indicates that sufficient time has not passed for
the PLL to lock.
0
0 R/W1C PLLLMIS 6
0x0 RO reserved 5:4
Main Oscillator Failure Masked Interrupt Status
Description Value
signaled because the main oscillator failed.
Writing a 1 to this bit clears it and also the MOFRIS bit in the
RIS register.
1
When read, a 0 indicates that the main oscillator has not failed.
0
0 RO MOFMIS 3
0 RO reserved 2
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VDD under BOR1 Masked Interrupt Status
Description Value
signaled because of a BOR1 condition.
Writing a 1 to this bit clears it and also the BOR1RIS bit in the
RIS register.
1
When read, a 0 indicates that a BOR1 condition has not
occurred.
0
0 R/W1C BOR1MIS 1
0 RO reserved 0
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System Control
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an power-on reset is the cause, in which
case, all bits other than POR in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MOSCFAIL reserved
- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EXT POR BOR WDT0 SW WDT1 reserved
R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO Type
- - - - - - 0 0 0 0 0 0 0 0 0 0 Reset
MOSC Failure Reset
Description Value
When read, this bit indicates that the MOSCcircuit was enabled
for clock validation and failed while the MOSCIM bit in the
MOSCCTL register is clear, generating a reset event.
1
When read, this bit indicates that a MOSC failure has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
0
- R/W MOSCFAIL 16
Watchdog Timer 1 Reset
Description Value
When read, this bit indicates that Watchdog Timer 1 timed out
and generated a reset.
1
When read, this bit indicates that Watchdog Timer 1 has not
0
- R/W WDT1 5
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Software Reset
Description Value
When read, this bit indicates that a software reset has caused
a reset event.
1
When read, this bit indicates that a software reset has not
0
- R/W SW 4
Watchdog Timer 0 Reset
Description Value
When read, this bit indicates that Watchdog Timer 0 timed out
and generated a reset.
1
When read, this bit indicates that Watchdog Timer 0 has not
0
- R/W WDT0 3
Brown-Out Reset
Description Value
When read, this bit indicates that a brown-out (BOR0 or BOR1)
reset has caused a reset event.
1
When read, this bit indicates that a brown-out (BOR0 or BOR1)
reset has not generated a reset since the previous power-on
reset.
0
- R/W BOR 2
Power-On Reset
Description Value
When read, this bit indicates that a power-on reset has caused
a reset event.
1
When read, this bit indicates that a power-on reset has not
generated a reset.
0
- R/W POR 1
External Reset
Description Value
When read, this bit indicates that an external reset (RST
assertion) has caused a reset event.
1
When read, this bit indicates that an external reset (RST
assertion) has not caused a reset event since the previous
power-on reset.
0
- R/W EXT 0
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Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
The bits in this register configure the system clock and oscillators.
The USEPWMDIV and PWMDIV fields in the PWM Peripheral Configuration (PWMPC)
register should be used to control the PWM clock. To support legacy software, the
USEPWMDIV and PWMDIV fields in this register are available. A write to these legacy
fields also writes the corresponding fields in the PWMPC register. If these fields are
changed by writing to this register, they can be read back correctly with a read of this
register. If software uses the PWMPC register to configure the PWM clock, the PWM
clock operates as specified, but the value of USEPWMDIV and PWMDIV fields in this
register are not modified.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x078E.3AD1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved PWMDIV USEPWMDIV reserved USESYSDIV SYSDIV ACG reserved
RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W RO RO RO RO Type
0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MOSCDIS reserved OSCSRC XTAL BYPASS reserved PWRDN reserved
R/W RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W RO R/W RO RO Type
1 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 Reset
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the microcontroller enters a Sleep
or Deep-Sleep mode (respectively).
Description Value
The SCGCn or DCGCn registers are used to control the clocks
distributed to the peripherals when the microcontroller is in a
sleep mode. The SCGCn and DCGCn registers allow unused
peripherals to consume less power when the microcontroller is
in a sleep mode.
1
The Run-Mode Clock Gating Control (RCGCn) registers are
used when the microcontroller enters a sleep mode.
0
The RCGCn registers are always used to control the clocks in Run
mode.
0 R/W ACG 27
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System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-4 on page 211 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 401), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
0xF R/W SYSDIV 26:23
Enable System Clock Divider
Description Value
The systemclock divider is the source for the systemclock. The
system clock divider is forced to be used when the PLL is
selected as the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2
field in the RCC2 register is used as the system clock divider
rather than the SYSDIV field in this register.
1
The system clock is used undivided. 0
0 R/W USESYSDIV 22
0 RO reserved 21
Enable PWM Clock Divisor
Description Value
The PWM clock divider is the source for the PWM clock. 1
The system clock is the source for the PWM clock. 0
Note that when the PWM divisor is used, it is applied to the clock for
both PWM modules.
0 R/W USEPWMDIV 20
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. The rising
edge of this clock is synchronous with the system clock.
Divisor Value
/2 0x0
/4 0x1
/8 0x2
/16 0x3
/32 0x4
/64 0x5
/64 0x6
/64 (default) 0x7
0x7 R/W PWMDIV 19:17
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System Control
PLL Power Down
Description Value
The PLL is powered down. Care must be taken to ensure that
another clock source is functioning and that the BYPASS bit is
set before setting this bit.
1
The PLL is operating normally. 0
1 R/W PWRDN 13
1 RO reserved 12
PLL Bypass
Description Value
The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV.
1
The system clock is the PLL output clock divided by the divisor
specified by SYSDIV.
0
See Table 5-4 on page 211 for programming guidelines.
Note: The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
1 R/W BYPASS 11
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Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Crystal Frequency (MHz)
Using the PLL
Crystal Frequency (MHz) Not
Using the PLL
Value
reserved 0x00-0x5
reserved 4 MHz 0x06
reserved 4.096 MHz 0x07
5 MHz 0x09
5.12 MHz 0x0A
6 MHz 0x0B
6.144 MHz 0x0C
7.3728 MHz 0x0D
8 MHz 0x0E
8.192 MHz 0x0F
10.0 MHz 0x10
12.0 MHz 0x11
12.288 MHz 0x12
13.56 MHz 0x13
14.31818 MHz 0x14
16.0 MHz 0x15
16.384 MHz 0x16
18.0 MHz 0x17
20.0 MHz 0x18
24.0 MHz 0x19
25.0 MHz 0x1A
0x0B R/W XTAL 10:6
Oscillator Source
Selects the input source for the OSC. The values are:
Input Source Value
MOSC
Main oscillator
0x0
PIOSC
Precision internal oscillator
(default)
0x1
PIOSC/4
Precision internal oscillator / 4
0x2
LFIOSC
Low-frequency internal oscillator
0x3
For additional oscillator sources, see the RCC2 register.
0x1 R/W OSCSRC 5:4
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System Control
0x0 RO reserved 3:1
Main Oscillator Disable
Description Value
The main oscillator is disabled (default). 1
The main oscillator is enabled. 0
1 R/W MOSCDIS 0
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Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C
This register controls which internal bus is used to access each GPIO port. When a bit is clear, the
corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and
through the APB memory aperture. When a bit is set, the corresponding port is accessed across
the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each
GPIO port can be individually configured to use AHB or APB, but may be accessed only through
one aperture. The AHB bus provides better back-to-back access performance than the APB bus.
The address aperture in the memory map changes for the ports that are enabled for AHB access
(see Table 9-6 on page 601).
Important: Ports K-N and P-Q are only available on the AHB bus, and therefore the corresponding
bits reset to 1. If one of these bits is cleared, the corresponding port is disabled. If any
of these ports is in use, read-modify-write operations should be used to change the
value of this register so that these ports remain enabled.
GPIO High-Performance Bus Control (GPIOHBCTL)
Base 0x400F.E000
Offset 0x06C
Type R/W, reset 0x0000.7E00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PORTA PORTB PORTC PORTD PORTE PORTF PORTG reserved
R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Port G Advanced High-Performance Bus
This bit defines the memory aperture for Port G.
Description Value
Advanced High-Performance Bus (AHB) 1
Advanced Peripheral Bus (APB). This bus is the legacy bus. 0
0 R/W PORTG 6
Port F Advanced High-Performance Bus
This bit defines the memory aperture for Port F.
Description Value
0 R/W PORTF 5
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System Control
Port E Advanced High-Performance Bus
This bit defines the memory aperture for Port E.
Description Value
0 R/W PORTE 4
Port D Advanced High-Performance Bus
This bit defines the memory aperture for Port D.
Description Value
0 R/W PORTD 3
Port C Advanced High-Performance Bus
This bit defines the memory aperture for Port C.
Description Value
0 R/W PORTC 2
Port B Advanced High-Performance Bus
This bit defines the memory aperture for Port B.
Description Value
0 R/W PORTB 1
Port A Advanced High-Performance Bus
This bit defines the memory aperture for Port A.
Description Value
0 R/W PORTA 0
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Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCCequivalent register fields, as shown in Table 5-8, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.
Table 5-8. RCC2 Fields that Override RCC Fields
Overrides RCC Field RCC2 Field...
SYSDIV, bits[26:23] SYSDIV2, bits[28:23]
PWRDN, bit[13] PWRDN2, bit[13]
BYPASS, bit[11] BYPASS2, bit[11]
OSCSRC, bits[5:4] OSCSRC2, bits[6:4]
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x07C0.6810
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved SYSDIV2LSB SYSDIV2 reserved DIV400 USERCC2
RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO R/W R/W Type
0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved OSCSRC2 reserved BYPASS2 reserved PWRDN2 reserved
RO RO RO RO R/W R/W R/W RO RO RO RO R/W RO R/W RO RO Type
0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 Reset
Use RCC2
Description Value
The RCC2 register fields override the RCC register fields. 1
The RCC register fields are used, and the fields in RCC2 are
ignored.
0
0 R/W USERCC2 31
Divide PLL as 400 MHz vs. 200 MHz
This bit, along with the SYSDIV2LSB bit, allows additional frequency
choices.
Description Value
Append the SYSDIV2LSB bit to the SYSDIV2 field to create a
7 bit divisor using the 400 MHz PLL output, see Table
5-6 on page 212.
1
Use SYSDIV2 as is and apply to 200 MHz predivided PLL
output. See Table 5-5 on page 212 for programming guidelines.
0
0 R/W DIV400 30
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System Control
0x0 RO reserved 29
System Clock Divisor 2
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on howthe BYPASS2
bit is configured). SYSDIV2 is used for the divisor when both the
USESYSDIV bit in the RCC register and the USERCC2 bit in this register
are set. See Table 5-5 on page 212 for programming guidelines.
0x0F R/W SYSDIV2 28:23
Additional LSB for SYSDIV2
When DIV400 is set, this bit becomes the LSB of SYSDIV2. If DIV400
is clear, this bit is not used. See Table 5-5 on page 212 for programming
guidelines.
This bit can only be set or cleared when DIV400 is set.
1 R/W SYSDIV2LSB 22
Power-Down PLL 2
Description Value
The PLL is powered down. 1
The PLL operates normally. 0
1 R/W PWRDN2 13
0 RO reserved 12
PLL Bypass 2
Description Value
The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV2.
1
The system clock is the PLL output clock divided by the divisor
specified by SYSDIV2.
0
See Table 5-5 on page 212 for programming guidelines.
Note: The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
1 R/W BYPASS2 11
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Oscillator Source 2
Selects the input source for the OSC. The values are:
Description Value
MOSC
Main oscillator
0x0
PIOSC
Precision internal oscillator
0x1
PIOSC/4
Precision internal oscillator / 4
0x2
LFIOSC
Low-frequency internal oscillator
0x3
Reserved 0x4-0x7
0x1 R/W OSCSRC2 6:4
0x0 RO reserved 3:0
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System Control
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C
This register provides control over the features of the main oscillator, including the ability to enable
the MOSC clock verification circuit, what action to take when the MOSC fails, and whether or not a
crystal is connected. When enabled, this circuit monitors the frequency of the MOSC to verify that
the oscillator is operating within specified limits. If the clock goes invalid after being enabled, the
microcontroller issues a power-on reset and reboots to the NMI handler or generates an interrupt.
Main Oscillator Control (MOSCCTL)
Base 0x400F.E000
Offset 0x07C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CVAL MOSCIM NOXTAL reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
No Crystal Connected
Description Value
This bit should be set when a crystal or external oscillator is not
connected to the OSC0 and OSC1 inputs to reduce power
consumption.
1
This bit should be cleared when a crystal or oscillator is
connected to the OSC0 and OSC1 inputs, regardless of whether
or not the MOSC is used or powered down.
0
0 R/W NOXTAL 2
MOSC Failure Action
Description Value
If the MOSC fails, an interrupt is generated as indicated by the
MOFRIS bit in the RIS register..
1
If the MOSCfails, a MOSCfailure reset is generated and reboots
to the NMI handler.
0
Regardless of the action taken, if the MOSC fails, the oscillator source
is switched to the PIOSC automatically.
0 R/W MOSCIM 1
Clock Validation for MOSC
Description Value
The MOSC monitor circuit is enabled. 1
The MOSC monitor circuit is disabled. 0
0 R/W CVAL 0
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Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved DSDIVORIDE reserved
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO Type
0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved PIOSCPD reserved DSOSCSRC reserved
RO R/W RO RO R/W R/W R/W RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Divider Field Override
If Deep-Sleep mode is enabled when the PLL is running, the PLL is
disabled. This 6-bit field contains a system divider field that overrides
the SYSDIV field in the RCC register or the SYSDIV2 field in the RCC2
register during Deep Sleep. This divider is applied to the source selected
by the DSOSCSRC field.
Description Value
/1 0x0
/2 0x1
/3 0x2
/4 0x3
... ...
/64 0x3F
0x0F R/W DSDIVORIDE 28:23
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System Control
Clock Source
Specifies the clock source during Deep-Sleep mode.
Description Value
MOSC
Use the main oscillator as the source. To use the MOSC as
the Deep-Sleep mode clock source, the MOSC must also be
configured as the Run mode clock source in the Run-Mode
Clock Configuration (RCC) register.
0x0
Note: If the PIOSC is being used as the clock reference
for the PLL, the PIOSC is the clock source instead
of MOSC in Deep-Sleep mode.
PIOSC
Use the precision internal 16-MHz oscillator as the source.
0x1
Reserved 0x2
LFIOSC
Use the low-frequency internal oscillator as the source.
0x3
Reserved 0x4-0x7
0x0 R/W DSOSCSRC 6:4
0x0 RO reserved 3:2
PIOSC Power Down Request
Allows software to request the PIOSC to be powered-down in
Deep-Sleep mode. If the PIOSC is needed by an enabled peripheral
during Deep-Sleep, the PIOSC is powered down, but a warning is
generated using the PPDW bit in the SDPMST register. If it is not possible
to power down the PIOSC, an error is reported using the PPDERR bit in
the SDPMST register.
This bit can only be used to power down the PIOSCwhen the PIOSCPDE
bit in the SYSPROP register is set.
Description Value
No action. 0
Software requests that the PIOSC is powered down during
Deep-Sleep mode.
1
0 R/W PIOSCPD 1
0 RO reserved 0
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Register 13: System Properties (SYSPROP), offset 0x14C
This register provides information on whether certain System Control properties are present on the
microcontroller.
System Properties (SYSPROP)
Base 0x400F.E000
Offset 0x14C
Type RO, reset 0x0000.1D31
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FPU reserved FLASHLPM reserved SRAMLPM SRAMSM PIOSCPDE reserved
1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 Reset
PIOSC Power Down Present
This bit determines whether the PIOSCPD bit in the DSLPCLKCFG
register can be set to power down the PIOSC in Deep-sleep mode.
Description Value
The status of the PIOSCPD bit is ignored. 0
The PIOSCPD bit can be set to power down the PIOSC in
Deep-sleep mode.
1
1 RO PIOSCPDE 12
SRAM Sleep/Deep-sleep Standby Mode Present
This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into
Standby mode while in Sleep or Deep-sleep mode.
Description Value
A value of 0x1 in the SRAMPM fields is ignored. 0
The SRAMPM fields can be configured to put the SRAM into
Standby mode while in Sleep or Deep-sleep mode.
1
1 RO SRAMSM 11
SRAM Sleep/Deep-sleep Low Power Mode Present
This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into Low
Power mode while in Sleep or Deep-sleep mode.
Description Value
A value of 0x3 in the SRAMPM fields is ignored. 0
The SRAMPM fields can be configured to put the SRAMinto Low
Power mode while in Sleep or Deep-sleep mode.
1
1 RO SRAMLPM 10
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0 RO reserved 9
Flash Memory Sleep/Deep-sleep Low Power Mode Present
This bit determines whether the FLASHPM field in the SLPPWRCFG
and DSLPPWRCFGregisters can be configured to put the Flash memory
into Low Power mode while in Sleep or Deep-sleep mode.
Description Value
A value of 0x2 in the FLASHPM fields is ignored. 0
The FLASHPM fields can be configured to put the Flash memory
into Low Power mode while in Sleep or Deep-sleep mode.
1
1 RO FLASHLPM 8
0x0 RO reserved 7:1
FPU Present
This bit indicates if the FPU is present in the Cortex-M4 core.
Description Value
FPU is not present. 0
FPU is present. 1
0x1 RO FPU 0
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Register 14: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150
This register provides the ability to update or recalibrate the precision internal oscillator.
Precision Internal Oscillator Calibration (PIOSCCAL)
Base 0x400F.E000
Offset 0x150
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved UTEN
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
UT reserved UPDATE reserved
R/W R/W R/W R/W R/W R/W R/W RO R/W RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Use User Trim Value
Description Value
The trimvalue in bits[6:0] of this register are used for any update
trim operation.
1
The factory calibration value is used for an update trimoperation. 0
0 R/W UTEN 31
Update Trim
Description Value
Updates the PIOSC trim value with the UT bit. Used with UTEN. 1
No action. 0
This bit is auto-cleared after the update.
0 R/W UPDATE 8
0 RO reserved 7
User Trim Value
User trim value that can be loaded into the PIOSC.
Refer to Main PLL Frequency Configuration on page 213 for more
information on calibrating the PIOSC.
0x0 R/W UT 6:0
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System Control
Register 15: PLL Frequency 0 (PLLFREQ0), offset 0x160
This register always contains the current M value presented to the system PLL.
The PLL frequency can be calculated using the following equation:
PLL frequency = (XTAL frequency * MDIV) / ((Q + 1) * (N + 1))
where
MDIV = MINT + (MFRAC / 1024)
The Q and N values are shown in the PLLFREQ1 register. Table 22-14 on page 1198 shows the M,
Q, and N values as well as the resulting PLL frequency for the various XTAL configurations.
PLL Frequency 0 (PLLFREQ0)
Base 0x400F.E000
Offset 0x160
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MFRAC reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MINT MFRAC
0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 Reset
PLL M Fractional Value
This field contains the integer value of the PLL M value.
0x32 RO MFRAC 19:10
PLL M Integer Value
This field contains the integer value of the PLL M value.
0x00 RO MINT 9:0
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Register 16: PLL Frequency 1 (PLLFREQ1), offset 0x164
This register always contains the current Q and N values presented to the system PLL.
The M value is shown in the PLLFREQ0 register. Table 22-14 on page 1198 shows the M, Q, and N
values as well as the resulting PLL frequency for the various XTAL configurations.
PLL Frequency 1 (PLLFREQ1)
Base 0x400F.E000
Offset 0x164
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
N reserved Q reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PLL Q Value
This field contains the PLL Q value.
0x0 RO Q 12:8
0x0 RO reserved 7:5
PLL N Value
This field contains the PLL N value.
0x1 RO N 4:0
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Register 17: PLL Status (PLLSTAT), offset 0x168
This register shows the direct status of the PLL lock.
PLL Status (PLLSTAT)
Base 0x400F.E000
Offset 0x168
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LOCK reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PLL Lock
Description Value
The PLL powered and locked. 1
The PLL is unpowered or is not yet locked. 0
0x0 RO LOCK 0
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Register 18: Sleep Power Configuration (SLPPWRCFG), offset 0x188
This register provides configuration information for the power control of the SRAMand Flash memory
while in Sleep mode.
Sleep Power Configuration (SLPPWRCFG)
Base 0x400F.E000
Offset 0x188
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SRAMPM reserved FLASHPM reserved
R/W R/W RO RO R/W R/W RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Flash Power Modes
Description Value
Active Mode
Flash memory is not placed in a lower power mode. This mode
provides the fastest time to sleep and wakeup but the highest
power consumption while the microcontroller is in Sleep mode.
0x0
Reserved 0x1
Low Power Mode
Flash memory is placed in lowpower mode. This mode provides
the lowers power consumption but requires more time to come
out of Sleep mode.
0x2
Reserved 0x3
0x0 R/W FLASHPM 5:4
0x0 RO reserved 3:2
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System Control
SRAM Power Modes
This field controls the low power modes of the on-chip SRAM while the
microcontroller is in Deep-Sleep mode.
Description Value
Active Mode
SRAMis not placed in a lower power mode. This mode provides
the fastest time to sleep and wakeup but the highest power
consumption while the microcontroller is in Sleep mode.
0x0
Standby Mode
SRAM is place in standby mode while in Sleep mode.
0x1
Reserved 0x2
Low Power Mode
SRAM is placed in low power mode. This mode provides the
slowest time to sleep and wakeup but the lowest power
consumption while in Sleep mode.
0x3
0x0 R/W SRAMPM 1:0
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Register 19: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C
This register provides configuration information for the power control of the SRAMand Flash memory
while in Deep-Sleep mode.
Deep-Sleep Power Configuration (DSLPPWRCFG)
Base 0x400F.E000
Offset 0x18C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SRAMPM reserved FLASHPM reserved
R/W R/W RO RO R/W R/W RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Flash Power Modes
Description Value
Active Mode
Flash memory is not placed in a lower power mode. This mode
provides the fastest time to sleep and wakeup but the highest
power consumption while the microcontroller is in Deep-Sleep
mode.
0x0
Reserved 0x1
Low Power Mode
Flash memory is placed in lowpower mode. This mode provides
the lowers power consumption but requires more time to come
out of Deep-Sleep mode.
0x2
Reserved 0x3
0x0 R/W FLASHPM 5:4
0x0 RO reserved 3:2
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SRAM Power Modes
This field controls the low power modes of the on-chip SRAM while the
microcontroller is in Deep-Sleep mode.
Description Value
Active Mode
SRAMis not placed in a lower power mode. This mode provides
the fastest time to sleep and wakeup but the highest power
consumption while the microcontroller is in Deep-Sleep mode.
0x0
Standby Mode
SRAM is place in standby mode while in Deep-Sleep mode.
0x1
Reserved 0x2
Low Power Mode
SRAM is placed in low power mode. This mode provides the
slowest time to sleep and wakeup but the lowest power
consumption while in Deep-Sleep mode.
0x3
0x0 R/W SRAMPM 1:0
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Register 20: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4
This register specifies the LDOoutput voltage while in Sleep mode. Writes to the VLDO bit field have
no effect on the LDO output voltage, regardless of what is specified for the VADJEN bit. The LDO
output voltage is fixed at the recommended factory reset value.
16 MHz 80 MHz 1.2
16 MHz 20 MHz 0.9
Note: The LDO will not automatically adjust in Sleep/Deepsleep mode if a debugger has been
connected since the last power-on reset.
If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or
Deep-sleep mode.
LDO Sleep Power Control (LDOSPCTL)
Base 0x400F.E000
Offset 0x1B4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved VADJEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VLDO reserved
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Reset
Voltage Adjust Enable
This bit enables the value of the VLDO field to be used to specify the
output voltage of the LDO in Sleep mode.
Description Value
The LDO output voltage is set to the factory default value in
Sleep mode. The value of the VLDO field does not affect the
LDO operation.
0
The LDOoutput value in Sleep mode is configured by the value
in the VLDO field.
1
0 R/W VADJEN 31
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System Control
LDO Output Voltage
This field provides program control of the LDO output voltage in Run
mode. The value of the field is only used for the LDO voltage when the
VADJEN bit is set.
For lowest power in Sleep mode, it is recommended to configure an
LDO output voltage that is equal to or lower than the default value of
1.2 V.
Description Value
0.90 V 0x12
0.95 V 0x13
1.00 V 0x14
1.05 V 0x15
1.10 V 0x16
1.15 V 0x17
1.20 V 0x18
reserved 0x19 - 0xFF
0x18 R/W VLDO 7:0
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Register 21: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8
This register provides factory determined values that are recommended for the VLDO field in the
LDOSPCTL register while in Sleep mode.
LDO Sleep Power Calibration (LDOSPCAL)
Base 0x400F.E000
Offset 0x1B8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NOPLL WITHPLL
0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 Reset
Sleep with PLL
The value in this field is the suggested value for the VLDO field in the
LDOSPCTL register when using the PLL. This value provides the lowest
recommended LDOoutput voltage for use with the PLL at the maximum
specified value.
0x18 RO WITHPLL 15:8
Sleep without PLL
LDOSPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use without the PLL.
0x18 RO NOPLL 7:0
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System Control
Register 22: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC
This register specifies the LDO output voltage while in Deep-Sleep mode. Writes to the VLDO bit
field have no effect on the LDO output voltage, regardless of what is specified for the VADJEN bit.
The LDO output voltage is fixed at the recommended factory reset value.
16 MHz 80 MHz 1.2
16 MHz 20 MHz 0.9
Note: The LDO will not automatically adjust in Sleep/Deepsleep mode if a debugger has been
connected since the last power-on reset.
If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or
Deep-sleep mode.
LDO Deep-Sleep Power Control (LDODPCTL)
Base 0x400F.E000
Offset 0x1BC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved VADJEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VLDO reserved
0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Reset
Voltage Adjust Enable
This bit enables the value of the VLDO field to be used to specify the
output voltage of the LDO in Deep-Sleep mode.
Description Value
The LDO output voltage is set to the factory default value in
Deep-Sleep mode. The value of the VLDO field does not affect
the LDO operation.
0
The LDOoutput value in Deep-Sleep mode is configured by the
value in the VLDO field.
1
0 R/W VADJEN 31
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LDO Output Voltage
This field provides program control of the LDO output voltage in Run
mode. The value of the field is only used for the LDO voltage when the
VADJEN bit is set.
For lowest power in Deep-sleep mode, it is recommended to configure
the LDO output voltage to the default value of 0.90 V.
Description Value
0.90 V 0x12
0.95 V 0x13
1.00 V 0x14
1.05 V 0x15
1.10 V 0x16
1.15 V 0x17
1.20 V 0x18
reserved 0x19 - 0xFF
0x12 R/W VLDO 7:0
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System Control
Register 23: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0
This register provides factory determined values that are recommended for the VLDO field in the
LDODPCTL register while in Deep-Sleep mode.
LDO Deep-Sleep Power Calibration (LDODPCAL)
Base 0x400F.E000
Offset 0x1C0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30KHZ NOPLL
0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 Reset
Deep-Sleep without PLL
LDODPCTL register when not using the PLL. This value provides the
lowest recommended LDOoutput voltage for use with the systemclock.
0x12 RO NOPLL 15:8
Deep-Sleep with IOSC
LDODPCTL register when not using the PLL. This value provides the
lowest recommended LDOoutput voltage for use with the low-frequency
internal oscillator.
0x12 RO 30KHZ 7:0
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Register 24: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC
This register provides status information on the Sleep and Deep-Sleep power modes as well as
some real time status that can be viewed by a debugger or the core if it is running. These events
do not trigger an interrupt and are meant to provide information that can help tune software for power
management. The status register gets written at the beginning of every Dynamic Power Management
event request with the results of any error checking. There is no mechanism to clear the bits; they
are overwritten on the next event. The LDOUA, FLASHLP, LOWPWR, PRACT bits provide real time
data and there are no events to register that information.
Sleep / Deep-Sleep Power Mode Status (SDPMST)
Base 0x400F.E000
Offset 0x1CC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PRACT LOWPWR FLASHLP LDOUA reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SPDERR FPDERR PPDERR LDMINERR LSMINERR reserved LMAXERR PPDW reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LDO Update Active
Description Value
The LDO voltage level is changing. 1
The LDO voltage level is not changing. 0
0 RO LDOUA 19
Flash Memory in Low Power State
Description Value
The Flash memory is currently in the low power state as
programmed in the SLPPWRCFG or DSLPPWRCFG register.
1
The Flash memory is currently in the active state. 0
0 RO FLASHLP 18
Sleep or Deep-Sleep Mode
Description Value
The microcontroller is currently in Sleep or Deep-Sleep mode
and is waiting for an interrupt or is in the process of powering
up. The status of this bit is not affected by the power state of
the Flash memory or SRAM.
1
The microcontroller is currently in Run mode. 0
0 RO LOWPWR 17
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Sleep or Deep-Sleep Power Request Active
Description Value
The microcontroller is currently in Deep-sleep mode or is in
Sleep mode and a request to put the SRAM and/or Flash
memory into a lower power mode is currently active as
configured by the the SLPPWRCFG register.
1
A power request is not active. 0
0 RO PRACT 16
PIOSC Power Down Request Warning
Description Value
A warning has occurred because software has requested that
the PIOSC be powered down during Deep-Sleep using the
PIOSCPD bit in the DSLPCLKCFG register and a peripheral
requires that it be active in Deep-Sleep. The PIOSC is powered
down regardless of the warning.
1
No error. 0
0 RO PPDW 7
VLDO Value Above Maximum Error
Description Value
An error has occurred because software has requested that the
LDO voltage be above the maximum value allowed using the
VLDO bit in the LDOSPCTL or LDODPCTL register.
In this situation, the LDO is set to the factory default value.
1
No error. 0
0 RO LMAXERR 6
0 RO reserved 5
VLDO Value Below Minimum Error in Sleep Mode
Description Value
LDO voltage be below the minimum value allowed using the
VLDO bit in the LDOSPCTL register.
In this situation, the LDO voltage is not changed when entering
Sleep mode.
1
No error. 0
0 RO LSMINERR 4
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VLDO Value Below Minimum Error in Deep-Sleep Mode
Description Value
LDO voltage be below the minimum value allowed using the
VLDO bit in the LDODPCTL register.
In this situation, the LDO voltage is not changed when entering
Deep-sleep mode.
1
No error. 0
0 RO LDMINERR 3
PIOSC Power Down Request Error
Description Value
PIOSC be powered down during Deep-Sleep and it is not
possible to power down the PIOSC.
In this situation, the PIOSC is not powered down when entering
Deep-sleep mode.
1
No error. 0
0 RO PPDERR 2
Flash Memory Power Down Request Error
Description Value
An error has occurred because software has requested a Flash
memory power down mode that is not available using the
FLASHPM field in the SLPPWRCFG or the DSLPPWRCFG
register.
1
No error. 0
0 RO FPDERR 1
SRAM Power Down Request Error
Description Value
An error has occurred because software has requested an
SRAMpower down mode that is not available using the SRAMPM
field in the SLPPWRCFG or the DSLPPWRCFG register.
1
No error. 0
0 RO SPDERR 0
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Register 25: Watchdog Timer Peripheral Present (PPWD), offset 0x300
The PPWD register provides software information regarding the watchdog modules.
Important: This register should be used to determine which watchdog timers are implemented on
this microcontroller. However, to support legacy software, the DC1 register is available.
A read of the DC1 register correctly identifies if a legacy module is present.
Watchdog Timer Peripheral Present (PPWD)
Base 0x400F.E000
Offset 0x300
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 P1 reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Watchdog Timer 1 Present
Description Value
Watchdog module 1 is present. 1
Watchdog module 1 is not present. 0
0x1 RO P1 1
Description Value
Watchdog module 0 is present. 1
Watchdog module 0 is not present. 0
0x1 RO P0 0
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Register 26: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER),
offset 0x304
The PPTIMERregister provides software information regarding the 16/32-bit general-purpose timer
modules.
Important: This register should be used to determine which timers are implemented on this
microcontroller. However, to support legacy software, the DC2 register is available. A
read of the DC2 register correctly identifies if a legacy module is present. Software must
use this register to determine if a module that is not supported by the DC2 register is
present.
16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER)
Base 0x400F.E000
Offset 0x304
Type RO, reset 0x0000.003F
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 P1 P2 P3 P4 P5 reserved
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
16/32-Bit General-Purpose Timer 5 Present
Description Value
16/32-bit general-purpose timer module 5 is present. 1
16/32-bit general-purpose timer module 6 is not present. 0
0x1 RO P5 5
Description Value
0x1 RO P4 4
Description Value
0x1 RO P3 3
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Description Value
0x1 RO P2 2
Description Value
0x1 RO P1 1
Description Value
0x1 RO P0 0
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Register 27: General-Purpose Input/Output Peripheral Present (PPGPIO),
offset 0x308
The PPGPIO register provides software information regarding the general-purpose input/output
modules.
Important: This register should be used to determine which GPIO ports are implemented on this
read of the DC4 register correctly identifies if a legacy module is present. Software must
use this register to determine if a module that is not supported by the DC4 register is
present.
General-Purpose Input/Output Peripheral Present (PPGPIO)
Base 0x400F.E000
Offset 0x308
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 reserved
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:15
GPIO Port Q Present
Description Value
GPIO Port Q is present. 1
GPIO Port Q is not present. 0
0x0 RO P14 14
GPIO Port P Present
Description Value
GPIO Port P is present. 1
GPIO Port P is not present. 0
0x0 RO P13 13
GPIO Port N Present
Description Value
GPIO Port N is present. 1
GPIO Port N is not present. 0
0x0 RO P12 12
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GPIO Port M Present
Description Value
GPIO Port M is present. 1
GPIO Port M is not present. 0
0x0 RO P11 11
GPIO Port L Present
Description Value
GPIO Port L is present. 1
GPIO Port L is not present. 0
0x0 RO P10 10
GPIO Port K Present
Description Value
GPIO Port K is present. 1
GPIO Port K is not present. 0
0x0 RO P9 9
GPIO Port J Present
Description Value
GPIO Port J is present. 1
GPIO Port J is not present. 0
0x0 RO P8 8
GPIO Port H Present
Description Value
GPIO Port H is present. 1
GPIO Port H is not present. 0
0x0 RO P7 7
GPIO Port G Present
Description Value
GPIO Port G is present. 1
GPIO Port G is not present. 0
0x1 RO P6 6
GPIO Port F Present
Description Value
GPIO Port F is present. 1
GPIO Port F is not present. 0
0x1 RO P5 5
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GPIO Port E Present
Description Value
GPIO Port E is present. 1
GPIO Port E is not present. 0
0x1 RO P4 4
GPIO Port D Present
Description Value
GPIO Port D is present. 1
GPIO Port D is not present. 0
0x1 RO P3 3
GPIO Port C Present
Description Value
GPIO Port C is present. 1
GPIO Port C is not present. 0
0x1 RO P2 2
GPIO Port B Present
Description Value
GPIO Port B is present. 1
GPIO Port B is not present. 0
0x1 RO P1 1
GPIO Port A Present
Description Value
GPIO Port A is present. 1
GPIO Port A is not present. 0
0x1 RO P0 0
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System Control
Register 28: Micro Direct Memory Access Peripheral Present (PPDMA), offset
0x30C
The PPDMA register provides software information regarding the DMA module.
Important: This register should be used to determine if the DMA module is implemented on this
read of the DC7 register correctly identifies if the DMA module is present.
Micro Direct Memory Access Peripheral Present (PPDMA)
Base 0x400F.E000
Offset 0x30C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
DMA Module Present
Description Value
DMA module is present. 1
DMA module is not present. 0
0x1 RO P0 0
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Register 29: Hibernation Peripheral Present (PPHIB), offset 0x314
The PPHIB register provides software information regarding the Hibernation module.
Important: This register should be used to determine if the Hibernation module is implemented on
A read of the DC1 register correctly identifies if the Hibernation module is present.
Hibernation Peripheral Present (PPHIB)
Base 0x400F.E000
Offset 0x314
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
Hibernation Module Present
Description Value
Hibernation module is present. 1
Hibernation module is not present. 0
0x0 RO P0 0
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System Control
Register 30: Universal Asynchronous Receiver/Transmitter Peripheral Present
(PPUART), offset 0x318
The PPUART register provides software information regarding the UART modules.
Important: This register should be used to determine which UART modules are implemented on
A read of the DC2 register correctly identifies if a legacy UART module is present.
Software must use this register to determine if a module that is not supported by the
DC2 register is present.
Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART)
Base 0x400F.E000
Offset 0x318
Type RO, reset 0x0000.00FF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 P1 P2 P3 P4 P5 P6 P7 reserved
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
UART Module 7 Present
Description Value
UART module 7 is present. 1
UART module 7 is not present. 0
0x1 RO P7 7
Description Value
0x1 RO P6 6
Description Value
0x1 RO P5 5
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Description Value
0x1 RO P4 4
Description Value
0x1 RO P3 3
Description Value
0x1 RO P2 2
Description Value
0x1 RO P1 1
Description Value
0x1 RO P0 0
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System Control
Register 31: Synchronous Serial Interface Peripheral Present (PPSSI), offset
0x31C
The PPSSI register provides software information regarding the SSI modules.
Important: This register should be used to determine which SSI modules are implemented on this
read of the DC2 register correctly identifies if a legacy SSI module is present. Software
must use this register to determine if a module that is not supported by the DC2 register
is present.
Synchronous Serial Interface Peripheral Present (PPSSI)
Base 0x400F.E000
Offset 0x31C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 P1 P2 P3 reserved
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
SSI Module 3 Present
Description Value
SSI module 3 is present. 1
SSI module 3 is not present. 0
0x1 RO P3 3
Description Value
0x1 RO P2 2
Description Value
0x1 RO P1 1
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Description Value
0x1 RO P0 0
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System Control
Register 32: Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320
The PPI2C register provides software information regarding the I
2
C modules.
Important: This register should be used to determine which I
2
C modules are implemented on this
read of the DC2 register correctly identifies if a legacy I
2
C module is present. Software
must use this register to determine if a module that is not supported by the DC2 register
is present.
Inter-Integrated Circuit Peripheral Present (PPI2C)
Base 0x400F.E000
Offset 0x320
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
I
2
C Module 5 Present
Description Value
I
2
C module 5 is present. 1
I
2
C module 5 is not present. 0
0x1 RO P5 5
I
2
C Module 4 Present
Description Value
I
2
I
2
0x1 RO P4 4
I
2
C Module 3 Present
Description Value
I
2
I
2
0x1 RO P3 3
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I
2
C Module 2 Present
Description Value
I
2
I
2
0x1 RO P2 2
I
2
C Module 1 Present
Description Value
I
2
I
2
0x1 RO P1 1
I
2
C Module 0 Present
Description Value
I
2
I
2
0x1 RO P0 0
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System Control
Register 33: Universal Serial Bus Peripheral Present (PPUSB), offset 0x328
The PPUSB register provides software information regarding the USB module.
Important: This register should be used to determine if the USB module is implemented on this
read of the DC6 register correctly identifies if the USB module is present.
Universal Serial Bus Peripheral Present (PPUSB)
Base 0x400F.E000
Offset 0x328
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
USB Module Present
Description Value
USB module is present. 1
USB module is not present. 0
0x0 RO P0 0
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Register 34: Controller Area Network Peripheral Present (PPCAN), offset 0x334
The PPCAN register provides software information regarding the CAN modules.
Important: This register should be used to determine which CAN modules are implemented on
A read of the DC1 register correctly identifies if a legacy CAN module is present.
Controller Area Network Peripheral Present (PPCAN)
Base 0x400F.E000
Offset 0x334
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 P1 reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
CAN Module 1 Present
Description Value
CAN module 1 is present. 1
CAN module 1 is not present. 0
0x1 RO P1 1
Description Value
CAN module 0 is present. 1
CAN module 0 is not present. 0
0x1 RO P0 0
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System Control
Register 35: Analog-to-Digital Converter Peripheral Present (PPADC), offset
0x338
The PPADC register provides software information regarding the ADC modules.
Important: This register should be used to determine which ADC modules are implemented on
A read of the DC1 register correctly identifies if a legacy ADC module is present.
Analog-to-Digital Converter Peripheral Present (PPADC)
Base 0x400F.E000
Offset 0x338
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 P1 reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
ADC Module 1 Present
Description Value
ADC module 1 is present. 1
ADC module 1 is not present. 0
0x1 RO P1 1
Description Value
ADC module 0 is present. 1
ADC module 0 is not present. 0
0x1 RO P0 0
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Register 36: Analog Comparator Peripheral Present (PPACMP), offset 0x33C
The PPACMP register provides software information regarding the analog comparator module.
Important: This register should be used to determine if the analog comparator module is
implemented on this microcontroller. However, to support legacy software, the DC2
register is available. A read of the DC2 register correctly identifies if the analog
comparator module is present.
Note that the Analog Comparator Peripheral Properties (ACMPPP) register indicates
how many analog comparator blocks are included in the module.
Analog Comparator Peripheral Present (PPACMP)
Base 0x400F.E000
Offset 0x33C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
Analog Comparator Module Present
Description Value
Analog comparator module is present. 1
Analog comparator module is not present. 0
0x1 RO P0 0
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System Control
Register 37: Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340
The PPPWM register provides software information regarding the PWM modules.
Important: This register should be used to determine which PWM modules are implemented on
A read of the DC1 register correctly identifies if the legacy PWM module is present.
Software must use this register to determine if a module that is not supported by the
DC1 register is present.
Pulse Width Modulator Peripheral Present (PPPWM)
Base 0x400F.E000
Offset 0x340
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 P1 reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
PWM Module 1 Present
Description Value
PWM module 1 is present. 1
PWM module 1 is not present. 0
0x1 RO P1 1
Description Value
PWM module 0 is present. 1
PWM module 0 is not present. 0
0x1 RO P0 0
289 April 10, 2013
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Register 38: Quadrature Encoder Interface Peripheral Present (PPQEI), offset
0x344
The PPQEI register provides software information regarding the QEI modules.
Important: This register should be used to determine which QEI modules are implemented on this
read of the DC2 register correctly identifies if a legacy QEI module is present.
Quadrature Encoder Interface Peripheral Present (PPQEI)
Base 0x400F.E000
Offset 0x344
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 P1 reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
QEI Module 1 Present
Description Value
QEI module 1 is present. 1
QEI module 1 is not present. 0
0x1 RO P1 1
Description Value
QEI module 0 is present. 1
QEI module 0 is not present. 0
0x1 RO P0 0
April 10, 2013 290
System Control
Register 39: EEPROM Peripheral Present (PPEEPROM), offset 0x358
The PPEEPROM register provides software information regarding the EEPROM module.
EEPROM Peripheral Present (PPEEPROM)
Base 0x400F.E000
Offset 0x358
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P0 reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
EEPROM Module Present
Description Value
EEPROM module is present. 1
EEPROM module is not present. 0
0x1 RO P0 0
291 April 10, 2013
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Register 40: 32/64-Bit Wide General-Purpose Timer Peripheral Present
(PPWTIMER), offset 0x35C
The PPWTIMERregister provides software information regarding the 32/64-bit wide general-purpose
timer modules.
32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER)
Base 0x400F.E000
Offset 0x35C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
32/64-Bit Wide General-Purpose Timer 5 Present
Description Value
32/64-bit wide general-purpose timer module 5 is present. 1
32/64-bit wide general-purpose timer module 5 is not present. 0
0x1 RO P5 5
Description Value
0x1 RO P4 4
Description Value
0x1 RO P3 3
Description Value
0x1 RO P2 2
April 10, 2013 292
System Control
Description Value
0x1 RO P1 1
Description Value
0x1 RO P0 0
293 April 10, 2013
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Register 41: Watchdog Timer Software Reset (SRWD), offset 0x500
The SRWD register provides software the capability to reset the available watchdog modules. This
register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the watchdog modules and has the same bit polarity as the corresponding SRCRn
bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRWD register. While the SRWD bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRWD bit.
There may be latency from the clearing of the SRWD bit to when the peripheral is ready for use.
Software can check the corresponding PRWD bit to be sure.
Important: This register should be used to reset the watchdog modules. To support legacy software,
the SRCR0 register is available. Setting a bit in the SRCR0 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR0 register can
be read back correctly when reading the SRCR0 register. If software uses this register
to reset a legacy peripheral (such as Watchdog 1), the write causes proper operation,
but the value of that bit is not reflected in the SRCR0 register. If software uses both
legacy and peripheral-specific register accesses, the peripheral-specific registers must
be accessed by read-modify-write operations that affect only peripherals that are not
present in the legacy registers. In this manner, both the peripheral-specific and legacy
registers have coherent information.
Watchdog Timer Software Reset (SRWD)
Base 0x400F.E000
Offset 0x500
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Watchdog Timer 1 Software Reset
Description Value
Watchdog module 1 is reset. 1
Watchdog module 1 is not reset. 0
0 R/W R1 1
April 10, 2013 294
System Control
Watchdog Timer 0 Software Reset
Description Value
Watchdog module 0 is reset. 1
Watchdog module 0 is not reset. 0
0 R/W R0 0
295 April 10, 2013
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Register 42: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER),
offset 0x504
The SRTIMERregister provides software the capability to reset the available 16/32-bit timer modules.
This register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the timer modules and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRTIMER register. While the SRTIMER bit is 1, the peripheral
is held in reset.
2. Software completes the reset process by clearing the SRTIMER bit.
There may be latency from the clearing of the SRTIMER bit to when the peripheral is ready for use.
Software can check the corresponding PRTIMER bit to be sure.
Important: This register should be used to reset the timer modules. To support legacy software,
be read back correctly when reading the SRCR1 register. Software must use this register
to reset modules that are not present in the legacy registers. If software uses this register
to reset a legacy peripheral (such as Timer 1), the write causes proper operation, but
the value of that bit is not reflected in the SRCR1 register. If software uses both legacy
and peripheral-specific register accesses, the peripheral-specific registers must be
accessed by read-modify-write operations that affect only peripherals that are not present
in the legacy registers. In this manner, both the peripheral-specific and legacy registers
have coherent information.
16/32-Bit General-Purpose Timer Software Reset (SRTIMER)
Base 0x400F.E000
Offset 0x504
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 R2 R3 R4 R5 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
16/32-Bit General-Purpose Timer 5 Software Reset
Description Value
16/32-bit general-purpose timer module 5 is reset. 1
16/32-bit general-purpose timer module 5 is not reset. 0
0 R/W R5 5
April 10, 2013 296
System Control
Description Value
0 R/W R4 4
Description Value
0 R/W R3 3
Description Value
0 R/W R2 2
Description Value
0 R/W R1 1
Description Value
0 R/W R0 0
297 April 10, 2013
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Register 43: General-Purpose Input/Output Software Reset (SRGPIO), offset
0x508
The SRGPIO register provides software the capability to reset the available GPIO modules. This
specifically for the GPIO modules and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRGPIO register. While the SRGPIO bit is 1, the peripheral
is held in reset.
2. Software completes the reset process by clearing the SRGPIO bit.
There may be latency from the clearing of the SRGPIO bit to when the peripheral is ready for use.
Software can check the corresponding PRGPIO bit to be sure.
Important: This register should be used to reset the GPIO modules. To support legacy software,
to reset a legacy peripheral (such as GPIO A), the write causes proper operation, but
General-Purpose Input/Output Software Reset (SRGPIO)
Base 0x400F.E000
Offset 0x508
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 R2 R3 R4 R5 R6 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:7
GPIO Port G Software Reset
Description Value
GPIO Port G is reset. 1
GPIO Port G is not reset. 0
0 R/W R6 6
April 10, 2013 298
System Control
GPIO Port F Software Reset
Description Value
GPIO Port F is reset. 1
GPIO Port F is not reset. 0
0 R/W R5 5
GPIO Port E Software Reset
Description Value
GPIO Port E is reset. 1
GPIO Port E is not reset. 0
0 R/W R4 4
GPIO Port D Software Reset
Description Value
GPIO Port D is reset. 1
GPIO Port D is not reset. 0
0 R/W R3 3
GPIO Port C Software Reset
Description Value
GPIO Port C is reset. 1
GPIO Port C is not reset. 0
0 R/W R2 2
GPIO Port B Software Reset
Description Value
GPIO Port B is reset. 1
GPIO Port B is not reset. 0
0 R/W R1 1
GPIO Port A Software Reset
Description Value
GPIO Port A is reset. 1
GPIO Port A is not reset. 0
0 R/W R0 0
299 April 10, 2013
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Register 44: Micro Direct Memory Access Software Reset (SRDMA), offset
0x50C
The SRDMA register provides software the capability to reset the available DMA module. This
specifically for the DMA module and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRDMA register. While the SRDMA bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRDMA bit.
There may be latency from the clearing of the SRDMA bit to when the peripheral is ready for use.
Software can check the corresponding PRDMA bit to be sure.
Important: This register should be used to reset the DMA module. To support legacy software,
the SRCR2 register is available. Setting the UDMA bit in the SRCR2 register also resets
the DMA module. If the UDMA bit is set by writing to the SRCR2 register, it can be read
back correctly when reading the SRCR2 register. If software uses this register to reset
the DMA module, the write causes proper operation, but the value of the UDMA bit is
not reflected in the SRCR2 register. If software uses both legacy and peripheral-specific
register accesses, the peripheral-specific registers must be accessed by
read-modify-write operations that affect only peripherals that are not present in the
Micro Direct Memory Access Software Reset (SRDMA)
Base 0x400F.E000
Offset 0x50C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
DMA Module Software Reset
Description Value
DMA module is reset. 1
DMA module is not reset. 0
0 R/W R0 0
April 10, 2013 300
System Control
Register 45: Universal Asynchronous Receiver/Transmitter Software Reset
(SRUART), offset 0x518
The SRUART register provides software the capability to reset the available UART modules. This
specifically for the UART modules and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRUART register. While the SRUART bit is 1, the peripheral
is held in reset.
2. Software completes the reset process by clearing the SRUART bit.
There may be latency from the clearing of the SRUART bit to when the peripheral is ready for use.
Software can check the corresponding PRUART bit to be sure.
Important: This register should be used to reset the UART modules. To support legacy software,
to reset a legacy peripheral (such as UART0), the write causes proper operation, but
Universal Asynchronous Receiver/Transmitter Software Reset (SRUART)
Base 0x400F.E000
Offset 0x518
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 R2 R3 R4 R5 R6 R7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
UART Module 7 Software Reset
Description Value
UART module 7 is reset. 1
UART module 7 is not reset. 0
0 R/W R7 7
301 April 10, 2013
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Description Value
0 R/W R6 6
Description Value
0 R/W R5 5
Description Value
0 R/W R4 4
Description Value
0 R/W R3 3
Description Value
0 R/W R2 2
Description Value
0 R/W R1 1
Description Value
0 R/W R0 0
April 10, 2013 302
System Control
Register 46: Synchronous Serial Interface Software Reset (SRSSI), offset
0x51C
The SRSSI register provides software the capability to reset the available SSI modules. This register
provides the same capability as the legacy Software Reset Control n SRCRn registers specifically
for the SSI modules and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRSSI register. While the SRSSI bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRSSI bit.
There may be latency from the clearing of the SRSSI bit to when the peripheral is ready for use.
Software can check the corresponding PRSSI bit to be sure.
Important: This register should be used to reset the SSI modules. To support legacy software, the
SRCR1 register is available. Setting a bit in the SRCR1 register also resets the
to reset a legacy peripheral (such as SSI0), the write causes proper operation, but the
value of that bit is not reflected in the SRCR1 register. If software uses both legacy and
Synchronous Serial Interface Software Reset (SRSSI)
Base 0x400F.E000
Offset 0x51C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 R2 R3 reserved
R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
SSI Module 3 Software Reset
Description Value
SSI module 3 is reset. 1
SSI module 3 is not reset. 0
0 R/W R3 3
303 April 10, 2013
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Description Value
0 R/W R2 2
Description Value
0 R/W R1 1
Description Value
0 R/W R0 0
April 10, 2013 304
System Control
Register 47: Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520
The SRI2Cregister provides software the capability to reset the available I
2
Cmodules. This register
for the I
2
C modules and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRI2C register. While the SRI2C bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRI2C bit.
There may be latency from the clearing of the SRI2C bit to when the peripheral is ready for use.
Software can check the corresponding PRI2C bit to be sure.
Important: This register should be used to reset the I
2
C modules. To support legacy software, the
to reset a legacy peripheral (such as I2C0), the write causes proper operation, but the
Inter-Integrated Circuit Software Reset (SRI2C)
Base 0x400F.E000
Offset 0x520
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
I
2
C Module 5 Software Reset
Description Value
I
2
C module 5 is reset. 1
I
2
C module 5 is not reset. 0
0 R/W R5 5
305 April 10, 2013
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I
2
Description Value
I
2
I
2
0 R/W R4 4
I
2
Description Value
I
2
I
2
0 R/W R3 3
I
2
Description Value
I
2
I
2
0 R/W R2 2
I
2
Description Value
I
2
I
2
0 R/W R1 1
I
2
Description Value
I
2
I
2
0 R/W R0 0
April 10, 2013 306
System Control
Register 48: Controller Area Network Software Reset (SRCAN), offset 0x534
The SRCAN register provides software the capability to reset the available CAN modules. This
specifically for the CAN modules and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRCAN register. While the SRCAN bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRCAN bit.
There may be latency from the clearing of the SRCAN bit to when the peripheral is ready for use.
Software can check the corresponding PRCAN bit to be sure.
Important: This register should be used to reset the CAN modules. To support legacy software,
to reset a legacy peripheral (such as CAN0), the write causes proper operation, but the
Controller Area Network Software Reset (SRCAN)
Base 0x400F.E000
Offset 0x534
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
CAN Module 1 Software Reset
Description Value
CAN module 1 is reset. 1
CAN module 1 is not reset. 0
0 R/W R1 1
307 April 10, 2013
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CAN Module 0 Software Reset
Description Value
CAN module 0 is reset. 1
CAN module 0 is not reset. 0
0 R/W R0 0
April 10, 2013 308
System Control
Register 49: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538
The SRADC register provides software the capability to reset the available ADC modules. This
specifically for the ADC modules and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRADC register. While the SRADC bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRADC bit.
There may be latency from the clearing of the SRADC bit to when the peripheral is ready for use.
Software can check the corresponding PRADC bit to be sure.
Important: This register should be used to reset the ADC modules. To support legacy software,
to reset a legacy peripheral (such as ADC0), the write causes proper operation, but the
Analog-to-Digital Converter Software Reset (SRADC)
Base 0x400F.E000
Offset 0x538
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
ADC Module 1 Software Reset
Description Value
ADC module 1 is reset. 1
ADC module 1 is not reset. 0
0 R/W R1 1
309 April 10, 2013
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ADC Module 0 Software Reset
Description Value
ADC module 0 is reset. 1
ADC module 0 is not reset. 0
0 R/W R0 0
April 10, 2013 310
System Control
Register 50: Analog Comparator Software Reset (SRACMP), offset 0x53C
The SRACMP register provides software the capability to reset the available analog comparator
module. This register provides the same capability as the legacy Software Reset Control n SRCRn
registers specifically for the analog comparator module and has the same bit polarity as the
corresponding SRCRn bits.
A block is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRACMP register. While the SRACMP bit is 1, the module
is held in reset.
2. Software completes the reset process by clearing the SRACMP bit.
There may be latency from the clearing of the SRACMP bit to when the module is ready for use.
Software can check the corresponding PRACMP bit to be sure.
Important: This register should be used to reset the analog comparator module. To support legacy
software, the SRCR1 register is available. Setting any of the COMPn bits in the SRCR0
register also resets the analog comparator module. If any of the COMPn bits are set by
writing to the SRCR1 register, it can be read back correctly when reading the SRCR0
register. If software uses this register to reset the analog comparator module, the write
causes proper operation, but the value of R0 is not reflected by the COMPn bits in the
SRCR1 register. If software uses both legacy and peripheral-specific register accesses,
the peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Analog Comparator Software Reset (SRACMP)
Base 0x400F.E000
Offset 0x53C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
Analog Comparator Module 0 Software Reset
Description Value
Analog comparator module is reset. 1
Analog comparator module is not reset. 0
0 R/W R0 0
311 April 10, 2013
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Register 51: Pulse Width Modulator Software Reset (SRPWM), offset 0x540
The SRPWM register provides software the capability to reset the available PWM modules. This
specifically for the PWM modules and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRPWM register. While the SRPWM bit is 1, the peripheral
is held in reset.
2. Software completes the reset process by clearing the SRPWM bit.
There may be latency from the clearing of the SRPWM bit to when the peripheral is ready for use.
Software can check the corresponding PRPWM bit to be sure.
Important: This register should be used to reset the PWM modules. To support legacy software,
the SRCR0 register is available. Setting the PWM bit in the SRCR0 register also resets
the PWM0 module. If the PWM bit is changed by writing to the SRCR0 register, it can
to reset PWM1, which is not present in the legacy registers. If software uses this register
to reset PWM0, the write causes proper operation, but the value of that bit is not reflected
in the SRCR0 register. If software uses both legacy and peripheral-specific register
accesses, the peripheral-specific registers must be accessed by read-modify-write
operations that affect only peripherals that are not present in the legacy registers. In
this manner, both the peripheral-specific and legacy registers have coherent information.
Pulse Width Modulator Software Reset (SRPWM)
Base 0x400F.E000
Offset 0x540
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
PWM Module 1 Software Reset
Description Value
PWM module 1 is reset. 1
PWM module 1 is not reset. 0
0 R/W R1 1
April 10, 2013 312
System Control
PWM Module 0 Software Reset
Description Value
PWM module 0 is reset. 1
PWM module 0 is not reset. 0
0 R/W R0 0
313 April 10, 2013
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Register 52: Quadrature Encoder Interface Software Reset (SRQEI), offset
0x544
The SRQEI register provides software the capability to reset the available QEI modules. This register
for the QEI modules and has the same bit polarity as the corresponding SRCRn bits.
1. Software sets a bit (or bits) in the SRQEI register. While the SRQEI bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRQEI bit.
There may be latency from the clearing of the SRQEI bit to when the peripheral is ready for use.
Software can check the corresponding PRQEI bit to be sure.
Important: This register should be used to reset the QEI modules. To support legacy software, the
to reset a legacy peripheral (such as QEI0), the write causes proper operation, but the
Quadrature Encoder Interface Software Reset (SRQEI)
Base 0x400F.E000
Offset 0x544
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
QEI Module 1 Software Reset
Description Value
QEI module 1 is reset. 1
QEI module 1 is not reset. 0
0 R/W R1 1
April 10, 2013 314
System Control
QEI Module 0 Software Reset
Description Value
QEI module 0 is reset. 1
QEI module 0 is not reset. 0
0 R/W R0 0
315 April 10, 2013
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Register 53: EEPROM Software Reset (SREEPROM), offset 0x558
The SREEPROM register provides software the capability to reset the available EEPROM module.
1. Software sets a bit (or bits) in the SREEPROM register. While the SREEPROM bit is 1, the
peripheral is held in reset.
2. Software completes the reset process by clearing the SREEPROM bit.
There may be latency from the clearing of the SREEPROM bit to when the peripheral is ready for
use. Software can check the corresponding PREEPROM bit to be sure.
EEPROM Software Reset (SREEPROM)
Base 0x400F.E000
Offset 0x558
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
EEPROM Module Software Reset
Description Value
EEPROM module is reset. 1
EEPROM module is not reset. 0
0 R/W R0 0
April 10, 2013 316
System Control
Register 54: 32/64-Bit Wide General-Purpose Timer Software Reset
(SRWTIMER), offset 0x55C
The SRWTIMER register provides software the capability to reset the available 32/64-bit wide timer
modules.
1. Software sets a bit (or bits) in the SRWTIMER register. While the SRWTIMER bit is 1, the
peripheral is held in reset.
2. Software completes the reset process by clearing the SRWTIMER bit.
There may be latency from the clearing of the SRWTIMER bit to when the peripheral is ready for
use. Software can check the corresponding PRWTIMER bit to be sure.
32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER)
Base 0x400F.E000
Offset 0x55C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
32/64-Bit Wide General-Purpose Timer 5 Software Reset
Description Value
32/64-bit wide general-purpose timer module 5 is reset. 1
32/64-bit wide general-purpose timer module 5 is not reset. 0
0 R/W R5 5
Description Value
0 R/W R4 4
Description Value
0 R/W R3 3
317 April 10, 2013
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Description Value
0 R/W R2 2
Description Value
0 R/W R1 1
Description Value
0 R/W R0 0
April 10, 2013 318
System Control
Register 55: Watchdog Timer Run Mode Clock Gating Control (RCGCWD),
offset 0x600
The RCGCWD register provides software the capability to enable and disable watchdog modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the watchdog modules. To
support legacy software, the RCGC0 register is available. A write to the RCGC0 register
also writes the corresponding bit in this register. Any bits that are changed by writing
to the RCGC0 register can be read back correctly with a read of the RCGC0 register.
If software uses this register to write a legacy peripheral (such as Watchdog 0), the
write causes proper operation, but the value of that bit is not reflected in the RCGC0
register. If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
Watchdog Timer Run Mode Clock Gating Control (RCGCWD)
Base 0x400F.E000
Offset 0x600
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Watchdog Timer 1 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to Watchdog module 1 in Run mode. 1
Watchdog module 1 is disabled. 0
0 R/W R1 1
Watchdog Timer 0 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to Watchdog module 0 in Run mode. 1
0 R/W R0 0
319 April 10, 2013
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Register 56: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control
(RCGCTIMER), offset 0x604
The RCGCTIMER register provides software the capability to enable and disable 16/32-bit timer
modules in Run mode. When enabled, a module is provided a clock and accesses to module registers
are allowed. When disabled, the clock is disabled to save power and accesses to module registers
Gating Control Register n RCGCn registers specifically for the timer modules and has the same
bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the timer modules. To support
legacy software, the RCGC1 register is available. A write to the RCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
RCGC1 register can be read back correctly with a read of the RCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as Timer 0), the write
causes proper operation, but the value of that bit is not reflected in the RCGC1 register.
If software uses both legacy and peripheral-specific register accesses, the
16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER)
Base 0x400F.E000
Offset 0x604
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to 16/32-bit general-purpose timer
module 5 in Run mode.
1
16/32-bit general-purpose timer module 5 is disabled. 0
0 R/W R5 5
April 10, 2013 320
System Control
Description Value
1
0 R/W R4 4
Description Value
1
0 R/W R3 3
Description Value
1
0 R/W R2 2
Description Value
1
0 R/W R1 1
Description Value
1
0 R/W R0 0
321 April 10, 2013
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Register 57: General-Purpose Input/Output Run Mode Clock Gating Control
(RCGCGPIO), offset 0x608
The RCGCGPIO register provides software the capability to enable and disable GPIO modules in
Run mode. When enabled, a module is provided a clock and accesses to module registers are
Important: This register should be used to control the clocking for the GPIO modules. To support
If software uses this register to write a legacy peripheral (such as GPIO A), the write
General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO)
Base 0x400F.E000
Offset 0x608
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:7
GPIO Port G Run Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port G in Run mode. 1
GPIO Port G is disabled. 0
0 R/W R6 6
GPIO Port F Run Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port F in Run mode. 1
GPIO Port F is disabled. 0
0 R/W R5 5
April 10, 2013 322
System Control
GPIO Port E Run Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port E in Run mode. 1
GPIO Port E is disabled. 0
0 R/W R4 4
GPIO Port D Run Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port D in Run mode. 1
GPIO Port D is disabled. 0
0 R/W R3 3
GPIO Port C Run Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port C in Run mode. 1
GPIO Port C is disabled. 0
0 R/W R2 2
GPIO Port B Run Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port B in Run mode. 1
GPIO Port B is disabled. 0
0 R/W R1 1
GPIO Port A Run Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port A in Run mode. 1
GPIO Port A is disabled. 0
0 R/W R0 0
323 April 10, 2013
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Register 58: Micro Direct Memory Access Run Mode Clock Gating Control
(RCGCDMA), offset 0x60C
The RCGCDMA register provides software the capability to enable and disable the DMA module
in Run mode. When enabled, the module is provided a clock and accesses to module registers are
Important: This register should be used to control the clocking for the DMA module. To support
legacy software, the RCGC2 register is available. A write to the UDMA bit in the RCGC2
register also writes the R0 bit in this register. If the UDMA bit is changed by writing to the
RCGC2 register, it can be read back correctly with a read of the RCGC2 register. If
software uses this register to control the clock for the DMA module, the write causes
proper operation, but the UDMA bit in the RCGC2 register does not reflect the value of
the R0 bit. If software uses both legacy and peripheral-specific register accesses, the
Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA)
Base 0x400F.E000
Offset 0x60C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
DMA Module Run Mode Clock Gating Control
Description Value
Enable and provide a clock to the DMA module in Run mode. 1
DMA module is disabled. 0
0 R/W R0 0
April 10, 2013 324
System Control
Register 59: Universal Asynchronous Receiver/Transmitter Run Mode Clock
Gating Control (RCGCUART), offset 0x618
The RCGCUART register provides software the capability to enable and disable the UART modules
Important: This register should be used to control the clocking for the UART modules. To support
If software uses this register to write a legacy peripheral (such as UART0), the write
Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART)
Base 0x400F.E000
Offset 0x618
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
UART Module 7 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to UART module 7 in Run mode. 1
UART module 7 is disabled. 0
0 R/W R7 7
Description Value
0 R/W R6 6
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Description Value
0 R/W R5 5
Description Value
0 R/W R4 4
Description Value
0 R/W R3 3
Description Value
0 R/W R2 2
Description Value
0 R/W R1 1
Description Value
0 R/W R0 0
April 10, 2013 326
System Control
Register 60: Synchronous Serial Interface Run Mode Clock Gating Control
(RCGCSSI), offset 0x61C
The RCGCSSI register provides software the capability to enable and disable the SSI modules in
Important: This register should be used to control the clocking for the SSI modules. To support
If software uses this register to write a legacy peripheral (such as SSI0), the write causes
proper operation, but the value of that bit is not reflected in the RCGC1 register. If
software uses both legacy and peripheral-specific register accesses, the
Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI)
Base 0x400F.E000
Offset 0x61C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
SSI Module 3 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to SSI module 3 in Run mode. 1
SSI module 3 is disabled. 0
0 R/W R3 3
Description Value
0 R/W R2 2
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Description Value
0 R/W R1 1
Description Value
0 R/W R0 0
April 10, 2013 328
System Control
Register 61: Inter-Integrated Circuit Run Mode Clock Gating Control
(RCGCI2C), offset 0x620
The RCGCI2C register provides software the capability to enable and disable the I
2
C modules in
Important: This register should be used to control the clocking for the I
2
C modules. To support
If software uses this register to write a legacy peripheral (such as I2C0), the write causes
proper operation, but the value of that bit is not reflected in the RCGC1 register. If
Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C)
Base 0x400F.E000
Offset 0x620
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
I
2
C Module 5 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to I
2
C module 5 in Run mode. 1
I
2
C module 5 is disabled. 0
0 R/W R5 5
I
2
Description Value
2
I
2
0 R/W R4 4
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I
2
Description Value
2
I
2
0 R/W R3 3
I
2
Description Value
2
I
2
0 R/W R2 2
I
2
Description Value
2
I
2
0 R/W R1 1
I
2
Description Value
2
I
2
0 R/W R0 0
April 10, 2013 330
System Control
Register 62: Controller Area Network Run Mode Clock Gating Control
(RCGCCAN), offset 0x634
The RCGCCAN register provides software the capability to enable and disable the CAN modules
Important: This register should be used to control the clocking for the CAN modules. To support
RCGC0 register can be read back correctly with a read of the RCGC0 register. If software
uses this register to write a legacy peripheral (such as CAN0), the write causes proper
operation, but the value of that bit is not reflected in the RCGC0 register. If software
uses both legacy and peripheral-specific register accesses, the peripheral-specific
registers must be accessed by read-modify-write operations that affect only peripherals
that are not present in the legacy registers. In this manner, both the peripheral-specific
and legacy registers have coherent information.
Controller Area Network Run Mode Clock Gating Control (RCGCCAN)
Base 0x400F.E000
Offset 0x634
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
CAN Module 1 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to CAN module 1 in Run mode. 1
CAN module 1 is disabled. 0
0 R/W R1 1
CAN Module 0 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to CAN module 0 in Run mode. 1
0 R/W R0 0
331 April 10, 2013
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Register 63: Analog-to-Digital Converter Run Mode Clock Gating Control
(RCGCADC), offset 0x638
The RCGCADC register provides software the capability to enable and disable the ADC modules
Important: This register should be used to control the clocking for the ADC modules. To support
uses this register to write a legacy peripheral (such as ADC0), the write causes proper
Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC)
Base 0x400F.E000
Offset 0x638
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
ADC Module 1 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to ADC module 1 in Run mode. 1
ADC module 1 is disabled. 0
0 R/W R1 1
ADC Module 0 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to ADC module 0 in Run mode. 1
0 R/W R0 0
April 10, 2013 332
System Control
Register 64: Analog Comparator Run Mode Clock Gating Control
(RCGCACMP), offset 0x63C
The RCGCACMP register provides software the capability to enable and disable the analog
comparator module in Run mode. When enabled, the module is provided a clock and accesses to
module registers are allowed. When disabled, the clock is disabled to save power and accesses to
module registers generate a bus fault. This register provides the same capability as the legacy Run
Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules
and has the same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the analog comparator module.
To support legacy software, the RCGC1 register is available. Setting any of the COMPn
bits in the RCGC1 register also sets the R0 bit in this register. If any of the COMPn bits
are set by writing to the RCGC1 register, it can be read back correctly when reading
the RCGC1 register. If software uses this register to change the clocking for the analog
comparator module, the write causes proper operation, but the value R0 is not reflected
by the COMPn bits in the RCGC1 register. If software uses both legacy and
Analog Comparator Run Mode Clock Gating Control (RCGCACMP)
Base 0x400F.E000
Offset 0x63C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
Analog Comparator Module 0 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to the analog comparator module
in Run mode.
1
Analog comparator module is disabled. 0
0 R/W R0 0
333 April 10, 2013
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Register 65: Pulse Width Modulator Run Mode Clock Gating Control
(RCGCPWM), offset 0x640
The RCGCPWM register provides software the capability to enable and disable the PWM modules
Important: This register should be used to control the clocking for the PWM modules. To support
legacy software, the RCGC0 register is available. A write to the PWM bit in the RCGC0
register also writes the R0 bit in this register. If the PWM bit is changed by writing to the
RCGC0 register, it can be read back correctly with a read of the RCGC0 register.
Software must use this register to support modules that are not present in the legacy
registers. If software uses this register to write to R0, the write causes proper operation,
but the value of that bit is not reflected in the PWM bit in the RCGC0 register. If software
Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM)
Base 0x400F.E000
Offset 0x640
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
PWM Module 1 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to PWM module 1 in Run mode. 1
PWM module 1 is disabled. 0
0 R/W R1 1
PWM Module 0 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to PWM module 0 in Run mode. 1
0 R/W R0 0
April 10, 2013 334
System Control
Register 66: Quadrature Encoder Interface Run Mode Clock Gating Control
(RCGCQEI), offset 0x644
The RCGCQEI register provides software the capability to enable and disable the QEI modules in
Important: This register should be used to control the clocking for the QEI modules. To support
uses this register to write a legacy peripheral (such as QEI0), the write causes proper
Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI)
Base 0x400F.E000
Offset 0x644
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
QEI Module 1 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to QEI module 1 in Run mode. 1
QEI module 1 is disabled. 0
0 R/W R1 1
QEI Module 0 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to QEI module 0 in Run mode. 1
0 R/W R0 0
335 April 10, 2013
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Register 67: EEPROMRun Mode Clock Gating Control (RCGCEEPROM), offset
0x658
The RCGCEEPROM register provides software the capability to enable and disable the EEPROM
module in Run mode. When enabled, the module is provided a clock and accesses to module
registers are allowed. When disabled, the clock is disabled to save power and accesses to module
registers generate a bus fault.
EEPROM Run Mode Clock Gating Control (RCGCEEPROM)
Base 0x400F.E000
Offset 0x658
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
EEPROM Module Run Mode Clock Gating Control
Description Value
Enable and provide a clock to the EEPROM module in Run
mode.
1
EEPROM module is disabled. 0
0 R/W R0 0
April 10, 2013 336
System Control
Register 68: 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating
Control (RCGCWTIMER), offset 0x65C
The RCGCWTIMER register provides software the capability to enable and disable 3264-bit timer
modules in Run mode. When enabled, a module is provided a clock and accesses to module registers
are allowed. When disabled, the clock is disabled to save power and accesses to module registers
Gating Control Register n RCGCn registers specifically for the timer modules and has the same
bit polarity as the corresponding RCGCn bits.
32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER)
Base 0x400F.E000
Offset 0x65C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
32/64-Bit Wide General-Purpose Timer 5 Run Mode Clock Gating Control
Description Value
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 5 in Run mode.
1
32/64-bit wide general-purpose timer module 5 is disabled. 0
0 R/W R5 5
Description Value
1
0 R/W R4 4
Description Value
1
0 R/W R3 3
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Description Value
1
0 R/W R2 2
Description Value
1
0 R/W R1 1
Description Value
1
0 R/W R0 0
April 10, 2013 338
System Control
Register 69: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD),
offset 0x700
The SCGCWD register provides software the capability to enable and disable watchdog modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
support legacy software, the SCGC0 register is available. A write to the SCGC0 register
to the SCGC0 register can be read back correctly with a read of the SCGC0 register.
write causes proper operation, but the value of that bit is not reflected in the SCGC0
Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD)
Base 0x400F.E000
Offset 0x700
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 S1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Watchdog Timer 1 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to Watchdog module 1 in sleep
mode.
1
0 R/W S1 1
Watchdog Timer 0 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to Watchdog module 0 in sleep
mode.
1
0 R/W S0 0
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Register 70: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control
(SCGCTIMER), offset 0x704
The SCGCTIMER register provides software the capability to enable and disable 16/32-bit timer
modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock
Gating Control Register n SCGCn registers specifically for the timer modules and has the same
bit polarity as the corresponding SCGCn bits.
legacy software, the SCGC1 register is available. A write to the SCGC1 register also
SCGC1 register can be read back correctly with a read of the SCGC1 register. Software
causes proper operation, but the value of that bit is not reflected in the SCGC1 register.
16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER)
Base 0x400F.E000
Offset 0x704
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 S1 S2 S3 S4 S5 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control
Description Value
module 5 in sleep mode.
1
0 R/W S5 5
Description Value
1
0 R/W S4 4
April 10, 2013 340
System Control
Description Value
1
0 R/W S3 3
Description Value
1
0 R/W S2 2
Description Value
1
0 R/W S1 1
Description Value
1
0 R/W S0 0
341 April 10, 2013
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Register 71: General-Purpose Input/Output Sleep Mode Clock Gating Control
(SCGCGPIO), offset 0x708
The SCGCGPIO register provides software the capability to enable and disable GPIO modules in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO)
Base 0x400F.E000
Offset 0x708
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 S1 S2 S3 S4 S5 S6 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:7
GPIO Port G Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port G in sleep mode. 1
0 R/W S6 6
GPIO Port F Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port F in sleep mode. 1
0 R/W S5 5
April 10, 2013 342
System Control
GPIO Port E Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port E in sleep mode. 1
0 R/W S4 4
GPIO Port D Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port D in sleep mode. 1
0 R/W S3 3
GPIO Port C Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port C in sleep mode. 1
0 R/W S2 2
GPIO Port B Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port B in sleep mode. 1
0 R/W S1 1
GPIO Port A Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIO Port A in sleep mode. 1
0 R/W S0 0
343 April 10, 2013
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Register 72: Micro Direct Memory Access Sleep Mode Clock Gating Control
(SCGCDMA), offset 0x70C
The SCGCDMA register provides software the capability to enable and disable the DMA module
legacy software, the SCGC2 register is available. A write to the UDMA bit in the SCGC2
register also writes the S0 bit in this register. If the UDMA bit is changed by writing to the
SCGC2 register, it can be read back correctly with a read of the SCGC2 register. If
proper operation, but the UDMA bit in the SCGC2 register does not reflect the value of
the S0 bit. If software uses both legacy and peripheral-specific register accesses, the
Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA)
Base 0x400F.E000
Offset 0x70C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
DMA Module Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to the DMA module in sleep mode. 1
0 R/W S0 0
April 10, 2013 344
System Control
Register 73: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock
Gating Control (SCGCUART), offset 0x718
The SCGCUART register provides software the capability to enable and disable the UART modules
Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART)
Base 0x400F.E000
Offset 0x718
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 S1 S2 S3 S4 S5 S6 S7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
UART Module 7 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to UART module 7 in sleep mode. 1
0 R/W S7 7
Description Value
0 R/W S6 6
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Description Value
0 R/W S5 5
Description Value
0 R/W S4 4
Description Value
0 R/W S3 3
Description Value
0 R/W S2 2
Description Value
0 R/W S1 1
Description Value
0 R/W S0 0
April 10, 2013 346
System Control
Register 74: Synchronous Serial Interface Sleep Mode Clock Gating Control
(SCGCSSI), offset 0x71C
The SCGCSSI register provides software the capability to enable and disable the SSI modules in
proper operation, but the value of that bit is not reflected in the SCGC1 register. If
Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI)
Base 0x400F.E000
Offset 0x71C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 S1 S2 S3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
SSI Module 3 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to SSI module 3 in sleep mode. 1
0 R/W S3 3
Description Value
0 R/W S2 2
347 April 10, 2013
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Description Value
0 R/W S1 1
Description Value
0 R/W S0 0
April 10, 2013 348
System Control
Register 75: Inter-Integrated Circuit Sleep Mode Clock Gating Control
(SCGCI2C), offset 0x720
The SCGCI2C register provides software the capability to enable and disable the I
2
C modules in
2
If software uses this register to write a legacy peripheral (such as I
2
C0), the write causes
proper operation, but the value of that bit is not reflected in the SCGC1 register. If
Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C)
Base 0x400F.E000
Offset 0x720
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
I
2
C Module 5 Sleep Mode Clock Gating Control
Description Value
2
C module 5 in sleep mode. 1
I
2
0 R/W S5 5
I
2
Description Value
2
I
2
0 R/W S4 4
349 April 10, 2013
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I
2
Description Value
2
I
2
0 R/W S3 3
I
2
Description Value
2
I
2
0 R/W S2 2
I
2
Description Value
2
I
2
0 R/W S1 1
I
2
Description Value
2
I
2
0 R/W S0 0
April 10, 2013 350
System Control
Register 76: Controller Area Network Sleep Mode Clock Gating Control
(SCGCCAN), offset 0x734
The SCGCCAN register provides software the capability to enable and disable the CAN modules
SCGC0 register can be read back correctly with a read of the SCGC0 register. If software
operation, but the value of that bit is not reflected in the SCGC0 register. If software
Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN)
Base 0x400F.E000
Offset 0x734
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 S1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
CAN Module 1 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to CAN module 1 in sleep mode. 1
0 R/W S1 1
CAN Module 0 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to CAN module 0 in sleep mode. 1
0 R/W S0 0
351 April 10, 2013
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Register 77: Analog-to-Digital Converter Sleep Mode Clock Gating Control
(SCGCADC), offset 0x738
The SCGCADC register provides software the capability to enable and disable the ADC modules
Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC)
Base 0x400F.E000
Offset 0x738
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 S1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
ADC Module 1 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to ADC module 1 in sleep mode. 1
0 R/W S1 1
ADC Module 0 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to ADC module 0 in sleep mode. 1
0 R/W S0 0
April 10, 2013 352
System Control
Register 78: Analog Comparator Sleep Mode Clock Gating Control
(SCGCACMP), offset 0x73C
The SCGCACMP register provides software the capability to enable and disable the analog
comparator module in sleep mode. When enabled, a module is provided a clock. When disabled,
the clock is disabled to save power. This register provides the same capability as the legacy Sleep
Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules
and has the same bit polarity as the corresponding SCGCn bits.
To support legacy software, the SCGC1 register is available. Setting any of the COMPn
bits in the SCGC1 register also sets the S0 bit in this register. If any of the COMPn bits
are set by writing to the SCGC1 register, it can be read back correctly when reading
the SCGC1 register. If software uses this register to change the clocking for the analog
comparator module, the write causes proper operation, but the value S0 is not reflected
by the COMPn bits in the SCGC1 register. If software uses both legacy and
Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP)
Base 0x400F.E000
Offset 0x73C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
Analog Comparator Module 0 Sleep Mode Clock Gating Control
Description Value
in sleep mode.
1
0 R/W S0 0
353 April 10, 2013
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Register 79: Pulse Width Modulator Sleep Mode Clock Gating Control
(SCGCPWM), offset 0x740
The SCGCPWM register provides software the capability to enable and disable the PWM modules
legacy software, the SCGC0 register is available. A write to the PWM bit in the SCGC0
register also writes the S0 bit in this register. If the PWM bit is changed by writing to the
SCGC0 register, it can be read back correctly with a read of the SCGC0 register.
registers. If software uses this register to write to S0, the write causes proper operation,
but the value of that bit is not reflected in the PWM bit in the SCGC0 register. If software
Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM)
Base 0x400F.E000
Offset 0x740
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 S1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
PWM Module 1 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to PWM module 1 in sleep mode. 1
0 R/W S1 1
PWM Module 0 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to PWM module 0 in sleep mode. 1
0 R/W S0 0
April 10, 2013 354
System Control
Register 80: Quadrature Encoder Interface Sleep Mode Clock Gating Control
(SCGCQEI), offset 0x744
The SCGCQEI register provides software the capability to enable and disable the QEI modules in
Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI)
Base 0x400F.E000
Offset 0x744
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 S1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
QEI Module 1 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to QEI module 1 in sleep mode. 1
0 R/W S1 1
QEI Module 0 Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to QEI module 0 in sleep mode. 1
0 R/W S0 0
355 April 10, 2013
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Register 81: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM),
offset 0x758
The SCGCEEPROM register provides software the capability to enable and disable the EEPROM
module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.
EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM)
Base 0x400F.E000
Offset 0x758
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
EEPROM Module Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to the EEPROM module in sleep
mode.
1
0 R/W S0 0
April 10, 2013 356
System Control
Register 82: 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating
Control (SCGCWTIMER), offset 0x75C
The SCGCWTIMER register provides software the capability to enable and disable 3264-bit timer
modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock
Gating Control Register n SCGCn registers specifically for the timer modules and has the same
bit polarity as the corresponding SCGCn bits.
32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER)
Base 0x400F.E000
Offset 0x75C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
32/64-Bit Wide General-Purpose Timer 5 Sleep Mode Clock Gating
Control
Description Value
timer module 5 in sleep mode.
1
0 R/W S5 5
Control
Description Value
1
0 R/W S4 4
Control
Description Value
1
0 R/W S3 3
357 April 10, 2013
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Control
Description Value
1
0 R/W S2 2
Control
Description Value
1
0 R/W S1 1
Control
Description Value
1
0 R/W S0 0
April 10, 2013 358
System Control
Register 83: Watchdog Timer Deep-Sleep Mode Clock Gating Control
(DCGCWD), offset 0x800
The DCGCWD register provides software the capability to enable and disable watchdog modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode
Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has
the same bit polarity as the corresponding DCGCn bits.
support legacy software, the DCGC0 register is available. A write to the DCGC0 register
to the DCGC0 register can be read back correctly with a read of the DCGC0 register.
write causes proper operation, but the value of that bit is not reflected in the DCGC0
Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD)
Base 0x400F.E000
Offset 0x800
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to Watchdog module 1 in deep-sleep
mode.
1
0 R/W D1 1
Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to Watchdog module 0 in deep-sleep
mode.
1
0 R/W D0 0
359 April 10, 2013
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Register 84: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating
Control (DCGCTIMER), offset 0x804
The DCGCTIMER register provides software the capability to enable and disable 16/32-bit timer
modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the
clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep
Mode Clock Gating Control Register n DCGCn registers specifically for the timer modules and
has the same bit polarity as the corresponding DCGCn bits.
legacy software, the DCGC1 register is available. A write to the DCGC1 register also
DCGC1 register can be read back correctly with a read of the DCGC1 register. Software
causes proper operation, but the value of that bit is not reflected in the DCGC1 register.
16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER)
Base 0x400F.E000
Offset 0x804
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating
Control
Description Value
module 5 in deep-sleep mode.
1
0 R/W D5 5
April 10, 2013 360
System Control
Control
Description Value
1
0 R/W D4 4
Control
Description Value
1
0 R/W D3 3
Control
Description Value
1
0 R/W D2 2
Control
Description Value
1
0 R/W D1 1
Control
Description Value
1
0 R/W D0 0
361 April 10, 2013
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Register 85: General-Purpose Input/Output Deep-Sleep Mode Clock Gating
Control (DCGCGPIO), offset 0x808
The DCGCGPIO register provides software the capability to enable and disable GPIO modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock
Gating Control Register n DCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding DCGCn bits.
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO)
Base 0x400F.E000
Offset 0x808
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:7
GPIO Port G Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIOPort Gin deep-sleep mode. 1
0 R/W D6 6
GPIO Port F Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIOPort F in deep-sleep mode. 1
0 R/W D5 5
April 10, 2013 362
System Control
GPIO Port E Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIOPort E in deep-sleep mode. 1
0 R/W D4 4
GPIO Port D Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIOPort Din deep-sleep mode. 1
0 R/W D3 3
GPIO Port C Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIOPort Cin deep-sleep mode. 1
0 R/W D2 2
GPIO Port B Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIOPort B in deep-sleep mode. 1
0 R/W D1 1
GPIO Port A Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to GPIOPort A in deep-sleep mode. 1
0 R/W D0 0
363 April 10, 2013
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Register 86: Micro Direct Memory Access Deep-Sleep Mode Clock Gating
Control (DCGCDMA), offset 0x80C
The DCGCDMA register provides software the capability to enable and disable the DMA module
legacy software, the DCGC2 register is available. A write to the UDMA bit in the DCGC2
register also writes the D0 bit in this register. If the UDMA bit is changed by writing to the
DCGC2 register, it can be read back correctly with a read of the DCGC2 register. If
proper operation, but the UDMA bit in the DCGC2 register does not reflect the value of
the D0 bit. If software uses both legacy and peripheral-specific register accesses, the
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA)
Base 0x400F.E000
Offset 0x80C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
DMA Module Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to the DMA module in deep-sleep
mode.
1
0 R/W D0 0
April 10, 2013 364
System Control
Register 87: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode
Clock Gating Control (DCGCUART), offset 0x818
The DCGCUART register provides software the capability to enable and disable the UART modules
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART)
Base 0x400F.E000
Offset 0x818
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
UART Module 7 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to UART module 7 in deep-sleep
mode.
1
0 R/W D7 7
Description Value
mode.
1
0 R/W D6 6
365 April 10, 2013
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Description Value
mode.
1
0 R/W D5 5
Description Value
mode.
1
0 R/W D4 4
Description Value
mode.
1
0 R/W D3 3
Description Value
mode.
1
0 R/W D2 2
Description Value
mode.
1
0 R/W D1 1
Description Value
mode.
1
0 R/W D0 0
April 10, 2013 366
System Control
Register 88: Synchronous Serial Interface Deep-Sleep Mode Clock Gating
Control (DCGCSSI), offset 0x81C
The DCGCSSI register provides software the capability to enable and disable the SSI modules in
proper operation, but the value of that bit is not reflected in the DCGC1 register. If
Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI)
Base 0x400F.E000
Offset 0x81C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
SSI Module 3 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to SSI module 3 in deep-sleep mode. 1
0 R/W D3 3
Description Value
0 R/W D2 2
367 April 10, 2013
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Description Value
0 R/W D1 1
Description Value
0 R/W D0 0
April 10, 2013 368
System Control
Register 89: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control
(DCGCI2C), offset 0x820
The DCGCI2C register provides software the capability to enable and disable the I
2
C modules in
2
If software uses this register to write a legacy peripheral (such as I
2
C0), the write causes
proper operation, but the value of that bit is not reflected in the DCGC1 register. If
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C)
Base 0x400F.E000
Offset 0x820
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
I
2
C Module 5 Deep-Sleep Mode Clock Gating Control
Description Value
2
Cmodule 5 in deep-sleep mode. 1
I
2
0 R/W D5 5
I
2
Description Value
2
I
2
0 R/W D4 4
369 April 10, 2013
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I
2
Description Value
2
I
2
0 R/W D3 3
I
2
Description Value
2
I
2
0 R/W D2 2
I
2
Description Value
2
I
2
0 R/W D1 1
I
2
Description Value
2
I
2
0 R/W D0 0
April 10, 2013 370
System Control
Register 90: Controller Area Network Deep-Sleep Mode Clock Gating Control
(DCGCCAN), offset 0x834
The DCGCCAN register provides software the capability to enable and disable the CAN modules
DCGC0 register can be read back correctly with a read of the DCGC0 register. If software
operation, but the value of that bit is not reflected in the DCGC0 register. If software
Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN)
Base 0x400F.E000
Offset 0x834
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
CAN Module 1 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to CAN module 1 in deep-sleep
mode.
1
0 R/W D1 1
CAN Module 0 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to CAN module 0 in deep-sleep
mode.
1
0 R/W D0 0
371 April 10, 2013
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Register 91: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating
Control (DCGCADC), offset 0x838
The DCGCADC register provides software the capability to enable and disable the ADC modules
Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC)
Base 0x400F.E000
Offset 0x838
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
ADC Module 1 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to ADC module 1 in deep-sleep
mode.
1
0 R/W D1 1
ADC Module 0 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to ADC module 0 in deep-sleep
mode.
1
0 R/W D0 0
April 10, 2013 372
System Control
Register 92: Analog Comparator Deep-Sleep Mode Clock Gating Control
(DCGCACMP), offset 0x83C
The DCGCACMP register provides software the capability to enable and disable the analog
comparator module in deep-sleep mode. When enabled, a module is provided a clock. When
disabled, the clock is disabled to save power. This register provides the same capability as the
legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the
watchdog modules and has the same bit polarity as the corresponding DCGCn bits.
To support legacy software, the DCGC1 register is available. Setting any of the COMPn
bits in the DCGC1 register also sets the D0 bit in this register. If any of the COMPn bits
are set by writing to the DCGC1 register, it can be read back correctly when reading
the DCGC1 register. If software uses this register to change the clocking for the analog
comparator module, the write causes proper operation, but the value D0 is not reflected
by the COMPn bits in the DCGC1 register. If software uses both legacy and
Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP)
Base 0x400F.E000
Offset 0x83C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control
Description Value
in deep-sleep mode.
1
0 R/W D0 0
373 April 10, 2013
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Register 93: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control
(DCGCPWM), offset 0x840
The DCGCPWM register provides software the capability to enable and disable the PWM modules
legacy software, the DCGC0 register is available. A write to the PWM bit in the DCGC0
register also writes the D0 bit in this register. If the PWM bit is changed by writing to the
DCGC0 register, it can be read back correctly with a read of the DCGC0 register.
registers. If software uses this register to write to D0, the write causes proper operation,
but the value of that bit is not reflected in the PWM bit in the DCGC0 register. If software
Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM)
Base 0x400F.E000
Offset 0x840
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
PWM Module 1 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to PWM module 1 in deep-sleep
mode.
1
0 R/W D1 1
PWM Module 0 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to PWM module 0 in deep-sleep
mode.
1
0 R/W D0 0
April 10, 2013 374
System Control
Register 94: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating
Control (DCGCQEI), offset 0x844
The DCGCQEI register provides software the capability to enable and disable the QEI modules in
Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI)
Base 0x400F.E000
Offset 0x844
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
QEI Module 1 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to QEI module 1 in deep-sleep
mode.
1
0 R/W D1 1
QEI Module 0 Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to QEI module 0 in deep-sleep
mode.
1
0 R/W D0 0
375 April 10, 2013
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Register 95: EEPROMDeep-SleepMode Clock GatingControl (DCGCEEPROM),
offset 0x858
The DCGCEEPROM register provides software the capability to enable and disable the EEPROM
module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock
is disabled to save power.
EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM)
Base 0x400F.E000
Offset 0x858
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
EEPROM Module Deep-Sleep Mode Clock Gating Control
Description Value
Enable and provide a clock to the EEPROM module in
deep-sleep mode.
1
0 R/W D0 0
April 10, 2013 376
System Control
Register 96: 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock
Gating Control (DCGCWTIMER), offset 0x85C
The DCGCWTIMER register provides software the capability to enable and disable 32/64-bit wide
timer modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled,
the clock is disabled to save power. This register provides the same capability as the legacy
Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the timer
modules and has the same bit polarity as the corresponding DCGCn bits.
32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCWTIMER)
Base 0x400F.E000
Offset 0x85C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
32/64-Bit Wide General-Purpose Timer 5 Deep-Sleep Mode Clock Gating
Control
Description Value
timer module 5 in deep-sleep mode.
1
0 R/W D5 5
Control
Description Value
1
0 R/W D4 4
Control
Description Value
1
0 R/W D3 3
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Control
Description Value
1
0 R/W D2 2
Control
Description Value
1
0 R/W D1 1
Control
Description Value
1
0 R/W D0 0
April 10, 2013 378
System Control
Register 97: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00
The PRWD register indicates whether the watchdog modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCWD bit is changed. A reset change is initiated if the
corresponding SRWD bit is changed from 0 to 1.
The PRWD bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Watchdog Timer Peripheral Ready (PRWD)
Base 0x400F.E000
Offset 0xA00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Watchdog Timer 1 Peripheral Ready
Description Value
Watchdog module 1 is ready for access. 1
Watchdog module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
0 RO R1 1
Watchdog Timer 0 Peripheral Ready
Description Value
Watchdog module 0 is ready for access. 1
Watchdog module 0 is not ready for access. It is unclocked,
0
0 RO R0 0
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Register 98: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER),
offset 0xA04
The PRTIMER register indicates whether the timer modules are ready to be accessed by software
is initiated if the corresponding RCGCTIMER bit is changed. A reset change is initiated if the
corresponding SRTIMER bit is changed from 0 to 1.
The PRTIMER bit is cleared on any of the above events and is not set again until the module is
16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER)
Base 0x400F.E000
Offset 0xA04
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
16/32-Bit General-Purpose Timer 5 Peripheral Ready
Description Value
16/32-bit timer module 5 is ready for access. 1
16/32-bit timer module 5 is not ready for access. It is unclocked,
0
0 RO R5 5
Description Value
0
0 RO R4 4
Description Value
0
0 RO R3 3
April 10, 2013 380
System Control
Description Value
0
0 RO R2 2
Description Value
0
0 RO R1 1
Description Value
0
0 RO R0 0
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Register 99: General-Purpose Input/Output Peripheral Ready (PRGPIO), offset
0xA08
The PRGPIO register indicates whether the GPIO modules are ready to be accessed by software
is initiated if the corresponding RCGCGPIO bit is changed. A reset change is initiated if the
corresponding SRGPIO bit is changed from 0 to 1.
The PRGPIO bit is cleared on any of the above events and is not set again until the module is
General-Purpose Input/Output Peripheral Ready (PRGPIO)
Base 0x400F.E000
Offset 0xA08
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:7
GPIO Port G Peripheral Ready
Description Value
GPIO Port G is ready for access. 1
GPIOPort Gis not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
0
0 RO R6 6
GPIO Port F Peripheral Ready
Description Value
GPIO Port F is ready for access. 1
GPIOPort F is not ready for access. It is unclocked, unpowered,
0
0 RO R5 5
GPIO Port E Peripheral Ready
Description Value
GPIO Port E is ready for access. 1
GPIOPort E is not ready for access. It is unclocked, unpowered,
0
0 RO R4 4
April 10, 2013 382
System Control
GPIO Port D Peripheral Ready
Description Value
GPIO Port D is ready for access. 1
GPIOPort Dis not ready for access. It is unclocked, unpowered,
0
0 RO R3 3
GPIO Port C Peripheral Ready
Description Value
GPIO Port C is ready for access. 1
GPIOPort Cis not ready for access. It is unclocked, unpowered,
0
0 RO R2 2
GPIO Port B Peripheral Ready
Description Value
GPIO Port B is ready for access. 1
GPIOPort B is not ready for access. It is unclocked, unpowered,
0
0 RO R1 1
GPIO Port A Peripheral Ready
Description Value
GPIO Port A is ready for access. 1
GPIOPort A is not ready for access. It is unclocked, unpowered,
0
0 RO R0 0
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Register 100: Micro Direct Memory Access Peripheral Ready (PRDMA), offset
0xA0C
The PRDMA register indicates whether the DMA module is ready to be accessed by software
is initiated if the corresponding RCGCDMA bit is changed. A reset change is initiated if the
corresponding SRDMA bit is changed from 0 to 1.
The PRDMA bit is cleared on any of the above events and is not set again until the module is
Micro Direct Memory Access Peripheral Ready (PRDMA)
Base 0x400F.E000
Offset 0xA0C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
DMA Module Peripheral Ready
Description Value
The DMA module is ready for access. 1
The DMA module is not ready for access. It is unclocked,
0
0 RO R0 0
April 10, 2013 384
System Control
Register 101: Universal Asynchronous Receiver/Transmitter Peripheral Ready
(PRUART), offset 0xA18
The PRUART register indicates whether the UART modules are ready to be accessed by software
is initiated if the corresponding RCGCUART bit is changed. A reset change is initiated if the
corresponding SRUART bit is changed from 0 to 1.
The PRUART bit is cleared on any of the above events and is not set again until the module is
Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART)
Base 0x400F.E000
Offset 0xA18
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
UART Module 7 Peripheral Ready
Description Value
UART module 7 is ready for access. 1
UART module 7 is not ready for access. It is unclocked,
0
0 RO R7 7
Description Value
0
0 RO R6 6
Description Value
0
0 RO R5 5
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Description Value
0
0 RO R4 4
Description Value
0
0 RO R3 3
Description Value
0
0 RO R2 2
Description Value
0
0 RO R1 1
Description Value
0
0 RO R0 0
April 10, 2013 386
System Control
Register 102: Synchronous Serial Interface Peripheral Ready (PRSSI), offset
0xA1C
The PRSSI register indicates whether the SSI modules are ready to be accessed by software
is initiated if the corresponding RCGCSSI bit is changed. A reset change is initiated if the
corresponding SRSSI bit is changed from 0 to 1.
The PRSSI bit is cleared on any of the above events and is not set again until the module is
Synchronous Serial Interface Peripheral Ready (PRSSI)
Base 0x400F.E000
Offset 0xA1C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
SSI Module 3 Peripheral Ready
Description Value
SSI module 3 is ready for access. 1
SSI module 3 is not ready for access. It is unclocked,
0
0 RO R3 3
Description Value
0
0 RO R2 2
Description Value
0
0 RO R1 1
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Description Value
0
0 RO R0 0
April 10, 2013 388
System Control
Register 103: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20
The PRI2Cregister indicates whether the I
2
Cmodules are ready to be accessed by software following
a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated
if the corresponding RCGCI2Cbit is changed. A reset change is initiated if the corresponding SRI2C
bit is changed from 0 to 1.
The PRI2C bit is cleared on any of the above events and is not set again until the module is
Inter-Integrated Circuit Peripheral Ready (PRI2C)
Base 0x400F.E000
Offset 0xA20
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
I
2
C Module 5 Peripheral Ready
Description Value
I
2
C module 5 is ready for access. 1
I
2
Cmodule 5 is not ready for access. It is unclocked, unpowered,
0
0 RO R5 5
I
2
Description Value
I
2
I
2
0
0 RO R4 4
I
2
Description Value
I
2
I
2
0
0 RO R3 3
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I
2
Description Value
I
2
I
2
0
0 RO R2 2
I
2
Description Value
I
2
I
2
0
0 RO R1 1
I
2
Description Value
I
2
I
2
0
0 RO R0 0
April 10, 2013 390
System Control
Register 104: Controller Area Network Peripheral Ready (PRCAN), offset
0xA34
The PRCAN register indicates whether the CAN modules are ready to be accessed by software
is initiated if the corresponding RCGCCAN bit is changed. A reset change is initiated if the
corresponding SRCAN bit is changed from 0 to 1.
The PRCAN bit is cleared on any of the above events and is not set again until the module is
Controller Area Network Peripheral Ready (PRCAN)
Base 0x400F.E000
Offset 0xA34
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
CAN Module 1 Peripheral Ready
Description Value
CAN module 1 is ready for access. 1
CAN module 1 is not ready for access. It is unclocked,
0
0 RO R1 1
CAN Module 0 Peripheral Ready
Description Value
CAN module 0 is ready for access. 1
CAN module 0 is not ready for access. It is unclocked,
0
0 RO R0 0
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Register 105: Analog-to-Digital Converter Peripheral Ready (PRADC), offset
0xA38
The PRADC register indicates whether the ADC modules are ready to be accessed by software
is initiated if the corresponding RCGCADC bit is changed. A reset change is initiated if the
corresponding SRADC bit is changed from 0 to 1.
The PRADC bit is cleared on any of the above events and is not set again until the module is
Analog-to-Digital Converter Peripheral Ready (PRADC)
Base 0x400F.E000
Offset 0xA38
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
ADC Module 1 Peripheral Ready
Description Value
ADC module 1 is ready for access. 1
ADC module 1 is not ready for access. It is unclocked,
0
0 RO R1 1
ADC Module 0 Peripheral Ready
Description Value
ADC module 0 is ready for access. 1
ADC module 0 is not ready for access. It is unclocked,
0
0 RO R0 0
April 10, 2013 392
System Control
Register 106: Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C
The PRACMP register indicates whether the analog comparator module is ready to be accessed
by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking
change is initiated if the corresponding RCGCACMP bit is changed. A reset change is initiated if
the corresponding SRACMP bit is changed from 0 to 1.
The PRACMP bit is cleared on any of the above events and is not set again until the module is
Analog Comparator Peripheral Ready (PRACMP)
Base 0x400F.E000
Offset 0xA3C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
Analog Comparator Module 0 Peripheral Ready
Description Value
The analog comparator module is ready for access. 1
The analog comparator module is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
0
0 RO R0 0
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Register 107: Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40
The PRPWM register indicates whether the PWM modules are ready to be accessed by software
is initiated if the corresponding RCGCPWM bit is changed. A reset change is initiated if the
corresponding SRPWM bit is changed from 0 to 1.
The PRPWM bit is cleared on any of the above events and is not set again until the module is
Pulse Width Modulator Peripheral Ready (PRPWM)
Base 0x400F.E000
Offset 0xA40
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
PWM Module 1 Peripheral Ready
Description Value
PWM module 1 is ready for access. 1
PWM module 1 is not ready for access. It is unclocked,
0
0 RO R1 1
PWM Module 0 Peripheral Ready
Description Value
PWM module 0 is ready for access. 1
PWM module 0 is not ready for access. It is unclocked,
0
0 RO R0 0
April 10, 2013 394
System Control
Register 108: Quadrature Encoder Interface Peripheral Ready (PRQEI), offset
0xA44
The PRQEI register indicates whether the QEI modules are ready to be accessed by software
is initiated if the corresponding RCGCQEI bit is changed. A reset change is initiated if the
corresponding SRQEI bit is changed from 0 to 1.
The PRQEI bit is cleared on any of the above events and is not set again until the module is
Quadrature Encoder Interface Peripheral Ready (PRQEI)
Base 0x400F.E000
Offset 0xA44
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 R1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
QEI Module 1 Peripheral Ready
Description Value
QEI module 1 is ready for access. 1
QEI module 1 is not ready for access. It is unclocked,
0
0 RO R1 1
QEI Module 0 Peripheral Ready
Description Value
QEI module 0 is ready for access. 1
QEI module 0 is not ready for access. It is unclocked,
0
0 RO R0 0
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Register 109: EEPROM Peripheral Ready (PREEPROM), offset 0xA58
The PREEPROM register indicates whether the EEPROM module is ready to be accessed by
software following a change in status of power, Run mode clocking, or reset. A Run mode clocking
change is initiated if the corresponding RCGCEEPROM bit is changed. A reset change is initiated
if the corresponding SREEPROM bit is changed from 0 to 1.
The PREEPROM bit is cleared on any of the above events and is not set again until the module is
EEPROM Peripheral Ready (PREEPROM)
Base 0x400F.E000
Offset 0xA58
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
EEPROM Module Peripheral Ready
Description Value
The EEPROM module is ready for access. 1
The EEPROM module is not ready for access. It is unclocked,
0
0 RO R0 0
April 10, 2013 396
System Control
Register 110: 32/64-Bit Wide General-Purpose Timer Peripheral Ready
(PRWTIMER), offset 0xA5C
The PRWTIMERregister indicates whether the timer modules are ready to be accessed by software
is initiated if the corresponding RCGCWTIMER bit is changed. A reset change is initiated if the
corresponding SRWTIMER bit is changed from 0 to 1.
The PRWTIMER bit is cleared on any of the above events and is not set again until the module is
32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER)
Base 0x400F.E000
Offset 0xA5C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
32/64-Bit Wide General-Purpose Timer 5 Peripheral Ready
Description Value
32/64-bit wide timer module 5 is ready for access. 1
32/64-bit wide timer module 5 is not ready for access. It is
sequence.
0
0 RO R5 5
Description Value
sequence.
0
0 RO R4 4
Description Value
sequence.
0
0 RO R3 3
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Description Value
sequence.
0
0 RO R2 2
Description Value
sequence.
0
0 RO R1 1
Description Value
sequence.
0
0 RO R0 0
5.6 System Control Legacy Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
Important: Register in this section are provided for legacy software support only; registers in
System Control Register Descriptions on page 224 should be used instead.
April 10, 2013 398
System Control
Register 111: Device Capabilities 0 (DC0), offset 0x008
This legacy register is predefined by the part and can be used to verify features.
Important: This register is provided for legacy software support only.
The Flash Size (FSIZE) and SRAMSize (SSIZE) registers should be used to determine
this microcontroller's memory sizes. A read of DC0 correctly identifies legacy memory
sizes but software must use FSIZE and SSIZE for memory sizes that are not listed
below.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x007F.007F
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SRAMSZ
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FLASHSZ
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Reset
SRAM Size
Indicates the size of the on-chip SRAM.
Description Value
2 KB of SRAM 0x7
4 KB of SRAM 0xF
6 KB of SRAM 0x17
8 KB of SRAM 0x1F
12 KB of SRAM 0x2F
16 KB of SRAM 0x3F
20 KB of SRAM 0x4F
24 KB of SRAM 0x5F
32 KB of SRAM 0x7F
0x7F RO SRAMSZ 31:16
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Flash Size
Indicates the size of the on-chip Flash memory.
Description Value
8 KB of Flash 0x3
16 KB of Flash 0x7
32 KB of Flash 0xF
64 KB of Flash 0x1F
96 KB of Flash 0x2F
128 KB of Flash 0x3F
0x7F RO FLASHSZ 15:0
April 10, 2013 400
System Control
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, DCGC0, and the
peripheral-specific RCGC, SCGC, and DCGC registers cannot be set.
The Peripheral Present registers should be used to determine which modules are
implemented on this microcontroller. A read of DC1 correctly identifies if a legacy module
is present but software must use the Peripheral Present registers to determine if a
module is present that is not supported by the DCn registers.
Likewise, the ADCPeripheral Properties (ADCPP) register should be used to determine
the maximumADCsample rate and whether the temperature sensor is present. However,
to support legacy software, the MAXADCnSPD fields and the TEMPSNS bit are available.
A read of DC1 correctly identifies the maximum ADC sample rate for legacy rates and
whether the temperature sensor is present.
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x1333.2FBF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADC0 ADC1 reserved PWM0 PWM1 reserved CAN0 CAN1 reserved WDT1 reserved
1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
JTAG SWD SWO WDT0 PLL TEMPSNS HIB MPU MAXADC0SPD MAXADC1SPD MINSYSDIV
1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 0 Reset
0 RO reserved 31:29
Watchdog Timer1 Present
When set, indicates that watchdog timer 1 is present.
0x1 RO WDT1 28
0 RO reserved 27:26
When set, indicates that CAN unit 1 is present.
0x1 RO CAN1 25
When set, indicates that CAN unit 0 is present.
0x1 RO CAN0 24
0 RO reserved 23:22
When set, indicates that the PWM module is present.
0x1 RO PWM1 21
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When set, indicates that the PWM module is present.
0x1 RO PWM0 20
0 RO reserved 19:18
When set, indicates that ADC module 1 is present.
0x1 RO ADC1 17
When set, indicates that ADC module 0 is present
0x1 RO ADC0 16
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Description Value
Specifies an 80-MHz CPU clock with a PLL divider of 2.5. 0x1
Specifies a 66-MHz CPU clock with a PLL divider of 3. 0x2
Specifies a 25-MHz clock with a PLL divider of 8. 0x7
Specifies a 20-MHz clock with a PLL divider of 10. 0x9
0x2 RO MINSYSDIV 15:12
Max ADC1 Speed
This field indicates the maximum rate at which the ADC samples data.
Description Value
1M samples/second 0x3
500K samples/second 0x2
0x3 RO MAXADC1SPD 11:10
Max ADC0 Speed
This field indicates the maximum rate at which the ADC samples data.
Description Value
MPU Present
When set, indicates that the Cortex-M4F Memory Protection Unit (MPU)
module is present. See the "Cortex-M4F Peripherals" chapter for details
on the MPU.
0x1 RO MPU 7
April 10, 2013 402
System Control
Hibernation Module Present
When set, indicates that the Hibernation module is present.
0x0 RO HIB 6
Temp Sensor Present
When set, indicates that the on-chip temperature sensor is present.
0x1 RO TEMPSNS 5
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
0x1 RO PLL 4
When set, indicates that watchdog timer 0 is present.
0x1 RO WDT0 3
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
0x1 RO SWO 2
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
0x1 RO SWD 1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
0x1 RO JTAG 0
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peripheral-specific RCGC, SCGC, and DCGC registers registers cannot be set.
Note that the Analog Comparator Peripheral Present (PPACMP) register identifies
whether the analog comparator module is present. The Analog Comparator Peripheral
Properties (ACMPPP) register indicates how many analog comparator blocks are
present in the module.
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x030F.F337
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TIMER0 TIMER1 TIMER2 TIMER3 reserved COMP0 COMP1 COMP2 reserved I2S0 reserved EPI0 reserved
1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
UART0 UART1 UART2 reserved SSI0 SSI1 reserved QEI0 QEI1 reserved I2C0 I2C0HS I2C1 I2C1HS
1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 Reset
0 RO reserved 31
EPI Module 0 Present
When set, indicates that EPI module 0 is present.
0x0 RO EPI0 30
0 RO reserved 29
I2S Module 0 Present
When set, indicates that I2S module 0 is present.
0x0 RO I2S0 28
0 RO reserved 27
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
0x0 RO COMP2 26
0x1 RO COMP1 25
April 10, 2013 404
System Control
0x1 RO COMP0 24
0 RO reserved 23:20
Timer Module 3 Present
When set, indicates that General-Purpose Timer module 3 is present.
0x1 RO TIMER3 19
0x1 RO TIMER2 18
0x1 RO TIMER1 17
0x1 RO TIMER0 16
I2C Module 1 Speed
When set, indicates that I2Cmodule 1 can operate in high-speed mode.
0x1 RO I2C1HS 15
I2C Module 1 Present
When set, indicates that I2C module 1 is present.
0x1 RO I2C1 14
I2C Module 0 Speed
When set, indicates that I2Cmodule 0 can operate in high-speed mode.
0x1 RO I2C0HS 13
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
0x1 RO I2C0 12
0 RO reserved 11:10
When set, indicates that QEI module 1 is present.
0x1 RO QEI1 9
When set, indicates that QEI module 0 is present.
0x1 RO QEI0 8
0 RO reserved 7:6
When set, indicates that SSI module 1 is present.
0x1 RO SSI1 5
When set, indicates that SSI module 0 is present.
0x1 RO SSI0 4
0 RO reserved 3
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When set, indicates that UART module 2 is present.
0x1 RO UART2 2
0x1 RO UART1 1
0x1 RO UART0 0
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System Control
register, the feature is not present.
For some modules, the peripheral-resident Peripheral Properties registers should be
used to determine which pins are available on this microcontroller. A read of DC3
correctly identifies if a legacy pin is present but software must use the Peripheral
Properties registers to determine if a pin is present that is not supported by the DCn
registers.
Base 0x400F.E000
Offset 0x018
Type RO, reset 0xBFFF.8FFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADC0AIN0 ADC0AIN1 ADC0AIN2 ADC0AIN3 ADC0AIN4 ADC0AIN5 ADC0AIN6 ADC0AIN7 CCP0 CCP1 CCP2 CCP3 CCP4 CCP5 reserved 32KHZ
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 C0MINUS C0PLUS C0O C1MINUS C1PLUS C1O C2MINUS C2PLUS C2O PWMFAULT
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Reset
32KHz Input Clock Available
When set, indicates an even CCP pin is present and can be used as a
32-KHz input clock.
Note: The GPTMPP register does not provide this information.
0x1 RO 32KHZ 31
0 RO reserved 30
T2CCP1 Pin Present
When set, indicates that Capture/Compare/PWMpin T2CCP1 is present.
0x1 RO CCP5 29
T2CCP0 Pin Present
0x1 RO CCP4 28
T1CCP1 Pin Present
0x1 RO CCP3 27
T1CCP0 Pin Present
0x1 RO CCP2 26
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T0CCP1 Pin Present
0x1 RO CCP1 25
T0CCP0 Pin Present
0x1 RO CCP0 24
ADC Module 0 AIN7 Pin Present
When set, indicates that ADC module 0 input pin 7 is present.
Note: The CH field in the ADCPP register provides this information.
0x1 RO ADC0AIN7 23
0x1 RO ADC0AIN6 22
0x1 RO ADC0AIN5 21
0x1 RO ADC0AIN4 20
0x1 RO ADC0AIN3 19
0x1 RO ADC0AIN2 18
0x1 RO ADC0AIN1 17
0x1 RO ADC0AIN0 16
PWM Fault Pin Present
When set, indicates that a PWM Fault pin is present. See DC5 for
specific Fault pins on this device.
Note: The FCNT field in the PWMPP register provides this
information.
0x1 RO PWMFAULT 15
C2o Pin Present
When set, indicates that the analog comparator 2 output pin is present.
Note: The C2O bit in the ACMPPP register provides this information.
0x0 RO C2O 14
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C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
Note: This pin is present when analog comparator 2 is present.
0x0 RO C2PLUS 13
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
0x0 RO C2MINUS 12
C1o Pin Present
0x1 RO C1O 11
C1+ Pin Present
0x1 RO C1PLUS 10
C1- Pin Present
0x1 RO C1MINUS 9
C0o Pin Present
0x1 RO C0O 8
C0+ Pin Present
0x1 RO C0PLUS 7
C0- Pin Present
0x1 RO C0MINUS 6
PWM5 Pin Present
When set, indicates that the PWM pin 5 is present.
Note: The GCNT field in the PWMPP register provides this
information.
0x1 RO PWM5 5
PWM4 Pin Present
information.
0x1 RO PWM4 4
PWM3 Pin Present
information.
0x1 RO PWM3 3
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PWM2 Pin Present
information.
0x1 RO PWM2 2
PWM1 Pin Present
information.
0x1 RO PWM1 1
PWM0 Pin Present
information.
0x1 RO PWM0 0
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Register 115: Device Capabilities 4 (DC4), offset 0x01C
peripheral-specific RCGC, SCGC, and DCGC registers registers cannot be set.
The peripheral-resident Peripheral Properties registers should be used to determine
which pins and features are available on this microcontroller. A read of DC4 correctly
identifies if a legacy pin or feature is present. Software must use the Peripheral Properties
registers to determine if a pin or feature is present that is not supported by the DCn
registers.
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x0004.F07F
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved PICAL reserved E1588 reserved EMAC0 reserved EPHY0 reserved
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG GPIOH GPIOJ reserved ROM UDMA CCP6 CCP7
1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 Reset
0 RO reserved 31
Ethernet PHY Layer 0 Present
When set, indicates that Ethernet PHY layer 0 is present.
0x0 RO EPHY0 30
0 RO reserved 29
Ethernet MAC Layer 0 Present
When set, indicates that Ethernet MAC layer 0 is present.
0x0 RO EMAC0 28
0 RO reserved 27:25
1588 Capable
When set, indicates that Ethernet MAC layer 0 is 1588 capable.
0x0 RO E1588 24
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0 RO reserved 23:19
PIOSC Calibrate
When set, indicates that the PIOSC can be calibrated by software.
0x1 RO PICAL 18
0 RO reserved 17:16
T3CCP1 Pin Present
0x1 RO CCP7 15
T3CCP0 Pin Present
0x1 RO CCP6 14
Micro-DMA Module Present
When set, indicates that the micro-DMA module present.
0x1 RO UDMA 13
Internal Code ROM Present
When set, indicates that internal code ROM is present.
0x1 RO ROM 12
0 RO reserved 11:9
GPIO Port J Present
When set, indicates that GPIO Port J is present.
0x0 RO GPIOJ 8
GPIO Port H Present
When set, indicates that GPIO Port H is present.
0x0 RO GPIOH 7
GPIO Port G Present
When set, indicates that GPIO Port G is present.
0x1 RO GPIOG 6
GPIO Port F Present
When set, indicates that GPIO Port F is present.
0x1 RO GPIOF 5
GPIO Port E Present
When set, indicates that GPIO Port E is present.
0x1 RO GPIOE 4
GPIO Port D Present
When set, indicates that GPIO Port D is present.
0x1 RO GPIOD 3
GPIO Port C Present
When set, indicates that GPIO Port C is present.
0x1 RO GPIOC 2
GPIO Port B Present
When set, indicates that GPIO Port B is present.
0x1 RO GPIOB 1
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GPIO Port A Present
When set, indicates that GPIO Port A is present.
0x1 RO GPIOA 0
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This register is predefined by the part and can be used to verify PWM features. If any bit is clear in
this register, the module is not present.
The PWMPeripheral Properties (PWMPP) register should be used to determine what
pins and features are available on PWM modules. A read of this register correctly
identifies if a legacy pin or feature is present. Software must use the PWMPP register
to determine if a pin or feature that is not supported by the DCn registers is present.
Base 0x400F.E000
Offset 0x020
Type RO, reset 0x0730.00FF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved PWMESYNC PWMEFLT reserved PWMFAULT0 PWMFAULT1 PWMFAULT2 PWMFAULT3 reserved
0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 reserved
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:28
PWM Fault 3 Pin Present
When set, indicates that the PWM Fault 3 pin is present.
0x0 RO PWMFAULT3 27
0x1 RO PWMFAULT2 26
0x1 RO PWMFAULT1 25
0x1 RO PWMFAULT0 24
0 RO reserved 23:22
PWM Extended Fault Active
When set, indicates that the PWM Extended Fault feature is active.
0x1 RO PWMEFLT 21
PWM Extended SYNC Active
When set, indicates that the PWM Extended SYNC feature is active.
0x1 RO PWMESYNC 20
0 RO reserved 19:8
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PWM7 Pin Present
0x1 RO PWM7 7
PWM6 Pin Present
0x1 RO PWM6 6
PWM5 Pin Present
0x1 RO PWM5 5
PWM4 Pin Present
0x1 RO PWM4 4
PWM3 Pin Present
0x1 RO PWM3 3
PWM2 Pin Present
0x1 RO PWM2 2
PWM1 Pin Present
0x1 RO PWM1 1
PWM0 Pin Present
0x1 RO PWM0 0
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register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
The USB Peripheral Properties (USBPP) register should be used to determine what
features are available on the USB module. A read of this register correctly identifies if
a legacy feature is present. Software must use the USBPP register to determine if a
pin or feature that is not supported by the DCn registers is present.
Base 0x400F.E000
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
USB0 reserved USB0PHY reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:5
USB Module 0 PHY Present
When set, indicates that the USB module 0 PHY is present.
0x0 RO USB0PHY 4
0 RO reserved 3:2
USB Module 0 Present
This field indicates that USB module 0 is present and specifies its
capability.
Description sysValue
NA
USB0 is not present.
0x0
DEVICE
USB0 is Device Only.
0x1
HOST
USB0 is Device or Host.
0x2
OTG
USB0 is OTG.
0x3
0x0 RO USB0 1:0
April 10, 2013 416
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This register is predefined by the part and can be used to verify DMA channel features. A 1 indicates
the channel is available on this device; a 0 that the channel is only available on other devices in the
family. Channels can have multiple assignments, see Channel Assignments on page 529 for more
information.
Important: This register is provided for legacy software support only. The DMACHANS bit field in
the DMA Status (DMASTAT) register indicates the number of DMA channels.
Base 0x400F.E000
Offset 0x028
Type RO, reset 0xFFFF.FFFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DMACH16 DMACH17 DMACH18 DMACH19 DMACH20 DMACH21 DMACH22 DMACH23 DMACH24 DMACH25 DMACH26 DMACH27 DMACH28 DMACH29 DMACH30 reserved
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DMACH0 DMACH1 DMACH2 DMACH3 DMACH4 DMACH5 DMACH6 DMACH7 DMACH8 DMACH9 DMACH10 DMACH11 DMACH12 DMACH13 DMACH14 DMACH15
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
DMA Channel 31
When set, indicates DMA channel 31 is available.
0x1 RO reserved 31
DMA Channel 30
0x1 RO DMACH30 30
DMA Channel 29
0x1 RO DMACH29 29
DMA Channel 28
0x1 RO DMACH28 28
DMA Channel 27
0x1 RO DMACH27 27
DMA Channel 26
0x1 RO DMACH26 26
DMA Channel 25
0x1 RO DMACH25 25
DMA Channel 24
0x1 RO DMACH24 24
DMA Channel 23
0x1 RO DMACH23 23
DMA Channel 22
0x1 RO DMACH22 22
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DMA Channel 21
0x1 RO DMACH21 21
DMA Channel 20
0x1 RO DMACH20 20
DMA Channel 19
0x1 RO DMACH19 19
DMA Channel 18
0x1 RO DMACH18 18
DMA Channel 17
0x1 RO DMACH17 17
DMA Channel 16
0x1 RO DMACH16 16
DMA Channel 15
0x1 RO DMACH15 15
DMA Channel 14
0x1 RO DMACH14 14
DMA Channel 13
0x1 RO DMACH13 13
DMA Channel 12
0x1 RO DMACH12 12
DMA Channel 11
0x1 RO DMACH11 11
DMA Channel 10
0x1 RO DMACH10 10
DMA Channel 9
0x1 RO DMACH9 9
DMA Channel 8
0x1 RO DMACH8 8
DMA Channel 7
0x1 RO DMACH7 7
DMA Channel 6
0x1 RO DMACH6 6
DMA Channel 5
0x1 RO DMACH5 5
DMA Channel 4
0x1 RO DMACH4 4
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DMA Channel 3
0x1 RO DMACH3 3
DMA Channel 2
0x1 RO DMACH2 2
DMA Channel 1
0x1 RO DMACH1 1
DMA Channel 0
0x1 RO DMACH0 0
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Register 119: Device Capabilities 8 (DC8), offset 0x02C
This register is predefined by the part and can be used to verify features.
The ADC Peripheral Properties (ADCPP) register should be used to determine how
many input channels are available on the ADC module. A read of this register correctly
identifies if legacy channels are present but software must use the ADCPP register to
determine if a channel is present that is not supported by the DCn registers.
Base 0x400F.E000
Offset 0x02C
Type RO, reset 0x0FFF.0FFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADC1AIN0 ADC1AIN1 ADC1AIN2 ADC1AIN3 ADC1AIN4 ADC1AIN5 ADC1AIN6 ADC1AIN7 ADC1AIN8 ADC1AIN9 ADC1AIN10 ADC1AIN11 ADC1AIN12 ADC1AIN13 ADC1AIN14 ADC1AIN15
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADC0AIN0 ADC0AIN1 ADC0AIN2 ADC0AIN3 ADC0AIN4 ADC0AIN5 ADC0AIN6 ADC0AIN7 ADC0AIN8 ADC0AIN9 ADC0AIN10 ADC0AIN11 ADC0AIN12 ADC0AIN13 ADC0AIN14 ADC0AIN15
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 Reset
0x0 RO ADC1AIN15 31
0x0 RO ADC1AIN14 30
0x0 RO ADC1AIN13 29
0x0 RO ADC1AIN12 28
0x1 RO ADC1AIN11 27
0x1 RO ADC1AIN10 26
0x1 RO ADC1AIN9 25
0x1 RO ADC1AIN8 24
0x1 RO ADC1AIN7 23
0x1 RO ADC1AIN6 22
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0x1 RO ADC1AIN5 21
0x1 RO ADC1AIN4 20
0x1 RO ADC1AIN3 19
0x1 RO ADC1AIN2 18
0x1 RO ADC1AIN1 17
0x1 RO ADC1AIN0 16
0x0 RO ADC0AIN15 15
0x0 RO ADC0AIN14 14
0x0 RO ADC0AIN13 13
0x0 RO ADC0AIN12 12
0x1 RO ADC0AIN11 11
0x1 RO ADC0AIN10 10
0x1 RO ADC0AIN9 9
0x1 RO ADC0AIN8 8
0x1 RO ADC0AIN7 7
0x1 RO ADC0AIN6 6
0x1 RO ADC0AIN5 5
0x1 RO ADC0AIN4 4
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0x1 RO ADC0AIN3 3
0x1 RO ADC0AIN2 2
0x1 RO ADC0AIN1 1
0x1 RO ADC0AIN0 0
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Register 120: Software Reset Control 0 (SRCR0), offset 0x040
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 1 (DC1) register.
The peripheral-specific Software Reset registers (such as SRWD) should be used to
reset specific peripherals. A write to this legacy register also writes the corresponding
bit in the peripheral-specific register. Any bits that are changed by writing to this legacy
register can be read back correctly with a read of this register. Software must use the
peripheral-specific registers to support modules that are not present in the legacy
registers. If software uses a peripheral-specific register to write a legacy peripheral
(such as Watchdog 1), the write causes proper operation, but the value of that bit is not
reflected in this register. If software uses both legacy and peripheral-specific register
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADC0 ADC1 reserved PWM0 reserved CAN0 CAN1 reserved WDT1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved WDT0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:29
WDT1 Reset Control
When this bit is set, Watchdog Timer module 1 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
0x0 RO WDT1 28
0 RO reserved 27:26
CAN1 Reset Control
When this bit is set, CAN module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
0x0 RO CAN1 25
CAN0 Reset Control
When this bit is set, CAN module 0 is reset. All internal data is lost and
0x0 RO CAN0 24
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0 RO reserved 23:21
PWM Reset Control
When this bit is set, PWM module 0 is reset. All internal data is lost and
0x0 RO PWM0 20
0 RO reserved 19:18
ADC1 Reset Control
When this bit is set, ADC module 1 is reset. All internal data is lost and
0x0 RO ADC1 17
ADC0 Reset Control
When this bit is set, ADC module 0 is reset. All internal data is lost and
0x0 RO ADC0 16
0 RO reserved 15:4
WDT0 Reset Control
When this bit is set, Watchdog Timer module 0 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
0x0 RO WDT0 3
0 RO reserved 2:0
April 10, 2013 424
System Control
The peripheral-specific Software Reset registers (such as SRTIMER) should be used
to reset specific peripherals. A write to this register also writes the corresponding bit in
the peripheral-specific register. Any bits that are changed by writing to this register can
be read back correctly with a read of this register. Software must use the
(such as TIMER0), the write causes proper operation, but the value of that bit is not
Note that the Software Reset Analog Comparator (SRACMP) register has only one
bit to set the analog comparator module. Resetting the module resets all the blocks. If
any of the COMPn bits are set, the entire analog comparator module is reset. It is not
possible to reset the blocks individually.
Base 0x400F.E000
Offset 0x044
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TIMER0 TIMER1 TIMER2 TIMER3 reserved COMP0 COMP1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
UART0 UART1 UART2 reserved SSI0 SSI1 reserved QEI0 QEI1 reserved I2C0 reserved I2C1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:26
Analog Comp 1 Reset Control
When this bit is set, Analog Comparator module 1 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
0x0 RO COMP1 25
Analog Comp 0 Reset Control
When this bit is set, Analog Comparator module 0 is reset. All internal
0x0 RO COMP0 24
0 RO reserved 23:20
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Timer 3 Reset Control
Timer 3 Reset Control. When this bit is set, General-Purpose Timer
module 3 is reset. All internal data is lost and the registers are returned
to their reset states. This bit must be manually cleared after being set.
0x0 RO TIMER3 19
When this bit is set, General-Purpose Timer module 2 is reset. All internal
0x0 RO TIMER2 18
0x0 RO TIMER1 17
0x0 RO TIMER0 16
0 RO reserved 15
I2C1 Reset Control
When this bit is set, I2C module 1 is reset. All internal data is lost and
0x0 RO I2C1 14
0 RO reserved 13
I2C0 Reset Control
When this bit is set, I2C module 0 is reset. All internal data is lost and
0x0 RO I2C0 12
0 RO reserved 11:10
QEI1 Reset Control
When this bit is set, QEI module 1 is reset. All internal data is lost and
0x0 RO QEI1 9
QEI0 Reset Control
When this bit is set, QEI module 0 is reset. All internal data is lost and
0x0 RO QEI0 8
0 RO reserved 7:6
April 10, 2013 426
System Control
SSI1 Reset Control
When this bit is set, SSI module 1 is reset. All internal data is lost and
0x0 RO SSI1 5
SSI0 Reset Control
When this bit is set, SSI module 0 is reset. All internal data is lost and
0x0 RO SSI0 4
0 RO reserved 3
UART2 Reset Control
When this bit is set, UART module 2 is reset. All internal data is lost and
0x0 RO UART2 2
UART1 Reset Control
0x0 RO UART1 1
UART0 Reset Control
0x0 RO UART0 0
427 April 10, 2013
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The peripheral-specific Software Reset registers (such as SRDMA) should be used to
reset specific peripherals. A write to this legacy register also writes the corresponding
bit in the peripheral-specific register. Any bits that are changed by writing to this register
can be read back correctly with a read of this register. Software must use the
(such as the DMA), the write causes proper operation, but the value of that bit is not
Base 0x400F.E000
Offset 0x048
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG reserved UDMA reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:14
Micro-DMA Reset Control
When this bit is set, uDMA module is reset. All internal data is lost and
0x0 RO UDMA 13
0 RO reserved 12:7
Port G Reset Control
When this bit is set, Port G module is reset. All internal data is lost and
0x0 RO GPIOG 6
Port F Reset Control
When this bit is set, Port F module is reset. All internal data is lost and
0x0 RO GPIOF 5
April 10, 2013 428
System Control
Port E Reset Control
When this bit is set, Port E module is reset. All internal data is lost and
0x0 RO GPIOE 4
Port D Reset Control
When this bit is set, Port D module is reset. All internal data is lost and
0x0 RO GPIOD 3
Port C Reset Control
When this bit is set, Port C module is reset. All internal data is lost and
0x0 RO GPIOC 2
Port B Reset Control
When this bit is set, Port B module is reset. All internal data is lost and
0x0 RO GPIOB 1
Port A Reset Control
When this bit is set, Port A module is reset. All internal data is lost and
0x0 RO GPIOA 0
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Register 123: Run Mode Clock Gating Control Register 0 (RCGC0), offset
0x100
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes. Note that there must be a delay of 3 system clocks after a module clock is enabled before
any registers in that module are accessed.
The peripheral-specific Run Mode Clock Gating Control registers (such as RCGCWD)
should be used to reset specific peripherals. A write to this legacy register also writes
the corresponding bit in the peripheral-specific register. Any bits that are changed by
writing to this register can be read back correctly with a read of this register. Software
must use the peripheral-specific registers to support modules that are not present in
the legacy registers. If software uses a peripheral-specific register to write a legacy
peripheral (such as Watchdog 1), the write causes proper operation, but the value of
that bit is not reflected in this register. If software uses both legacy and peripheral-specific
Likewise, the ADC Peripheral Configuration (ADCPC) register should be used to
configure the ADCsample rate. However, to support legacy software, the MAXADCnSPD
fields are available. A write to these legacy fields also writes the corresponding field in
the peripheral-specific register. If a field is changed by writing to this register, it can be
read back correctly with a read of this register. Software must use the peripheral-specific
registers to support rates that are not available in this register. If software uses a
peripheral-specific register to set the ADC rate, the write causes proper operation, but
the value of that field is not reflected in this register. If software uses both legacy and
April 10, 2013 430
System Control
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved WDT0 reserved reserved reserved MAXADC0SPD MAXADC1SPD reserved
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:29
WDT1 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 1. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
0x0 RO WDT1 28
0 RO reserved 27:26
CAN1 Clock Gating Control
This bit controls the clock gating for CAN module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0x0 RO CAN1 25
0x0 RO CAN0 24
0 RO reserved 23:21
PWM Clock Gating Control
This bit controls the clock gating for the PWMmodule. If set, the module
0x0 RO PWM0 20
0 RO reserved 19:18
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ADC1 Clock Gating Control
This bit controls the clock gating for SAR ADC module 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
0x0 RO ADC1 17
This bit controls the clock gating for ADC module 0. If set, the module
0x0 RO ADC0 16
0 RO reserved 15:12
ADC1 Sample Speed
This field sets the rate at which ADCmodule 1 samples data. You cannot
set the rate higher than the maximum rate. You can set the sample rate
by setting the MAXADC1SPD bit as follows (all other encodings are
reserved):
Description Value
ADC0 Sample Speed
This field sets the rate at which ADC0 samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADC0SPD bit as follows (all other encodings are reserved):
Description Value
0 RO reserved 7
0x1 RO reserved 6
0 RO reserved 5:4
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0x0 RO WDT0 3
0 RO reserved 2:0
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0x104
The peripheral-specific Run Mode Clock Gating Control registers (such as RCGCTIMER)
peripheral (such as Timer 0), the write causes proper operation, but the value of that
bit is not reflected in this register. If software uses both legacy and peripheral-specific
Base 0x400F.E000
Offset 0x104
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:26
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System Control
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
0x0 RO COMP1 25
0x0 RO COMP0 24
0 RO reserved 23:20
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
0x0 RO TIMER3 19
0x0 RO TIMER2 18
0x0 RO TIMER1 17
0x0 RO TIMER0 16
0 RO reserved 15
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
0x0 RO I2C1 14
0 RO reserved 13
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0x0 RO I2C0 12
0 RO reserved 11:10
QEI1 Clock Gating Control
This bit controls the clock gating for QEI module 1. If set, the module
0x0 RO QEI1 9
0x0 RO QEI0 8
0 RO reserved 7:6
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
0x0 RO SSI1 5
0x0 RO SSI0 4
0 RO reserved 3
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
0x0 RO UART2 2
0x0 RO UART1 1
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0x0 RO UART0 0
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0x108
The peripheral-specific Run Mode Clock Gating Control registers (such as RCGCDMA)
peripheral (such as the DMA), the write causes proper operation, but the value of that
Base 0x400F.E000
Offset 0x108
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:14
April 10, 2013 438
System Control
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
0x0 RO UDMA 13
0 RO reserved 12:7
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0x0 RO GPIOG 6
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
bus fault.
0x0 RO GPIOF 5
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
0x0 RO GPIOE 4
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
0x0 RO GPIOD 3
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
bus fault.
0x0 RO GPIOC 2
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
bus fault.
0x0 RO GPIOB 1
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
bus fault.
0x0 RO GPIOA 0
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Register 126: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
modes.
The peripheral-specific Sleep Mode Clock Gating Control registers (such as SCGCWD)
peripheral (such as Watchdog 1), the write causes proper operation, but the value of
that bit is not reflected in this register. If software uses both legacy and peripheral-specific
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved WDT0 reserved reserved reserved
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:29
This bit controls the clock gating for Watchdog Timer module 1. If set,
the module receives a clock and functions. Otherwise, the module is
0x0 RO WDT1 28
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System Control
0 RO reserved 27:26
0x0 RO CAN1 25
0x0 RO CAN0 24
0 RO reserved 23:21
0x0 RO PWM0 20
0 RO reserved 19:18
0x0 RO ADC1 17
0x0 RO ADC0 16
0 RO reserved 15:7
0x1 RO reserved 6
0 RO reserved 5:4
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0x0 RO WDT0 3
0 RO reserved 2:0
April 10, 2013 442
System Control
0x114
modes.
The peripheral-specific Sleep Mode Clock Gating Control registers (such as
SCGCTIMER) should be used to reset specific peripherals. A write to this legacy register
also writes the corresponding bit in the peripheral-specific register. Any bits that are
changed by writing to this register can be read back correctly with a read of this register.
present in the legacy registers. If software uses a peripheral-specific register to write a
legacy peripheral (such as Timer 0), the write causes proper operation, but the value
of that bit is not reflected in this register. If software uses both legacy and
Base 0x400F.E000
Offset 0x114
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:26
0x0 RO COMP1 25
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0x0 RO COMP0 24
0 RO reserved 23:20
0x0 RO TIMER3 19
0x0 RO TIMER2 18
0x0 RO TIMER1 17
0x0 RO TIMER0 16
0 RO reserved 15
0x0 RO I2C1 14
0 RO reserved 13
0x0 RO I2C0 12
0 RO reserved 11:10
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System Control
0x0 RO QEI1 9
0x0 RO QEI0 8
0 RO reserved 7:6
0x0 RO SSI1 5
0x0 RO SSI0 4
0 RO reserved 3
0x0 RO UART2 2
0x0 RO UART1 1
0x0 RO UART0 0
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0x118
modes.
The peripheral-specific Sleep Mode Clock Gating Control registers (such as SCGCDMA)
peripheral (such as the DMA), the write causes proper operation, but the value of that
Base 0x400F.E000
Offset 0x118
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:14
0x0 RO UDMA 13
April 10, 2013 446
System Control
0 RO reserved 12:7
bus fault.
0x0 RO GPIOG 6
bus fault.
0x0 RO GPIOF 5
0x0 RO GPIOE 4
0x0 RO GPIOD 3
bus fault.
0x0 RO GPIOC 2
bus fault.
0x0 RO GPIOB 1
bus fault.
0x0 RO GPIOA 0
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Register 129: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
modes.
The peripheral-specific Deep Sleep Mode Clock Gating Control registers (such as
DCGCWD) should be used to reset specific peripherals. A write to this legacy register
legacy peripheral (such as Watchdog 1), the write causes proper operation, but the
value of that bit is not reflected in this register. If software uses both legacy and
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved WDT0 reserved reserved reserved
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:29
0x0 RO WDT1 28
April 10, 2013 448
System Control
0 RO reserved 27:26
0x0 RO CAN1 25
0x0 RO CAN0 24
0 RO reserved 23:21
0x0 RO PWM0 20
0 RO reserved 19:18
0x0 RO ADC1 17
0x0 RO ADC0 16
0 RO reserved 15:7
0x1 RO reserved 6
0 RO reserved 5:4
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0x0 RO WDT0 3
0 RO reserved 2:0
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System Control
Register 130: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
modes.
DCGCTIMER) should be used to reset specific peripherals. A write to this legacy register
legacy peripheral (such as Timer 0), the write causes proper operation, but the value
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:26
0x0 RO COMP1 25
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0x0 RO COMP0 24
0 RO reserved 23:20
0x0 RO TIMER3 19
0x0 RO TIMER2 18
0x0 RO TIMER1 17
0x0 RO TIMER0 16
0 RO reserved 15
0x0 RO I2C1 14
0 RO reserved 13
0x0 RO I2C0 12
0 RO reserved 11:10
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System Control
0x0 RO QEI1 9
0x0 RO QEI0 8
0 RO reserved 7:6
0x0 RO SSI1 5
0x0 RO SSI0 4
0 RO reserved 3
0x0 RO UART2 2
0x0 RO UART1 1
0x0 RO UART0 0
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Register 131: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
modes.
DCGCDMA) should be used to reset specific peripherals. A write to this legacy register
legacy peripheral (such as the DMA), the write causes proper operation, but the value
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:14
0x0 RO UDMA 13
April 10, 2013 454
System Control
0 RO reserved 12:7
bus fault.
0x0 RO GPIOG 6
bus fault.
0x0 RO GPIOF 5
0x0 RO GPIOE 4
0x0 RO GPIOD 3
bus fault.
0x0 RO GPIOC 2
bus fault.
0x0 RO GPIOB 1
bus fault.
0x0 RO GPIOA 0
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This register is predefined by the part and can be used to verify ADC digital comparator features.
The ADC Peripheral Properties (ADCPP) register should be used to determine how
many digital comparators are available on the ADC module. A read of this register
correctly identifies if legacy comparators are present. Software must use the ADCPP
register to determine if a comparator that is not supported by the DCn registers is
present.
Base 0x400F.E000
Offset 0x190
Type RO, reset 0x00FF.00FF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADC1DC0 ADC1DC1 ADC1DC2 ADC1DC3 ADC1DC4 ADC1DC5 ADC1DC6 ADC1DC7 reserved
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADC0DC0 ADC0DC1 ADC0DC2 ADC0DC3 ADC0DC4 ADC0DC5 ADC0DC6 ADC0DC7 reserved
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:24
ADC1 DC7 Present
When set, indicates that ADCmodule 1 Digital Comparator 7 is present.
0x1 RO ADC1DC7 23
ADC1 DC6 Present
0x1 RO ADC1DC6 22
ADC1 DC5 Present
0x1 RO ADC1DC5 21
ADC1 DC4 Present
0x1 RO ADC1DC4 20
ADC1 DC3 Present
0x1 RO ADC1DC3 19
ADC1 DC2 Present
0x1 RO ADC1DC2 18
ADC1 DC1 Present
0x1 RO ADC1DC1 17
ADC1 DC0 Present
0x1 RO ADC1DC0 16
April 10, 2013 456
System Control
0 RO reserved 15:8
ADC0 DC7 Present
0x1 RO ADC0DC7 7
ADC0 DC6 Present
0x1 RO ADC0DC6 6
ADC0 DC5 Present
0x1 RO ADC0DC5 5
ADC0 DC4 Present
0x1 RO ADC0DC4 4
ADC0 DC3 Present
0x1 RO ADC0DC3 3
ADC0 DC2 Present
0x1 RO ADC0DC2 2
ADC0 DC1 Present
0x1 RO ADC0DC1 1
ADC0 DC0 Present
0x1 RO ADC0DC0 0
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Register 133: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0
This register is predefined by the part and can be used to verify features.
The ROM Third-Party Software (ROMSWMAP) register should be used to determine
the presence of third-party software in the on-chip ROM on this microcontroller. A read
of the TPSW bit in this register correctly identifies the presence of legacy third-party
software. Software should use the ROMSWMAP register for software that is not on
legacy devices.
Non-Volatile Memory Information (NVMSTAT)
Base 0x400F.E000
Offset 0x1A0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FWB reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
32 Word Flash Write Buffer Available
When set, indicates that the 32 word Flash memory write buffer feature
is available.
0x1 RO FWB 0
April 10, 2013 458
System Control
6 System Exception Module
This module is an AHBperipheral that handles system-level Cortex-M4 FPUexceptions. For functions
with registers mapped into this aperture, if the function is not available on a device, then all writes
to the associated registers are ignored and reads return zeros.
The System Exception module provides control and status of the system-level interrupts. All the
interrupt events are ORed together before being sent to the interrupt controller, so the System
Exception module can only generate a single interrupt request to the controller at any given time.
Software can service multiple interrupt events in a single interrupt service routine by reading the
SystemException Masked Interrupt Status (SYSEXCMIS) register. The interrupt events that can
trigger a controller-level interrupt are defined in the SystemException Interrupt Mask (SYSEXCIM)
register by setting the corresponding interrupt mask bits. If interrupts are not used, the raw interrupt
status is always visible via the System Exception Raw Interrupt Status (SYSEXCRIS) register.
Interrupts are always cleared (for both the SYSEXCMIS and SYSEXCRIS registers) by writing a 1
to the corresponding bit in the System Exception Interrupt Clear (SYSEXCIC) register.
6.2 Register Map
Table 6-1 on page 459 lists the SystemException module registers. The offset listed is a hexadecimal
increment to the register's address, relative to the System Exception base address of 0x400F.9000.
Note: Spaces in the System Exception register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 6-1. System Exception Register Map
See
page
460 System Exception Raw Interrupt Status 0x0000.0000 RO SYSEXCRIS 0x000
462 System Exception Interrupt Mask 0x0000.0000 R/W SYSEXCIM 0x004
464 System Exception Masked Interrupt Status 0x0000.0000 RO SYSEXCMIS 0x008
466 System Exception Interrupt Clear 0x0000.0000 W1C SYSEXCIC 0x00C
All addresses given are relative to the System Exception base address of 0x400F.9000.
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Register 1: SystemException RawInterrupt Status (SYSEXCRIS), offset 0x000
The SYSEXCRIS register is the raw interrupt status register. On a read, this register gives the
current raw status value of the corresponding interrupt. A write has no effect.
System Exception Raw Interrupt Status (SYSEXCRIS)
Base 0x400F.9000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FPIDCRIS FPDZCRIS FPIOCRIS FPUFCRIS FPOFCRIS FPIXCRIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Floating-Point Inexact Exception Raw Interrupt Status
Description Value
No interrupt 0
A floating-point inexact exception has occurred. 1
This bit is cleared by writing a 1 to the IXCIC bit in the SYSEXCIC
register.
0 RO FPIXCRIS 5
Floating-Point Overflow Exception Raw Interrupt Status
Description Value
No interrupt 0
A floating-point overflow exception has occurred. 1
This bit is cleared by writing a 1 to the OFCIC bit in the SYSEXCIC
register.
0 RO FPOFCRIS 4
Floating-Point Underflow Exception Raw Interrupt Status
Description Value
No interrupt 0
A floating-point underflow exception has occurred. 1
This bit is cleared by writing a 1 to the UFCIC bit in the SYSEXCIC
register.
0 RO FPUFCRIS 3
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System Exception Module
Floating-Point Invalid Operation Raw Interrupt Status
Description Value
No interrupt 0
A floating-point invalid operation exception has occurred. 1
This bit is cleared by writing a 1 to the IOCIC bit in the SYSEXCIC
register.
0 RO FPIOCRIS 2
Floating-Point Divide By 0 Exception Raw Interrupt Status
Description Value
No interrupt 0
A floating-point divide by 0 exception has occurred. 1
This bit is cleared by writing a 1 to the DZCIC bit in the SYSEXCIC
register.
0 RO FPDZCRIS 1
Floating-Point Input Denormal Exception Raw Interrupt Status
Description Value
No interrupt 0
A floating-point input denormal exception has occurred. 1
This bit is cleared by writing a 1 to the IDCIC bit in the SYSEXCIC
register.
0 RO FPIDCRIS 0
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Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004
The SYSEXCIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
System Exception Interrupt Mask (SYSEXCIM)
Base 0x400F.9000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FPIDCIM FPDZCIM FPIOCIM FPUFCIM FPOFCIM FPIXCIM reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0000.00 R/W reserved 31:6
Floating-Point Inexact Exception Interrupt Mask
Description Value
The FPIXCRIS interrupt is suppressed and not sent to the
0
FPISCRIS bit in the SYSEXCRIS register is set.
1
0 R/W FPIXCIM 5
Floating-Point Overflow Exception Interrupt Mask
Description Value
The FPOFCIS interrupt is suppressed and not sent to the
0
FPOFCRIS bit in the SYSEXCRIS register is set.
1
0 R/W FPOFCIM 4
Floating-Point Underflow Exception Interrupt Mask
Description Value
The FPUFCRIS interrupt is suppressed and not sent to the
0
FPUFCRIS bit in the SYSEXCRIS register is set.
1
0 R/W FPUFCIM 3
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Floating-Point Invalid Operation Interrupt Mask
Description Value
The FPIOCRIS interrupt is suppressed and not sent to the
0
FPIOCRIS bit in the SYSEXCRIS register is set.
1
0 R/W FPIOCIM 2
Floating-Point Divide By 0 Exception Interrupt Mask
Description Value
The FPDZCRIS interrupt is suppressed and not sent to the
0
FPDZCRIS bit in the SYSEXCRIS register is set.
1
0 R/W FPDZCIM 1
Floating-Point Input Denormal Exception Interrupt Mask
Description Value
The FPIDCRIS interrupt is suppressed and not sent to the
0
FPIDCRIS bit in the SYSEXCRIS register is set.
1
0 R/W FPIDCIM 0
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Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset
0x008
The SYSEXCMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
System Exception Masked Interrupt Status (SYSEXCMIS)
Base 0x400F.9000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FPIDCMIS FPDZCMIS FPIOCMIS FPUFCMIS FPOFCMIS FPIXCMIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Floating-Point Inexact Exception Masked Interrupt Status
Description Value
An interrupt has not occurred or is masked. 0
An unmasked interrupt was signaled due to an inexact
exception.
1
This bit is cleared by writing a 1 to the FPIXCIC bit in the SYSEXCIC
register.
0 RO FPIXCMIS 5
Floating-Point Overflow Exception Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to an overflow
exception.
1
This bit is cleared by writing a 1 to the FPOFCIC bit in the SYSEXCIC
register.
0 RO FPOFCMIS 4
Floating-Point Underflow Exception Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to an underflow
exception.
1
This bit is cleared by writing a 1 to the FPUFCIC bit in the SYSEXCIC
register.
0 RO FPUFCMIS 3
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Floating-Point Invalid Operation Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to an invalid operation. 1
This bit is cleared by writing a 1 to the FPIOCIC bit in the SYSEXCIC
register.
0 RO FPIOCMIS 2
Floating-Point Divide By 0 Exception Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to a divide by 0
exception.
1
This bit is cleared by writing a 1 to the FPDZCIC bit in the SYSEXCIC
register.
0 RO FPDZCMIS 1
Floating-Point Input Denormal Exception Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to an input denormal
exception.
1
This bit is cleared by writing a 1 to the FPIDCIC bit in the SYSEXCIC
register.
0 RO FPIDCMIS 0
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Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C
The SYSEXCIC register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
System Exception Interrupt Clear (SYSEXCIC)
Base 0x400F.9000
Offset 0x00C
Type W1C, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FPIDCIC FPDZCIC FPIOCIC FPUFCIC FPOFCIC FPIXCIC reserved
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0000.00 W1C reserved 31:6
Floating-Point Inexact Exception Interrupt Clear
Writing a 1 to this bit clears the FPIXCRIS bit in the SYSEXCRISregister
and the FPIXCMIS bit in the SYSEXCMIS register.
0 W1C FPIXCIC 5
Floating-Point Overflow Exception Interrupt Clear
Writing a 1 to this bit clears the FPOFCRIS bit in the SYSEXCRISregister
and the FPOFCMIS bit in the SYSEXCMIS register.
0 W1C FPOFCIC 4
Floating-Point Underflow Exception Interrupt Clear
Writing a 1 to this bit clears the FPUFCRIS bit in the SYSEXCRISregister
and the FPUFCMIS bit in the SYSEXCMIS register.
0 W1C FPUFCIC 3
Floating-Point Invalid Operation Interrupt Clear
Writing a 1 to this bit clears the FPIOCRIS bit in the SYSEXCRISregister
and the FPIOCMIS bit in the SYSEXCMIS register.
0 W1C FPIOCIC 2
Floating-Point Divide By 0 Exception Interrupt Clear
Writing a 1 to this bit clears the FPDZCRIS bit in the SYSEXCRISregister
and the FPDZCMIS bit in the SYSEXCMIS register.
0 W1C FPDZCIC 1
Floating-Point Input Denormal Exception Interrupt Clear
Writing a 1 to this bit clears the FPIDCRIS bit in the SYSEXCRISregister
and the FPIDCMIS bit in the SYSEXCMIS register.
0 W1C FPIDCIC 0
April 10, 2013 466
7 Internal Memory
The TM4C123AH6PM microcontroller comes with 32 KB of bit-banded SRAM, internal ROM, 256
KB of Flash memory, and 2KB of EEPROM. The Flash memory controller provides a user-friendly
interface, making Flash memory programming a simple task. Flash memory is organized in 1-KB
independently erasable blocks and memory protection can be applied to the Flash memory on a
2-KBblock basis. The EEPROMmodule provides a well-defined register interface to support accesses
to the EEPROM with both a random access style of read and write as well as a rolling or sequential
access scheme. A password model allows the application to lock one or more EEPROM blocks to
control access on 16-word boundaries.
7.1 Block Diagram
Figure 7-1 on page 467 illustrates the internal SRAM, ROM, and Flash memory blocks and control
logic. The dashed boxes in the figure indicate registers residing in the System Control module.
Figure 7-1. Internal Memory Block Diagram
ROM Control
RMCTL
ROM Array
Flash Control
FMA
FMD
FCIM
FCMISC
Flash Array
Cortex-M4F
Bridge
SRAM Array
S
y
s
t
e
m
B
u
s
Icode Bus
Dcode Bus
FMPRE
FMPPE
Flash Protection
FMPREn
FMPPEn
User Registers
BOOTCFG
USER_REG0
USER_REG1
USER_REG2
USER_REG3
FMC
FCRIS
FMC2
FWBVAL
FWBn
32 words
FSIZE
SSIZE
Flash Write Buffer
ROMSWMAP
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Figure 7-2 on page 468 illustrates the internal EEPROMblock and control logic. The EEPROMblock
is connected to the AHB bus.
Figure 7-2. EEPROM Block Diagram
Block 0
Block 1
Block 2
Block n
...
EEBLOCK
EEOFFSET
EERDWR
EERDWRINC
Security
Program
EEPROM Array EEPROM Control
EEDONE
EESUPP
EEUNLOCK
EEPROT
EEPASS0
EEPASS1
EEPASS2
EEINT
EEHIDE
EEDBGME
EESIZE
Block 3
EEPROMPP
This section describes the functionality of the SRAM, ROM, Flash, and EEPROM memories.
Note: The DMA controller can transfer data to and from the on-chip SRAM. However, because
the Flash memory and ROM are located on a separate internal bus, it is not possible to
transfer data from the Flash memory or ROM with the DMA controller.
7.2.1 SRAM
The internal SRAMof the TM4C123AH6PMdevice is located at address 0x2000.0000 of the device
memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM
provides bit-banding technology in the processor. With a bit-band-enabled processor, certain regions
in the memory map (SRAM and peripheral space) can use address aliases to access individual bits
in a single, atomic operation. The bit-band base is located at address 0x2200.0000.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see Bit-Banding on page 86.
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Note: The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays).
The banks are partitioned such that one bank contains all even words (the even bank) and
the other contains all odd words (the odd bank). A write access that is followed immediately
by a read access to the same bank incurs a stall of a single clock cycle. However, a write
to one bank followed by a read of the other bank can occur in successive clock cycles
without incurring any delay.
7.2.2 ROM
The internal ROM of the TM4C123AH6PM device is located at address 0x0100.0000 of the device
memory map. Detailed information on the ROM contents can be found in the TM4C123AH6PM
ROM Users Guide.
The ROM contains the following components:
TivaWare
Boot Loader and vector table

TivaWare Peripheral Driver Library (DriverLib) release for product-specific peripherals and
interfaces
Cyclic Redundancy Check (CRC) error detection functionality
The boot loader is used as an initial program loader (when the Flash memory is empty) as well as
an application-initiated firmware upgrade mechanism (by calling back to the boot loader). The
Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory
requirements and freeing the Flash memory to be used for other purposes (such as additional
features in the application). Advance Encryption Standard (AES) is a publicly defined encryption
standard used by the U.S. Government and Cyclic Redundancy Check (CRC) is a technique to
validate if a block of data has the same contents as when previously checked.
7.2.2.1 Boot Loader Overview
The TivaWare Boot Loader is used to download code to the Flash memory of a device without the
use of a debug interface. When the core is reset, the user has the opportunity to direct the core to
execute the ROMBoot Loader or the application in Flash memory by using any GPIOsignal in Ports
A-H as configured in the Boot Configuration (BOOTCFG) register (see page 523).
3. If the EN bit is set or the status doesn't match the specified polarity, the data at address
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The boot loader uses a simple packet interface to provide synchronous communication with the
device. The speed of the boot loader is determined by the internal oscillator (PIOSC) frequency as
it does not enable the PLL. The following serial interfaces can be used:
UART0
SSI0
I
2
C0
USB
The data format and communication protocol are identical for the UART0, SSI0, and I2C0 interfaces.
Note: The Flash-memory-resident version of the boot loader also supports CAN.
See the TivaWare Boot Loader for C Series User's Guide for information on the boot loader
software. The USB boot loader uses the standard Device Firmware Upgrade USB device class.
Considerations When Using the UART Boot Loader in ROM
U0Tx is not driven by the ROM boot loader until the auto-bauding process has completed. If U0Tx
is floating during this time, the receiver it is connected to may see transitions on the signal, which
could be interpreted by its UART as valid characters. To handle this situation, put a pull-up or
pull-down on U0Tx, providing a defined state for the signal until the ROM boot loader begins driving
U0Tx. A pull-up is preferred as it indicates that the UART is idle, rather than a pull-down, which
indicates a break condition.
7.2.2.2 TivaWare Peripheral Driver Library
The TivaWare Peripheral Driver Library contains a file called driverlib/rom.h that assists with
calling the peripheral driver library functions in the ROM. The detailed description of each function
is available in the TM4C123AH6PM ROM Users Guide. See the "Using the ROM" chapter of the
TivaWare Peripheral Driver Library for C Series User's Guide for more details on calling the ROM
functions and using driverlib/rom.h. The driverlib/rom_map.h header file is also provided
to aid portability when using different Tiva C Series devices which might have a different subset
of DriverLib functions in ROM. The driverlib/rom_map.h header file uses build-time labels to
route function calls to the ROMif those functions are available on a given device, otherwise, it routes
to Flash-resident versions of the functions.
A table at the beginning of the ROM points to the entry points for the APIs that are provided in the
ROM. Accessing the API through these tables provides scalability; while the API locations may
change in future versions of the ROM, the API tables will not. The tables are split into two levels;
the main table contains one pointer per peripheral which points to a secondary table that contains
one pointer per API that is associated with that peripheral. The main table is located at 0x0100.0010,
right after the Cortex-M4F vector table in the ROM.
DriverLib functions are described in detail in the TivaWare Peripheral Driver Library for C Series
User's Guide.
Additional APIs are available for graphics and USB functions, but are not preloaded into ROM. The
TivaWare Graphics Library provides a set of graphics primitives and a widget set for creating graphical
user interfaces on Tiva C Series microcontroller-based boards that have a graphical display (for
more information, see the TivaWare Graphics Library for C Series User's Guide).
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7.2.2.3 Advanced Encryption Standard (AES) Cryptography Tables
AES is a strong encryption method with reasonable performance and size. AES is fast in both
hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for
applications that can use pre-arranged keys, such as setup during manufacturing or configuration.
Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the
forward S-box substitution table, the second is the reverse S-box substitution table, the third is the
forward polynomial table, and the final is the reverse polynomial table. See the TM4C123AH6PM
ROM Users Guide for more information on AES.
7.2.2.4 Cyclic Redundancy Check (CRC) Error Detection
The CRC technique can be used to validate correct receipt of messages (nothing lost or modified
in transit), to validate data after decompression, to validate that Flash memory contents have not
been changed, and for other cases where the data needs to be validated. A CRC is preferred over
a simple checksum (e.g. XOR all bits) because it catches changes more readily. See the
TM4C123AH6PM ROM Users Guide for more information on CRC.
7.2.3 Flash Memory
At system clock speeds of 40 MHz and below, the Flash memory is read in a single cycle. The Flash
memory is organized as a set of 1-KB blocks that can be individually erased. An individual 32-bit
word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability
to program 32 continuous words in Flash memory in half the time of programming the words
individually. Erasing a block causes the entire contents of the block to be reset to all 1s. The 1-KB
blocks are paired into sets of 2-KB blocks that can be individually protected. The protection allows
blocks to be marked as read-only or execute-only, providing different levels of code protection.
Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from
being modified. Execute-only blocks cannot be erased or programmed and can only be read by the
controller instruction fetch mechanism, protecting the contents of those blocks from being read by
either the controller or a debugger.
7.2.3.1 Prefetch Buffer
The Flash memory controller has a prefetch buffer that is automatically used when the CPUfrequency
is greater than 40 MHz. In this mode, the Flash memory operates at half of the system clock. The
prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait
states while code is executing linearly. The fetch buffer includes a branch speculation mechanism
that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short
loop branches often stay in the buffer. As a result, some branches can be executed with no wait
states. Other branches incur a single wait state.
7.2.3.2 Flash Memory Protection
The user is provided two forms of Flash memory protection per 2-KB Flash memory block in four
pairs of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per
policy per block) in the FMPPEn and FMPREn registers.
Flash Memory Protection Program Enable (FMPPEn): If a bit is set, the corresponding block
may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be
changed.
Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
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The policies may be combined as shown in Table 7-1 on page 472.
Table 7-1. Flash Memory Protection Policy Combinations
Protection FMPREn FMPPEn
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
0 0
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
0 1
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
1 0
No protection. The block may be written, erased, executed or read. 1 1
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are effective immediately, but are not
permanent until the register is committed (saved), at which point the bit change is permanent. If a
bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset
sequence. The changes are committed using the Flash Memory Control (FMC) register. Details
on programming these bits are discussed in Non-Volatile Register Programming on page 475.
7.2.3.3 Execute-Only Protection
Execute-only protection prevents both modification and visibility to a protected flash block. This
mode is intended to be used in situations where a device requires debug capability, yet portions of
the application space must be protected from external access. An example of this is a company
who wishes to sell Tiva C Series devices with their proprietary software pre-programmed, yet
allowthe end user to add customcode to an unprotected region of the flash (such as a motor control
module with a customizable motor configuration section in flash).
Literal data introduces a complication to the protection mechanism. When C code is compiled and
linked, literal data (constants, and so on) is typically placed in the text section, between functions,
by the compiler. The literal data is accessed at run time through the use of the LDR instruction,
which loads the data from memory using a PC-relative memory address. The execution of the LDR
instruction generates a read transaction across the Cortex-M3's DCode bus, which is subject to the
execute-only protection mechanism. If the accessed block is marked as execute only, the transaction
is blocked, and the processor is prevented from loading the constant data and, therefore, inhibiting
correct execution. Therefore, using execute-only protection requires that literal data be handled
differently. There are three ways to address this:
1. Use a compiler that allows literal data to be collected into a separate section that is put into one
or more read-enabled flash blocks. Note that the LDR instruction may use a PC-relative
address-in which case the literal pool cannot be located outside the span of the offset-or the
software may reserve a register to point to the base address of the literal pool and the LDR
offset is relative to the beginning of the pool.
2. Use a compiler that generates literal data from arithmetic instruction immediate data and
subsequent computation.
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3. Use method 1 or 2, but in assembly language, if the compiler does not support either method.
7.2.3.4 Read-Only Protection
Read-only protection prevents the contents of the flash block from being re-programmed, while still
allowing the content to be read by processor or the debug interface. Note that if a FMPREn bit is
cleared, all read accesses to the Flash memory block are disallowed, including any data accesses.
Care must be taken not to store required data in a Flash memory block that has the associated
FMPREn bit cleared.
The read-only mode does not prevent read access to the stored program, but it does provide
protection against accidental (or malicious) erasure or programming. Read-only is especially useful
for utilities like the boot loader when the debug interface is permanently disabled. In such
combinations, the boot loader, which provides access control to the Flash memory, is protected
from being erased or modified.
7.2.3.5 Permanently Disabling Debug
For extremely sensitive applications, the debug interface to the processor and peripherals can be
permanently disabled, blocking all accesses to the device through the JTAG or SWD interfaces.
With the debug interface disabled, it is still possible to perform standard IEEE instructions (such as
boundary scan operations), but access to the processor and peripherals is blocked.
The DBG0 and DBG1 bits of the Boot Configuration (BOOTCFG) register control whether the debug
interface is turned on or off.
The debug interface should not be permanently disabled without providing some mechanism-such
as the boot loader-to provide customer-installable updates or bug fixes. Disabling the debug
interface is permanent and cannot be reversed.
7.2.3.6 Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
Programming Interrupt - signals when a program or erase action is complete.
Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 491) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 488).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 493).
7.2.3.7 Flash Memory Programming
The Tiva C Series devices provide a user-friendly interface for Flash memory programming. All
erase/program operations are handled via three registers: Flash Memory Address (FMA), Flash
Memory Data (FMD), and Flash Memory Control (FMC). Note that if the debug capabilities of the
microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be
performed in order to reactivate the debug module. See Recovering a "Locked"
Microcontroller on page 194.
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During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory
is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation
is complete. If instruction execution is required during a Flash memory operation, the code that is
executing must be placed in SRAMand executed fromthere while the flash operation is in progress.
Note: When programming Flash memory, the following characteristics of the memory must be
considered:
Only an erase can change bits from 0 to 1.
A write can only change bits from 1 to 0. If the write attempts to change a 0 to a 1, the
write fails and no bits are changed.
A flash operation can be started before entering the Sleep or Deep-sleep mode (using
the wait for interrupt instruction, WFI). It can also be completed while in Sleep or
Deep-sleep. If the Flash program/erase event comes in succession to EEPROMaccess,
the Flash event gets completed after waking from Sleep/Deep-sleep and is started after
the wake-up.
7.2.3.8 Basic Program / Erase Operations
To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the Flash memory write key and the WRITE bit to the FMC register. Depending on the
value of the KEY bit in the BOOTCFG register, the value 0xA442 or 0x71D5 must be written
into the WRKEY field for a Flash memory write to occur.
4. Poll the FMC register until the WRITE bit is cleared.
To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the Flash memory write key and the ERASE bit to the FMC register. Depending on the
3. Poll the FMC register until the ERASE bit is cleared or, alternatively, enable the programming
interrupt using the PMASK bit in the FCIM register.
To perform a mass erase of the Flash memory
1. Write the Flash memory write key and the MERASE bit to the FMC register. Depending on the
2. Poll the FMC register until the MERASE bit is cleared or, alternatively, enable the programming
interrupt using the PMASK bit in the FCIM register.
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7.2.3.9 32-Word Flash Memory Write Buffer
A 32-word write buffer provides the capability to perform faster write accesses to the Flash memory
by programming 2 32-bit words at a time, allowing 32 words to be programmed in the same time
as 16 would take using the method described above. The data for the buffered write is written to
the Flash Write Buffer (FWBn) registers.
The registers are 32-word aligned with Flash memory, and therefore the register FWB0 corresponds
with the address in FMA where bits [6:0] of FMA are all 0. FWB1 corresponds with the address in
FMA + 0x4 and so on. Only the FWBn registers that have been updated since the previous buffered
Flash memory write operation are written. The Flash Write Buffer Valid (FWBVAL) register shows
which registers have been written since the last buffered Flash memory write operation. This register
contains a bit for each of the 32 FWBn registers, where bit[n] of FWBVAL corresponds to FWBn.
The FWBn register has been updated if the corresponding bit in the FWBVAL register is set.
To program 32 words with a single buffered Flash memory write operation
1. Write the source data to the FWBn registers.
2. Write the target address to the FMA register. This must be a 32-word aligned address (that is,
bits [6:0] in FMA must be 0s).
3. Write the Flash memory write key and the WRBUF bit to the FMC2 register. Depending on the
4. Poll the FMC2 register until the WRBUF bit is cleared or wait for the PMIS interrupt to be signaled.
7.2.3.10 Non-Volatile Register Programming
Note: The Boot Configuration (BOOTCFG) register requires a POR before the committed
changes take effect.
This section discusses howto update the registers shown in Table 7-2 on page 476 that are resident
within the Flash memory itself. These registers exist in a separate space fromthe main Flash memory
array and are not affected by an ERASE or MASS ERASE operation. With the exception of the Boot
Configuration (BOOTCFG) register, the settings in these registers can be written, their functions
verified, and their values read back before they are committed, at which point they become
non-volatile. If a value in one of these registers has not been committed, a power-on reset restores
the last committed value or the default value if the register has never been committed. Other types
of reset have no effect. Once the register contents are committed, the only way to restore the factory
default values is to perform the sequence described in Recovering a "Locked"
To write to a non-volatile register:
Bits can only be changed from 1 to 0.
For all registers except the BOOTCFG register, write the data to the register address provided
in the register description. For the BOOTCFG register, write the data to the FMD register.
The registers can be read to verify their contents. To verify what is to be stored in the BOOTCFG
register, read the FMDregister. Reading the BOOTCFGregister returns the previously committed
value or the default value if the register has never been committed.
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The new values are effectively immediately for all registers except BOOTCFG, as the new value
for the register is not stored in the register until it has been committed.
Prior to committing the register value, a power-on reset restores the last committed value or the
default value if the register has never been committed.
To commit a new value to a non-volatile register:
Write the data as described above.
Write to the FMA register the value shown in Table 7-2 on page 476.
Write the Flash memory write key and set the COMT bit in the FMC register. These values must
be written to the FMC register at the same time.
Committing a non-volatile register has the same timing as a write to regular Flash memory,
defined by T
PROG64
, as shown in Table 22-23 on page 1205. Software can poll the COMT bit in the
FMC register to determine when the operation is complete, or an interrupt can be enabled by
setting the PMASK bit in the FCIM register.
When committing the BOOTCFG register, the INVDRIS bit in the FCRIS register is set if a bit
that has already been committed as a 0 is attempted to be committed as a 1.
Once the value has been committed, a power-on reset has no effect on the register contents.
Changes to the BOOTCFG register are effective after the next power-on reset.
Once the NW bit has been changed to 0 and committed, further changes to the BOOTCFGregister
are not allowed.
Important: After being committed, these registers can only be restored to their factory default values
by performing the sequence described in Recovering a "Locked"
Microcontroller on page 194. The mass erase of the main Flash memory array caused
by the sequence is performed prior to restoring these registers.
Table 7-2. User-Programmable Flash Memory Resident Registers
Data Source FMA Value Register to be Committed
FMPRE0 0x0000.0000 FMPRE0
FMPPE0 0x0000.0001 FMPPE0
USER_REG0 0x8000.0000 USER_REG0
FMD 0x7510.0000 BOOTCFG
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7.2.4 EEPROM
The TM4C123AH6PM microcontroller includes an EEPROM with the following features:
2Kbytes of memory accessible as 512 32-bit words
32 blocks of 16 words (64 bytes) each
Built-in wear leveling
Access protection per block
Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock
codes (application selectable)
Interrupt support for write completion to avoid polling
Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion)
to 15M operations (when cycling through two pages ) per each 2-page block.
7.2.4.1 Functional Description
The EEPROMmodule provides a well-defined register interface to support accesses to the EEPROM
with both a random access style of read and write as well as a rolling or sequential access scheme.
A protection mechanism allows locking EEPROM blocks to prevent writes under a set of
circumstances as well as reads under the same or different circumstances. The password model
allows the application to lock one or more EEPROMblocks to control access on 16-word boundaries.
Important: The configuration of the systemclock must not be changed while an EEPROMoperation
is in process. Software must wait until the WORKING bit in the EEPROM Done Status
(EEDONE) register is clear before making any changes to the system clock.
Blocks
There are 32 blocks of 16 words each in the EEPROM. Bytes and half-words can be read, and
these accesses do not have to occur on a word boundary. The entire word is read and any unneeded
data is simply ignored. They are writable only on a word basis. To write a byte, it is necessary to
read the word value, modify the appropriate byte, and write the word back.
Each block is addressable as an offset within the EEPROM, using a block select register. Each
word is offset addressable within the selected block.
The current block is selected by the EEPROM Current Block (EEBLOCK) register. The current
offset is selected and checked for validity by the EEPROM Current Offset (EEOFFSET) register.
The application may write the EEOFFSET register any time, and it is also automatically incremented
when the EEPROM Read-Write with Increment (EERDWRINC) register is accessed. However,
the EERDWRINC register does not increment the block number, but instead wraps within the block.
Blocks are individually protectable. Attempts to read from a block for which the application does not
have permission return 0xFFFF.FFFF. Attempts to write into a block for which the application does
not have permission results in an error in the EEDONE register.
Timing Considerations
After enabling or resetting the EEPROM module, software must wait until the WORKING bit in the
EEDONE register is clear before accessing any EEPROM registers.
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In the event that there are Flash memory writes or erases and EEPROM writes active, it is possible
for the EEPROMprocess to be interrupted by the Flash memory write/erase and then continue after
the Flash memory write is completed. This action may change the amount of time that the EEPROM
operation takes.
EEPROM operations must be completed before entering Sleep or Deep-Sleep mode. Ensure the
EEPROM operations have completed by checking the EEPROM Done Status (EEDONE) register
before issuing a WFI instruction to enter Sleep or Deep-Sleep.
Reads of words within a block are at direct speed, which means that wait states are automatically
generated if the system clock is faster than the speed of the EEPROM. The read access time is
specified in Table 22-24 on page 1205.
Writing the EEOFFSET register also does not incur any penalties.
Writing the EEBLOCK register is not delayed, but any attempt to access data within that block is
delayed by 4 clocks after writing EEBLOCK. This time is used to load block specific information.
Writes to words within a block are delayed by a variable amount of time. The application may use
an interrupt to be notified when the write is done, or alternatively poll for the done status in the
EEDONE register. The variability ranges from the write timing of the EEPROM to the erase timing
of EEPROM, where the erase timing is less than the write timing of most external EEPROMs.
Locking and Passwords
The EEPROM can be locked at both the module level and the block level. The lock is controlled by
a password that is stored in the EEPROM Password (EEPASSn) registers and can be any 32-bit
to 96-bit value other than all 1s. Block 0 is the master block, the password for block 0 protects the
control registers as well as all other blocks. Each block can be further protected with a password
for that block.
If a password is registered for block 0, then the whole module is locked at reset. The locking behavior
is such that blocks 1 to 31 are inaccessible until block 0 is unlocked, and block 0 follows the rules
defined by its protection bits. As a result, the EEBLOCK register cannot be changed from 0 until
block 0 is unlocked.
A password registered with any block, including block 0, allows for protection rules that control
access of that block based on whether it is locked or unlocked. Generally, the lock can be used to
prevent write accesses when locked or can prevent read and write accesses when locked.
All password-protected blocks are locked at reset. To unlock a block, the correct password value
must be written to the EEPROM Unlock (EEUNLOCK) register by writing to it one to three times
to form the 32-bit, 64-bit, or 96-bit password registered using the EEPASSn register. The value
used to configure the EEPASS0 register must always be written last. For example, for a 96-bit
password, the value used to configure the EEPASS2 register must be written first, followed by the
EEPASS1 and the EEPASS0 register values. A block or the module may be re-locked by writing
0xFFFF.FFFF to the EEUNLOCK register because 0xFFFF.FFFF is not a valid password.
Protection and Access Control
The protection bits provide discrete control of read and write access for each block which allows
various protection models per block, including:
Without password: Readable and writable at any time. This mode is the default when there is
no password.
Without password: Readable but not writable.
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With password: Readable, but only writable when unlocked by the password. This mode is the
default when there is a password.
With password: Readable or writable only when unlocked.
With password: Readable only when unlocked, not writable.
Additionally, access protection may be applied based on the processor mode. This configuration
allows for supervisor-only access or supervisor and user access, which is the default. Supervisor-only
access mode also prevents access by the DMA and Debugger.
Additionally, the master block may be used to control access protection for the protection mechanism
itself. If access control for block 0 is for supervisor only, then the whole module may only be accessed
in supervisor mode. In addition, the protection level for block 0 sets the minimum protection level
for the entire EEPROM. For example, if the PROT field in the EEPROT register is configured to 0x1
for block 0, then block 1 could be configured with the PROT field to be 0x1, 0x2, or 0x3, but not 0x0.
Note that for blocks 1 to 31, they are inaccessible for read or write if block 0 has a password and it
is not unlocked. If block 0 has a master password, then the strictest protection defined for block 0
or an individual block is implemented on the remaining blocks.
Hidden Blocks
Hiding provides a temporary form of protection. Every block except block 0 can be hidden, which
prevents all accesses until the next reset.
This mechanism can allow a boot or initialization routine to access some data which is then made
inaccessible to all further accesses. Because boot and initialization routines control the capabilities
of the application, hidden blocks provide a powerful isolation of the data when debug is disabled.
A typical use model would be to have the initialization code store passwords, keys, and/or hashes
to use for verification of the rest of the application. Once performed, the block is then hidden and
made inaccessible until the next reset which then re-enters the initialization code.
Power and Reset Safety
Once the EEDONE register indicates that a location has been successfully written, the data is
retained until that location is written again. There is no power or reset race after the EEDONE register
indicates a write has completed.
Interrupt Control
The EEPROM module allows for an interrupt when a write completes to eliminate the need for
polling. The interrupt can be used to drive an application ISR which can then write more words or
verify completion. The interrupt mechanismis used any time the EEDONEregister goes fromworking
to done, whether because of an error or the successful completion of a program or erase operation.
This interrupt mechanism works for data writes, writes to password and protection registers, forced
erase by the EEPROM Support Control and Status (EESUPP) register, and mass erase using
the EEPROM Debug Mass Erase (EEDGBME) register. The EEPROM interrupt is signaled to the
core using the Flash memory interrupt vector. Software can determine that the source of the interrupt
was the EEPROM by examining bit 2 of the Flash Controller Masked Interrupt Status and Clear
(FCMISC) register.
Theory of Operation
The EEPROM operates using a traditional Flash bank model which implements EEPROM-type
cells, but uses sector erase. Additionally, words are replicated in the pages to allow 500K+ erase
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cycles when needed, which means that each word has a latest version. As a result, a write creates
a new version of the word in a new location, making the previous value obsolete.
Each sector contains two blocks. Each block contains locations for the active copy plus six redundant
copies. Passwords, protection bits, and control data are all stored in the pages.
When a page runs out of room to store the latest version of a word, a copy buffer is used. The copy
buffer copies the latest words of each block. The original page is then erased. Finally, the copy
buffer contents are copied back to the page. This mechanism ensures that data cannot be lost due
to power down, even during an operation. The EEPROM mechanism properly tracks all state
information to provide complete safety and protection. Although it should not normally be possible,
errors during programming can occur in certain circumstances, for example, the voltage rail dropping
during programming. In these cases, the EESUPP register can be used to finish an operation as
described in the section called Error During Programming on page 480.
Manual Copy Buffer Erase
The copy buffer is only used when a main block is full because a word has been written seven times
and there is no more room to store its latest version. In this situation, the latest versions of all the
words in the block are copied to the copy buffer, allowing the main block to be erased safely, providing
power down safety. If the copy buffer itself is full, then it must first be erased, which adds extra time.
By performing a manual erase of the copy buffer, this overhead does not occur during a future write
access. The EREQ bit in the EESUPP register is set if the copy buffer must be erased. If so, the
START bit can be written by the application to force the erase at a more convenient time. The
EEDONE and EEINT registers can be used to detect completion.
Debug Mass Erase
The EEPROM debug mass erase allows the developer to mass erase the EEPROM. For the mass
erase to occur correctly, there can be no active EEPROM operations. After the last EEPROM
operation, the application must ensure that no EEPROM registers are updated, including modifying
the EEBLOCK and the EEOFFSET registers without doing an actual read or write operation. To
hold off these operations, the application should reset the EEPROM module by setting the R0 bit in
the EEPROMSoftware Reset (SREEPROM) register, wait until WORKING bit in the EEPROMDone
Status (EEDONE) register is clear, and then enable the debug mass erase by setting the ME bit in
the EEPROM Debug Mass Erase (EEDBGME) register.
Error During Programming
Operations such as data-write, password set, protection set, and copy buffer erase may perform
multiple operations. For example, a normal write performs two underlying writes: the control word
write and the data write. If the control word writes but the data fails (for example, due to a voltage
drop), the overall write fails with indication provided in the EEDONEregister. Failure and the corrective
action is broken down by the type of operation:
If a normal write fails such that the control word is written but the data fails to write, the safe
course of action is to retry the operation once the system is otherwise stable, for example, when
the voltage is stabilized. After the retry, the control word and write data are advanced to the next
location.
If a password or protection write fails, the safe course of action is to retry the operation once the
system is otherwise stable. In the event that multi-word passwords may be written outside of a
manufacturing or bring-up mode, care must be taken to ensure all words are written in immediate
succession. If not, then partial password unlock would need to be supported to recover.
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Internal Memory
If the word write requires the block to be written to the copy buffer, then it is possible to fail or
lose power during the subsequent operations. A control word mechanism is used to track what
step the EEPROM was in if a failure occurs. If not completed, the EESUPP register indicates
the partial completion, and the EESUPP START bit can be written to allow it to continue to
completion.
If a copy buffer erase fails or power is lost while erasing, the EESUPP register indicates it is not
complete and allows it to be restarted
After a reset and prior to writing any data to the EEPROM, software must read the EESUPP register
and check for the presence of any error condition which may indicate that a write or erase was in
progress when the system was reset due to a voltage drop. If either the PRETRY or ERETRY bits are
set, the peripheral should be reset by setting and then clearing the R0 bit in the EEPROMSoftware
Reset (SREEPROM) register and waiting for the WORKING bit in the EEDONE register to clear
before again checking the EESUPP register for error indicators. This procedure should allow the
EEPROM to recover from the write or erase error. In very isolated cases, the EESUPP register may
continue to register an error after this operation, in which case the reset should be repeated. After
recovery, the application should rewrite the data which was being programmed when the initial
failure occurred.
Endurance
Endurance is per meta-block which is 2 blocks. Endurance is measured in two ways:
1. To the application, it is the number of writes that can be performed.
2. To the microcontroller, it is the number of erases that can be performed on the meta-block.
Because of the second measure, the number of writes depends on how the writes are performed.
For example:
One word can be written more than 500K times, but, these writes impact the meta-block that the
word is within. As a result, writing one word 500K times, then trying to write a nearby word 500K
times is not assured to work. To ensure success, the words should be written more in parallel.
All words can be written in a sweep with a total of more than 500K sweeps which updates all
words more than 500K times.
Different words can be written such that any or all words can be written more than 500K times
when write counts per word stay about the same. For example, offset 0 could be written 3 times,
then offset 1 could be written 2 times, then offset 2 is written 4 times, then offset 1 is written
twice, then offset 0 is written again. As a result, all 3 offsets would have 4 writes at the end of
the sequence. This kind of balancing within 7 writes maximizes the endurance of different words
within the same meta-block.
7.2.4.2 EEPROM Initialization and Configuration
Before writing to any EEPROM registers, the clock to the EEPROM module must be enabled, see
page 336.
A common setup is as follows:
Block 0 has a password.
Block 0 is readable by all, but only writable when unlocked.
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Block 0 has an ID and other public data.
In this configuration, the ID is readable any time, but the rest of the EEPROM is locked to accesses
by the application. The rest of the blocks only become available when parts of the application that
are allowed to access the EEPROM choose to unlock block 0.
7.3 Register Map
Table 7-3 on page 482 lists the ROMController register and the Flash memory and control registers.
The offset listed is a hexadecimal increment to the particular memory controller's base address.
The Flash memory register offsets are relative to the Flash memory control base address of
0x400F.D000. The EEPROM registers are relative to the EEPROM base address of 0x400A.F000.
The ROM and Flash memory protection register offsets are relative to the System Control base
address of 0x400F.E000.
Table 7-3. Flash Register Map
See
page
Flash Memory Registers (Flash Control Offset)
484 Flash Memory Address 0x0000.0000 R/W FMA 0x000
485 Flash Memory Data 0x0000.0000 R/W FMD 0x004
486 Flash Memory Control 0x0000.0000 R/W FMC 0x008
488 Flash Controller Raw Interrupt Status 0x0000.0000 RO FCRIS 0x00C
491 Flash Controller Interrupt Mask 0x0000.0000 R/W FCIM 0x010
493 Flash Controller Masked Interrupt Status and Clear 0x0000.0000 R/W1C FCMISC 0x014
496 Flash Memory Control 2 0x0000.0000 R/W FMC2 0x020
497 Flash Write Buffer Valid 0x0000.0000 R/W FWBVAL 0x030
498 Flash Write Buffer n 0x0000.0000 R/W FWBn
0x100 -
0x17C
499 Flash Size 0x0000.007F RO FSIZE 0xFC0
500 SRAM Size 0x0000.007F RO SSIZE 0xFC4
501 ROM Software Map 0x0000.0000 RO ROMSWMAP 0xFCC
EEPROM Registers (EEPROM Control Offset)
502 EEPROM Size Information 0x0020.0200 RO EESIZE 0x000
503 EEPROM Current Block 0x0000.0000 R/W EEBLOCK 0x004
504 EEPROM Current Offset 0x0000.0000 R/W EEOFFSET 0x008
505 EEPROM Read-Write - R/W EERDWR 0x010
506 EEPROM Read-Write with Increment - R/W EERDWRINC 0x014
507 EEPROM Done Status 0x0000.0000 RO EEDONE 0x018
509 EEPROM Support Control and Status - R/W EESUPP 0x01C
511 EEPROM Unlock - R/W EEUNLOCK 0x020
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Internal Memory
Table 7-3. Flash Register Map (continued)
See
page
512 EEPROM Protection 0x0000.0000 R/W EEPROT 0x030
514 EEPROM Password - R/W EEPASS0 0x034
514 EEPROM Password - R/W EEPASS1 0x038
514 EEPROM Password - R/W EEPASS2 0x03C
515 EEPROM Interrupt 0x0000.0000 R/W EEINT 0x040
516 EEPROM Block Hide 0x0000.0000 R/W EEHIDE 0x050
517 EEPROM Debug Mass Erase 0x0000.0000 R/W EEDBGME 0x080
518 EEPROM Peripheral Properties 0x0000.001F RO EEPROMPP 0xFC0
Memory Registers (System Control Offset)
519 ROM Control - R/W1C RMCTL 0x0F0
520 Flash Memory Protection Read Enable 0 0xFFFF.FFFF R/W FMPRE0 0x130
521 Flash Memory Protection Program Enable 0 0xFFFF.FFFF R/W FMPPE0 0x134
523 Boot Configuration 0xFFFF.FFFE RO BOOTCFG 0x1D0
526 User Register 0 0xFFFF.FFFF R/W USER_REG0 0x1E0
526 User Register 3 0xFFFF.FFFF R/W USER_REG3 0x1EC
520 Flash Memory Protection Read Enable 3 0xFFFF.FFFF R/W FMPRE3 0x20C
521 Flash Memory Protection Program Enable 3 0xFFFF.FFFF R/W FMPPE3 0x40C
7.4 Flash Memory Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a single word write operation, this register contains a 4-byte-aligned address and specifies
where the data is written. During a write operation that uses the write buffer, this register contains
a 128-byte (32-word) aligned address that specifies the start of the 32-word block to be written.
During erase operations, this register contains a 1 KB-aligned CPU byte address and specifies
which block is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
OFFSET reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OFFSET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Address Offset
Address offset in Flash memory where operation is performed, except
for non-volatile registers (see Non-Volatile Register
Programming on page 475 for details on values for this field).
0x0 R/W OFFSET 17:0
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Internal Memory
Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle. This register is not used
during erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DATA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Data Value
Data value for write operation.
0x0000.0000 R/W DATA 31:0
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Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the Flash memory controller initiates the appropriate access cycle for
the location specified by the Flash Memory Address (FMA) register (see page 484). If the access
is a write access, the data contained in the Flash Memory Data (FMD) register (see page 485) is
written to the specified address.
This register must be the final register written and initiates the memory operation. The four control
bits in the lower byte of this register are used to initiate memory operations.
Care must be taken not to set multiple control bits as the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WRKEY
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WRITE ERASE MERASE COMT reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Flash Memory Write Key
This field contains a write key, which is used to minimize the incidence
of accidental Flash memory writes. Depending on the value of the KEY
bit in the BOOTCFG register, the value 0xA442 or 0x71D5 must be
written into this field for a Flash memory write to occur. Writes to the
FMC register without this WRKEY value are ignored. A read of this field
returns the value 0.
0x0000 WO WRKEY 31:16
Commit Register Value
This bit is used to commit writes to Flash-memory-resident registers
and to monitor the progress of that process.
Description Value
When read, a 0 indicates that the previous commit access is
complete.
0
Set this bit to commit (write) the register value to a
Flash-memory-resident register.
When read, a 1 indicates that the previous commit access is
not complete.
1
See Non-Volatile Register Programming on page 475 for more
information on programming Flash-memory-resident registers.
0 R/W COMT 3
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Internal Memory
Mass Erase Flash Memory
This bit is used to mass erase the Flash main memory and to monitor
the progress of that process.
Description Value
When read, a 0 indicates that the previous mass erase operation
is complete.
0
Set this bit to erase the Flash main memory.
When read, a 1 indicates that the previous mass erase operation
is not complete.
1
For information on erase time, see Flash Memory and
EEPROM on page 1205.
0 R/W MERASE 2
Erase a Page of Flash Memory
This bit is used to erase a page of Flash memory and to monitor the
progress of that process.
Description Value
When read, a 0 indicates that the previous page erase operation
is complete.
0
Set this bit to erase the Flash memory page specified by the
contents of the FMA register.
When read, a 1 indicates that the previous page erase operation
is not complete.
1
For information on erase time, see Flash Memory and
0 R/W ERASE 1
Write a Word into Flash Memory
This bit is used to write a word into Flash memory and to monitor the
progress of that process.
Description Value
When read, a 0 indicates that the previous write update
operation is complete.
0
Set this bit to write the data stored in the FMD register into the
Flash memory location specified by the contents of the FMA
register.
When read, a 1 indicates that the write update operation is not
complete.
1
For information on programming time, see Flash Memory and
0 R/W WRITE 0
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Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the Flash memory controller has an interrupt condition. An interrupt is
sent to the interrupt controller only if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ARIS PRIS ERIS reserved VOLTRIS INVDRIS ERRIS reserved PROGRIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:14
Program Verify Error Raw Interrupt Status
Description Value
An interrupt has not occurred. 0
An interrupt is pending because the verify of a PROGRAM
operation failed. If this error occurs when using the Flash write
buffer, software must inspect the affected words to determine
where the error occurred.
1
This bit is cleared by writing a 1 to the PROGMISC bit in the FCMISC
register.
0 RO PROGRIS 13
0 RO reserved 12
Erase Verify Error Raw Interrupt Status
Description Value
An interrupt is pending because the verify of an ERASE
operation failed. If this error occurs when using the Flash write
buffer, software must inspect the affected words to determine
where the error occurred.
1
This bit is cleared by writing a 1 to the ERMISC bit in the FCMISC
register.
0 RO ERRIS 11
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Internal Memory
Invalid Data Raw Interrupt Status
Description Value
An interrupt is pending because a bit that was previously
programmed as a 0 is now being requested to be programmed
as a 1.
1
This bit is cleared by writing a 1 to the INVMISC bit in the FCMISC
register.
0 RO INVDRIS 10
Pump Voltage Raw Interrupt Status
Description Value
An interrupt is pending because the regulated voltage of the
pump went out of spec during the Flash operation and the
operation was terminated.
1
This bit is cleared by writing a 1 to the VOLTMISC bit in the FCMISC
register.
0 RO VOLTRIS 9
0 RO reserved 8:3
EEPROM Raw Interrupt Status
This bit provides status EEPROM operation.
Description Value
An EEPROM interrupt has not occurred. 0
An EEPROM interrupt has occurred. 1
This bit is cleared by writing a 1 to the EMISC bit in the FCMISCregister.
0 RO ERIS 2
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or erase
actions generated through the FMCor FMC2 register bits (see page 486
and page 496).
Description Value
The programming or erase cycle has not completed. 0
The programming or erase cycle has completed. 1
This status is sent to the interrupt controller when the PMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISCregister.
0 RO PRIS 1
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Access Raw Interrupt Status
Description Value
No access has tried to improperly program or erase the Flash
memory.
0
A program or erase action was attempted on a block of Flash
memory that contradicts the protection policy for that block as
set in the FMPPEn registers.
1
This status is sent to the interrupt controller when the AMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the AMISC bit in the FCMISCregister.
0 RO ARIS 0
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Internal Memory
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the Flash memory controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
AMASK PMASK EMASK reserved VOLTMASK INVDMASK ERMASK reserved PROGMASK reserved
R/W R/W R/W RO RO RO RO RO RO R/W R/W R/W RO R/W RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:14
PROGVER Interrupt Mask
Description Value
The PROGRIS interrupt is suppressed and not sent to the
0
An interrupt is sent to the interrupt controller when the PROGRIS
bit is set.
1
0 R/W PROGMASK 13
0 RO reserved 12
ERVER Interrupt Mask
Description Value
The ERRIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the ERRIS
bit is set.
1
0 R/W ERMASK 11
Invalid Data Interrupt Mask
Description Value
The INVDRIS interrupt is suppressed and not sent to the
0
An interrupt is sent to the interrupt controller when the INVDRIS
bit is set.
1
0 R/W INVDMASK 10
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VOLT Interrupt Mask
Description Value
The VOLTRIS interrupt is suppressed and not sent to the
0
An interrupt is sent to the interrupt controller when the VOLTRIS
bit is set.
1
0 R/W VOLTMASK 9
0 RO reserved 8:3
EEPROM Interrupt Mask
Description Value
The ERIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the ERIS bit
is set.
1
0 R/W EMASK 2
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the interrupt controller.
Description Value
The PRIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the PRIS bit
is set.
1
0 R/W PMASK 1
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
Description Value
The ARIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the ARIS bit
is set.
1
0 R/W AMASK 0
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Internal Memory
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
AMISC PMISC EMISC reserved VOLTMISC INVDMISC ERMISC reserved PROGMISC reserved
R/W1C R/W1C R/W1C RO RO RO RO RO RO R/W1C R/W1C R/W1C RO R/W1C RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:14
PROGVER Masked Interrupt Status and Clear
Description Value
When read, a 0 indicates that an interrupt has not occurred.
0
signaled.
Writing a 1 to this bit clears PROGMISC and also the PROGRIS
bit in the FCRIS register (see page 488).
1
0 R/W1C PROGMISC 13
0 RO reserved 12
ERVER Masked Interrupt Status and Clear
Description Value
0
signaled.
Writing a 1 to this bit clears ERMISC and also the ERRIS bit in
the FCRIS register (see page 488).
1
0 R/W1C ERMISC 11
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Invalid Data Masked Interrupt Status and Clear
Description Value
0
signaled.
Writing a 1 to this bit clears INVDMISC and also the INVDRIS
1
0 R/W1C INVDMISC 10
VOLT Masked Interrupt Status and Clear
Description Value
0
signaled.
Writing a 1 to this bit clears VOLTMISC and also the VOLTRIS
1
0 R/W1C VOLTMISC 9
0 RO reserved 8:3
EEPROM Masked Interrupt Status and Clear
Description Value
0
signaled.
Writing a 1 to this bit clears EMISC and also the ERIS bit in the
FCRIS register (see page 488).
1
0 R/W1C EMISC 2
Programming Masked Interrupt Status and Clear
Description Value
When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
0
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
1
0 R/W1C PMISC 1
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Access Masked Interrupt Status and Clear
Description Value
When read, a 0 indicates that no improper accesses have
occurred.
0
signaled because a program or erase action was attempted on
a block of Flash memory that contradicts the protection policy
for that block as set in the FMPPEn registers.
Writing a 1 to this bit clears AMISC and also the ARIS bit in the
1
0 R/W1C AMISC 0
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Register 7: Flash Memory Control 2 (FMC2), offset 0x020
When this register is written, the Flash memory controller initiates the appropriate access cycle for
the location specified by the Flash Memory Address (FMA) register (see page 484). If the access
is a write access, the data contained in the Flash Write Buffer (FWB) registers is written.
This register must be the final register written as it initiates the memory operation.
Flash Memory Control 2 (FMC2)
Base 0x400F.D000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WRKEY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WRBUF reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Flash Memory Write Key
This field contains a write key, which is used to minimize the incidence
of accidental Flash memory writes. Depending on the value of the KEY
bit in the BOOTCFG register, the value 0xA442 or 0x71D5 must be
written into this field for a Flash memory write to occur. Writes to the
FMC2 register without this WRKEY value are ignored. A read of this field
returns the value 0.
0x0000 WO WRKEY 31:16
Buffered Flash Memory Write
This bit is used to start a buffered write to Flash memory.
Description Value
When read, a 0 indicates that the previous buffered Flash
memory write access is complete.
0
Set this bit to write the data stored in the FWBn registers to the
location specified by the contents of the FMA register.
When read, a 1 indicates that the previous buffered Flash
memory write access is not complete.
1
For information on programming time, see Flash Memory and
0 R/W WRBUF 0
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Internal Memory
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030
This register provides a bitwise status of which FWBn registers have been written by the processor
since the last write of the Flash memory write buffer. The entries with a 1 are written on the next
write of the Flash memory write buffer. This register is cleared after the write operation by hardware.
A protection violation on the write operation also clears this status.
Software can programthe same 32 words to various Flash memory locations by setting the FWB[n]
bits after they are cleared by the write operation. The next write operation then uses the same data
as the previous one. In addition, if a FWBn register change should not be written to Flash memory,
software can clear the corresponding FWB[n] bit to preserve the existing data when the next write
operation occurs.
Flash Write Buffer Valid (FWBVAL)
Base 0x400F.D000
Offset 0x030
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FWB[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FWB[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Flash Memory Write Buffer
Description Value
The corresponding FWBn register has no newdata to be written. 0
The corresponding FWBn register has been updated since the
last buffer write operation and is ready to be written to Flash
memory.
1
Bit 0 corresponds to FWB0, offset 0x100, and bit 31 corresponds to
FWB31, offset 0x13C.
0x0 R/W FWB[n] 31:0
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Register 9: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C
These 32 registers hold the contents of the data to be written into the Flash memory on a buffered
Flash memory write operation. The offset selects one of the 32-bit registers. Only FWBn registers
that have been updated since the preceding buffered Flash memory write operation are written into
the Flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or
2 words. The FWBn registers are written into the Flash memory with the FWB0 register corresponding
to the address contained in FMA. FWB1 is written to the address FMA+0x4 etc. Note that only data
bits that are 0 result in the Flash memory being modified. A data bit that is 1 leaves the content of
the Flash memory bit at its previous value.
Flash Write Buffer n (FWBn)
Base 0x400F.D000
Offset 0x100 - 0x17C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DATA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Data
Data to be written into the Flash memory.
0x0000.0000 R/W DATA 31:0
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Internal Memory
Register 10: Flash Size (FSIZE), offset 0xFC0
This register indicates the size of the on-chip Flash memory.
Important: This register should be used to determine the size of the Flash memory that is
implemented on this microcontroller. However, to support legacy software, the DC0
register is available. A read of the DC0 register correctly identifies legacy memory sizes.
Software must use the FSIZE register for memory sizes that are not listed in the DC0
register description.
Flash Size (FSIZE)
Base 0x400F.D000
Offset 0xFC0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SIZE
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Reset
Flash Size
Indicates the size of the on-chip Flash memory.
Description Value
0x7F RO SIZE 15:0
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Register 11: SRAM Size (SSIZE), offset 0xFC4
This register indicates the size of the on-chip SRAM.
Important: This register should be used to determine the size of the SRAM that is implemented
on this microcontroller. However, to support legacy software, the DC0 register is
available. A read of the DC0 register correctly identifies legacy memory sizes. Software
must use the SSIZE register for memory sizes that are not listed in the DC0 register
description.
SRAM Size (SSIZE)
Base 0x400F.D000
Offset 0xFC4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SIZE
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Reset
SRAM Size
Indicates the size of the on-chip SRAM.
Description Value
32 KB of SRAM 0x007F
0x7F RO SIZE 15:0
April 10, 2013 500
Internal Memory
Register 12: ROM Software Map (ROMSWMAP), offset 0xFCC
This register indicates the presence of third-party software in the on-chip ROM.
Important: This register should be used to determine the presence of third-party software in the
on-chip ROM on this microcontroller. However, to support legacy software, the
NVMSTAT register is available. A read of the TPSW bit in the NVMSTAT register correctly
identifies the presence of legacy third-party software. Software should use the
ROMSWMAP register for software that is not on legacy devices.
ROM Software Map (ROMSWMAP)
Base 0x400F.D000
Offset 0xFCC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SAFERTOS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SafeRTOS Present
Description Value
SafeRTOS is not in the on-chip ROM. 0
SafeRTOS is in the on-chip ROM. 1
0x0 RO SAFERTOS 0
7.5 EEPROM Register Descriptions (EEPROM Offset)
This section lists and describes the EEPROM registers, in numerical order by address offset.
Registers in this section are relative to the EEPROM base address of 0x400A.F000.
Note that the EEPROM module clock must be enabled before the registers can be programmed
(see page 336). There must be a delay of 3 systemclocks after the EEPROMmodule clock is enabled
before any EEPROM module registers are accessed. In addition, after enabling or resetting the
EEPROM module, software must wait until the WORKING bit in the EEDONE register is clear before
accessing any EEPROM registers.
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Register 13: EEPROM Size Information (EESIZE), offset 0x000
The EESIZE register indicates the number of 16-word blocks and 32-bit words in the EEPROM.
EEPROM Size Information (EESIZE)
Base 0x400A.F000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BLKCNT reserved
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WORDCNT
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Reset
0 RO reserved 31:27
Number of 16-Word Blocks
This value encoded in this field describes the number of 16-word blocks
in the EEPROM.
0x20 RO BLKCNT 26:16
Number of 32-Bit Words
This value encoded in this field describes the number of 32-bit words
in the EEPROM.
0x200 RO WORDCNT 15:0
April 10, 2013 502
Internal Memory
Register 14: EEPROM Current Block (EEBLOCK), offset 0x004
The EEBLOCK register is used to select the EEPROM block for subsequent reads, writes, and
protection control. The value is a block offset into the EEPROM, such that the first block is 0, then
second block is 1, etc. Each block contains 16 words. Attempts to set an invalid block causes the
BLOCK field to be configured to 0. To verify that the intended block is being accessed, software can
read the BLOCK field after it has been written. An invalid block can be either a non-existent block or
a block that has been hidden using the EEHIDE register. Note that block 0 cannot be hidden.
EEPROM Current Block (EEBLOCK)
Base 0x400A.F000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BLOCK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Current Block
This field specifies the block in the EEPROM that is selected for
subsequent accesses. Once this field is configured, the read-write
registers operate against the specified block, using the EEOFFSET
register to select the word within the block. Additionally, the protection
and unlock registers are used for the selected block. The maximum
value that can be written into this register is determined by the block
count, as indicated by the EESIZE register. Attempts to write this field
larger than the maximum number of blocks or to a locked block causes
this field to be configured to 0.
0x0000 R/W BLOCK 15:0
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Register 15: EEPROM Current Offset (EEOFFSET), offset 0x008
The EEOFFSET register is used to select the EEPROM word to read or write within the block
selected by the EEBLOCK register. The value is a word offset into the block. Because accesses to
the EERDWRINC register change the offset, software can read the contents of this register to
determine the current offset.
EEPROM Current Offset (EEOFFSET)
Base 0x400A.F000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OFFSET reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Current Address Offset
This value is the current address specified as an offset into the block
selected by the EEBLOCK register. Once configured, the read-write
registers, EERDRWRand EERDWRINC, operate against that address.
The offset is automatically incremented by the EERDWRINC register,
with wrap around within the block, which means the offset is incremented
from 15 back to 0.
0x0 R/W OFFSET 3:0
April 10, 2013 504
Internal Memory
Register 16: EEPROM Read-Write (EERDWR), offset 0x010
The EERDWR register is used to read or write the EEPROM word at the address pointed to by the
EEBLOCK and EEOFFSET registers. If the protection or access rules do not permit access, the
operation is handled as follows: if reading is not allowed, the value 0xFFFF.FFFF is returned in all
cases; if writing is not allowed, the EEDONE register is configured to indicate an error.
EEPROM Read-Write (EERDWR)
Base 0x400A.F000
Offset 0x010
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VALUE
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VALUE
- - - - - - - - - - - - - - - - Reset
EEPROM Read or Write Data
On a read, this field contains the value at the word pointed to by
EEOFFSET. On a write, this field contains the data to be stored at the
word pointed to by EEOFFSET. For writes, configuring this field starts
the write process. If protection and access rules do not permit reads,
all 1s are returned. If protection and access rules do not permit writes,
the write fails and the EEDONE register indicates failure.
- R/W VALUE 31:0
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Register 17: EEPROMRead-Write with Increment (EERDWRINC), offset 0x014
The EERDWRINC register is used to read or write the EEPROM word at the address pointed to by
the EEBLOCK and EEOFFSET registers, and then increment the OFFSET field in the EEOFFSET
register. If the protection or access rules do not permit access, the operation is handled as follows:
if reading is not allowed, the value 0xFFFF.FFFF is returned in all cases; if writing is not allowed,
the EEDONE register is configured to indicate an error. In all cases, the OFFSET field is incremented.
If the last value is reached, OFFSET wraps around to 0 and points to the first word.
EEPROM Read-Write with Increment (EERDWRINC)
Base 0x400A.F000
Offset 0x014
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VALUE
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VALUE
- - - - - - - - - - - - - - - - Reset
EEPROM Read or Write Data with Increment
On a read, this field contains the value at the word pointed to by
EEOFFSET. On a write, this field contains the data to be stored at the
word pointed to by EEOFFSET. For writes, configuring this field starts
the write process. If protection and access rules do not permit reads,
all 1s are returned. If protection and access rules do not permit writes,
the write fails and the EEDONE register indicates failure.
Regardless of error, the OFFSET field in the EEOFFSET register is
incremented by 1, and the value wraps around if the last word is reached.
- R/W VALUE 31:0
April 10, 2013 506
Internal Memory
Register 18: EEPROM Done Status (EEDONE), offset 0x018
The EEDONE register indicates the successful or failed completion of a write using the EERDWR
or EERDWRINC register, protection set using the EEPROT register, password registered using the
EEPASS register, copy buffer erase or program retry using the EESUPP register, or a debug mass
erase using the EEDBGME register. The EEDONE register can be used with the EEINT register to
generate an interrupt to report the status. The normal usage is to poll the EEDONE register or read
the register after an interrupt is triggered. When the EEDONE bit 0 is set, then the operation is still
in progress. When the EEDONE bit 0 is clear, then the value of EEDONE indicates the completion
status. If EEDONE==0, then the write completed successfully. If EEDONE!=0, then an error occurred
and the source of the error is given by the set bit(s). If an error occurs, corrective action may be
taken as explained on page 509.
EEPROM Done Status (EEDONE)
Base 0x400A.F000
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WORKING reserved WKERASE WKCOPY NOPERM WRBUSY reserved INVPL reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Invalid Program Voltage Level
Description Value
No error 0
An error occurred during programming due to the voltage level
dropping below the level required for EEPROM programming.
This operation can be retried, however the voltage must be
stabilized before retrying.
1
0 RO INVPL 8
0x0 RO reserved 7:6
Write Busy
Description Value
No error 0
An attempt to access the EEPROMwas made while a write was
in progress.
1
0 RO WRBUSY 5
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Write Without Permission
Description Value
No error 0
An attempt was made to write without permission. This error
can result because the block is locked, the write violates the
programmed access protection, or when an attempt is made to
write a password when the password has already been written.
1
0 RO NOPERM 4
Working on a Copy
Description Value
The EEPROM is not copying. 0
A write is in progress and is waiting for the EEPROM to copy
to or from the copy buffer.
1
0 RO WKCOPY 3
Working on an Erase
Description Value
The EEPROM is not erasing. 0
A write is in progress and the original block is being erased after
being copied.
1
0 RO WKERASE 2
0 RO reserved 1
EEPROM Working
Description Value
The EEPROM is not working. 0
The EEPROM is performing the requested operation. 1
0 RO WORKING 0
April 10, 2013 508
Internal Memory
Register 19: EEPROM Support Control and Status (EESUPP), offset 0x01C
The EESUPP register indicates if internal operations are required because an internal copy buffer
must be erased or a programming failure has occurred and the operation must be completed. These
conditions are explained below as well as in more detail in the section called Manual Copy Buffer
Erase on page 480 and the section called Error During Programming on page 480.
The EREQ bit is set if the internal copy buffer must be erased the next time it is used because it
is full. To avoid the delay of waiting for the copy buffer to be erased on the next write, it can be
erased manually using this register by setting the START bit.
If either PRETRY or ERETRY is set indicating that an operation must be completed, setting the
START bit causes the operation to be performed again.
These bits are not changed by reset, so any condition that occurred before a reset is still indicated
after a reset.
EEPROM Support Control and Status (EESUPP)
Base 0x400A.F000
Offset 0x01C
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
START EREQ ERETRY PRETRY reserved
0 - - - 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Programming Must Be Retried
Description Value
Programming has not failed. 0
Programming from a copy in either direction failed to complete
and must be restarted by setting the START bit.
1
- RO PRETRY 3
Erase Must Be Retried
Description Value
Erasing has not failed. 0
Erasing failed to complete and must be restarted by setting the
START bit. If the failed erase is due to the erase of a main buffer,
the copy will be performed after the erase completes
successfully.
1
- RO ERETRY 2
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Erase Required
Description Value
The copy buffer has available space. 0
An erase of the copy buffer is required. 1
- RO EREQ 1
Start Erase
Setting this bit starts error recovery if the PRETRY or ERETRY bit is set.
If both the PRETRY and the ERETRY bits are clear, setting this bit starts
erasing the copy buffer if EREQ is set. If none of the other bits in this
register are set, setting this bit is ignored. After this bit is set, the
WORKING bit in the EEDONE register is set and is cleared when the
operation is complete. In addition, the EEINT register can be used to
generate an interrupt on completion.
If this bit is set while an operation is in progress, the write is ignored.
The START bit is automatically cleared when the operation completes.
0 R/W START 0
April 10, 2013 510
Internal Memory
Register 20: EEPROM Unlock (EEUNLOCK), offset 0x020
The EEUNLOCK register can be used to unlock the whole EEPROM or a single block using a
password. Unlocking is only required if a password is registered using the EEPASSn registers for
the block that is selected by the EEBLOCKregister. If block 0 has a password, it locks the remaining
blocks from any type of access, but uses its own protection mechanism, for example readable, but
not writable when locked. In addition, if block 0 has a password, it must be unlocked before unlocking
any other block.
The EEUNLOCK register is written between 1 and 3 times to form the 32-bit, 64-bit, or 96-bit
password registered using the EEPASSn registers. The value used to configure the EEPASS0
register must always be written last. For example, for a 96-bit password, the value used to configure
the EEPASS2 register must be written first followed by the EEPASS1 and EEPASS0 register values.
The block or the whole EEPROM can be re-locked by writing 0xFFFF.FFFF to this register.
In the event that an invalid value is written to this register, the block remains locked. The state of
the EEPROM lock can be determined by reading back the EEUNLOCK register. If a multi-word
password is set and the number of words written is incorrect, writing 0xFFFF.FFFF to this register
reverts the EEPROM lock to the locked state, and the proper unlock sequence can be retried.
Note that the internal logic is balanced to prevent any electrical or time-based attack being used to
find the correct password or its length.
EEPROM Unlock (EEUNLOCK)
Base 0x400A.F000
Offset 0x020
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UNLOCK
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
UNLOCK
- - - - - - - - - - - - - - - - Reset
EEPROM Unlock
Description Value
The EEPROM is locked. 0
The EEPROM is unlocked. 1
The EEPROMis locked if the block referenced by the EEBLOCKregister
has a password registered, or if the master block (block 0) has a
password. Unlocking is performed by writing the password to this
register. The block or the EEPROM stays unlocked until it is locked
again or until the next reset. It can be locked again by writing
0xFFFF.FFFF to this register.
- R/W UNLOCK 31:0
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Register 21: EEPROM Protection (EEPROT), offset 0x030
The EEPROT register is used to set or read the protection for the current block, as selected by the
EEBLOCK register. Protection and access control is used to determine when a block's contents
can be read or written. The protection level for block 0 sets the minimum protection level for the
entire EEPROM. For example, if the PROT field is configured to 0x1 for block 0, then block 1 could
be configured with the PROT field to be 0x1, 0x2, or 0x3, but not 0x0.
EEPROM Protection (EEPROT)
Base 0x400A.F000
Offset 0x030
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PROT ACC reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Access Control
Description Value
Both user and supervisor code may access this block of the
EEPROM.
0
Only supervisor code may access this block of the EEPROM.
DMA and Debug are also prevented from accessing the
EEPROM.
1
If this bit is set for block 0, then the whole EEPROM may only be
accessed by supervisor code.
0 R/W ACC 3
April 10, 2013 512
Internal Memory
Protection Control
The Protection bits control what context is needed for reading and writing
the block selected by the EEBLOCK register, or if block 0 is selected,
all blocks. The following values are allowed:
Description Value
This setting is the default. If there is no password, the block is
not protected and is readable and writable.
If there is a password, the block is readable, but only writable
when unlocked.
0x0
If there is a password, the block is readable or writable only
when unlocked.
This value has no meaning when there is no password.
0x1
If there is no password, the block is readable, not writable.
If there is a password, the block is readable only when unlocked,
but is not writable under any conditions.
0x2
Reserved 0x3
0x0 R/W PROT 2:0
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Register 22: EEPROM Password (EEPASS0), offset 0x034
Register 23: EEPROM Password (EEPASS1), offset 0x038
Register 24: EEPROM Password (EEPASS2), offset 0x03C
The EEPASSn registers are used to configure a password for a block. A password may only be set
once and cannot be changed. The password may be 32-bits, 64-bits, or 96-bits. Each word of the
password can be any 32-bit value other than 0xFFFF.FFFF (all 1s). To set a password, the EEPASS0
register is written to with a value other than 0xFFFF.FFFF. When the write completes, as indicated
in the EEDONE register, the application may choose to write to the EEPASS1 register with a value
other than 0xFFFF.FFFF. When that write completes, the application may choose to write to the
EEPASS2 register with a value other than 0xFFFF.FFFF to create a 96-bit password. The registers
do not have to be written consecutively, and the EEPASS1 and EEPASS2 registers may be written
at a later date. Based on whether 1, 2, or all 3 registers have been written, the unlock code also
requires the same number of words to unlock.
Note: Once the password is written, the block is not actually locked until either a reset occurs or
0xFFFF.FFFF is written to EEUNLOCK.
EEPROM Password (EEPASSn)
Base 0x400A.F000
Offset 0x034
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PASS
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PASS
- - - - - - - - - - - - - - - - Reset
Password
This register reads as 0x1 if a password is registered for this block and
0x0 if no password is registered. A write to this register if it reads as 0x0
sets the password. If an attempt is made to write to this register when
it reads as 0x1, the write is ignored and the NOPERM bit in the EEDONE
register is set.
- R/W PASS 31:0
April 10, 2013 514
Internal Memory
Register 25: EEPROM Interrupt (EEINT), offset 0x040
The EEINT register is used to control whether an interrupt should be generated when a write to
EEPROM completes as indicated by the EEDONE register value changing from 0x1 to any other
value. If the INT bit in this register is set, the ERIS bit in the Flash Controller RawInterrupt Status
(FCRIS) register is set whenever the EEDONE register value changes from0x1 as the Flash memory
and the EEPROM share an interrupt vector.
EEPROM Interrupt (EEINT)
Base 0x400A.F000
Offset 0x040
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Enable
Description Value
No interrupt is generated. 0
An interrupt is generated when the EEDONE register transitions
from 1 to 0 or an error occurs. The EEDONE register provides
status after a write to an offset location as well as a write to the
password and protection bits.
1
0 R/W INT 0
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Register 26: EEPROM Block Hide (EEHIDE), offset 0x050
The EEHIDE register is used to hide one or more blocks other than block 0. Once hidden, the block
is not accessible until the next reset. This model allows initialization code to have access to data
which is not visible to the rest of the application. This register also provides for additional security
in that there is no password to search for in the code or data.
EEPROM Block Hide (EEHIDE)
Base 0x400A.F000
Offset 0x050
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Hn
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved Hn
RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Hide Block
Description Value
The corresponding block is not hidden. 0
The block number that corresponds to the bit number is hidden.
A hidden block cannot be accessed, and the OFFSET value in
the EEBLOCK register cannot be set to that block number. If
an attempt is made to configure the OFFSET field to a hidden
block, the EEBLOCK register is cleared.
Any attempt to clear a bit in this register that is set is ignored.
1
0x0000.000 R/W Hn 31:1
0 RO reserved 0
April 10, 2013 516
Internal Memory
Register 27: EEPROM Debug Mass Erase (EEDBGME), offset 0x080
The EEDBGME register is used to mass erase the EEPROM block back to its default state from
the factory. This register is intended to be used only for debug and test purposes, not in production
environments. The erase takes place in such a way as to be secure. It first erases all data and then
erases the protection mechanism. This register can only be written from supervisor mode by the
core, and can also be written by the TM4C123AH6PM debug controller when enabled. A key is
used to avoid accidental use of this mechanism. Note that if a power down takes place while erasing,
the mechanism should be used again to complete the operation. Powering off prematurely does not
expose secured data.
To start a mass erase, the whole register must be written as 0xE37B.0001. The register reads back
as 0x1 until the erase is fully completed at which time it reads as 0x0. The EEDONE register is set
to 0x1 when the erase is started and changes to 0x0 or an error when the mass erase is complete.
Note that mass erasing the EEPROM block means that the wear-leveling counters are also reset
to the factory default.
EEPROM Debug Mass Erase (EEDBGME)
Base 0x400A.F000
Offset 0x080
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
KEY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ME reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Erase Key
This field must be written with 0xE37B for the ME field to be effective.
0x0000 WO KEY 31:16
Mass Erase
Description Value
No action. 0
When written as a 1, the EEPROM is mass erased. This bit
continues to read as 1 until the EEPROM is fully erased.
1
0 R/W ME 0
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Register 28: EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0
The EEPROMPP register indicates the size of the EEPROM for this part.
EEPROM Peripheral Properties (EEPROMPP)
Base 0x400A.F000
Offset 0xFC0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SIZE reserved
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Reset
2-KB EEPROM Size 0x1F RO SIZE 4:0
7.6 Memory Register Descriptions (System Control Offset)
The remainder of this section lists and describes the registers that reside in the System Control
address space, in numerical order by address offset. Registers in this section are relative to the
System Control base address of 0x400F.E000.
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Internal Memory
Register 29: ROM Control (RMCTL), offset 0x0F0
This register provides control of the ROMcontroller state. This register offset is relative to the System
Control base address of 0x400F.E000.
ROM Control (RMCTL)
Base 0x400F.E000
Offset 0x0F0
Type R/W1C, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BA reserved
R/W1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Boot Alias
Description Value
The Flash memory is at address 0x0. 0
The microcontroller's ROM appears at address 0x0. 1
This bit is cleared by writing a 1 to this bit position.
1 R/W1C BA 0
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Register 30: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Register 33: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note: The FMPRE0 register is aliased for backwards compatibility.
Note: Offset is relative to System Control base address of 0x400F.E000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits).
This register is loaded during the power-on reset sequence. The factory settings for the FMPREn
and FMPPEn registers are a value of 1 for all implemented 2-KB blocks. This achieves a policy of
open access and programmability. The register bits may be changed by writing the specific register
bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and
may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved),
at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it
may be restored by executing a power-on reset sequence. The reset value shown only applies to
power-on reset; any other type of reset does not affect this register. Once committed, the only way
to restore the factory default value of this register is to performthe sequence detailed in Recovering
a "Locked" Microcontroller on page 194.
Each FMPREn register controls a 64-k block of Flash. For additional information, see Flash Memory
Protection on page 471.
FMPRE0: 0 to 64 KB
FMPRE1: 65 to 128 KB
Flash Memory Protection Read Enable n (FMPREn)
Base 0x400F.E000
Offset 0x130 and 0x200
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
READ_ENABLE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
READ_ENABLE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
Flash Read Enable
Each bit configures a 2-KB flash block to be read only.
0xFFFF.FFFF R/W READ_ENABLE 31:0
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Internal Memory
Register 34: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
0x404
0x408
0x40C
Note: The FMPPE0 register is aliased for backwards compatibility.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
read-only protection bits).
This register is loaded during the power-on reset sequence. The factory settings for the FMPREn
and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open
access and programmability. The register bits may be changed by writing the specific register bit.
However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may
NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at
which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it
may be restored by executing a power-on reset sequence. The reset value shown only applies to
power-on reset; any other type of reset does not affect this register. Once committed, the only way
to restore the factory default value of this register is to performthe sequence detailed in Recovering
a "Locked" Microcontroller on page 194. For additional information, see Flash Memory
Each FMPPEn register controls a 64-k block of Flash. For additional information, see Flash Memory
FMPPE0: 0 to 64 KB
FMPPE1: 65 to 128 KB
Flash Memory Protection Program Enable n (FMPPEn)
Base 0x400F.E000
Offset 0x134 and 0x400
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PROG_ENABLE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PROG_ENABLE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
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Flash Programming Enable
Each bit configures a 2-KB flash block to be execute only.
0xFFFF.FFFF R/W PROG_ENABLE 31:0
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Internal Memory
Register 38: Boot Configuration (BOOTCFG), offset 0x1D0
Note: The Boot Configuration (BOOTCFG) register requires a POR before the committed
changes take effect.
This register is not written directly, but instead uses the FMD register as explained in Non-Volatile
Register Programming on page 475. This register provides configuration of a GPIO pin to enable
the ROM Boot Loader as well as a write-once mechanism to disable external debugger access to
the device. At reset, the user has the opportunity to direct the core to execute the ROM Boot Loader
or the application in Flash memory by using any GPIO signal from Ports A-Q as configured by the
bits in this register. At reset, the following sequence is performed:
The DBG0 bit is cleared by the factory and the DBG1 bit is set, which enables external debuggers.
Clearing the DBG1 bit disables any external debugger access to the device, starting with the next
power-up cycle of the device. The NW bit indicates that bits in the register can be changed from 1
to 0.
By committing the register values using the COMT bit in the FMC register, the register contents
become non-volatile and are therefore retained following power cycling. Prior to being committed,
bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset when
the register is not yet committed; any other type of reset does not affect this register. Once committed,
the register retains its value through power-on reset. Once committed, the only way to restore the
factory default value of this register is to perform the sequence detailed in Recovering a "Locked"
Boot Configuration (BOOTCFG)
Base 0x400F.E000
Offset 0x1D0
Type RO, reset 0xFFFF.FFFE
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved NW
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DBG0 DBG1 reserved KEY reserved EN POL PIN PORT
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
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Not Written
When set, this bit indicates that the values in this register can be changed
from1 to 0. When clear, this bit specifies that the contents of this register
cannot be changed.
1 RO NW 31
0xFFFF RO reserved 30:16
Boot GPIO Port
This field selects the port of the GPIO port pin that enables the ROM
boot loader at reset.
Description Value
Port A 0x0
Port B 0x1
Port C 0x2
Port D 0x3
Port E 0x4
Port F 0x5
Port G 0x6
Port H 0x7
0x7 RO PORT 15:13
Boot GPIO Pin
This field selects the pin number of the GPIO port pin that enables the
ROM boot loader at reset.
Description Value
Pin 0 0x0
Pin 1 0x1
Pin 2 0x2
Pin 3 0x3
Pin 4 0x4
Pin 5 0x5
Pin 6 0x6
Pin 7 0x7
0x7 RO PIN 12:10
Boot GPIO Polarity
When set, this bit selects a high level for the GPIO port pin to enable
the ROM boot loader at reset. When clear, this bit selects a low level
for the GPIO port pin.
1 RO POL 9
Boot GPIO Enable
Clearing this bit enables the use of a GPIO pin to enable the ROM Boot
Loader at reset. When this bit is set, the contents of address
0x0000.0004 are checked to see if the Flash memory has been
programmed. If the contents are not 0xFFFF.FFFF, the core executes
out of Flash memory. If the Flash has not been programmed, the core
executes out of ROM.
1 RO EN 8
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Internal Memory
0x7 RO reserved 7:5
KEY Select
This bit chooses between using the value 0xA442 or 0x71D5 as the
WRKEY value in the FMC/FMC2 register.
Description Value
The value 0x71D5 is used as the WRKEY in the FMC/FMC2
register. Writes to the FMC/FMC2 register with a 0xA442 key
are ignored.
0
0xA442 is used as the WRKEY in the FMC/FMC2 register. Writes
to theFMC/FMC2 register with a 0x71D5 key are ignored.
1
1 RO KEY 4
0x3 RO reserved 3:2
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
1 RO DBG1 1
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0 RO DBG0 0
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Register 39: User Register 0 (USER_REG0), offset 0x1E0
Register 42: User Register 3 (USER_REG3), offset 0x1EC
These registers each provide 32 bits of user-defined data that is non-volatile. Bits can only be
changed from 1 to 0. The reset value shown only applies to power-on reset when the register is not
yet committed; any other type of reset does not affect this register. Once committed, the register
retains its value through power-on reset. Once committed, the only way to restore the factory default
value of this register is to perform the sequence detailed in Recovering a "Locked"
User Register n (USER_REGn)
Base 0x400F.E000
Offset 0x1E0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DATA
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
User Data
Contains the user data value. This field is initialized to all 1s and once
committed, retains its value through power-on reset.
0xFFFF.FFFF R/W DATA 31:0
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Internal Memory
8 Micro Direct Memory Access (DMA)
The TM4C123AH6PM microcontroller includes a Direct Memory Access (DMA) controller, known
as micro-DMA (DMA). The DMA controller provides a way to offload data transfer tasks from the
Cortex
-M4F processor, allowing for more efficient use of the processor and the available bus
bandwidth. The DMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
performtransfers between peripherals and memory as the peripheral is ready to transfer more data.
The DMA controller provides the following features:
ARM
PrimeCell
32-channel configurable DMA controller

Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
Basic for simple transfer scenarios
Ping-pong for continuous data flow
Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single
request
Highly flexible and configurable channel operation
Independently configured and operated channels
Dedicated channels for supported on-chip modules
Flexible channel assignments
One channel each for receive and transmit path for bidirectional modules
Dedicated channel for software-initiated transfers
Per-channel configurable priority scheme
Optional software-initiated requests for any channel
Two levels of priority
Design optimizations for improved bus access performance between DMA controller and the
processor core
DMA controller access is subordinate to core access
RAM striping
Peripheral bus segmentation
Data sizes of 8, 16, and 32 bits
Transfer size is programmable in binary steps from 1 to 1024
Source and destination address increment size of byte, half-word, word, or no increment
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Maskable peripheral requests
Interrupt on transfer completion, with a separate interrupt per channel
8.1 Block Diagram
Figure 8-1. DMA Block Diagram
System Memory
CH Control Table
Transfer Buffers
Used by DMA
uDMA
Controller
DMASRCENDP
DMADSTENDP
DMACHCTL
DMASRCENDP
DMADSTENDP
DMACHCTRL
DMA error
Peripheral
DMA Channel 0
Peripheral
DMA Channel N-1
DMASTAT
DMACFG
DMACTLBASE
DMAALTBASE
DMAWAITSTAT
DMASWREQ
DMAUSEBURSTSET
DMAUSEBURSTCLR
DMAREQMASKSET
DMAREQMASKCLR
DMAENASET
DMAENACLR
DMAALTSET
DMAALTCLR
DMAPRIOSET
DMAPRIOCLR
DMAERRCLR
request
done
request
done
General
Peripheral N
Registers
Nested
Vectored
Interrupt
Controller
(NVIC)
ARM
Cortex-M4F
IRQ
request
done
DMACHASGN
DMACHIS
DMACHMAPn
The DMA controller is a flexible and highly configurable DMA controller designed to work efficiently
with the microcontroller's Cortex-M4F processor core. It supports multiple data sizes and address
increment schemes, multiple levels of priority among DMA channels, and several transfer modes
to allow for sophisticated programmed data transfers. The DMA controller's usage of the bus is
always subordinate to the processor core, so it never holds up a bus transaction by the processor.
Because the DMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth
it provides is essentially free, with no impact on the rest of the system. The bus architecture has
been optimized to greatly enhance the ability of the processor core and the DMA controller to
efficiently share the on-chip bus, thus improving performance. The optimizations include RAM
striping and peripheral bus segmentation, which in many cases allow both the processor core and
the DMA controller to access the bus and perform simultaneous data transfers.
The DMA controller can transfer data to and from the on-chip SRAM. However, because the Flash
memory and ROM are located on a separate internal bus, it is not possible to transfer data from the
Flash memory or ROM with the DMA controller.
Each peripheral function that is supported has a dedicated channel on the DMA controller that can
be configured independently. The DMA controller implements a unique configuration method using
channel control structures that are maintained in system memory by the processor. While simple
transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that
allow the DMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part
of a single transfer request. The DMA controller also supports the use of ping-pong buffering to
accommodate constant streaming of data to or from a peripheral.
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Micro Direct Memory Access (DMA)
Each channel also has a configurable arbitration size. The arbitration size is the number of items
that are transferred in a burst before the DMA controller rearbitrates for channel priority. Using the
arbitration size, it is possible to control exactly howmany items are transferred to or froma peripheral
each time it makes a DMA service request.
8.2.1 Channel Assignments
Each DMA channel has up to five possible assignments which are selected using the DMAChannel
Map Select n (DMACHMAPn) registers with 4-bit assignment fields for each DMA channel.
Table 8-1 on page 529 shows the DMA channel mapping. The Enc. column shows the encoding
for the respective DMACHMAPn bit field. Encodings 0x5 - 0xF are all reserved. To support legacy
software which uses the DMA Channel Assignment (DMACHASGN) register, Enc. 0 is equivalent
to a DMACHASGN bit being clear, and Enc. 1 is equivalent to a DMACHASGN bit being set. If the
DMACHASGN register is read, bit fields return 0 if the corresponding DMACHMAPn register field
value are equal to 0, otherwise they return 1 if the corresponding DMACHMAPn register field values
are not equal to 0. The Type indication in the table indicates if a particular peripheral uses a single
request (S), burst request (B) or either (SB).
Note: Channels noted in the table as "Software" may be assigned to peripherals in the future.
However, they are currently available for software use. Channel 30 is dedicated for software
use.
Table 8-1. DMA Channel Assignments
4 3 2 1 0 Enc.
Type Peripheral Type Peripheral Type Peripheral Type Peripheral Type Peripheral Ch #
B Software B GPTimer 4A B Software SB UART2 RX B Software 0
B Software B GPTimer 4B B Software SB UART2 TX B Software 1
B Software B Software B Software B GPTimer 3A B Software 2
B Software B Software B Software B GPTimer 3B B Software 3
B Software B GPIO A B Software B GPTimer 2A B Software 4
B Software B GPIO B B Software B GPTimer 2B B Software 5
B Software B GPIO C SB UART5 RX B GPTimer 2A B Software 6
B Software B GPIO D SB UART5 TX B GPTimer 2B B Software 7
B Software B GPTimer 5A B Software SB UART1 RX SB UART0 RX 8
B Software B GPTimer 5B B Software SB UART1 TX SB UART0 TX 9
B Software B GPTimer 6A SB UART6 RX SB SSI1 RX SB SSI0 RX 10
B Software B GPTimer 6B SB UART6 TX SB SSI1 TX SB SSI0 TX 11
B Software B GPTimer 7A SB SSI2 RX SB UART2 RX B Software 12
B Software B GPTimer 7B SB SSI2 TX SB UART2 TX B Software 13
B Software B GPIO E SB SSI3 RX B GPTimer 2A B ADC0 SS0 14
B Software B GPIO F SB SSI3 TX B GPTimer 2B B ADC0 SS1 15
B Software B GPTimer 8A SB UART3 RX B Software B ADC0 SS2 16
B Software B GPTimer 8B SB UART3 TX B Software B ADC0 SS3 17
B Software B GPIO B SB UART4 RX B GPTimer 1A B GPTimer 0A 18
B Software B GPIO G SB UART4 TX B GPTimer 1B B GPTimer 0B 19
B Software B Software SB UART7 RX B Software B GPTimer 1A 20
B Software B Software SB UART7 TX B Software B GPTimer 1B 21
B Software B Software B Software B Software SB UART1 RX 22
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Table 8-1. DMA Channel Assignments (continued)
4 3 2 1 0 Enc.
Type Peripheral Type Peripheral Type Peripheral Type Peripheral Type Peripheral Ch #
B Software B Software B Software B Software SB UART1 TX 23
B Software B GPTimer 9A B Software B ADC1 SS0 SB SSI1 RX 24
B Software B GPTimer 9B B Software B ADC1 SS1 SB SSI1 TX 25
B Software B GPTimer 10A B Software B ADC1 SS2 B Software 26
B Software B GPTimer 10B B Software B ADC1 SS3 B Software 27
B Software B GPTimer 11A B Software B Software B Software 28
B Software B GPTimer 11B B Software B Software B Software 29
B Software B Software B Software B Software B Software 30
B Reserved B Reserved B Reserved B Reserved B Reserved 31
8.2.2 Priority
The DMA controller assigns priority to each channel based on the channel number and the priority
level bit for the channel. Channel number 0 has the highest priority and as the channel number
increases, the priority of a channel decreases. Each channel has a priority level bit to provide two
levels of priority: default priority and high priority. If the priority level bit is set, then that channel has
higher priority than all other channels at default priority. If multiple channels are set for high priority,
then the channel number is used to determine relative priority among all the high priority channels.
The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET)
register and cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register.
8.2.3 Arbitration Size
When a DMA channel requests a transfer, the DMA controller arbitrates among all the channels
making a request and services the DMA channel with the highest priority. Once a transfer begins,
it continues for a selectable number of transfers before rearbitrating among the requesting channels
again. The arbitration size can be configured for each channel, ranging from1 to 1024 itemtransfers.
After the DMA controller transfers the number of items specified by the arbitration size, it then
checks among all the channels making a request and services the channel with the highest priority.
If a lower priority DMA channel uses a large arbitration size, the latency for higher priority channels
is increased because the DMA controller completes the lower priority burst before checking for
higher priority requests. Therefore, lower priority channels should not use a large arbitration size
for best response on high priority channels.
The arbitration size can also be thought of as a burst size. It is the maximum number of items that
are transferred at any one time in a burst. Here, the termarbitration refers to determination of DMA
channel priority, not arbitration for the bus. When the DMA controller arbitrates for the bus, the
processor always takes priority. Furthermore, the DMA controller is held off whenever the processor
must perform a bus transaction on the same bus, even in the middle of a burst transfer.
8.2.4 Request Types
The DMA controller responds to two types of requests from a peripheral: single or burst. Each
peripheral may support either or both types of requests. A single request means that the peripheral
is ready to transfer one item, while a burst request means that the peripheral is ready to transfer
multiple items.
April 10, 2013 530
The DMA controller responds differently depending on whether the peripheral is making a single
request or a burst request. If both are asserted, and the DMA channel has been set up for a burst
transfer, then the burst request takes precedence. See Table 8-2 on page 531, which shows how
each peripheral supports the two request types.
Table 8-2. Request Type Support
Event that generates Burst Request Event that generates Single Request Peripheral
FIFO half full None ADC
Trigger event None General-Purpose Timer
None Raw interrupt pulse GPIO
TX FIFO Level (fixed at 4) TX FIFO Not Full SSI TX
RX FIFO Level (fixed at 4) RX FIFO Not Empty SSI RX
TX FIFO Level (configurable) TX FIFO Not Full UART TX
RX FIFO Level (configurable) RX FIFO Not Empty UART RX
8.2.4.1 Single Request
When a single request is detected, and not a burst request, the DMA controller transfers one item
and then stops to wait for another request.
8.2.4.2 Burst Request
When a burst request is detected, the DMA controller transfers the number of items that is the
lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration
size should be the same as the number of data items that the peripheral can accommodate when
making a burst request. For example, the UART generates a burst request based on the FIFOtrigger
level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer
when the trigger level is reached. A burst transfer runs to completion once it is started, and cannot
be interrupted, even by a higher priority channel. Burst transfers complete in a shorter time than the
same number of non-burst transfers.
It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps
the nature of the data is such that it only makes sense when transferred together as a single unit
rather than one piece at a time. The single request can be disabled by using the DMA Channel
Useburst Set (DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the
DMA controller only responds to burst requests for that channel.
8.2.5 Channel Configuration
The DMA controller uses an area of system memory to store a set of channel control structures
in a table. The control table may have one or two entries for each DMA channel. Each entry in the
table structure contains source and destination pointers, transfer size, and transfer mode. The
control table can be located anywhere in system memory, but it must be contiguous and aligned on
a 1024-byte boundary.
Table 8-3 on page 532 shows the layout in memory of the channel control table. Each channel may
have one or two control structures in the control table: a primary control structure and an optional
alternate control structure. The table is organized so that all of the primary entries are in the first
half of the table, and all the alternate structures are in the second half of the table. The primary entry
is used for simple transfer modes where transfers can be reconfigured and restarted after each
transfer is complete. In this case, the alternate control structures are not used and therefore only
the first half of the table must be allocated in memory; the second half of the control table is not
necessary, and that memory can be used for something else. If a more complex transfer mode is
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used such as ping-pong or scatter-gather, then the alternate control structure is also used and
memory space should be allocated for the entire table.
Any unused memory in the control table may be used by the application. This includes the control
structures for any channels that are unused by the application as well as the unused control word
for each channel.
Table 8-3. Control Structure Memory Map
Channel Offset
0, Primary 0x0
1, Primary 0x10
... ...
31, Primary 0x1F0
0, Alternate 0x200
1, Alternate 0x210
... ...
31, Alternate 0x3F0
Table 8-4 shows an individual control structure entry in the control table. Each entry is aligned on
a 16-byte boundary. The entry contains four long words: the source end pointer, the destination end
pointer, the control word, and an unused entry. The end pointers point to the ending address of the
transfer and are inclusive. If the source or destination is non-incrementing (as for a peripheral
register), then the pointer should point to the transfer address.
Table 8-4. Channel Control Structure
Description Offset
Source End Pointer 0x000
Destination End Pointer 0x004
Control Word 0x008
Unused 0x00C
The control word contains the following fields:
Source and destination data sizes
Source and destination address increment size
Number of transfers before bus arbitration
Total number of items to transfer
Useburst flag
Transfer mode
The control word and each field are described in detail in DMA Channel Control
Structure on page 550. The DMA controller updates the transfer size and transfer mode fields as
the transfer is performed. At the end of a transfer, the transfer size indicates 0, and the transfer
mode indicates "stopped." Because the control word is modified by the DMA controller, it must be
reconfigured before each new transfer. The source and destination end pointers are not modified,
so they can be left unchanged if the source or destination addresses remain the same.
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Prior to starting a transfer, a DMA channel must be enabled by setting the appropriate bit in the
DMA Channel Enable Set (DMAENASET) register. A channel can be disabled by setting the
channel bit in the DMA Channel Enable Clear (DMAENACLR) register. At the end of a complete
DMA transfer, the controller automatically disables the channel.
8.2.6 Transfer Modes
The DMA controller supports several transfer modes. Two of the modes support simple one-time
transfers. Several complex modes support a continuous flow of data.
8.2.6.1 Stop Mode
While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word.
When the mode field has this value, the DMA controller does not performany transfers and disables
the channel if it is enabled. At the end of a transfer, the DMA controller updates the control word
to set the mode to Stop.
8.2.6.2 Basic Mode
In Basic mode, the DMA controller performs transfers as long as there are more items to transfer,
and a transfer request is present. This mode is used with peripherals that assert a DMA request
signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any
situation where the request is momentary even though the entire transfer should be completed. For
example, a software-initiated transfer creates a momentary request, and in Basic mode, only the
number of transfers specified by the ARBSIZE field in the DMAChannel Control Word (DMACHCTL)
register is transferred on a software request, even if there is more data to transfer.
When all of the items have been transferred using Basic mode, the DMA controller sets the mode
for that channel to Stop.
8.2.6.3 Auto Mode
Auto mode is similar to Basic mode, except that once a transfer request is received, the transfer
runs to completion, even if the DMA request is removed. This mode is suitable for software-triggered
transfers. Generally, Auto mode is not used with a peripheral.
When all the items have been transferred using Auto mode, the DMA controller sets the mode for
that channel to Stop.
8.2.6.4 Ping-Pong
Ping-Pong mode is used to support a continuous data flowto or froma peripheral. To use Ping-Pong
mode, both the primary and alternate data structures must be implemented. Both structures are set
up by the processor for data transfer between memory and a peripheral. The transfer is started
using the primary control structure. When the transfer using the primary control structure is complete,
the DMA controller reads the alternate control structure for that channel to continue the transfer.
Each time this happens, an interrupt is generated, and the processor can reload the control structure
for the just-completed transfer. Data flow can continue indefinitely this way, using the primary and
alternate control structures to switch back and forth between buffers as the data flows to or from
the peripheral.
Refer to Figure 8-2 on page 534 for an example showing operation in Ping-Pong mode.
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Figure 8-2. Example of Ping-Pong DMA Transaction
Alternate Structure
Primary Structure
Primary Structure
Alternate Structure
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8.2.6.5 Memory Scatter-Gather
Memory Scatter-Gather mode is a complex mode used when data must be transferred to or from
varied locations in memory instead of a set of contiguous locations in a memory buffer. For example,
a gather DMA operation could be used to selectively read the payload of several stored packets
of a communication protocol and store them together in sequence in a memory buffer.
April 10, 2013 534
In Memory Scatter-Gather mode, the primary control structure is used to program the alternate
control structure from a table in memory. The table is set up by the processor software and contains
a list of control structures, each containing the source and destination end pointers, and the control
word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode.
Each entry in the table is copied in turn to the alternate structure where it is then executed. The
DMA controller alternates between using the primary control structure to copy the next transfer
instruction from the list and then executing the new transfer instruction. The end of the list is marked
by programming the control word for the last entry to use Auto transfer mode. Once the last transfer
is performed using Auto mode, the DMA controller stops. A completion interrupt is generated only
after the last transfer. It is possible to loop the list by having the last entry copy the primary control
structure to point back to the beginning of the list (or to a new list). It is also possible to trigger a set
of other channels to performa transfer, either directly, by programming a write to the software trigger
for another channel, or indirectly, by causing a peripheral action that results in a DMA request.
By programming the DMA controller using this method, a set of up to 256 arbitrary transfers can
be performed based on a single DMA request.
Refer to Figure 8-3 on page 536 and Figure 8-4 on page 537, which show an example of operation
in Memory Scatter-Gather mode. This example shows a gather operation, where data in three
separate buffers in memory is copied together into one buffer. Figure 8-3 on page 536 shows how
the application sets up a DMA task list in memory that is used by the controller to perform three
sets of copy operations from different locations in memory. The primary control structure for the
channel that is used for the operation is configured to copy from the task list to the alternate control
structure.
Figure 8-4 on page 537 shows the sequence as the DMA controller performs the three sets of copy
operations. First, using the primary control structure, the DMA controller loads the alternate control
structure with task A. It then performs the copy operation specified by task A, copying the data from
the source buffer A to the destination buffer. Next, the DMA controller again uses the primary
control structure to load task B into the alternate control structure, and then performs the B operation
with the alternate control structure. The process is repeated for task C.
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Figure 8-3. Memory Scatter-Gather, Setup and Configuration
NOTES:
1. Application has a need to copy data items from three separate locations in memory into one combined buffer.
2. Application sets up DMA task list in memory, which contains the pointers and control configuration for three
DMA copy tasks.
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the
alternate control structure, where it is executed by the DMA controller.
4. The SRC and DST pointers in the task list must point to the last location in the corresponding buffer.
C
4 WORDS (SRC A)
16 WORDS (SRC B)
SRC
DST
ITEMS=16
Unused
SRC
DST
ITEMS=1
1 WORD (SRC C)
4 (DEST A)
16 (DEST B)
1 (DEST C)
DST
A
B
TASK A
TASK B
TASK C
SRC
DST
ITEMS=12
SRC
DST
ITEMS=n
Task List in Memory
2 1 3
Source and Destination
Buffer in Memory
Channel Control
Table in Memory
Channel Primary
Control Structure
Channel Alternate
Control Structure
Unused
ITEMS=4
SRC
Unused
April 10, 2013 536
Figure 8-4. Memory Scatter-Gather, DMA Copy Sequence
SRC
DST
COPIED
SRC
DST
COPIED
PRI
ALT
SRC
DST
COPIED
SRC
DST
COPIED
SRC
DST
COPIED
SRC
DST
COPIED
Task List
in Memory
DMA Control Table
in Memory
Buffers
in Memory
TASK B
TASK C
PRI
ALT
SRC B
SRC C
DEST B
DEST C
Using the channels primary control structure, the DMA
controller copies task A configuration to the channels
alternate control structure.
Then, using the channels alternate control structure, the
DMA controller copies data from the source buffer A to
the destination buffer.
Task List
in Memory
DMA Control Table
in Memory
Buffers
in Memory
controller copies task B configuration to the channels
DMA controller copies data from the source buffer B to
DMA Control Table
in Memory
Buffers
in Memory
controller copies task C configuration to the channels
DMA controller copies data from the source buffer C to
PRI
ALT
Task List
in Memory
TASK A
TASK B
TASK A
TASK C
SRC A
SRC C
DEST A
DEST C
SRC A
SRC B
DEST A
DEST B
TASK A
TASK B
SRC A
TASK C
SRC C
DEST C
SRC B
DEST B
DEST A
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8.2.6.6 Peripheral Scatter-Gather
Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers
are controlled by a peripheral making a DMA request. Upon detecting a request fromthe peripheral,
the DMA controller uses the primary control structure to copy one entry fromthe list to the alternate
control structure and then performs the transfer. At the end of this transfer, the next transfer is started
only if the peripheral again asserts a DMA request. The DMA controller continues to perform
transfers fromthe list only when the peripheral is making a request, until the last transfer is complete.
A completion interrupt is generated only after the last transfer.
By using this method, the DMA controller can transfer data to or from a peripheral from a set of
arbitrary locations whenever the peripheral is ready to transfer data.
Refer to Figure 8-5 on page 539 and Figure 8-6 on page 540, which show an example of operation
in Peripheral Scatter-Gather mode. This example shows a gather operation, where data from three
separate buffers in memory is copied to a single peripheral data register. Figure 8-5 on page 539
shows how the application sets up a DMA task list in memory that is used by the controller to
perform three sets of copy operations from different locations in memory. The primary control
structure for the channel that is used for the operation is configured to copy from the task list to the
Figure 8-6 on page 540 shows the sequence as the DMA controller performs the three sets of copy
operations. First, using the primary control structure, the DMA controller loads the alternate control
structure with task A. It then performs the copy operation specified by task A, copying the data from
the source buffer A to the peripheral data register. Next, the DMA controller again uses the primary
control structure to load task B into the alternate control structure, and then performs the B operation
with the alternate control structure. The process is repeated for task C.
April 10, 2013 538
Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration
C
4 WORDS (SRC A)
16 WORDS (SRC B)
1 WORD (SRC C)
A
B
SRC
DST
ITEMS=12
SRC
DST
ITEMS=n
Task List in Memory
2 1 3
Source Buffer
in Memory
Channel Control
Table in Memory
Channel Primary
Control Structure
Channel Alternate
Control Structure
DEST
Peripheral Data
Register
SRC
DST
ITEMS=16
Unused
SRC
DST
ITEMS=1
DST
TASK A
TASK B
TASK C
Unused
ITEMS=4
SRC
Unused
NOTES:
1. Application has a need to copy data items from three separate locations in memory into a peripheral data
register.
2. Application sets up DMA task list in memory, which contains the pointers and control configuration for three
DMA copy tasks.
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the
alternate control structure, where it is executed by the DMA controller.
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Figure 8-6. Peripheral Scatter-Gather, DMA Copy Sequence
SRC C
TASK A
SRC
DST
COPIED
SRC
DST
COPIED
PRI
ALT
SRC
DST
COPIED
SRC
DST
COPIED
SRC
DST
COPIED
SRC
DST
COPIED
Task List
in Memory
DMA Control Table
in Memory
Buffers
in Memory
TASK B
TASK C
PRI
ALT
controller copies task A configuration to the channels
DMA controller copies data from the source buffer A to
the peripheral data register.
Task List
in Memory
DMA Control Table
in Memory
Buffers
in Memory
controller copies task B configuration to the channels
DMA controller copies data from the source buffer B to
DMA Control Table
in Memory
Buffers
in Memory
controller copies task C configuration to the channels
DMA controller copies data from the source buffer C to
PRI
ALT
Task List
in Memory
TASK A
TASK B
TASK A
TASK C
Peripheral
Data
Register
SRC B
SRC C
Peripheral
Data
Register
SRC A
SRC C
Peripheral
Data
Register
SRC A
SRC B
TASK B
TASK C
SRC B
SRC A
April 10, 2013 540
8.2.7 Transfer Size and Increment
The DMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination
data size must be the same for any given transfer. The source and destination address can be
auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and
destination address increment values can be set independently, and it is not necessary for the
address increment to match the data size as long as the increment is the same or larger than the
data size. For example, it is possible to performa transfer using 8-bit data size, but using an address
increment of full words (4 bytes). The data to be transferred must be aligned in memory according
to the data size (8, 16, or 32 bits).
Table 8-5 shows the configuration to read from a peripheral that supplies 8-bit data.
Table 8-5. DMA Read Example: 8-Bit Peripheral
Configuration Field
8 bits Source data size
8 bits Destination data size
No increment Source address increment
Byte Destination address increment
Peripheral read FIFO register Source end pointer
End of the data buffer in memory Destination end pointer
8.2.8 Peripheral Interface
Each peripheral that supports DMA has a single request and/or burst request signal that is asserted
when the peripheral is ready to transfer data (see Table 8-2 on page 531). The request signal can
be disabled or enabled using the DMA Channel Request Mask Set (DMAREQMASKSET) and
DMA Channel Request Mask Clear (DMAREQMASKCLR) registers. The DMA request signal
is disabled, or masked, when the channel request mask bit is set. When the request is not masked,
the DMA channel is configured correctly and enabled, and the peripheral asserts the request signal,
the DMA controller begins the transfer.
Note: When using DMA to transfer data to and from a peripheral, the peripheral must disable all
interrupts to the NVIC.
When a DMA transfer is complete, the DMA controller generates an interrupt, see Interrupts and
Errors on page 542 for more information.
For more information on how a specific peripheral interacts with the DMA controller, refer to the
DMA Operation section in the chapter that discusses that peripheral.
8.2.9 Software Request
One DMA channel is dedicated to software-initiated transfers. This channel also has a dedicated
interrupt to signal completion of a DMA transfer. A transfer is initiated by software by first configuring
and enabling the transfer, and then issuing a software request using the DMA Channel Software
Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should be
used.
It is possible to initiate a transfer on any channel using the DMASWREQ register. If a request is
initiated by software using a peripheral DMA channel, then the completion interrupt occurs on the
interrupt vector for the peripheral instead of the software interrupt vector. Any channel may be used
for software requests as long as the corresponding peripheral is not using DMA for data transfer.
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8.2.10 Interrupts and Errors
When a DMA transfer is complete, the DMA controller generates a completion interrupt on the
interrupt vector of the peripheral. Therefore, if DMA is used to transfer data for a peripheral and
interrupts are used, then the interrupt handler for that peripheral must be designed to handle the
DMA transfer completion interrupt. If the transfer uses the software DMA channel, then the
completion interrupt occurs on the dedicated software DMA interrupt vector (see Table
8-6 on page 542).
When DMA is enabled for a peripheral, the DMA controller stops the normal transfer interrupts
for a peripheral fromreaching the interrupt controller (the interrupts are still reported in the peripheral's
interrupt registers). Thus, when a large amount of data is transferred using DMA, instead of receiving
multiple interrupts fromthe peripheral as data flows, the interrupt controller receives only one interrupt
when the transfer is complete. Unmasked peripheral error interrupts continue to be sent to the
When a DMAchannel generates a completion interrupt, the CHIS bit corresponding to the peripheral
channel is set in the DMA Channel Interrupt Status (DMACHIS) register (see page 577). This
register can be used by the peripheral interrupt handler code to determine if the interrupt was caused
by the DMA channel or an error event reported by the peripheral's interrupt registers. The completion
interrupt request from the DMA controller is automatically cleared when the interrupt handler is
activated.
If the DMA controller encounters a bus or memory protection error as it attempts to perform a data
transfer, it disables the DMA channel that caused the error and generates an interrupt on the DMA
error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register
to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be
cleared by writing a 1 to the ERRCLR bit.
Table 8-6 shows the dedicated interrupt assignments for the DMA controller.
Table 8-6. DMA Interrupt Assignments
Assignment Interrupt
DMA Software Channel Transfer 46
DMA Error 47
8.3.1 Module Initialization
Before the DMA controller can be used, it must be enabled in the System Control block and in the
peripheral. The location of the channel control structure must also be programmed.
The following steps should be performed one time during system initialization:
1. Enable the DMA clock using the RCGCDMA register (see page 324).
2. Enable the DMA controller by setting the MASTEREN bit of the DMAConfiguration (DMACFG)
register.
3. Program the location of the channel control table by writing the base address of the table to the
DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be
aligned on a 1024-byte boundary.
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8.3.2 Configuring a Memory-to-Memory Transfer
DMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used
for software-initiated, memory-to-memory transfer if the associated peripheral is not being used.
8.3.2.1 Configure the Channel Attributes
First, configure the channel attributes:
1. Program bit 30 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 30 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 30 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
DMA controller to respond to single and burst requests.
4. Set bit 30 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the DMA controller to recognize requests for this channel.
8.3.2.2 Configure the Channel Control Structure
Now the channel control structure must be configured.
This example transfers 256 words from one memory buffer to another. Channel 30 is used for a
software transfer, and the control structure for channel 30 is at offset 0x1E0 of the channel control
table. The channel control structure for channel 30 is located at the offsets shown in Table 8-7.
Table 8-7. Channel Control Structure Offsets for Channel 30
Description Offset
Channel 30 Source End Pointer Control Table Base + 0x1E0
Channel 30 Destination End Pointer Control Table Base + 0x1E4
Channel 30 Control Word Control Table Base + 0x1E8
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
1. Program the source end pointer at offset 0x1E0 to the address of the source buffer + 0x3FC.
2. Program the destination end pointer at offset 0x1E4 to the address of the destination buffer +
0x3FC.
The control word at offset 0x1E8 must be programmed according to Table 8-8.
Table 8-8. Channel Control Word Configuration for Memory Transfer Example
Description Value Bits Field in DMACHCTL
32-bit destination address increment 2 31:30 DSTINC
32-bit destination data size 2 29:28 DSTSIZE
32-bit source address increment 2 27:26 SRCINC
32-bit source data size 2 25:24 SRCSIZE
Reserved 0 23:18 reserved
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Table 8-8. Channel Control Word Configuration for Memory Transfer Example (continued)
Arbitrates after 8 transfers 3 17:14 ARBSIZE
Transfer 256 items 255 13:4 XFERSIZE
N/A for this transfer type 0 3 NXTUSEBURST
Use Auto-request transfer mode 2 2:0 XFERMODE
8.3.2.3 Start the Transfer
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 30 of the DMA Channel Enable Set (DMAENASET) register.
2. Issue a transfer request by setting bit 30 of the DMAChannel Software Request (DMASWREQ)
register.
The DMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt
when the transfer is complete. If needed, the status can be checked by reading bit 30 of the
DMAENASET register. This bit is automatically cleared when the transfer is complete. The status
can also be checked by reading the XFERMODE field of the channel control word at offset 0x1E8.
This field is automatically cleared at the end of the transfer.
8.3.3 Configuring a Peripheral for Simple Transmit
This example configures the DMA controller to transmit a buffer of data to a peripheral. The
peripheral has a transmit FIFOwith a trigger level of 4. The example peripheral uses DMA channel
7.
1. Configure bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
This example transfers 64 bytes from a memory buffer to the peripheral's transmit FIFO register
using DMA channel 7. The control structure for channel 7 is at offset 0x070 of the channel control
table. The channel control structure for channel 7 is located at the offsets shown in Table 8-9.
Table 8-9. Channel Control Structure Offsets for Channel 7
Description Offset
Channel 7 Source End Pointer Control Table Base + 0x070
April 10, 2013 544
Table 8-9. Channel Control Structure Offsets for Channel 7 (continued)
Description Offset
Channel 7 Destination End Pointer Control Table Base + 0x074
Channel 7 Control Word Control Table Base + 0x078
Because the peripheral pointer does not change, it simply points to the peripheral's data register.
1. Program the source end pointer at offset 0x070 to the address of the source buffer + 0x3F.
2. Program the destination end pointer at offset 0x074 to the address of the peripheral's transmit
FIFO register.
The control word at offset 0x078 must be programmed according to Table 8-10.
Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example
Destination address does not increment 3 31:30 DSTINC
8-bit source address increment 0 27:26 SRCINC
Use Basic transfer mode 1 2:0 XFERMODE
Note: In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 4, the arbitration size is set to
4. If the peripheral does make a burst request, then 4 bytes are transferred, which is what
the FIFO can accommodate. If the peripheral makes a single request (if there is any space
in the FIFO), then one byte is transferred at a time. If it is important to the application that
transfers only be made in bursts, then the Channel Useburst SET[7] bit should be set in
the DMA Channel Useburst Set (DMAUSEBURSTSET) register.
8.3.3.3 Start the Transfer
The DMA controller is now configured for transfer on channel 7. The controller makes transfers to
the peripheral whenever the peripheral asserts a DMA request. The transfers continue until the
entire buffer of 64 bytes has been transferred. When that happens, the DMA controller disables
the channel and sets the XFERMODE field of the channel control word to 0 (Stopped). The status of
the transfer can be checked by reading bit 7 of the DMA Channel Enable Set (DMAENASET)
register. This bit is automatically cleared when the transfer is complete. The status can also be
checked by reading the XFERMODE field of the channel control word at offset 0x078. This field is
automatically cleared at the end of the transfer.
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If peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when
the entire transfer is complete.
8.3.4 Configuring a Peripheral for Ping-Pong Receive
This example configures the DMA controller to continuously receive 8-bit data from a peripheral
into a pair of 64-byte buffers. The peripheral has a receive FIFOwith a trigger level of 8. The example
peripheral uses DMA channel 8.
1. Configure bit 8 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
This example transfers bytes from the peripheral's receive FIFO register into two memory buffers
of 64 bytes each. As data is received, when one buffer is full, the DMA controller switches to use
the other.
To use Ping-Pong buffering, both primary and alternate channel control structures must be used.
The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the
alternate channel control structure is at offset 0x280. The channel control structures for channel 8
are located at the offsets shown in Table 8-11.
Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8
Description Offset
Channel 8 Primary Source End Pointer Control Table Base + 0x080
Channel 8 Primary Destination End Pointer Control Table Base + 0x084
Channel 8 Primary Control Word Control Table Base + 0x088
Channel 8 Alternate Source End Pointer Control Table Base + 0x280
Channel 8 Alternate Destination End Pointer Control Table Base + 0x284
Channel 8 Alternate Control Word Control Table Base + 0x288
Because the peripheral pointer does not change, it simply points to the peripheral's data register.
Both the primary and alternate sets of pointers must be configured.
1. Programthe primary source end pointer at offset 0x080 to the address of the peripheral's receive
buffer.
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2. Program the primary destination end pointer at offset 0x084 to the address of ping-pong buffer
A + 0x3F.
3. Program the alternate source end pointer at offset 0x280 to the address of the peripheral's
receive buffer.
4. Program the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer
B + 0x3F.
The primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially
programmed the same way.
1. Program the primary channel control word at offset 0x088 according to Table 8-12.
2. Program the alternate channel control word at offset 0x288 according to Table 8-12.
Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example
8-bit destination address increment 0 31:30 DSTINC
Source address does not increment 3 27:26 SRCINC
Use Ping-Pong transfer mode 3 2:0 XFERMODE
Note: In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 8, the arbitration size is set to
8. If the peripheral does make a burst request, then 8 bytes are transferred, which is what
the FIFO can accommodate. If the peripheral makes a single request (if there is any data
in the FIFO), then one byte is transferred at a time. If it is important to the application that
transfers only be made in bursts, then the Channel Useburst SET[8] bit should be set in
the DMA Channel Useburst Set (DMAUSEBURSTSET) register.
8.3.4.3 Configure the Peripheral Interrupt
An interrupt handler should be configured when using DMA Ping-Pong mode, it is best to use an
interrupt handler. However, the Ping-Pong mode can be configured without interrupts by polling.
The interrupt handler is triggered after each buffer is complete.
1. Configure and enable an interrupt handler for the peripheral.
8.3.4.4 Enable the DMA Channel
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8.3.4.5 Process Interrupts
The DMA controller is now configured and enabled for transfer on channel 8. When the peripheral
asserts the DMA request signal, the DMA controller makes transfers into buffer A using the primary
channel control structure. When the primary transfer to buffer A is complete, it switches to the
alternate channel control structure and makes transfers into buffer B. At the same time, the primary
channel control word mode field is configured to indicate Stopped, and an interrupt is pending.
When an interrupt is triggered, the interrupt handler must determine which buffer is complete and
process the data or set a flag that the data must be processed by non-interrupt buffer processing
code. Then the next buffer transfer must be set up.
In the interrupt handler:
1. Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the
field is 0, this means buffer A is complete. If buffer A is complete, then:
a. Process the newly received data in buffer A or signal the buffer processing code that buffer
A has data available.
b. Reprogram the primary channel control word at offset 0x88 according to Table
8-12 on page 547.
2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the
field is 0, this means buffer B is complete. If buffer B is complete, then:
a. Process the newly received data in buffer B or signal the buffer processing code that buffer
B has data available.
b. Reprogram the alternate channel control word at offset 0x288 according to Table
8-12 on page 547.
8.3.5 Configuring Channel Assignments
Channel assignments for each DMA channel can be changed using the DMACHMAPn registers.
Each 4-bit field represents a DMA channel.
Refer to Table 8-1 on page 529 for channel assignments.
8.4 Register Map
Table 8-13 on page 549 lists the DMA channel control structures and registers. The channel control
structure shows the layout of one entry in the channel control table. The channel control table is
located in systemmemory, and the location is determined by the application, thus, the base address
is n/a (not applicable) and noted as so above the register descriptions. In the table below, the offset
for the channel control structures is the offset from the entry in the channel control table. See
Channel Configuration on page 531 and Table 8-3 on page 532 for a description of how the entries
in the channel control table are located in memory. The DMA register addresses are given as a
hexadecimal increment, relative to the DMA base address of 0x400F.F000. Note that the DMA
module clock must be enabled before the registers can be programmed (see page 324). There must
be a delay of 3 system clocks after the DMA module clock is enabled before any DMA module
registers are accessed.
April 10, 2013 548
Table 8-13. DMA Register Map
See
page
DMA Channel Control Structure (Offset from Channel Control Table Base)
551 DMA Channel Source Address End Pointer - R/W DMASRCENDP 0x000
552 DMA Channel Destination Address End Pointer - R/W DMADSTENDP 0x004
553 DMA Channel Control Word - R/W DMACHCTL 0x008
DMA Registers (Offset from DMA Base Address)
558 DMA Status 0x001F.0000 RO DMASTAT 0x000
560 DMA Configuration - WO DMACFG 0x004
561 DMA Channel Control Base Pointer 0x0000.0000 R/W DMACTLBASE 0x008
562 DMA Alternate Channel Control Base Pointer 0x0000.0200 RO DMAALTBASE 0x00C
563 DMA Channel Wait-on-Request Status 0x03C3.CF00 RO DMAWAITSTAT 0x010
564 DMA Channel Software Request - WO DMASWREQ 0x014
565 DMA Channel Useburst Set 0x0000.0000 R/W DMAUSEBURSTSET 0x018
566 DMA Channel Useburst Clear - WO DMAUSEBURSTCLR 0x01C
567 DMA Channel Request Mask Set 0x0000.0000 R/W DMAREQMASKSET 0x020
568 DMA Channel Request Mask Clear - WO DMAREQMASKCLR 0x024
569 DMA Channel Enable Set 0x0000.0000 R/W DMAENASET 0x028
570 DMA Channel Enable Clear - WO DMAENACLR 0x02C
571 DMA Channel Primary Alternate Set 0x0000.0000 R/W DMAALTSET 0x030
572 DMA Channel Primary Alternate Clear - WO DMAALTCLR 0x034
573 DMA Channel Priority Set 0x0000.0000 R/W DMAPRIOSET 0x038
574 DMA Channel Priority Clear - WO DMAPRIOCLR 0x03C
575 DMA Bus Error Clear 0x0000.0000 R/W DMAERRCLR 0x04C
576 DMA Channel Assignment 0x0000.0000 R/W DMACHASGN 0x500
577 DMA Channel Interrupt Status 0x0000.0000 R/W1C DMACHIS 0x504
578 DMA Channel Map Select 0 0x0000.0000 R/W DMACHMAP0 0x510
581 DMA Channel Map Select 3 0x0000.0000 R/W DMACHMAP3 0x51C
586 DMA Peripheral Identification 4 0x0000.0004 RO DMAPeriphID4 0xFD0
582 DMA Peripheral Identification 0 0x0000.0030 RO DMAPeriphID0 0xFE0
583 DMA Peripheral Identification 1 0x0000.00B2 RO DMAPeriphID1 0xFE4
584 DMA Peripheral Identification 2 0x0000.000B RO DMAPeriphID2 0xFE8
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Table 8-13. DMA Register Map (continued)
See
page
585 DMA Peripheral Identification 3 0x0000.0000 RO DMAPeriphID3 0xFEC
587 DMA PrimeCell Identification 0 0x0000.000D RO DMAPCellID0 0xFF0
588 DMA PrimeCell Identification 1 0x0000.00F0 RO DMAPCellID1 0xFF4
589 DMA PrimeCell Identification 2 0x0000.0005 RO DMAPCellID2 0xFF8
590 DMA PrimeCell Identification 3 0x0000.00B1 RO DMAPCellID3 0xFFC
8.5 DMA Channel Control Structure
The DMA Channel Control Structure holds the transfer settings for a DMA channel. Each channel
has two control structures, which are located in a table in system memory. Refer to Channel
Configuration on page 531 for an explanation of the Channel Control Table and the Channel Control
Structure.
The channel control structure is one entry in the channel control table. Each channel has a primary
and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and
so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on.
April 10, 2013 550
Register 1: DMAChannel Source Address End Pointer (DMASRCENDP), offset
0x000
DMA Channel Source Address End Pointer (DMASRCENDP) is part of the Channel Control
Structure and is used to specify the source address for a DMA transfer.
The DMA controller can transfer data to and from the on-chip SRAM. However, because the Flash
memory and ROM are located on a separate internal bus, it is not possible to transfer data to/from
the Flash memory or ROM with the DMA controller.
Note: The offset specified is from the base address of the control structure in system memory,
not the DMA module base address.
DMA Channel Source Address End Pointer (DMASRCENDP)
Base n/a
Offset 0x000
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADDR
- - - - - - - - - - - - - - - - Reset
Source Address End Pointer
This field points to the last address of the DMA transfer source
(inclusive). If the source address is not incrementing (the SRCINC field
in the DMACHCTL register is 0x3), then this field points at the source
location itself (such as a peripheral data register).
- R/W ADDR 31:0
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Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP),
offset 0x004
DMA Channel Destination Address End Pointer (DMADSTENDP) is part of the Channel Control
Structure and is used to specify the destination address for a DMA transfer.
DMA Channel Destination Address End Pointer (DMADSTENDP)
Base n/a
Offset 0x004
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADDR
- - - - - - - - - - - - - - - - Reset
Destination Address End Pointer
This field points to the last address of the DMA transfer destination
(inclusive). If the destination address is not incrementing (the DSTINC
field in the DMACHCTL register is 0x3), then this field points at the
destination location itself (such as a peripheral data register).
- R/W ADDR 31:0
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Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008
DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used
to specify parameters of a DMA transfer.
DMA Channel Control Word (DMACHCTL)
Base n/a
Offset 0x008
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ARBSIZE reserved SRCSIZE SRCINC DSTSIZE DSTINC
R/W R/W RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Type
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
XFERMODE
N
X
T
U
S
E
B
U
R
S
T
XFERSIZE ARBSIZE
- - - - - - - - - - - - - - - - Reset
Destination Address Increment
This field configures the destination address increment.
The address increment value must be equal or greater than the value
of the destination size (DSTSIZE).
Description Value
Byte
Increment by 8-bit locations
0x0
Half-word
0x1
Word
0x2
No increment
Address remains set to the value of the Destination Address
End Pointer (DMADSTENDP) for the channel
0x3
- R/W DSTINC 31:30
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Destination Data Size
This field configures the destination item data size.
Note: DSTSIZE must be the same as SRCSIZE.
Description Value
Byte
8-bit data size
0x0
Half-word
16-bit data size
0x1
Word
32-bit data size
0x2
Reserved 0x3
- R/W DSTSIZE 29:28
Source Address Increment
This field configures the source address increment.
The address increment value must be equal or greater than the value
of the source size (SRCSIZE).
Description Value
Byte
0x0
Half-word
0x1
Word
0x2
No increment
Address remains set to the value of the Source Address End
Pointer (DMASRCENDP) for the channel
0x3
- R/W SRCINC 27:26
Source Data Size
This field configures the source item data size.
Note: DSTSIZE must be the same as SRCSIZE.
Description Value
Byte
8-bit data size.
0x0
Half-word
16-bit data size.
0x1
Word
32-bit data size.
0x2
Reserved 0x3
- R/W SRCSIZE 25:24
- RO reserved 23:18
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Arbitration Size
This field configures the number of transfers that can occur before the
DMAcontroller re-arbitrates. The possible arbitration rate configurations
represent powers of 2 and are shown below.
Description Value
1 Transfer
Arbitrates after each DMA transfer
0x0
2 Transfers 0x1
4 Transfers 0x2
8 Transfers 0x3
16 Transfers 0x4
32 Transfers 0x5
64 Transfers 0x6
128 Transfers 0x7
256 Transfers 0x8
512 Transfers 0x9
1024 Transfers
In this configuration, no arbitration occurs during the DMA
transfer because the maximum transfer size is 1024.
0xA-0xF
- R/W ARBSIZE 17:14
Transfer Size (minus 1)
This field configures the total number of items to transfer. The value of
this field is 1 less than the number to transfer (value 0 means transfer
1 item). The maximumvalue for this 10-bit field is 1023 which represents
a transfer size of 1024 items.
The transfer size is the number of items, not the number of bytes. If the
data size is 32 bits, then this value is the number of 32-bit words to
transfer.
The DMA controller updates this field immediately prior to entering the
arbitration process, so it contains the number of outstanding items that
is necessary to complete the DMA cycle.
- R/W XFERSIZE 13:4
Next Useburst
This field controls whether the Useburst SET[n] bit is automatically set
for the last transfer of a peripheral scatter-gather operation. Normally,
for the last transfer, if the number of remaining items to transfer is less
than the arbitration size, the DMA controller uses single transfers to
complete the transaction. If this bit is set, then the controller uses a burst
transfer to complete the last transfer.
- R/W NXTUSEBURST 3
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DMA Transfer Mode
This field configures the operating mode of the DMA cycle. Refer to
Transfer Modes on page 533 for a detailed explanation of transfer
modes.
Because this register is in systemRAM, it has no reset value. Therefore,
this field should be initialized to 0 before the channel is enabled.
Description Value
Stop 0x0
Basic 0x1
Auto-Request 0x2
Ping-Pong 0x3
Memory Scatter-Gather 0x4
Alternate Memory Scatter-Gather 0x5
Peripheral Scatter-Gather 0x6
Alternate Peripheral Scatter-Gather 0x7
- R/W XFERMODE 2:0
XFERMODE Bit Field Values.
Stop
Channel is stopped or configuration data is invalid. No more transfers can occur.
Basic
For each trigger (whether froma peripheral or a software request), the DMA controller performs
the number of transfers specified by the ARBSIZE field.
Auto-Request
The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer
of XFERSIZE items without any further requests.
Ping-Pong
This mode uses both the primary and alternate control structures for this channel. When the
number of transfers specified by the XFERSIZE field have completed for the current control
structure (primary or alternate), the DMA controller switches to the other one. These switches
continue until one of the control structures is not set to ping-pong mode. At that point, the DMA
controller stops. An interrupt is generated on completion of the transfers configured by each
control structure. See Ping-Pong on page 533.
Memory Scatter-Gather
When using this mode, the primary control structure for the channel is configured to allow a list
of operations (tasks) to be performed. The source address pointer specifies the start of a table
of tasks to be copied to the alternate control structure for this channel. The XFERMODE field for
the alternate control structure should be configured to 0x5 (Alternate memory scatter-gather)
to perform the task. When the task completes, the DMA switches back to the primary channel
control structure, which then copies the next task to the alternate control structure. This process
continues until the table of tasks is empty. The last task must have an XFERMODE value other
than 0x5. Note that for continuous operation, the last task can update the primary channel control
structure back to the start of the list or to another list. See Memory Scatter-Gather on page 534.
April 10, 2013 556
Alternate Memory Scatter-Gather
This value must be used in the alternate channel control data structure when the DMA controller
operates in Memory Scatter-Gather mode.
Peripheral Scatter-Gather
This value must be used in the primary channel control data structure when the DMA controller
operates in Peripheral Scatter-Gather mode. In this mode, the DMA controller operates exactly
the same as in Memory Scatter-Gather mode, except that instead of performing the number of
transfers specified by the XFERSIZE field in the alternate control structure at one time, the
DMA controller only performs the number of transfers specified by the ARBSIZE field per
trigger; see Basic mode for details. See Peripheral Scatter-Gather on page 538.
Alternate Peripheral Scatter-Gather
This value must be used in the alternate channel control data structure when the DMA controller
operates in Peripheral Scatter-Gather mode.
8.6 DMA Register Descriptions
The register addresses given are relative to the DMA base address of 0x400F.F000.
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Register 4: DMA Status (DMASTAT), offset 0x000
The DMA Status (DMASTAT) register returns the status of the DMA controller. You cannot read
this register when the DMA controller is in the reset state.
DMA Status (DMASTAT)
Base 0x400F.F000
Offset 0x000
Type RO, reset 0x001F.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DMACHANS reserved
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MASTEN reserved STATE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Available DMA Channels Minus 1
This field contains a value equal to the number of DMA channels the
DMA controller is configured to use, minus one. The value of 0x1F
corresponds to 32 DMA channels.
0x1F RO DMACHANS 20:16
Control State Machine Status
This field shows the current status of the control state machine. Status
can be one of the following.
Description Value
Idle 0x0
Reading channel controller data. 0x1
Reading source end pointer. 0x2
Reading destination end pointer. 0x3
Reading source data. 0x4
Writing destination data. 0x5
Waiting for DMA request to clear. 0x6
Writing channel controller data. 0x7
Stalled 0x8
Done 0x9
Undefined 0xA-0xF
0x0 RO STATE 7:4
0x0 RO reserved 3:1
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Master Enable Status
Description Value
The DMA controller is disabled. 0
The DMA controller is enabled. 1
0 RO MASTEN 0
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Register 5: DMA Configuration (DMACFG), offset 0x004
The DMACFG register controls the configuration of the DMA controller.
DMA Configuration (DMACFG)
Base 0x400F.F000
Offset 0x004
Type WO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MASTEN reserved
- - - - - - - - - - - - - - - - Reset
- WO reserved 31:1
Controller Master Enable
Description Value
Disables the DMA controller. 0
Enables DMA controller. 1
- WO MASTEN 0
April 10, 2013 560
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008
The DMACTLBASE register must be configured so that the base pointer points to a location in
system memory.
The amount of system memory that must be assigned to the DMA controller depends on the
number of DMA channels used and whether the alternate channel control data structure is used.
See Channel Configuration on page 531 for details about the Channel Control Table. The base
address must be aligned on a 1024-byte boundary. This register cannot be read when the DMA
controller is in the reset state.
DMA Channel Control Base Pointer (DMACTLBASE)
Base 0x400F.F000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved ADDR
RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Channel Control Base Address
This field contains the pointer to the base address of the channel control
table. The base address must be 1024-byte aligned.
0x0000.00 R/W ADDR 31:10
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Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE),
offset 0x00C
The DMAALTBASE register returns the base address of the alternate channel control data. This
register removes the necessity for application software to calculate the base address of the alternate
channel control structures. This register cannot be read when the DMA controller is in the reset
state.
DMA Alternate Channel Control Base Pointer (DMAALTBASE)
Base 0x400F.F000
Offset 0x00C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADDR
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Reset
Alternate Channel Address Pointer
This field provides the base address of the alternate channel control
structures.
0x0000.0200 RO ADDR 31:0
April 10, 2013 562
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset
0x010
This read-only register indicates that the DMA channel is waiting on a request. A peripheral can
hold off the DMA from performing a single request until the peripheral is ready for a burst request
to enhance the DMA performance. The use of this feature is dependent on the design of the
peripheral and is not controllable by software in any way. This register cannot be read when the
DMA controller is in the reset state.
DMA Channel Wait-on-Request Status (DMAWAITSTAT)
Base 0x400F.F000
Offset 0x010
Type RO, reset 0x03C3.CF00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WAITREQ[n]
1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WAITREQ[n]
0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 Reset
Channel [n] Wait Status
These bits provide the channel wait-on-request status. Bit 0 corresponds
to channel 0.
Description Value
The corresponding channel is waiting on a request. 1
The corresponding channel is not waiting on a request. 0
0x03C3.CF00 RO WAITREQ[n] 31:0
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Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014
Each bit of the DMASWREQ register represents the corresponding DMA channel. Setting a bit
generates a request for the specified DMA channel.
DMA Channel Software Request (DMASWREQ)
Base 0x400F.F000
Offset 0x014
Type WO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SWREQ[n]
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SWREQ[n]
- - - - - - - - - - - - - - - - Reset
Channel [n] Software Request
These bits generate software requests. Bit 0 corresponds to channel 0.
Description Value
Generate a software request for the corresponding channel. 1
No request generated. 0
These bits are automatically cleared when the software request has
been completed.
- WO SWREQ[n] 31:0
April 10, 2013 564
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018
Each bit of the DMAUSEBURSTSET register represents the corresponding DMA channel. Setting
a bit disables the channel's single request input from generating requests, configuring the channel
to only accept burst requests. Reading the register returns the status of USEBURST.
If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET[n]
bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than
the arbitration (burst) size, the DMA controller automatically clears the corresponding SET[n] bit,
allowing the remaining items to transfer using single requests. In order to resume transfers using
burst requests, the corresponding bit must be set again. A bit should not be set if the corresponding
peripheral does not support the burst request model.
Refer to Request Types on page 530 for more details about request types.
DMA Channel Useburst Set (DMAUSEBURSTSET)
Base 0x400F.F000
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Channel [n] Useburst Set
Description Value
DMA channel [n] responds to single or burst requests. 0
DMA channel [n] responds only to burst requests. 1
Bit 0 corresponds to channel 0. This bit is automatically cleared as
described above. A bit can also be manually cleared by setting the
corresponding CLR[n] bit in the DMAUSEBURSTCLR register.
0x0000.0000 R/W SET[n] 31:0
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Register 11: DMAChannel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C
Each bit of the DMAUSEBURSTCLRregister represents the corresponding DMA channel. Setting
a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register.
DMA Channel Useburst Clear (DMAUSEBURSTCLR)
Base 0x400F.F000
Offset 0x01C
Type WO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLR[n]
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLR[n]
- - - - - - - - - - - - - - - - Reset
Channel [n] Useburst Clear
Description Value
No effect. 0
Setting a bit clears the corresponding SET[n] bit in the
DMAUSEBURSTSET register meaning that DMA channel [n]
responds to single and burst requests.
1
- WO CLR[n] 31:0
April 10, 2013 566
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset
0x020
Each bit of the DMAREQMASKSET register represents the corresponding DMA channel. Setting
a bit disables DMA requests for the channel. Reading the register returns the request mask status.
When a DMA channel's request is masked, that means the peripheral can no longer request DMA
transfers. The channel can then be used for software-initiated transfers.
DMA Channel Request Mask Set (DMAREQMASKSET)
Base 0x400F.F000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Channel [n] Request Mask Set
Description Value
The peripheral associated with channel [n] is enabled to request
DMA transfers.
0
The peripheral associated with channel [n] is not able to request
DMA transfers. Channel [n] may be used for software-initiated
transfers.
1
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAREQMASKCLR register.
0x0000.0000 R/W SET[n] 31:0
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Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset
0x024
Each bit of the DMAREQMASKCLR register represents the corresponding DMA channel. Setting
a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register.
DMA Channel Request Mask Clear (DMAREQMASKCLR)
Base 0x400F.F000
Offset 0x024
Type WO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLR[n]
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLR[n]
- - - - - - - - - - - - - - - - Reset
Channel [n] Request Mask Clear
Description Value
No effect. 0
DMAREQMASKSET register meaning that the peripheral
associated with channel [n] is enabled to request DMA
transfers.
1
- WO CLR[n] 31:0
April 10, 2013 568
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028
Each bit of the DMAENASET register represents the corresponding DMA channel. Setting a bit
enables the corresponding DMA channel. Reading the register returns the enable status of the
channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the
channel can be used for software-initiated transfers.
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Channel [n] Enable Set
Description Value
DMA Channel [n] is disabled. 0
DMA Channel [n] is enabled. 1
corresponding CLR[n] bit in the DMAENACLR register or when the
end of a DMA transfer occurs.
0x0000.0000 R/W SET[n] 31:0
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Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C
Each bit of the DMAENACLR register represents the corresponding DMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAENASET register.
DMA Channel Enable Clear (DMAENACLR)
Base 0x400F.F000
Offset 0x02C
Type WO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLR[n]
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLR[n]
- - - - - - - - - - - - - - - - Reset
Clear Channel [n] Enable Clear
Description Value
No effect. 0
DMAENASET register meaning that channel [n] is disabled for
DMA transfers.
1
Note: The controller disables a channel when it completes the DMA
cycle.
- WO CLR[n] 31:0
April 10, 2013 570
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030
Each bit of the DMAALTSET register represents the corresponding DMA channel. Setting a bit
configures the DMA channel to use the alternate control data structure. Reading the register returns
the status of which control data structure is in use for the corresponding DMA channel.
DMA Channel Primary Alternate Set (DMAALTSET)
Base 0x400F.F000
Offset 0x030
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Channel [n] Alternate Set
Description Value
DMA channel [n] is using the primary control structure. 0
DMA channel [n] is using the alternate control structure. 1
corresponding CLR[n] bit in the DMAALTCLR register.
Note: For Ping-Pong and Scatter-Gather cycle types, the DMA
controller automatically sets these bits to select the alternate
channel control data structure.
0x0000.0000 R/W SET[n] 31:0
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Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset
0x034
Each bit of the DMAALTCLR register represents the corresponding DMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAALTSET register.
DMA Channel Primary Alternate Clear (DMAALTCLR)
Base 0x400F.F000
Offset 0x034
Type WO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLR[n]
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLR[n]
- - - - - - - - - - - - - - - - Reset
Channel [n] Alternate Clear
Description Value
No effect. 0
DMAALTSET register meaning that channel [n] is using the
primary control structure.
1
Note: For Ping-Pong and Scatter-Gather cycle types, the DMA
controller automatically sets these bits to select the alternate
channel control data structure.
- WO CLR[n] 31:0
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Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038
Each bit of the DMAPRIOSET register represents the corresponding DMA channel. Setting a bit
configures the DMA channel to have a high priority level. Reading the register returns the status
of the channel priority mask.
DMA Channel Priority Set (DMAPRIOSET)
Base 0x400F.F000
Offset 0x038
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SET[n]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Channel [n] Priority Set
Description Value
DMA channel [n] is using the default priority level. 0
DMA channel [n] is using a high priority level. 1
corresponding CLR[n] bit in the DMAPRIOCLR register.
0x0000.0000 R/W SET[n] 31:0
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Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C
Each bit of the DMAPRIOCLR register represents the corresponding DMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAPRIOSET register.
DMA Channel Priority Clear (DMAPRIOCLR)
Base 0x400F.F000
Offset 0x03C
Type WO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLR[n]
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLR[n]
- - - - - - - - - - - - - - - - Reset
Channel [n] Priority Clear
Description Value
No effect. 0
DMAPRIOSET register meaning that channel [n] is using the
default priority level.
1
- WO CLR[n] 31:0
April 10, 2013 574
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C
The DMAERRCLR register is used to read and clear the DMA bus error status. The error status
is set if the DMA controller encountered a bus error while performing a transfer. If a bus error
occurs on a channel, that channel is automatically disabled by the DMA controller. The other
channels are unaffected.
DMA Bus Error Clear (DMAERRCLR)
Base 0x400F.F000
Offset 0x04C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ERRCLR reserved
R/W1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DMA Bus Error Status
Description Value
No bus error is pending. 0
A bus error is pending. 1
0 R/W1C ERRCLR 0
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Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500
Each bit of the DMACHASGN register represents the corresponding DMA channel. Setting a bit
selects the secondary channel assignment as specified in Table 8-1 on page 529.
Note: This register is provided to support legacy software. New software should use the
DMACHMAPn registers. If a bit is clear in this register, the corresponding field in the
DMACHMAPn registers is configured to 0x0. If a bit is set in this register, the corresponding
field is configured to 0x1. If this register is read, a bit reads as 0 if the corresponding
DMACHMAPn register field value is equal to 0, otherwise it reads as 1 if the corresponding
DMACHMAPn register field value is not equal to 0.
DMA Channel Assignment (DMACHASGN)
Base 0x400F.F000
Offset 0x500
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CHASGN[n]
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CHASGN[n]
- - - - - - - - - - - - - - - - Reset
Channel [n] Assignment Select
Description Value
Use the primary channel assignment. 0
Use the secondary channel assignment. 1
- R/W CHASGN[n] 31:0
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Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504
Each bit of the DMACHIS register represents the corresponding DMA channel. A bit is set when
that DMA channel causes a completion interrupt. The bits are cleared by a writing a 1.
DMA Channel Interrupt Status (DMACHIS)
Base 0x400F.F000
Offset 0x504
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CHIS[n]
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CHIS[n]
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Channel [n] Interrupt Status
Description Value
The corresponding DMA channel caused an interrupt. 1
The corresponding DMA channel has not caused an interrupt. 0
0x0000.0000 R/W1C CHIS[n] 31:0
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Register 23: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510
Each 4-bit field of the DMACHMAP0 register configures the DMA channel assignment as specified
Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN)
register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1
is equivalent to a DMACHASGN bit being set.
DMA Channel Map Select 0 (DMACHMAP0)
Base 0x400F.F000
Offset 0x510
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CH4SEL CH5SEL CH6SEL CH7SEL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DMA Channel 7 Source Select
See Table 8-1 on page 529 for channel assignments.
0x00 R/W CH7SEL 31:28
0x00 R/W CH6SEL 27:24
0x00 R/W CH5SEL 23:20
0x00 R/W CH4SEL 19:16
0x00 R/W CH3SEL 15:12
0x00 R/W CH2SEL 11:8
0x00 R/W CH1SEL 7:4
0x00 R/W CH0SEL 3:0
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Base 0x400F.F000
Offset 0x514
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 R/W CH15SEL 31:28
0x00 R/W CH14SEL 27:24
0x00 R/W CH13SEL 23:20
0x00 R/W CH12SEL 19:16
0x00 R/W CH11SEL 15:12
0x00 R/W CH10SEL 11:8
0x00 R/W CH9SEL 7:4
0x00 R/W CH8SEL 3:0
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Base 0x400F.F000
Offset 0x518
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 R/W CH23SEL 31:28
0x00 R/W CH22SEL 27:24
0x00 R/W CH21SEL 23:20
0x00 R/W CH20SEL 19:16
0x00 R/W CH19SEL 15:12
0x00 R/W CH18SEL 11:8
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Register 26: DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C
Base 0x400F.F000
Offset 0x51C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 R/W CH31SEL 31:28
0x00 R/W CH30SEL 27:24
0x00 R/W CH29SEL 23:20
0x00 R/W CH28SEL 19:16
0x00 R/W CH27SEL 15:12
0x00 R/W CH26SEL 11:8
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Register 27: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0
The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA Peripheral Identification 0 (DMAPeriphID0)
Base 0x400F.F000
Offset 0xFE0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID0 reserved
0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Reset
DMA Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
0x30 RO PID0 7:0
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values.
Base 0x400F.F000
Offset 0xFE4
Type RO, reset 0x0000.00B2
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID1 reserved
0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset
0xB2 RO PID1 7:0
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values.
Base 0x400F.F000
Offset 0xFE8
Type RO, reset 0x0000.000B
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID2 reserved
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0B RO PID2 7:0
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Register 30: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC
The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset
values.
Base 0x400F.F000
Offset 0xFEC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID3 7:0
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Register 31: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0
values.
Base 0x400F.F000
Offset 0xFD0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID4 reserved
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DMA Peripheral ID Register
0x04 RO PID4 7:0
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Register 32: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0
The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 0 (DMAPCellID0)
Base 0x400F.F000
Offset 0xFF0
Type RO, reset 0x0000.000D
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID0 reserved
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DMA PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
0x0D RO CID0 7:0
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values.
Base 0x400F.F000
Offset 0xFF4
Type RO, reset 0x0000.00F0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID1 reserved
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Reset
0xF0 RO CID1 7:0
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values.
Base 0x400F.F000
Offset 0xFF8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID2 reserved
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x05 RO CID2 7:0
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Register 35: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC
values.
Base 0x400F.F000
Offset 0xFFC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID3 reserved
1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset
0xB1 RO CID3 7:0
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9 General-Purpose Input/Outputs (GPIOs)
The GPIOmodule is composed of seven physical GPIOblocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G). The GPIO module supports up to
49 programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
5-V-tolerant in input configuration
Ports A-G accessed through the Advanced Peripheral Bus (APB)
Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for
ports on APB
Programmable control for GPIO interrupts
Interrupt generation masking
Edge-triggered on rising, falling, or both
Level-sensitive on High or Low values
Bit masking in both read and write operations through address lines
Can be used to initiate an ADC sample sequence or a DMA transfer
Pins configured as digital inputs are Schmitt-triggered
Programmable control for GPIO pad configuration
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA
for high-current applications
Slew rate control for 8-mA pad drive
Open drain enables
Digital input enables
GPIO signals have alternate hardware functions. The following table lists the GPIO pins and their
analog and digital alternate functions. All GPIO signals are 5-V tolerant when configured as inputs
except for PD4, PD5, PB0 and PB1, which are limited to 3.6 V. The digital alternate hardware functions
are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL)
and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL)
register to the numeric encoding shown in the table below. Analog signals in the table below are
also 5-V tolerant and are configured by clearing the DEN bit in the GPIODigital Enable (GPIODEN)
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register. The AINx analog signals have internal circuitry to protect them from voltages over V
DD
(up
to the maximum specified in Table 22-4 on page 1184), but analog performance specifications are
only guaranteed if the input signal swing at the I/O pad is kept inside the range 0 V < V
IN
< V
DD
.
Note that each pin must be programmed individually; no type of grouping is implied by the columns
in the table. Table entries that are shaded gray are the default values for the corresponding GPIO
pin.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0), with the exception of
the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the
pins back to their default state.
Table 9-1. GPIO Pins With Non-Zero Reset Values
GPIOPCTL GPIOPUR GPIOPDR GPIODEN GPIOAFSEL Default State GPIO Pins
0x1 0 0 0 0 UART0 PA[1:0]
0x2 0 0 0 0 SSI0 PA[5:2]
0x3 0 0 0 0 I
2
C0 PB[3:2]
0x1 1 0 1 1 JTAG/SWD PC[3:0]
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware signals including the GPIO pins that can function as
JTAG/SWD signals and the NMI signal. The commit control process must be followed
for these pins, even if they are programmed as alternate functions other than JTAG/SWD
or NMI, see Commit Control on page 598.
Table 9-2. GPIO Pins and Alternate Functions (64LQFP)
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
a
Analog
Function
Pin IO
15 14 9 8 7 6 5 4 3 2 1
- - - CAN1Rx - - - - - - U0Rx - 17 PA0
- - - CAN1Tx - - - - - - U0Tx - 18 PA1
- - - - - - - - - SSI0Clk - - 19 PA2
- - - - - - - - - SSI0Fss - - 20 PA3
- - - - - - - - - SSI0Rx - - 21 PA4
- - - - - - - - - SSI0Tx - - 22 PA5
- - - - - - M1PWM2 - I2C1SCL - - - 23 PA6
- - - - - - M1PWM3 - I2C1SDA - - - 24 PA7
- - - - T2CCP0 - - - - - U1Rx - 45 PB0
- - - - T2CCP1 - - - - - U1Tx - 46 PB1
- - - - T3CCP0 - - - I2C0SCL - - - 47 PB2
- - - - T3CCP1 - - - I2C0SDA - - - 48 PB3
- - - CAN0Rx T1CCP0 - - M0PWM2 - SSI2Clk - AIN10 58 PB4
- - - CAN0Tx T1CCP1 - - M0PWM3 - SSI2Fss - AIN11 57 PB5
- - - - T0CCP0 - - M0PWM0 I2C5SCL SSI2Rx - - 1 PB6
- - - - T0CCP1 - - M0PWM1 I2C5SDA SSI2Tx - - 4 PB7
- - - - T4CCP0 - - - - -
TCK
SWCLK
- 52 PC0
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General-Purpose Input/Outputs (GPIOs)
Table 9-2. GPIO Pins and Alternate Functions (64LQFP) (continued)
a
Analog
Function
Pin IO
15 14 9 8 7 6 5 4 3 2 1
- - - - T4CCP1 - - - - -
TMS
SWDIO
- 51 PC1
- - - - T5CCP0 - - - - - TDI - 50 PC2
- - - - T5CCP1 - - - - -
TDO
SWO
- 49 PC3
- - - U1RTS WT0CCP0 IDX1 - M0PWM6 - U1Rx U4Rx C1- 16 PC4
- - - U1CTS WT0CCP1 PhA1 - M0PWM7 - U1Tx U4Tx C1+ 15 PC5
- - - - WT1CCP0 PhB1 - - - - U3Rx C0+ 14 PC6
- - - - WT1CCP1 - - - - - U3Tx C0- 13 PC7
- - - - WT2CCP0 - M1PWM0 M0PWM6 I2C3SCL SSI1Clk SSI3Clk AIN7 61 PD0
- - - - WT2CCP1 - M1PWM1 M0PWM7 I2C3SDA SSI1Fss SSI3Fss AIN6 62 PD1
- - - - WT3CCP0 - - M0FAULT0 - SSI1Rx SSI3Rx AIN5 63 PD2
- - - - WT3CCP1 IDX0 - - - SSI1Tx SSI3Tx AIN4 64 PD3
- - - - WT4CCP0 - - - - - U6Rx - 43 PD4
- - - - WT4CCP1 - - - - - U6Tx - 44 PD5
- - - - WT5CCP0 PhA0 - M0FAULT0 - - U2Rx - 53 PD6
- - - NMI WT5CCP1 PhB0 - M0FAULT1 - - U2Tx - 10 PD7
- - - - - - - - - - U7Rx AIN3 9 PE0
- - - - - - - - - - U7Tx AIN2 8 PE1
- - - - - - - - - - - AIN1 7 PE2
- - - - - - - - - - - AIN0 6 PE3
- - - CAN0Rx - - M1PWM2 M0PWM4 I2C2SCL - U5Rx AIN9 59 PE4
- - - CAN0Tx - - M1PWM3 M0PWM5 I2C2SDA - U5Tx AIN8 60 PE5
- - C0o NMI T0CCP0 PhA0 M1PWM4 - CAN0Rx SSI1Rx U1RTS - 28 PF0
- TRD1 C1o - T0CCP1 PhB0 M1PWM5 - - SSI1Tx U1CTS - 29 PF1
- TRD0 - - T1CCP0 - M1PWM6 M0FAULT0 - SSI1Clk - - 30 PF2
- TRCLK - - T1CCP1 - M1PWM7 M0FAULT1 CAN0Tx SSI1Fss - - 31 PF3
- - - - T2CCP0 IDX0 M1FAULT0 M0FAULT2 - - - - 5 PF4
- - - - T4CCP0 PhA1 M1FAULT1 - I2C3SCL - - - 37 PG0
- - - - T4CCP1 PhB1 M1FAULT2 - I2C3SDA - - - 36 PG1
- - - - T5CCP0 - M1PWM0 M0FAULT1 I2C4SCL - - - 35 PG2
- - - - T5CCP1 PhA1 M1PWM1 M0FAULT2 I2C4SDA - - - 34 PG3
- - - - WT0CCP0 PhB1 M1PWM2 M0PWM4 I2C1SCL - U2Rx - 33 PG4
- - - - WT0CCP1 IDX1 M1PWM3 M0PWM5 I2C1SDA - U2Tx - 32 PG5
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. Encodings 10-13 are not used
on this device.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
9-1 on page 594 and Figure 9-2 on page 595). The TM4C123AH6PMmicrocontroller contains seven
ports and thus seven of these physical GPIOblocks. Note that not all pins are implemented on every
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block. Some GPIOpins can function as I/Osignals for the on-chip peripheral modules. For information
on which GPIO pins are used for alternate hardware functions, refer to Table 21-5 on page 1176.
Figure 9-1. Digital I/O Pads
Pad
Control
Commit
Control
Data
Control
Interrupt
Control
M
U
X
M
U
X
D
E
M
U
X
Digital
I/O
Pad
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Pad Input
Pad Output
Enable
GPIOLOCK
GPIOCR
GPIODATA
GPIODIR
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Package I/O Pin
M
U
X
Periph 0
Periph 1
Periph n
Port
Control
GPIOPCTL
GPIOSI
Mode
Control
GPIOAFSEL
GPIOADCCTL
GPIODMACTL
GPIOAMSEL
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Figure 9-2. Analog/Digital I/O Pads
Pad
Control
Data
Control
GPIO Input
GPIO Output
GPIO Output Enable
Interrupt
Control
Interrupt
M
U
X
M
U
X
GPIODR8R
GPIODR2R
GPIODR4R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
GPIOAMSEL
GPIOIEV
GPIOIS
GPIOIBE
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIODATA
GPIODIR
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Analog Circuitry
(for GPIO pins that
connect to the ADC
input MUX)
ADC
Isolation
Circuit
Pad Output Enable
Package I/O Pin
Pad Input
Pad Output
Analog/Digital
I/O Pad
Commit
Control
GPIOLOCK
GPIOCR
Alternate Input
Alternate Output
Alternate Output Enable
M
U
X
Periph 0
Periph 1
Periph n
Port
Control
GPIOPCTL
D
E
M
U
X
Mode
Control
GPIOAFSEL
GPIOADCCTL
GPIODMACTL
GPIOSI
9.2.1 Data Control
The data control registers allowsoftware to configure the operational modes of the GPIOs. The data
direction register configures the GPIOas an input or an output while the data register either captures
incoming data or drives it out to the pads.
9.2.1.1 Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 604) is used to configure each individual pin as
an input or output. When the data direction bit is cleared, the GPIO is configured as an input, and
the corresponding data register bit captures and stores the value on the GPIO port. When the data
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direction bit is set, the GPIO is configured as an output, and the corresponding data register bit is
driven out on the GPIO port.
9.2.1.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 603) by using bits [9:2] of the address bus as a mask.
In this manner, software drivers can modify individual GPIO pins in a single instruction without
affecting the state of the other pins. This method is more efficient than the conventional method of
performing a read-modify-write operation to set or clear an individual GPIO pin. To implement this
feature, the GPIODATA register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set, the value of the GPIODATA
register is altered. If the address bit is cleared, the data bit is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 has the results shown in
Figure 9-3, where u indicates that data is unchanged by the write. This example demonstrates how
GPIODATA bits 5, 2, and 1 are written.
Figure 9-3. GPIODATA Write Example
0 1 0 0 1 1 0 0 0
u 1 u u 0 1 u u
9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 1 1
7 6 5 4 3 2 1 0
GPIODATA
0xEB
0x098
ADDR[9:2]
0
During a read, if the address bit associated with the data bit is set, the value is read. If the address
bit associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual
value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-4. This
example shows how to read GPIODATA bits 5, 4, and 0.
Figure 9-4. GPIODATA Read Example
0 1 0 1 0 0 0 1 0 0
0 1 0 1 0 0 0 0
9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 0
7 6 5 4 3 2 1 0
Returned Value
GPIODATA
0x0C4
ADDR[9:2]
9.2.2 Interrupt Control
The interrupt capabilities of each GPIOport are controlled by a set of seven registers. These registers
are used to select the source of the interrupt, its polarity, and the edge properties. When one or
more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for
the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any
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further interrupts. For a level-sensitive interrupt, the external source must hold the level constant
for the interrupt to be recognized by the controller.
Three registers define the edge or sense that causes interrupts:
GPIO Interrupt Sense (GPIOIS) register (see page 605)
GPIO Interrupt Both Edges (GPIOIBE) register (see page 606)
GPIO Interrupt Event (GPIOIEV) register (see page 607)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 608).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIORawInterrupt Status (GPIORIS) and GPIOMasked Interrupt Status (GPIOMIS) registers
(see page 609 and page 610). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates
that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the
For a GPIO level-detect interrupt, the interrupt signal generating the interrupt must be held until
serviced. Once the input signal deasserts from the interrupt generating logical sense, the
corresponding RIS bit in the GPIORIS register clears. For a GPIO edge-detect interrupt, the RIS
bit in the GPIORIS register is cleared by writing a 1 to the corresponding bit in the GPIO Interrupt
Clear (GPIOICR) register (see page 611). The corresponding GPIOMISbit reflects the masked value
of the RIS bit.
When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts
should be masked (GPIOIMcleared). Writing any value to an interrupt control register can generate
a spurious interrupt if the corresponding bits are enabled.
9.2.2.1 ADC Trigger Source
Any GPIO pin can be configured to be an external trigger for the ADC using the GPIOADC Control
(GPIOADCCTL) register. If any GPIO is configured as a non-masked interrupt pin (the appropriate
bit of GPIOIM is set), and an interrupt for that port is generated, a trigger signal is sent to the ADC.
If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger,
an ADC conversion is initiated. See page 774.
Note that if the Port B GPIOADCCTL register is cleared, PB4 can still be used as an external trigger
for the ADC. This is a legacy mode which allows code written for previous devices to operate on
this microcontroller.
9.2.2.2 DMA Trigger Source
Any GPIOpin can be configured to be an external trigger for the DMA using the GPIODMAControl
(GPIODMACTL) register. If any GPIO is configured as a non-masked interrupt pin (the appropriate
bit of GPIOIM is set), an interrupt for that port is generated and an external trigger signal is sent to
the DMA. If the DMA is configured to start a transfer based on the GPIO signal, a transfer is
initiated.
9.2.3 Mode Control
The GPIO pins can be controlled by either software or hardware. Software control is the default for
most signals and corresponds to the GPIO mode, where the GPIODATA register is used to read
or write the corresponding pins. When hardware control is enabled via the GPIOAlternate Function
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Select (GPIOAFSEL) register (see page 612), the pin state is controlled by its alternate function
(that is, the peripheral).
Further pin muxing options are provided through the GPIOPort Control (GPIOPCTL) register which
selects one of several peripheral functions for each GPIO. For information on the configuration
options, refer to Table 21-5 on page 1176.
Note: If any pin is to be used as an ADC input, the appropriate bit in the GPIOAMSEL register
must be set to disable the analog isolation circuit.
9.2.4 Commit Control
9.2.5 Pad Control
The pad control registers allow software to configure the GPIO pads based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable
for each GPIO. If 5 V is applied to a GPIO configured as an open-drain output, the output voltage
will depend on the strength of your pull-up resistor. The GPIO pad is not electrically configured to
output 5 V.
9.2.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the
Advanced Peripheral Bus (APB), is backwards-compatible with previous devices. The other aperture,
the Advanced High-Performance Bus (AHB), offers the same register map but provides better
back-to-back access performance than the APB bus. These apertures are mutually exclusive. The
aperture enabled for a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL
register (see page 244). Note that GPIO can only be accessed through the AHB aperture.
To configure the GPIO pins of a particular port, follow these steps:
1. Enable the clock to the port by setting the appropriate bits in the RCGCGPIO register (see
page 322). In addition, the SCGCGPIO and DCGCGPIO registers can be programmed in the
same manner to enable clocking in Sleep and Deep-sleep modes.
2. Set the direction of the GPIO port pins by programming the GPIODIR register. A write of a '1'
indicates output and a write of a '0' indicates input.
April 10, 2013 598
3. Configure the GPIOAFSEL register to programeach bit as a GPIOor alternate pin. If an alternate
pin is chosen for a bit, then the PMCx field must be programmed in the GPIOPCTL register for
the specific peripheral required. There are also two registers, GPIOADCCTL and GPIODMACTL,
which can be used to program a GPIO pin as a ADC or DMA trigger, respectively.
4. Set the drive strength for each of the pins through the GPIODR2R, GPIODR4R, and GPIODR8R
registers.
5. Programeach pad in the port to have either pull-up, pull-down, or open drain functionality through
the GPIOPUR, GPIOPDR, GPIOODR register. Slew rate may also be programmed, if needed,
through the GPIOSLR register.
6. To enable GPIO pins as digital I/Os, set the appropriate DEN bit in the GPIODEN register. To
enable GPIO pins to their analog function (if available), set the GPIOAMSEL bit in the
GPIOAMSEL register.
7. Program the GPIOIS, GPIOIBE, GPIOBE, GPIOEV, and GPIOIM registers to configure the
type, event, and mask of the interrupts for each port.
8. Optionally, software can lock the configurations of the NMI and JTAG/SWD pins on the GPIO
port pins, by setting the LOCK bits in the GPIOLOCK register.
When the internal PORsignal is asserted and until otherwise configured, all GPIOpins are configured
to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0, except for
the pins shown in Table 9-1 on page 592. Table 9-3 on page 599 shows all possible configurations
of the GPIO pads and the control register settings required to achieve them. Table 9-4 on page 600
shows how a rising edge interrupt is configured for pin 2 of a GPIO port.
Table 9-3. GPIO Pad Configuration Examples
GPIO Register Bit Value
a
Configuration
SLR DR8R DR4R DR2R PDR PUR DEN ODR DIR AFSEL
X X X X ? ? 1 0 0 0 Digital Input (GPIO)
? ? ? ? ? ? 1 0 1 0 Digital Output (GPIO)
? ? ? ? X X 1 1 1 0 Open Drain Output
(GPIO)
? ? ? ? X X 1 1 X 1 Open Drain
Input/Output (I2CSDA)
X X X X ? ? 1 0 X 1 Digital Input (Timer
CCP)
X X X X ? ? 1 0 X 1 Digital Input (QEI)
? ? ? ? ? ? 1 0 X 1 Digital Output (PWM)
? ? ? ? ? ? 1 0 X 1 Digital Output (Timer
PWM)
? ? ? ? ? ? 1 0 X 1 Digital Input/Output
(SSI)
? ? ? ? ? ? 1 0 X 1 Digital Input/Output
(UART)
X X X X 0 0 0 0 0 0 Analog Input
(Comparator)
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Table 9-3. GPIO Pad Configuration Examples (continued)
GPIO Register Bit Value
a
Configuration
SLR DR8R DR4R DR2R PDR PUR DEN ODR DIR AFSEL
? ? ? ? ? ? 1 0 X 1 Digital Output
(Comparator)
a. X=Ignored (dont care bit)
?=Can be either 0 or 1, depending on the configuration
Table 9-4. GPIO Interrupt Configuration Example
Pin 2 Bit Value
a
Desired Interrupt
Event Trigger
Register
0 1 2 3 4 5 6 7
X X 0 X X X X X 0=edge
1=level
GPIOIS
X X 0 X X X X X 0=single edge
1=both edges
GPIOIBE
X X 1 X X X X X 0=Low level, or falling
edge
1=High level, or rising
edge
GPIOIEV
0 0 1 0 0 0 0 0 0=masked
1=not masked
GPIOIM
a. X=Ignored (dont care bit)
9.4 Register Map
Table 9-6 on page 601 lists the GPIO registers. Each GPIO port can be accessed through one of
two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible
with previous devices. The other aperture, the Advanced High-Performance Bus (AHB), offers the
same register map but provides better back-to-back access performance than the APB bus.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to unconnected bits has no effect, and reading unconnected bits returns
no meaningful data. See Signal Description on page 591 for the GPIOs included on
this device.
The offset listed is a hexadecimal increment to the register's address, relative to that GPIO port's
base address:
GPIO Port A (APB): 0x4000.4000
GPIO Port A (AHB): 0x4005.8000
GPIO Port B (APB): 0x4000.5000
GPIO Port B (AHB): 0x4005.9000
GPIO Port C (APB): 0x4000.6000
GPIO Port C (AHB): 0x4005.A000
GPIO Port D (APB): 0x4000.7000
GPIO Port D (AHB): 0x4005.B000
GPIO Port E (APB): 0x4002.4000
GPIO Port E (AHB): 0x4005.C000
GPIO Port F (APB): 0x4002.5000
April 10, 2013 600
GPIO Port F (AHB): 0x4005.D000
GPIO Port G (APB): 0x4002.6000
GPIO Port G (AHB): 0x4005.E000
Note that each GPIO module clock must be enabled before the registers can be programmed (see
page 322). There must be a delay of 3 systemclocks after the GPIOmodule clock is enabled before
any GPIO module registers are accessed.
0x1 0 0 0 0 UART0 PA[1:0]
0x2 0 0 0 0 SSI0 PA[5:2]
0x3 0 0 0 0 I
2
C0 PB[3:2]
0x1 1 0 1 1 JTAG/SWD PC[3:0]
The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the
NMI pin and the four JTAG/SWD pins (PD7, PF0, and PC[3:0]). These six pins are the only GPIOs
that are protected by the GPIOCR register. Because of this, the register type for GPIO Port D7,
GPIO Port F0, and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCRregister is 0x0000.00FF for all GPIOpins, with the exception
of the NMI pin and the four JTAG/SWD pins (PD7, PF0, and PC[3:0]). To ensure that the JTAG
port is not accidentally programmed as GPIO pins, the PC[3:0] pins default to non-committable.
Similarly, to ensure that the NMI pin is not accidentally programmed as a GPIO pin, the PD7 and
PF0 pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO
Port C is 0x0000.00F0, for GPIO Port D is 0x0000.007F, and for GPIO Port F is 0x0000.00FE.
Table 9-6. GPIO Register Map
See
page
603 GPIO Data 0x0000.0000 R/W GPIODATA 0x000
604 GPIO Direction 0x0000.0000 R/W GPIODIR 0x400
605 GPIO Interrupt Sense 0x0000.0000 R/W GPIOIS 0x404
606 GPIO Interrupt Both Edges 0x0000.0000 R/W GPIOIBE 0x408
607 GPIO Interrupt Event 0x0000.0000 R/W GPIOIEV 0x40C
608 GPIO Interrupt Mask 0x0000.0000 R/W GPIOIM 0x410
609 GPIO Raw Interrupt Status 0x0000.0000 RO GPIORIS 0x414
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Table 9-6. GPIO Register Map (continued)
See
page
610 GPIO Masked Interrupt Status 0x0000.0000 RO GPIOMIS 0x418
611 GPIO Interrupt Clear 0x0000.0000 W1C GPIOICR 0x41C
612 GPIO Alternate Function Select - R/W GPIOAFSEL 0x420
614 GPIO 2-mA Drive Select 0x0000.00FF R/W GPIODR2R 0x500
615 GPIO 4-mA Drive Select 0x0000.0000 R/W GPIODR4R 0x504
616 GPIO 8-mA Drive Select 0x0000.0000 R/W GPIODR8R 0x508
617 GPIO Open Drain Select 0x0000.0000 R/W GPIOODR 0x50C
618 GPIO Pull-Up Select - R/W GPIOPUR 0x510
620 GPIO Pull-Down Select 0x0000.0000 R/W GPIOPDR 0x514
622 GPIO Slew Rate Control Select 0x0000.0000 R/W GPIOSLR 0x518
623 GPIO Digital Enable - R/W GPIODEN 0x51C
625 GPIO Lock 0x0000.0001 R/W GPIOLOCK 0x520
626 GPIO Commit - - GPIOCR 0x524
628 GPIO Analog Mode Select 0x0000.0000 R/W GPIOAMSEL 0x528
629 GPIO Port Control - R/W GPIOPCTL 0x52C
631 GPIO ADC Control 0x0000.0000 R/W GPIOADCCTL 0x530
632 GPIO DMA Control 0x0000.0000 R/W GPIODMACTL 0x534
633 GPIO Peripheral Identification 4 0x0000.0000 RO GPIOPeriphID4 0xFD0
636 GPIO Peripheral Identification 7 0x0000.0000 RO GPIOPeriphID7 0xFDC
637 GPIO Peripheral Identification 0 0x0000.0061 RO GPIOPeriphID0 0xFE0
640 GPIO Peripheral Identification 3 0x0000.0001 RO GPIOPeriphID3 0xFEC
641 GPIO PrimeCell Identification 0 0x0000.000D RO GPIOPCellID0 0xFF0
642 GPIO PrimeCell Identification 1 0x0000.00F0 RO GPIOPCellID1 0xFF4
643 GPIO PrimeCell Identification 2 0x0000.0005 RO GPIOPCellID2 0xFF8
644 GPIO PrimeCell Identification 3 0x0000.00B1 RO GPIOPCellID3 0xFFC
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
April 10, 2013 602
Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 604).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be set. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are set in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are clear in the address mask cause
the corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and written to the registers are
masked by the eight address lines [9:2]. Reads from this register return
its current state. Writes to this register only affect bits that are not masked
by ADDR[9:2] and are configured as outputs. See Data Register
Operation on page 596 for examples of reads and writes.
0x00 R/W DATA 7:0
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Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures
the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be
an input. All bits are cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
Offset 0x400
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIR reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIO Data Direction
Description Value
Corresponding pin is an input. 0
Corresponding pins is an output. 1
0x00 R/W DIR 7:0
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures
the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect
edges. All bits are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
Offset 0x404
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIO Interrupt Sense
Description Value
The edge on the corresponding pin is detected (edge-sensitive). 0
The level on the corresponding pin is detected (level-sensitive). 1
0x00 R/W IS 7:0
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the
GPIO Interrupt Sense (GPIOIS) register (see page 605) is set to detect edges, setting a bit in the
GPIOIBE register configures the corresponding pin to detect both rising and falling edges, regardless
of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 607). Clearing
a bit configures the pin to be controlled by the GPIOIEV register. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
Offset 0x408
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IBE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIO Interrupt Both Edges
Description Value
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 607).
0
Both edges on the corresponding pin trigger an interrupt. 1
0x00 R/W IBE 7:0
April 10, 2013 606
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures
the corresponding pin to detect rising edges or high levels, depending on the corresponding bit
value in the GPIO Interrupt Sense (GPIOIS) register (see page 605). Clearing a bit configures the
pin to detect falling edges or low levels, depending on the corresponding bit value in the GPIOIS
register. All bits are cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
Offset 0x40C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IEV reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIO Interrupt Event
Description Value
A falling edge or a Low level on the corresponding pin triggers
an interrupt.
0
A rising edge or a High level on the corresponding pin triggers
an interrupt.
1
0x00 R/W IEV 7:0
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Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows
interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the
combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being
sent to the interrupt controller. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
Offset 0x410
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IME reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
GPIO Interrupt Mask Enable
Description Value
The interrupt from the corresponding pin is masked. 0
The interrupt from the corresponding pin is sent to the interrupt
controller.
1
0x00 R/W IME 7:0
April 10, 2013 608
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the rawinterrupt status register. A bit in this register is set when an interrupt
condition occurs on the corresponding GPIO pin. If the corresponding bit in the GPIO Interrupt
Mask (GPIOIM) register (see page 608) is set, the interrupt is sent to the interrupt controller. Bits
read as zero indicate that corresponding input pins have not initiated an interrupt. For a GPIO
level-detect interrupt, the interrupt signal generating the interrupt must be held until serviced. Once
the input signal deasserts from the interrupt generating logical sense, the corresponding RIS bit in
the GPIORIS register clears. For a GPIO edge-detect interrupt, the RIS bit in the GPIORIS register
is cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register.
The corresponding GPIOMIS bit reflects the masked value of the RIS bit.
GPIO Raw Interrupt Status (GPIORIS)
Offset 0x414
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
GPIO Interrupt Raw Status
Description Value
An interrupt condition has not occurred on the corresponding
pin.
0
An interrupt condition has occurred on the corresponding pin. 1
For edge-detect interrupts, this bit is cleared by writing a 1 to the
corresponding bit in the GPIOICR register.
For a GPIO level-detect interrupt, the bit is cleared when the level is
deasserted.
0x00 RO RIS 7:0
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Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the
corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either
no interrupt has been generated, or the interrupt is masked.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
Offset 0x418
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
GPIO Masked Interrupt Status
Description Value
An interrupt condition on the corresponding pin is masked or
has not occurred.
0
An interrupt condition on the corresponding pin has triggered
an interrupt to the interrupt controller.
1
For edge-detect interrupts, this bit is cleared by writing a 1 to the
corresponding bit in the GPIOICR register.
For a GPIO level-detect interrupt, the bit is cleared when the level is
deasserted.
0x00 RO MIS 7:0
April 10, 2013 610
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. For edge-detect interrupts, writing a 1 to the
IC bit in the GPIOICR register clears the corresponding bit in the GPIORIS and GPIOMIS registers.
If the interrupt is a level-detect, the IC bit in this register has no effect. In addition, writing a 0 to any
of the bits in the GPIOICR register has no effect.
GPIO Interrupt Clear (GPIOICR)
Offset 0x41C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IC reserved
W1C W1C W1C W1C W1C W1C W1C W1C RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:8
GPIO Interrupt Clear
Description Value
The corresponding interrupt is unaffected. 0
The corresponding interrupt is cleared. 1
0x00 W1C IC 7:0
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Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. If a bit is clear, the pin is used as a
GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the
corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral
functions are multiplexed on each GPIO. The GPIO Port Control (GPIOPCTL) register is used to
select one of the possible functions. Table 21-5 on page 1176 details which functions are muxed on
each GPIO pin. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed
in the table below.
0x1 0 0 0 0 UART0 PA[1:0]
0x2 0 0 0 0 SSI0 PA[5:2]
0x3 0 0 0 0 I
2
C0 PB[3:2]
0x1 1 0 1 1 JTAG/SWD PC[3:0]
When using the I
2
C module, in addition to setting the GPIOAFSEL register bits for the I
2
C clock
and data pins, the data pins should be set to open drain using the GPIO Open Drain Select
(GPIOODR) register (see examples in Initialization and Configuration on page 598).
April 10, 2013 612
GPIO Alternate Function Select (GPIOAFSEL)
Offset 0x420
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
AFSEL reserved
- - - - - - - - 0 0 0 0 0 0 0 0 Reset
GPIO Alternate Function Select
Description Value
The associated pin functions as a GPIO and is controlled by
the GPIO registers.
0
The associated pin functions as a peripheral signal and is
controlled by the alternate hardware function.
The reset value for this register is 0x0000.0000 for GPIO ports
that are not listed in Table 9-1 on page 592.
1
- R/W AFSEL 7:0
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Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be
individually configured without affecting the other pads. When setting the DRV2 bit for a GPIOsignal,
the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are
automatically cleared by hardware. By default, all GPIO pins have 2-mA drive.
GPIO 2-mA Drive Select (GPIODR2R)
Offset 0x500
Type R/W, reset 0x0000.00FF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DRV2 reserved
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Reset
Output Pad 2-mA Drive Enable
Description Value
The drive for the corresponding GPIO pin is controlled by the
GPIODR4R or GPIODR8R register.
0
The corresponding GPIO pin has 2-mA drive. 1
Setting a bit in either the GPIODR4 register or the GPIODR8 register
clears the corresponding 2-mA enable bit. The change is effective on
the second clock cycle after the write if accessing GPIO via the APB
memory aperture. If using AHB access, the change is effective on the
next clock cycle.
0xFF R/W DRV2 7:0
April 10, 2013 614
automatically cleared by hardware.
Offset 0x504
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DRV4 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Value
0
next clock cycle.
0x00 R/W DRV4 7:0
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automatically cleared by hardware. The 8-mA setting is also used for high-current operation.
Note: There is no configuration difference between 8-mAand high-current operation. The additional
current capacity results from a shift in the V
OH
/V
OL
levels. See Recommended Operating
Conditions on page 1185 for further information.
Offset 0x508
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DRV8 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Value
0
next clock cycle.
0x00 R/W DRV8 7:0
April 10, 2013 616
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled, the
corresponding bit should also be set in the GPIODigital Enable (GPIODEN) register (see page 623).
Corresponding bits in the drive strength and slew rate control registers (GPIODR2R, GPIODR4R,
GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts
as an input if the corresponding bit in the GPIODIRregister is cleared. If open drain is selected while
the GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has
no effect until the GPIO is changed to an output.
When using the I
2
Cmodule, in addition to configuring the data pin to open drain, the GPIOAlternate
Function Select (GPIOAFSEL) register bits for the I
2
C clock and data pins should be set (see
examples in Initialization and Configuration on page 598).
GPIO Open Drain Select (GPIOODR)
Offset 0x50C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ODE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Output Pad Open Drain Enable
Description Value
The corresponding pin is not configured as open drain. 0
The corresponding pin is configured as open drain. 1
0x00 R/W ODE 7:0
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Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on
the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIOPull-Down Select (GPIOPDR) register (see page 620). Write access
to this register is protected with the GPIOCRregister. Bits in GPIOCRthat are cleared prevent writes
to the equivalent bit in this register.
0x1 0 0 0 0 UART0 PA[1:0]
0x2 0 0 0 0 SSI0 PA[5:2]
0x3 0 0 0 0 I
2
C0 PB[3:2]
0x1 1 0 1 1 JTAG/SWD PC[3:0]
Note: The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the GPIO pins that
can be used as the four JTAG/SWDpins (PC[3:0])and the NMI pin (PD7 and PF0). Writes
to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see
page 612), GPIO Pull Up Select (GPIOPUR) register (see page 618), GPIO Pull-Down
Select (GPIOPDR) register (see page 620), and GPIODigital Enable (GPIODEN) register
(see page 623) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 625) has been unlocked and the appropriate bits of the GPIOCommit (GPIOCR)
register (see page 626) have been set.
April 10, 2013 618
GPIO Pull-Up Select (GPIOPUR)
Offset 0x510
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PUE reserved
- - - - - - - - 0 0 0 0 0 0 0 0 Reset
Pad Weak Pull-Up Enable
Description Value
The corresponding pin's weak pull-up resistor is disabled. 0
The corresponding pin's weak pull-up resistor is enabled. 1
Setting a bit in the GPIOPDR register clears the corresponding bit in
the GPIOPUR register. The change is effective on the second clock
cycle after the write if accessing GPIO via the APB memory aperture.
If using AHB access, the change is effective on the next clock cycle.
The reset value for this register is 0x0000.0000 for GPIO ports that are
not listed in Table 9-1 on page 592.
- R/W PUE 7:0
619 April 10, 2013
Tiva
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set, a weak pull-down resistor
on the corresponding GPIO signal is enabled. Setting a bit in GPIOPDR automatically clears the
corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 618).
0x1 0 0 0 0 UART0 PA[1:0]
0x2 0 0 0 0 SSI0 PA[5:2]
0x3 0 0 0 0 I
2
C0 PB[3:2]
0x1 1 0 1 1 JTAG/SWD PC[3:0]
April 10, 2013 620
GPIO Pull-Down Select (GPIOPDR)
Offset 0x514
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PDE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Pad Weak Pull-Down Enable
Description Value
The corresponding pin's weak pull-down resistor is disabled. 0
The corresponding pin's weak pull-down resistor is enabled. 1
Setting a bit in the GPIOPUR register clears the corresponding bit in
the GPIOPDR register. The change is effective on the second clock
cycle after the write if accessing GPIO via the APB memory aperture.
If using AHB access, the change is effective on the next clock cycle.
0x00 R/W PDE 7:0
621 April 10, 2013
Tiva
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option. The selection of drive strength is done through the GPIO8-mA
Drive Select (GPIODR8R) register.
GPIO Slew Rate Control Select (GPIOSLR)
Offset 0x518
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SRL reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Slew Rate Limit Enable (8-mA drive only)
Description Value
Slew rate control is disabled for the corresponding pin. 0
Slew rate control is enabled for the corresponding pin. 1
0x00 R/W SRL 7:0
April 10, 2013 622
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note: Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed
below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do
not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To
use the pin as a digital input or output (either GPIOor alternate function), the corresponding GPIODEN
bit must be set.
0x1 0 0 0 0 UART0 PA[1:0]
0x2 0 0 0 0 SSI0 PA[5:2]
0x3 0 0 0 0 I
2
C0 PB[3:2]
0x1 1 0 1 1 JTAG/SWD PC[3:0]
623 April 10, 2013
Tiva
GPIO Digital Enable (GPIODEN)
Offset 0x51C
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DEN reserved
- - - - - - - - 0 0 0 0 0 0 0 0 Reset
Digital Enable
Description Value
The digital functions for the corresponding pin are disabled. 0
The digital functions for the corresponding pin are enabled.
The reset value for this register is 0x0000.0000 for GPIO ports
that are not listed in Table 9-1 on page 592.
1
- R/W DEN 7:0
April 10, 2013 624
Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 626). Writing
0x4C4F.434B to the GPIOLOCK register unlocks the GPIOCR register. Writing any other value to
the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the
lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCKregister returns 0x0000.0001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x0000.0000.
GPIO Lock (GPIOLOCK)
Offset 0x520
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LOCK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LOCK
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIO Lock
Awrite of the value 0x4C4F.434Bunlocks the GPIOCommit (GPIOCR)
register for write access.A write of any other value or a write to the
GPIOCR register reapplies the lock, preventing any register updates.
A read of this register returns the following values:
Description Value
The GPIOCR register is locked and may not be modified. 0x1
The GPIOCR register is unlocked and may be modified. 0x0
0x0000.0001 R/W LOCK 31:0
625 April 10, 2013
Tiva
Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN registers are committed when a
write to these registers is performed. If a bit in the GPIOCRregister is cleared, the data being written
to the corresponding bit in the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers cannot
be committed and retains its previous value. If a bit in the GPIOCR register is set, the data being
written to the corresponding bit of the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers
is committed to the register and reflects the new value.
The contents of the GPIOCR register can only be modified if the status in the GPIOLOCK register
is unlocked. Writes to the GPIOCR register are ignored if the status in the GPIOLOCK register is
locked.
Important: This register is designed to prevent accidental programming of the registers that control
connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the
GPIOCR register to 0 for PD7, PF0, and PC[3:0], the NMI and JTAG/SWD debug port
can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK,
GPIOCR, and the corresponding registers.
Because this protection is currently only implemented on the NMI and JTAG/SWD pins
on PD7, PF0, and PC[3:0], all of the other bits in the GPIOCR registers cannot be
written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to
commit new values to the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN register
bits of these other pins.
GPIO Commit (GPIOCR)
Offset 0x524
Type -, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CR reserved
- - - - - - - - RO RO RO RO RO RO RO RO Type
- - - - - - - - 0 0 0 0 0 0 0 0 Reset
April 10, 2013 626
GPIO Commit
Description Value
The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or
GPIODEN bits cannot be written.
0
The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or
GPIODEN bits can be written.
1
Note: The default register type for the GPIOCR register is RO for
all GPIO pins with the exception of the NMI pin and the four
JTAG/SWD pins (PD7, PF0, and PC[3:0]). These six pins
are the only GPIOs that are protected by the GPIOCRregister.
Because of this, the register type for GPIO Port D7, GPIO
Port F0, and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the NMI
pin and the four JTAG/SWD pins (PD7, PF0, and PC[3:0]).
To ensure that the JTAG port is not accidentally programmed
as GPIO pins, the PC[3:0] pins default to non-committable.
Similarly, to ensure that the NMI pin is not accidentally
programmed as a GPIO pin, the PD7 and PF0 pins default to
non-committable. Because of this, the default reset value of
GPIOCR for GPIO Port C is 0x0000.00F0, for GPIO Port D
is 0x0000.007F, and for GPIO Port F is 0x0000.00FE.
- - CR 7:0
627 April 10, 2013
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Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528
Important: This register is only valid for ports and pins that can be used as ADC AINx inputs.
If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be
set to disable the analog isolation circuit.
The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/Opad. Because
the GPIOs may be driven by a 5-V source and affect analog operation, analog circuitry requires
isolation from the pins when they are not used in their analog function.
Each bit of this register controls the isolation circuitry for the corresponding GPIO signal. For
information on which GPIO pins can be used for ADC functions, refer to Table 21-5 on page 1176.
GPIO Analog Mode Select (GPIOAMSEL)
Offset 0x528
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GPIOAMSEL reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIO Analog Mode Select
Description Value
The analog function of the pin is disabled, the isolation is
enabled, and the pin is capable of digital functions as specified
by the other GPIO configuration registers.
0
The analog function of the pin is enabled, the isolation is
disabled, and the pin is capable of analog functions.
1
Note: This register and bits are only valid for GPIO signals that
share analog function through a unified I/O pad.
The reset state of this register is 0 for all signals.
0x0 R/W GPIOAMSEL 3:0
April 10, 2013 628
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C
The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific
peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the
GPIOAFSEL register are cleared on reset, therefore most GPIO pins are configured as GPIOs by
default. When a bit is set in the GPIOAFSEL register, the corresponding GPIO signal is controlled
by an associated peripheral. The GPIOPCTL register selects one out of a set of peripheral functions
for each GPIO, providing additional flexibility in signal definition. For information on the defined
encodings for the bit fields in this register, refer to Table 21-5 on page 1176. The reset value for this
register is 0x0000.0000 for GPIO ports that are not listed in the table below.
Note: If the same signal is assigned to two different GPIOport pins configured as inputs, the signal
is assigned to the port with the lowest letter and the assignment to the higher letter port is
ignored. If the same signal is assigned to two different GPIOport pins configured as outputs,
the signal will output to both pins.
0x1 0 0 0 0 UART0 PA[1:0]
0x2 0 0 0 0 SSI0 PA[5:2]
0x3 0 0 0 0 I
2
C0 PB[3:2]
0x1 1 0 1 1 JTAG/SWD PC[3:0]
629 April 10, 2013
Tiva
GPIO Port Control (GPIOPCTL)
Offset 0x52C
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PMC4 PMC5 PMC6 PMC7
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PMC0 PMC1 PMC2 PMC3
- - - - - - - - - - - - - - - - Reset
Port Mux Control 7
This field controls the configuration for GPIO pin 7.
- R/W PMC7 31:28
Port Mux Control 6
- R/W PMC6 27:24
Port Mux Control 5
- R/W PMC5 23:20
Port Mux Control 4
- R/W PMC4 19:16
Port Mux Control 3
- R/W PMC3 15:12
Port Mux Control 2
- R/W PMC2 11:8
Port Mux Control 1
- R/W PMC1 7:4
Port Mux Control 0
- R/W PMC0 3:0
April 10, 2013 630
Register 23: GPIO ADC Control (GPIOADCCTL), offset 0x530
This register is used to configure a GPIO pin as a source for the ADC trigger.
GPIO ADC Control (GPIOADCCTL)
Offset 0x530
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADCEN reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ADC Trigger Enable
Description Value
The corresponding pin is not used to trigger the ADC. 0
The corresponding pin is used to trigger the ADC. 1
0x00 R/W ADCEN 7:0
631 April 10, 2013
Tiva
Register 24: GPIO DMA Control (GPIODMACTL), offset 0x534
This register is used to configure a GPIO pin as a source for the DMA trigger.
GPIO DMA Control (GPIODMACTL)
Offset 0x534
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DMAEN reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DMA Trigger Enable
Description Value
The corresponding pin is not used to trigger the DMA. 0
The corresponding pin is used to trigger the DMA. 1
0x00 R/W DMAEN 7:0
April 10, 2013 632
Register 25: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
Offset 0xFD0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID4 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIO Peripheral ID Register [7:0] 0x00 RO PID4 7:0
633 April 10, 2013
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Offset 0xFD4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID5 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
April 10, 2013 634
Offset 0xFD8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID6 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
635 April 10, 2013
Tiva
Register 28: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
Offset 0xFDC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
April 10, 2013 636
Register 29: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
Offset 0xFE0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID0 reserved
1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Reset
GPIO Peripheral ID Register [7:0]
0x61 RO PID0 7:0
637 April 10, 2013
Tiva
Offset 0xFE4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID1 7:0
April 10, 2013 638
Offset 0xFE8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID2 reserved
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Reset
0x18 RO PID2 7:0
639 April 10, 2013
Tiva
Register 32: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
Offset 0xFEC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID3 reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x01 RO PID3 7:0
April 10, 2013 640
Register 33: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
Offset 0xFF0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID0 reserved
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIO PrimeCell ID Register [7:0]
0x0D RO CID0 7:0
641 April 10, 2013
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Offset 0xFF4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID1 reserved
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Reset
0xF0 RO CID1 7:0
April 10, 2013 642
Offset 0xFF8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID2 reserved
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x05 RO CID2 7:0
643 April 10, 2013
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Register 36: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
Offset 0xFFC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID3 reserved
1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset
0xB1 RO CID3 7:0
April 10, 2013 644
10 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The TM4C123AH6PMGeneral-Purpose Timer Module (GPTM) contains six 16/32-bit GPTMblocks
and six 32/64-bit Wide GPTMblocks. Each 16/32-bit GPTMblock provides two 16-bit timers/counters
(referred to as Timer A and Timer B) that can be configured to operate independently as timers or
event counters, or concatenated to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Each 32/64-bit Wide GPTM block provides 32-bit timers for Timer A and Timer B that can be
concatenated to operate as a 64-bit timer. Timers can also be used to trigger DMA transfers.
In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger
signals from all of the general-purpose timers are ORed together before reaching the ADC module,
so only one timer should be used to trigger ADC events.
The GPT Module is one timing resource available on the Tiva C Series microcontrollers. Other
timer resources include the System Timer (SysTick) (see 112) and the PWM timer in the PWM
modules (see PWM Timer on page 1057).
The General-Purpose Timer Module (GPTM) contains six 16/32-bit GPTM blocks and six 32/64-bit
Wide GPTM blocks with the following functional options:
16-bit general-purpose timer with an 8-bit prescaler
16-bit input-edge count- or time-capture modes with an 8-bit prescaler
16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the
PWM signal
32-bit general-purpose timer with a 16-bit prescaler
32-bit input-edge count- or time-capture modes with a16-bit prescaler
32-bit PWM mode with a 16-bit prescaler and software-programmable output inversion of the
PWM signal
Count up or down
645 April 10, 2013
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Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
Timer synchronization allows selected timers to start counting on the same clock cycle
ADC event trigger
User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding
RTC mode)
Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine
Dedicated channel for each timer
Burst request generated on timer interrupt
10.1 Block Diagram
In the block diagram, the specific Capture Compare PWM (CCP) pins available depend on the
TM4C123AH6PM device. See Table 10-1 on page 647 for the available CCP pins and their timer
assignments.
Figure 10-1. GPTM Module Block Diagram
Clock / Edge
Detect
RTC Divider
Clock / Edge
Detect
32 KHz or
Even CCP Pin
Odd CCP Pin
TA Comparator
TB Comparator
GPTMTBR
GPTMTAR
Timer A
Interrupt
Timer B
Interrupt
System
Clock
En
En
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
GPTMTAV
GPTMTBV
Timer A
Free-Running
Value
Timer B
Free-Running
Value
Timer A Control
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
Timer B Control
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
GPTMTAPS
GPTMTBPS
GPTMTAPV
GPTMTBPV
RTC Predivider
GPTMRTCPD
0x0000 (Down Counter Modes, 16-/32-bit)
0xFFFF (Up Counter Modes, 16-/32-bit)
0x0000.0000 (Down Counter Modes, 32-/64-bit)
0xFFFF.FFFF (Up Counter Modes, 32-/64-bit)
0xFFFF.FFFF (Up Counter Modes, 32-/64-bit)
0x0000.0000 (Down Counter Modes, 32-/64-bit)
0xFFFF (Up Counter Modes, 16-/32-bit)
0x0000 (Down Counter Modes, 16-/32-bit)
GPTMSYNC
GPTMPP
April 10, 2013 646
General-Purpose Timers
Table 10-1. Available CCP Pins
CCP1 Pin CCP0 Pin Up/Down Counter Timer
- T0CCP0 Timer A
16/32-Bit Timer 0
T0CCP1 - Timer B
- T1CCP0 Timer A
16/32-Bit Timer 1
T1CCP1 - Timer B
- T2CCP0 Timer A
16/32-Bit Timer 2
T2CCP1 - Timer B
- T3CCP0 Timer A
16/32-Bit Timer 3
T3CCP1 - Timer B
- T4CCP0 Timer A
16/32-Bit Timer 4
T4CCP1 - Timer B
- T5CCP0 Timer A
16/32-Bit Timer 5
T5CCP1 - Timer B
- WT0CCP0 Timer A
32/64-Bit Wide Timer 0
WT0CCP1 - Timer B
- WT1CCP0 Timer A
WT1CCP1 - Timer B
- WT2CCP0 Timer A
WT2CCP1 - Timer B
- WT3CCP0 Timer A
WT3CCP1 - Timer B
- WT4CCP0 Timer A
WT4CCP1 - Timer B
- WT5CCP0 Timer A
WT5CCP1 - Timer B
The following table lists the external signals of the GP Timer module and describes the function of
each. The GP Timer signals are alternate functions for some GPIO signals and default to be GPIO
signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible
GPIO pin placements for these GP Timer signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 612) should be set to choose the GPTimer function. The number
in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port
Control (GPIOPCTL) register (page 629) to assign the GP Timer signal to the specified GPIO port
pin. For more information on configuring GPIOs, see General-Purpose Input/Outputs
Table 10-2. General-Purpose Timers Signals (64LQFP)
a
Assignment
Pin Number Pin Name
16/32-Bit Timer 0 Capture/Compare/PWM 0. TTL I/O PB6 (7)
PF0 (7)
1
28
T0CCP0
PF1 (7)
4
29
T0CCP1
647 April 10, 2013
Tiva
Table 10-2. General-Purpose Timers Signals (64LQFP) (continued)
a
Assignment
Pin Number Pin Name
16/32-Bit Timer 1 Capture/Compare/PWM 0. TTL I/O PF2 (7)
PB4 (7)
30
58
T1CCP0
PB5 (7)
31
57
T1CCP1
PB0 (7)
5
45
T2CCP0
16/32-Bit Timer 2 Capture/Compare/PWM 1. TTL I/O PB1 (7) 46 T2CCP1
16/32-Bit Timer 4 Capture/Compare/PWM 0. TTL I/O PG0 (7)
PC0 (7)
37
52
T4CCP0
PC1 (7)
36
51
T4CCP1
PC2 (7)
35
50
T5CCP0
PC3 (7)
34
49
T5CCP1
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0. TTL I/O PC4 (7)
PG4 (7)
16
33
WT0CCP0
PG5 (7)
15
32
WT0CCP1
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0. TTL I/O PC6 (7) 14 WT1CCP0
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0. TTL I/O PD0 (7) 61 WT2CCP0
The main components of each GPTM block are two free-running up/down counters (referred to as
Timer A and Timer B), two prescaler registers, two match registers, two prescaler match registers,
two shadow registers, and two load/initialization registers and their associated control functions.
The exact functionality of each GPTM is controlled by software and configured through the register
interface. Timer A and Timer B can be used individually, in which case they have a 16-bit counting
range for the 16/32-bit GPTM blocks and a 32-bit counting range for 32/64-bit Wide GPTM blocks.
In addition, Timer A and Timer B can be concatenated to provide a 32-bit counting range for the
16/32-bit GPTM blocks and a 64-bit counting range for the 32/64-bit Wide GPTM blocks. Note that
the prescaler can only be used when the timers are used individually.
The available modes for each GPTM block are shown in Table 10-3 on page 649. Note that when
counting down in one-shot or periodic modes, the prescaler acts as a true prescaler and contains
April 10, 2013 648
the least-significant bits of the count. When counting up in one-shot or periodic modes, the prescaler
acts as a timer extension and holds the most-significant bits of the count. In input edge count, input
edge time and PWM mode, the prescaler always acts as a timer extension, regardless of the count
direction.
Table 10-3. General-Purpose Timer Capabilities
Prescaler Behavior
(Count Direction)
Prescaler Size
a
Counter Size
Count
Direction
Timer Use Mode
32/64-bit
Wide GPTM
16/32-bit
GPTM
32/64-bit
Wide GPTM
16/32-bit
GPTM
Timer Extension (Up),
Prescaler (Down)
16-bit 8-bit 32-bit 16-bit Up or Down Individual
One-shot
N/A - - 64-bit 32-bit Up or Down Concatenated
Timer Extension (Up),
Prescaler (Down)
16-bit 8-bit 32-bit 16-bit Up or Down Individual
Periodic
N/A - - 64-bit 32-bit Up or Down Concatenated
N/A - - 64-bit 32-bit Up Concatenated RTC
Timer Extension
(Both)
16-bit 8-bit 32-bit 16-bit Up or Down Individual Edge
Count
Timer Extension
(Both)
16-bit 8-bit 32-bit 16-bit Up or Down Individual Edge
Time
Timer Extension 16-bit 8-bit 32-bit 16-bit Down Individual PWM
a. The prescaler is only available when the timers are used individually
Software configures the GPTMusing the GPTMConfiguration (GPTMCFG) register (see page 668),
the GPTM Timer A Mode (GPTMTAMR) register (see page 670), and the GPTM Timer B Mode
(GPTMTBMR) register (see page 674). When in one of the concatentated modes, Timer A and Timer
B can only operate in one mode. However, when configured in an individual mode, Timer A and
Timer B can be independently configured in any combination of the individual modes.
10.3.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all
1s, along with their corresponding registers:
Load Registers:
GPTM Timer A Interval Load (GPTMTAILR) register (see page 697)
GPTM Timer B Interval Load (GPTMTBILR) register (see page 698)
Shadow Registers:
GPTM Timer A Value (GPTMTAV) register (see page 707)
GPTM Timer B Value (GPTMTBV) register (see page 708)
The following prescale counters are initialized to all 0s:
GPTM Timer A Prescale (GPTMTAPR) register (see page 701)
GPTM Timer B Prescale (GPTMTBPR) register (see page 702)
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GPTM Timer A Prescale Snapshot (GPTMTAPS) register (see page 710)
GPTM Timer B Prescale Snapshot (GPTMTBPS) register (see page 711)
GPTM Timer A Prescale Value (GPTMTAPV) register (see page 712)
GPTM Timer B Prescale Value (GPTMTBPV) register (see page 713)
10.3.2 Timer Modes
This section describes the operation of the various timer modes. When using Timer A and Timer B
in concatenated mode, only the Timer A control and status bits must be used; there is no need to
use Timer B control and status bits. The GPTMis placed into individual/split mode by writing a value
of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 668). In the following sections,
the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer
B function. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count
mode is the value in the GPTMTimer n Interval Load (GPTMTnILR) and the optional GPTMTimer
n Prescale (GPTMTnPR) registers.
10.3.2.1 One-Shot/Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of
the GPTM Timer n Mode (GPTMTnMR) register (see page 670). The timer is configured to count
up or down using the TnCDIR bit in the GPTMTnMR register.
When software sets the TnEN bit in the GPTM Control (GPTMCTL) register (see page 678), the
timer begins counting up from 0x0 or down from its preloaded value. Alternatively, if the TnWOT bit
is set in the GPTMTnMR register, once the TnEN bit is set, the timer waits for a trigger to begin
counting (see Wait-for-Trigger Mode on page 659). Table 10-4 on page 650 shows the values that
are loaded into the timer registers when the timer is enabled.
Table 10-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes
Count Up Mode Count Down Mode Register
0x0 GPTMTnILR GPTMTnR
0x0 GPTMTnILR GPTMTnV
0x0 in individual mode; not available in
concatenated mode
GPTMTnPR in individual mode; not available in
concatenated mode
GPTMTnPS
0x0 in individual mode; not available in
concatenated mode
GPTMTnPR in individual mode; not available in
concatenated mode
GPTMTnPV
When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start
value from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is
counting up and it reaches the timeout event (the value in the GPTMTnILR and the optional
GPTMTnPR registers), the timer reloads with 0x0. If configured to be a one-shot timer, the timer
stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer,
the timer starts counting again on the next cycle.
In periodic, snap-shot mode (TnMR field is 0x2 and the TnSNAPS bit is set in the GPTMTnMR
register), the value of the timer at the time-out event is loaded into the GPTMTnR register and the
value of the prescaler is loaded into the GPTMTnPS register. The free-running counter value is
shown in the GPTMTnV register and the free-running prescaler value is shown in the GPTMTnPV
register. In this manner, software can determine the time elapsed from the interrupt assertion to the
ISRentry by examining the snapshot values and the current value of the free-running timer. Snapshot
mode is not available when the timer is configured in one-shot mode.
April 10, 2013 650
In addition to reloading the count value, the GPTMgenerates interrupts and triggers when it reaches
the time-out event. The GPTMsets the TnTORIS bit in the GPTMRawInterrupt Status (GPTMRIS)
register (see page 689), and holds it until it is cleared by writing the GPTMInterrupt Clear (GPTMICR)
register (see page 695). If the time-out interrupt is enabled in the GPTMInterrupt Mask (GPTMIMR)
register (see page 686), the GPTMalso sets the TnTOMIS bit in the GPTMMasked Interrupt Status
(GPTMMIS) register (see page 692). The time-out interrupt can be disabled entirely by setting the
TACINTD bit in the GPTMTimer n Mode (GPTMTnMR) register. In this case, the TnTORIS bit does
not even set in the GPTMRIS register.
By setting the TnMIE bit in the GPTMTnMR register, an interrupt condition can also be generated
when the Timer value equals the value loaded into the GPTM Timer n Match (GPTMTnMATCHR)
and GPTM Timer n Prescale Match (GPTMTnPMR) registers. This interrupt has the same status,
masking, and clearing functions as the time-out interrupt, but uses the match interrupt bits instead
(for example, the rawinterrupt status is monitored via TnMRIS bit in the GPTMRawInterrupt Status
(GPTMRIS) register). Note that the interrupt status bits are not updated by the hardware unless the
TnMIE bit in the GPTMTnMR register is set, which is different than the behavior for the time-out
interrupt. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL. The DMA trigger is
enabled by configuring and enabling the appropriate DMA channel. See Channel
Configuration on page 531.
If software updates the GPTMTnILRor the GPTMTnPRregister while the counter is counting down,
the counter loads the new value on the next clock cycle and continues counting from the new value
if the TnILD bit in the GPTMTnMR register is clear. If the TnILD bit is set, the counter loads the
new value after the next timeout. If software updates the GPTMTnILR or the GPTMTnPR register
while the counter is counting up, the timeout event is changed on the next cycle to the new value.
If software updates the GPTM Timer n Value (GPTMTnV) register while the counter is counting up
or down, the counter loads the new value on the next clock cycle and continues counting from the
newvalue. If software updates the GPTMTnMATCHRor the GPTMTnPMRregisters, the newvalues
are reflected on the next clock cycle if the TnMRSU bit in the GPTMTnMR register is clear. If the
TnMRSU bit is set, the new value will not take effect until the next timeout.
When using a 32/64-bit wide timer block in a 64-bit mode, certain registers must be accessed in the
manner described in Accessing Concatenated 32/64-Bit Wide GPTMRegister Values on page 661.
If the TnSTALL bit in the GPTMCTL register is set and the RTCEN bit is not set in the GPTMCTL
register, the timer freezes counting while the processor is halted by the debugger. The timer resumes
counting when the processor resumes execution. If the RTCEN bit is set, it prevents the TnSTALL
bit from freezing the count when the processor is halted by the debugger.
The following table shows a variety of configurations for a 16-bit free-running timer while using the
prescaler. All values assume an 80-MHz clock with Tc=12.5 ns (clock period). The prescaler can
only be used when a 16/32-bit timer is configured in 16-bit mode and when a 32/64-bit timer is
configured in 32-bit mode.
Table 10-5. 16-Bit Timer With Prescaler Configurations
Units Max Time # of Timer Clocks (Tc)
a
Prescale (8-bit value)
ms 0.8192 1 00000000
ms 1.6384 2 00000001
ms 2.4576 3 00000010
-- -- -- ------------
ms 208.0768 254 11111101
ms 208.896 255 11111110
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Table 10-5. 16-Bit Timer With Prescaler Configurations (continued)
a
ms 209.7152 256 11111111
a. Tc is the clock period.
The following table shows a variety of configurations for a 32-bit free-running timer using the prescaler
while configured in 32/64-bit mode. All values assume an 80-MHz clock with Tc=12.5 ns (clock
period).
Table 10-6. 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations
a
s 53.687 1 0x0000
s 107.374 2 0x0001
s 214.748 3 0x0002
-- -- -- ------------
10
6
s 0.879 65534 0xFFFD
10
6
s 1.759 65535 0xFFFE
10
6
s 3.518 65536 0xFFFF
a. Tc is the clock period.
10.3.2.2 Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers
are configured as an up-counter. When RTC mode is selected for the first time after reset, the
counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM
Timer n Interval Load (GPTMTnILR) registers (see page 697). If the GPTMTnILRregister is loaded
with a new value, the counter begins counting at that value and rolls over at the fixed value of
0xFFFFFFFF. Table 10-7 on page 652 shows the values that are loaded into the timer registers when
the timer is enabled.
Table 10-7. Counter Values When the Timer is Enabled in RTC Mode
0x1 Not available GPTMTnR
0x1 Not available GPTMTnV
Not available Not available GPTMTnPS
Not available Not available GPTMTnPV
The input clock on a CCP0 input is required to be 32.768 KHz in RTC mode. The clock signal is
then divided down to a 1-Hz rate and is passed along to the input of the counter.
When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from
its preloaded value of 0x1. When the current count value matches the preloaded value in the
GPTMTnMATCHRregisters, the GPTMasserts the RTCRIS bit in GPTMRIS and continues counting
until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer
value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the
RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and
generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
April 10, 2013 652
When using a 32/64-bit wide timer block in a RTC mode, certain registers must be accessed in the
manner described in Accessing Concatenated 32/64-Bit Wide GPTMRegister Values on page 661.
The value of the RTC predivider can be read in the GPTM RTC Predivide (GPTMRTCPD) register.
To ensure that the RTC value is coherent, software should follow the process detailed in Figure
10-2 on page 653.
Figure 10-2. Reading the RTC Value
Read Timer B = B
1
Read Timer A = A
1
Read Predivider
Read Timer A = A
2
Does
A
1
=A
2
?
Done
no
no
yes
yes
Does
B
1
=B
2
?
Read Timer B = B
2
In addition to generating an interrupt, the RTC also can generate a DMA trigger. The DMA trigger
is enabled by configuring and enabling the appropriate DMA channel. See Channel
Configuration on page 531.
10.3.2.3 Input Edge-Count Mode
Note: For rising-edge detection, the input signal must be High for at least two systemclock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
In Edge-Count mode, the timer is configured as a 24-bit or 48-bit up- or down-counter including the
optional prescaler with the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR)
register and the lower bits in the GPTMTnR register. In this mode, the timer is capable of capturing
three types of events: rising edge, falling edge, or both. To place the timer in Edge-Count mode,
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the TnCMR bit of the GPTMTnMR register must be cleared. The type of edge that the timer counts
is determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count
mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference
between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and
GPTMTnPMRregisters equals the number of edge events that must be counted. In up-count mode,
the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note
that when executing an up-count, that the value of GPTMTnPR and GPTMTnILR must be greater
than the value of GPTMTnPMR and GPTMTnMATCHR. Table 10-8 on page 654 shows the values
that are loaded into the timer registers when the timer is enabled.
Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode
0x0 GPTMTnILR GPTMTnR
0x0 GPTMTnILR GPTMTnV
0x0 GPTMTnPR GPTMTnPS
0x0 GPTMTnPR GPTMTnPV
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements or increments the counter by 1 until
the event count matches GPTMTnMATCHRand GPTMTnPMR. When the counts match, the GPTM
asserts the CnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until
it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode match
interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the
CnMMIS bit in the GPTMMasked Interrupt Status (GPTMMIS) register. In this mode, the GPTMTnR
and GPTMTnPS registers hold the count of the input events while the GPTMTnV and GPTMTnPV
registers hold the free-running timer value and the free-running prescaler value.
In addition to generating interrupts, an ADC and/or a DMA trigger can be generated. The ADC
trigger is enabled by setting the TnOTE bit in GPTMCTL.The DMA trigger is enabled by configuring
and enabling the appropriate DMA channel. See Channel Configuration on page 531.
After the match value is reached in down-count mode, the counter is then reloaded using the value
in GPTMTnILR and GPTMTnPR registers, and stopped because the GPTM automatically clears
the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events
are ignored until TnEN is re-enabled by software. In up-count mode, the timer is reloaded with 0x0
and continues counting.
Figure 10-3 on page 655 shows how Input Edge-Count mode works. In this case, the timer start
value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so
that four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted because the timer automatically clears the TnEN bit
after the current count matches the value in the GPTMTnMATCHR register.
April 10, 2013 654
Figure 10-3. Input Edge-Count Mode Example, Counting Down
Input Signal
Timer stops,
flags
asserted
Timer reload
on next cycle Ignored Ignored
Count
0x000A
0x0006
0x0007
0x0008
0x0009
10.3.2.4 Input Edge-Time Mode
Note: For rising-edge detection, the input signal must be High for at least two systemclock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
In Edge-Time mode, the timer is configured as a 24-bit or 48-bit up- or down-counter including the
optional prescaler with the upper timer value stored in the GPTMTnPR register and the lower bits
in the GPTMTnILRregister. In this mode, the timer is initialized to the value loaded in the GPTMTnILR
and GPTMTnPR registers when counting down and 0x0 when counting up. The timer is capable of
capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time
mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer
captures is determined by the TnEVENT fields of the GPTMCTL register. Table 10-9 on page 655
shows the values that are loaded into the timer registers when the timer is enabled.
Table 10-9. Counter Values When the Timer is Enabled in Input Event-Count Mode
0x0 GPTMTnILR TnR
0x0 GPTMTnILR TnV
0x0 GPTMTnPR TnPS
0x0 GPTMTnPR TnPV
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current timer counter value is captured in the
GPTMTnR and GPTMTnPS registers and is available to be read by the microcontroller. The GPTM
then asserts the CnERIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it
until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode
event interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets
the CnEMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. In this mode, the
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GPTMTnR and GPTMTnPSregisters hold the time at which the selected input event occurred while
the GPTMTnV and GPTMTnPV registers hold the free-running timer value and the free-running
prescaler value. These registers can be read to determine the time that elapsed between the interrupt
assertion and the entry into the ISR.
In addition to generating interrupts, an ADC and/or a DMA trigger can be generated. The ADC
trigger is enabled by setting the TnOTE bit in GPTMCTL.The DMA trigger is enabled by configuring
the appropriate DMA channel. See Channel Configuration on page 531.
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with 0x0 in up-count
mode and the value from the GPTMTnILR and GPTMTnPR registers in down-count mode.
Figure 10-4 on page 656 shows how input edge timing mode works. In the diagram, it is assumed
that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR and
GPTMTnPS registers, and is held there until another rising edge is detected (at which point the new
count value is loaded into the GPTMTnR and GPTMTnPS registers).
Figure 10-4. 16-Bit Input Edge-Time Mode Example
GPTMTnR=Y
Input Signal
Time
Count
GPTMTnR=X GPTMTnR=Z
Z
X
Y
0xFFFF
Note: When operating in Edge-time mode, the counter uses a modulo 2
24
count if prescaler is
enabled or 2
16
, if not. If there is a possibility the edge could take longer than the count, then
another timer configured in periodic-timer mode can be implemented to ensure detection
of the missed edge. The periodic timer should be configured in such a way that:
The periodic timer cycles at the same rate as the edge-time timer
The periodic timer interrupt has a higher interrupt priority than the edge-time timeout
interrupt.
If the periodic timer interrupt service routine is entered, software must check if an
edge-time interrupt is pending and if it is, the value of the counter must be subtracted
by 1 before being used to calculate the snapshot time of the event.
April 10, 2013 656
10.3.2.5 PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
24-bit or 48-bit down-counter with a start value (and thus period) defined by the GPTMTnILR and
GPTMTnPR registers. In this mode, the PWM frequency and period are synchronous events and
therefore guaranteed to be glitch free. PWM mode is enabled with the GPTMTnMR register by
setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. Table 10-10 on page 657
shows the values that are loaded into the timer registers when the timer is enabled.
Table 10-10. Counter Values When the Timer is Enabled in PWM Mode
Not available GPTMTnILR GPTMTnR
Not available GPTMTnILR GPTMTnV
Not available GPTMTnPR GPTMTnPS
Not available GPTMTnPR GPTMTnPV
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0 state. Alternatively, if the TnWOT bit is set in the GPTMTnMR register, once
the TnEN bit is set, the timer waits for a trigger to begin counting (see Wait-for-Trigger
Mode on page 659). On the next counter cycle in periodic mode, the counter reloads its start value
from the GPTMTnILR and GPTMTnPR registers and continues counting until disabled by software
clearing the TnEN bit in the GPTMCTL register. The timer is capable of generating interrupts based
on three types of events: rising edge, falling edge, or both. The event is configured by the TnEVENT
field of the GPTMCTL register, and the interrupt is enabled by setting the TnPWMIE bit in the
GPTMTnMR register. When the event occurs, the CnERIS bit is set in the GPTM Raw Interrupt
Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear
(GPTMICR) register . If the capture mode event interrupt is enabled in the GPTM Interrupt Mask
(GPTMIMR) register , the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status
(GPTMMIS) register. Note that the interrupt status bits are not updated unless the TnPWMIE bit is
set.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value, as do the
GPTMPnPS and the GPTMTnPV registers.
The output PWMsignal asserts when the counter is at the value of the GPTMTnILRand GPTMTnPR
registers (its start state), and is deasserted when the counter value equals the value in the
GPTMTnMATCHR and GPTMTnPMR registers. Software has the capability of inverting the output
PWM signal by setting the TnPWML bit in the GPTMCTL register.
Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if
a positive-edge interrupt trigger has been set and the PWM inversion generates a positive
edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative
edge of the PWM signal.
Figure 10-5 on page 658 shows how to generate an output PWMwith a 1-ms period and a 66%duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMTnILR=0xC350 and the match value is
GPTMTnMATCHR=0x411A.
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Figure 10-5. 16-Bit PWM Mode Example
Output
Signal
Time
Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0xC350
0x411A
TnPWML = 0
TnPWML = 1
TnEN set
When synchronizing the timers using the GPTMSYNCregister, the timer must be properly configured
to avoid glitches on the CCP outputs. Both the PLO and the MRSU bits must be set in the GPTMTnMR
register. Figure 10-6 on page 658 shows how the CCP output operates when the PLO and MRSU bits
are set and the GPTMTnMATCHR value is greater than the GPTMTnILR value.
Figure 10-6. CCP Output, GPTMTnMATCHR > GPTMTnILR
CCP
C
o
u
n
t
e
r
V
a
l
u
e
GPTMnMATCHR
GPTMnILR
CCP set if GPTMnMATCHR GPTMnILR
Figure 10-7 on page 659 shows how the CCP output operates when the PLO and MRSU bits are set
and the GPTMTnMATCHR value is the same as the GPTMTnILR value. In this situation, if the PLO
bit is 0, the CCP signal goes high when the GPTMTnILR value is loaded and the match would be
essentially ignored.
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Figure 10-7. CCP Output, GPTMTnMATCHR = GPTMTnILR
CCP
CCP not set if GPTMnMATCHR = GPTMnILR
GPTMnMATCHR
C
o
u
n
t
e
r
V
a
l
u
e
GPTMnILR
Figure 10-8 on page 659 shows how the CCP output operates when the PLO and MRSU bits are set
and the GPTMTnILR is greater than the GPTMTnMATCHR value.
Figure 10-8. CCP Output, GPTMTnILR > GPTMTnMATCHR
GPTMnMATCHR = GPTMnILR-1
GPTMnMATCHR = GPTMnILR-2
GPTMnILR
GPTMnMATCHR == 0
CCP
CCP
CCP
Pulse width is 1 clock when GPTMnMATCHR = GPTMnILR - 1
Pulse width is 2 clocks when GPTMnMATCHR = GPTMnILR - 2
Pulse width is GPTMnILR clocks when GPTMnMATCHR= 0
10.3.3 Wait-for-Trigger Mode
The Wait-for-Trigger mode allows daisy chaining of the timer modules such that once configured,
a single timer can initiate mulitple timing events using the Timer triggers. Wait-for-Trigger mode is
enabled by setting the TnWOT bit in the GPTMTnMR register. When the TnWOT bit is set, Timer N+1
does not begin counting until the timer in the previous position in the daisy chain (Timer N) reaches
its time-out event. The daisy chain is configured such that GPTM1 always follows GPTM0, GPTM2
follows GPTM1, and so on. If Timer A is configured as a 32-bit (16/32-bit mode) or 64-bit (32/64-bit
wide mode) timer (controlled by the GPTMCFG field in the GPTMCFG register), it triggers Timer A
in the next module. If Timer A is configured as a 16-bit (16/32-bit mode) or 32-bit (32/64-bit wide
mode) timer, it triggers Timer B in the same module, and Timer B triggers Timer A in the next module.
Care must be taken that the TAWOT bit is never set in GPTM0. Figure 10-9 on page 660 shows how
the GPTMCFG bit affects the daisy chain. This function is valid for one-shot, periodic, and PWM
modes.
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Figure 10-9. Timer Daisy Chain
GP Timer N
Timer B
Timer A
1 0 GPTMCFG
GP Timer N+1
Timer B
Timer A
1 0 GPTMCFG
Timer B ADC Trigger
Timer A ADC Trigger
Timer B ADC Trigger
Timer A ADC Trigger
10.3.4 Synchronizing GP Timer Blocks
The GPTM Synchronizer Control (GPTMSYNC) register in the GPTM0 block can be used to
synchronize selected timers to begin counting at the same time. Setting a bit in the GPTMSYNC
register causes the associated timer to perform the actions of a timeout event. An interrupt is not
generated when the timers are synchronized. If a timer is being used in concatenated mode, only
the bit for Timer A must be set in the GPTMSYNC register.
Note: All timers must use the same clock source for this feature to work correctly.
Table 10-11 on page 660 shows the actions for the timeout event performed when the timers are
synchronized in the various timer modes.
Table 10-11. Timeout Actions for GPTM Modes
Time Out Action Count Dir Mode
N/A 32- and 64-bit One-Shot
(concatenated timers)
Count value = ILR Down 32- and 64-bit Periodic
Count value = 0 Up
Count value = 0 Up 32- and 64-bit RTC
N/A 16- and 32- bit One Shot
(individual/split timers)
Count value = ILR Down 16- and 32- bit Periodic
Count value = 0 Up
Count value = ILR Down 16- and 32- bit
Edge-Count
Count value = 0 Up
Count value = ILR Down 16- and 32- bit
Edge-Time
Count value = 0 Up
Count value = ILR Down 16- and 32-bit PWM
10.3.5 DMA Operation
The timers each have a dedicated DMA channel and can provide a request signal to the DMA
controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs.
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The arbitration size of the DMA transfer should be set to the amount of data that should be
transferred whenever a timer event occurs.
For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a
periodic timeout at 10 ms. Configure the DMA transfer for a total of 256 items, with a burst size of
8 items. Each time the timer times out, the DMA controller transfers 8 items, until all 256 items
have been transferred.
No other special steps are needed to enable Timers for DMA operation. Refer to Micro Direct
Memory Access (DMA) on page 527 for more details about programming the DMA controller.
10.3.6 Accessing Concatenated 16/32-Bit GPTM Register Values
The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in
the GPTM Configuration (GPTMCFG) register. In both configurations, certain 16/32-bit GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 697
GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 698
GPTM Timer A (GPTMTAR) register [15:0], see page 705
GPTM Timer B (GPTMTBR) register [15:0], see page 706
GPTM Timer A Value (GPTMTAV) register [15:0], see page 707
GPTM Timer B Value (GPTMTBV) register [15:0], see page 708
GPTM Timer A Match (GPTMTAMATCHR) register [15:0], see page 699
GPTM Timer B Match (GPTMTBMATCHR) register [15:0], see page 700
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a 32-bit read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
A 32-bit read access to GPTMTAV returns the value:
GPTMTBV[15:0]:GPTMTAV[15:0]
10.3.7 Accessing Concatenated 32/64-Bit Wide GPTM Register Values
On the 32/64-bit wide GPTM blocks, concatenated register values (64-bits and 48-bits) are not
readily available as the bit width for these accesses is greater than the bus width of the processor
core. In the concatenated timer modes and the individual timer modes when using the prescaler,
software must perform atomic accesses for the value to be coherent. When reading timer values
that are greater than 32 bits, software should follow these steps:
1. Read the appropriate Timer B register or prescaler register.
2. Read the corresponding Timer A register.
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3. Re-read the Timer B register or prescaler register.
4. Compare the Timer B or prescaler values from the first and second reads. If they are the same,
the timer value is coherent. If they are not the same, repeat steps 1-4 once more so that they
are the same.
The following pseudo code illustrates this process:
high = timer_high;
low = timer_low;
if (high != timer_high); //low overflowed into high
{
high = timer_high;
low = timer_low;
}
The registers that must be read in this manner are shown below:
64-bit reads
GPTMTAV and GPTMTBV
GPTMTAR and GPTMTBR
48-bit reads
GPTMTAR and GPTMTAPS
GPTMTBR and GPTMTBPS
GPTMTAV and GPTMTAPV
GPTMTBV and GPTMTBPV
Similarly, write accesses must also be performed by writing the upper bits prior to writing the lower
bits as follows:
1. Write the appropriate Timer B register or prescaler register.
2. Write the corresponding Timer A register.
The registers that must be written in this manner are shown below:
64-bit writes
GPTMTAV and GPTMTBV
GPTMTAMATCHR and GPTMTBMATCHR
GPTMTAILR and GPTMTBILR
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48-bit writes
GPTMTAV and GPTMTAPV
GPTMTBV and GPTMTBPV
GPTMTAMATCHR and GPTMTAPMR
GPTMTBMATCHR and GPTMTBPMR
GPTMTAILR and GPTMTAPR
GPTMTBILR and GPTMTBPR
When writing a 64-bit value, If there are two consecutive writes to any of the registers listed above
under the "64-bit writes" heading, whether the register is in Timer A or Timer B, or if a register Timer
A is written prior to writing the corresponding register in Timer B, then an error is reported using the
WUERIS bit in the GPTMRIS register. This error can be promoted to interrupt if it is not masked.
Note that this error is not reported for the prescaler registers because use of the prescaler is optional.
As a result, programmers must take care to follow the protocol outlined above.
To use a GPTM, the appropriate TIMERn bit must be set in the RCGCTIMER or RCGCWTIMER
register (see page 320 and page 337). If using any CCP pins, the clock to the appropriate GPIO
module must be enabled via the RCGCGPIO register (see page 322). To find out which GPIO port
to enable, refer to Table 21-4 on page 1170. Configure the PMCn fields in the GPIOPCTL register to
assign the CCP signals to the appropriate pins (see page 629 and Table 21-5 on page 1176).
This section shows module initialization and configuration examples for each of the supported timer
modes.
10.4.1 One-Shot/Periodic Timer Mode
The GPTM is configured for One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000.
3. Configure the TnMR field in the GPTM Timer n Mode Register (GPTMTnMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in the GPTMTnMRregister
to select whether to capture the value of the free-running timer at time-out, use an external
trigger to start counting, configure an additional trigger or interrupt, and count up or down.
5. Load the start value into the GPTM Timer n Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register
(GPTMIMR).
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7. Set the TnEN bit in the GPTMCTL register to enable the timer and start counting.
8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases,
the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear
Register (GPTMICR).
If the TnMIE bit in the GPTMTnMR register is set, the RTCRIS bit in the GPTMRIS register is set,
and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out
event. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode reloads
the timer and continues counting after the time-out event.
10.4.2 Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on a CCP0 input. To enable
the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0001.
3. Write the match value to the GPTM Timer n Match Register (GPTMTnMATCHR).
4. Set/clear the RTCEN and TnSTALL bit in the GPTM Control Register (GPTMCTL) as needed.
5. If interrupts are required, set the RTCIM bit in the GPTMInterrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTnMATCHR register, the GPTM asserts the
RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware
reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register. Note that if the
GPTMTnILR register is loaded with a new value, the timer begins counting at this new value and
continues until it reaches 0xFFFF.FFFF, at which point it rolls over.
10.4.3 Input Edge-Count Mode
A timer is configured to Input Edge-Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPTMTnPR).
6. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
7. Load the prescaler match value (if any) in the GPTM Timer n Prescale Match (GPTMTnPMR)
register.
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8. Load the event count into the GPTM Timer n Match (GPTMTnMATCHR) register. Note that
when executing an up-count, the value of GPTMTnPR and GPTMTnILR must be greater than
the value of GPTMTnPMR and GPTMTnMATCHR.
9. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
10. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
11. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
When counting down in Input Edge-Count Mode, the timer stops after the programmed number of
edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and
repeat #4 on page 664 through #9 on page 665.
10.4.4 Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
(GPTMTnPR).
7. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMControl (GPTMCTL) register to enable the timer and start counting.
9. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timer n (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
10.4.5 PWM Mode
A timer is configured to PWM mode using the following sequence:
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3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field
of the GPTM Control (GPTMCTL) register.
(GPTMTnPR).
6. If PWM interrupts are used, configure the interrupt condition in the TnEVENT field in the
GPTMCTL register and enable the interrupts by setting the TnPWMIE bit in the GPTMTnMR
register. Note that edge detect interrupt behavior is reversed when the PWM output is inverted
(see page 678).
8. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value.
9. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
10.5 Register Map
Table 10-12 on page 667 lists the GPTM registers. The offset listed is a hexadecimal increment to
the registers address, relative to that timers base address:
16/32-bit Timer 0: 0x4003.0000
16/32-bit Timer 1: 0x4003.1000
16/32-bit Timer 2: 0x4003.2000
16/32-bit Timer 3: 0x4003.3000
16/32-bit Timer 4: 0x4003.4000
16/32-bit Timer 5: 0x4003.5000
32/64-bit Wide Timer 0: 0x4003.6000
32/64-bit Wide Timer 1: 0x4003.7000
32/64-bit Wide Timer 2: 0x4004.C000
32/64-bit Wide Timer 3: 0x4004.D000
32/64-bit Wide Timer 4: 0x4004.E000
32/64-bit Wide Timer 5: 0x4004.F000
The SIZE field in the GPTMPeripheral Properties (GPTMPP) register identifies whether a module
has a 16/32-bit or 32/64-bit wide timer.
Note that the GP Timer module clock must be enabled before the registers can be programmed
(see page 320 or page 337). There must be a delay of 3 system clocks after the Timer module clock
is enabled before any Timer module registers are accessed.
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Table 10-12. Timers Register Map
See
page
668 GPTM Configuration 0x0000.0000 R/W GPTMCFG 0x000
670 GPTM Timer A Mode 0x0000.0000 R/W GPTMTAMR 0x004
674 GPTM Timer B Mode 0x0000.0000 R/W GPTMTBMR 0x008
678 GPTM Control 0x0000.0000 R/W GPTMCTL 0x00C
682 GPTM Synchronize 0x0000.0000 R/W GPTMSYNC 0x010
686 GPTM Interrupt Mask 0x0000.0000 R/W GPTMIMR 0x018
689 GPTM Raw Interrupt Status 0x0000.0000 RO GPTMRIS 0x01C
692 GPTM Masked Interrupt Status 0x0000.0000 RO GPTMMIS 0x020
695 GPTM Interrupt Clear 0x0000.0000 W1C GPTMICR 0x024
697 GPTM Timer A Interval Load 0xFFFF.FFFF R/W GPTMTAILR 0x028
698 GPTM Timer B Interval Load - R/W GPTMTBILR 0x02C
699 GPTM Timer A Match 0xFFFF.FFFF R/W GPTMTAMATCHR 0x030
700 GPTM Timer B Match - R/W GPTMTBMATCHR 0x034
701 GPTM Timer A Prescale 0x0000.0000 R/W GPTMTAPR 0x038
702 GPTM Timer B Prescale 0x0000.0000 R/W GPTMTBPR 0x03C
703 GPTM TimerA Prescale Match 0x0000.0000 R/W GPTMTAPMR 0x040
704 GPTM TimerB Prescale Match 0x0000.0000 R/W GPTMTBPMR 0x044
705 GPTM Timer A 0xFFFF.FFFF RO GPTMTAR 0x048
706 GPTM Timer B - RO GPTMTBR 0x04C
707 GPTM Timer A Value 0xFFFF.FFFF RW GPTMTAV 0x050
708 GPTM Timer B Value - RW GPTMTBV 0x054
709 GPTM RTC Predivide 0x0000.7FFF RO GPTMRTCPD 0x058
710 GPTM Timer A Prescale Snapshot 0x0000.0000 RO GPTMTAPS 0x05C
711 GPTM Timer B Prescale Snapshot 0x0000.0000 RO GPTMTBPS 0x060
712 GPTM Timer A Prescale Value 0x0000.0000 RO GPTMTAPV 0x064
713 GPTM Timer B Prescale Value 0x0000.0000 RO GPTMTBPV 0x068
714 GPTM Peripheral Properties 0x0000.0000 RO GPTMPP 0xFC0
The remainder of this section lists and describes the GPTMregisters, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 64-bit mode (concatenated timers) or in 16- or 32-bit
mode (individual, split timers).
Important: Bits in this register should only be changed when the TAEN and TBEN bits in the
GPTMCTL register are cleared.
GPTM Configuration (GPTMCFG)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GPTMCFG reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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GPTM Configuration
The GPTMCFG values are defined as follows:
Description Value
For a 16/32-bit timer, this value selects the 32-bit timer
configuration.
For a 32/64-bit wide timer, this value selects the 64-bit timer
configuration.
0x0
For a 16/32-bit timer, this value selects the 32-bit real-time
clock (RTC) counter configuration.
For a 32/64-bit wide timer, this value selects the 64-bit
real-time clock (RTC) counter configuration.
0x1
Reserved 0x2-0x3
For a 16/32-bit timer, this value selects the 16-bit timer
configuration.
For a 32/64-bit wide timer, this value selects the 32-bit timer
configuration.
The function is controlled by bits 1:0 of GPTMTAMR and
GPTMTBMR.
0x4
Reserved 0x5-0x7
0x0 R/W GPTMCFG 2:0
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Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in PWM mode, set the TAAMS bit, clear the TACMR bit, and configure the TAMR field to 0x1 or
0x2.
This register controls the modes for Timer A when it is used individually. When Timer A and Timer
B are concatenated, this register controls the modes for both Timer A and Timer B, and the contents
of GPTMTBMR are ignored.
Important: Bits in this register should only be changed when the TAEN bit in the GPTMCTL register
is cleared.
GPTM Timer A Mode (GPTMTAMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TAMR TACMR TAAMS TACDIR TAMIE TAWOT TASNAPS TAILD TAPWMIE TAMRSU TAPLO reserved
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPTM Timer A PWM Legacy Operation
Description Value
Legacy operation with CCP pin driven Low when the
GPTMTAILR is reloaded after the timer reaches 0.
0
CCP is driven High when the GPTMTAILR is reloaded after the
timer reaches 0.
1
This bit is only valid in PWM mode.
0 R/W TAPLO 11
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GPTM Timer A Match Register Update
Description Value
Update the GPTMTAMATCHR register and the GPTMTAPR
register, if used, on the next cycle.
0
Update the GPTMTAMATCHR register and the GPTMTAPR
register, if used, on the next timeout.
1
If the timer is disabled (TAEN is clear) when this bit is set,
GPTMTAMATCHR and GPTMTAPR are updated when the timer is
enabled. If the timer is stalled (TASTALL is set), GPTMTAMATCHRand
GPTMTAPR are updated according to the configuration of this bit.
0 R/W TAMRSU 10
GPTM Timer A PWM Interrupt Enable
This bit enables interrupts in PWMmode on rising, falling, or both edges
of the CCP output, as defined by the TAEVENT field in the GPTMCTL
register.
Description Value
Capture event interrupt is disabled. 0
Capture event interrupt is enabled. 1
0 R/W TAPWMIE 9
GPTM Timer A Interval Load Write
Description Value
Update the GPTMTAR and GPTMTAV registers with the value
in the GPTMTAILR register on the next cycle. Also update the
GPTMTAPS and GPTMTAPV registers with the value in the
GPTMTAPR register on the next cycle.
0
Update the GPTMTAR and GPTMTAV registers with the value
in the GPTMTAILR and GPTMTAPV registers on the next
timeout. Also update the GPTMTAPS register with the value in
the GPTMTAPR register on the next timeout.
1
Note the state of this bit has no effect when counting up.
The bit descriptions above apply if the timer is enabled and running. If
the timer is disabled (TAEN is clear) when this bit is set, GPTMTAR,
GPTMTAV, GPTMTAPS, and GPTMTAPV are updated when the timer
is enabled. If the timer is stalled (TASTALL is set), GPTMTAR and
GPTMTAPS are updated according to the configuration of this bit.
0 R/W TAILD 8
GPTM Timer A Snap-Shot Mode
Description Value
Snap-shot mode is disabled. 0
If Timer A is configured in the periodic mode, the actual
free-running value of Timer A is loaded at the time-out event
into the GPTM Timer A (GPTMTAR) register. If the timer
prescaler is used, the prescaler snapshot is loaded into the
GPTM Timer A (GPTMTAPR).
1
0 R/W TASNAPS 7
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GPTM Timer A Wait-on-Trigger
Description Value
Timer A begins counting as soon as it is enabled. 0
If Timer A is enabled (TAEN is set in the GPTMCTL register),
Timer A does not begin counting until it receives a trigger from
the timer in the previous position in the daisy chain, see Figure
10-9 on page 660. This function is valid for one-shot, periodic,
and PWM modes.
1
This bit must be clear for GP Timer Module 0, Timer A.
0 R/W TAWOT 6
GPTM Timer A Match Interrupt Enable
Description Value
The match interrupt is disabled for match events. Additionally,
triggers to the DMA and ADC on match events are prevented.
0
An interrupt is generated when the match value in the
GPTMTAMATCHR register is reached in the one-shot and
periodic modes.
1
0 R/W TAMIE 5
GPTM Timer A Count Direction
Description Value
The timer counts down. 0
The timer counts up. When counting up, the timer starts from a
value of 0x0.
1
When in PWMor RTCmode, the status of this bit is ignored. PWMmode
always counts down and RTC mode always counts up.
0 R/W TACDIR 4
GPTM Timer A Alternate Mode Select
The TAAMS values are defined as follows:
Description Value
Capture or compare mode is enabled. 0
PWM mode is enabled. 1
Note: To enable PWMmode, you must also clear the TACMR
bit and configure the TAMR field to 0x1 or 0x2.
0 R/W TAAMS 3
GPTM Timer A Capture Mode
The TACMR values are defined as follows:
Description Value
Edge-Count mode 0
Edge-Time mode 1
0 R/W TACMR 2
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GPTM Timer A Mode
The TAMR values are defined as follows:
Description Value
Reserved 0x0
One-Shot Timer mode 0x1
Periodic Timer mode 0x2
Capture mode 0x3
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
0x0 R/W TAMR 1:0
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Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in PWM mode, set the TBAMS bit, clear the TBCMR bit, and configure the TBMR field to 0x1 or
0x2.
This register controls the modes for Timer B when it is used individually. When Timer A and Timer
B are concatenated, this register is ignored and GPTMTAMR controls the modes for both Timer A
and Timer B.
Important: Bits in this register should only be changed when the TBEN bit in the GPTMCTL register
is cleared.
GPTM Timer B Mode (GPTMTBMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TBMR TBCMR TBAMS TBCDIR TBMIE TBWOT TBSNAPS TBILD TBPWMIE TBMRSU TBPLO reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPTM Timer B PWM Legacy Operation
Description Value
Legacy operation with CCP pin driven Low when the
GPTMTAILR is reloaded after the timer reaches 0.
0
CCP is driven High when the GPTMTAILR is reloaded after the
timer reaches 0.
1
0 R/W TBPLO 11
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GPTM Timer B Match Register Update
Description Value
Update the GPTMTBMATCHR register and the GPTMTBPR
register, if used, on the next cycle.
0
Update the GPTMTBMATCHR register and the GPTMTBPR
register, if used, on the next timeout.
1
If the timer is disabled (TBEN is clear) when this bit is set,
GPTMTBMATCHR and GPTMTBPR are updated when the timer is
enabled. If the timer is stalled (TBSTALL is set), GPTMTBMATCHRand
GPTMTBPR are updated according to the configuration of this bit.
0 R/W TBMRSU 10
GPTM Timer B PWM Interrupt Enable
This bit enables interrupts in PWMmode on rising, falling, or both edges
of the CCP output as defined by the TBEVENT field in the GPTMCTL
register.
Description Value
Capture event interrupt is disabled. 0
Capture event is enabled. 1
0 R/W TBPWMIE 9
GPTM Timer B Interval Load Write
Description Value
Update the GPTMTBR and GPTMTBV registers with the value
in the GPTMTBILR register on the next cycle. Also update the
GPTMTBPS and GPTMTBPV registers with the value in the
GPTMTBPR register on the next cycle.
0
Update the GPTMTBR and GPTMTBV registers with the value
in the GPTMTBILR register on the next timeout. Also update
the GPTMTBPS and GPTMTBPV registers with the value in
the GPTMTBPR register on the next timeout.
1
Note the state of this bit has no effect when counting up.
The bit descriptions above apply if the timer is enabled and running. If
the timer is disabled (TBEN is clear) when this bit is set, GPTMTBR,
GPTMTBV, GPTMTBPS, and GPTMTBPV are updated when the timer
is enabled. If the timer is stalled (TBSTALL is set), GPTMTBR and
GPTMTBPS are updated according to the configuration of this bit.
0 R/W TBILD 8
GPTM Timer B Snap-Shot Mode
Description Value
Snap-shot mode is disabled. 0
If Timer B is configured in the periodic mode, the actual
free-running value of Timer B is loaded at the time-out event
into the GPTM Timer B (GPTMTBR) register. If the timer
prescaler is used, the prescaler snapshot is loaded into the
GPTM Timer B (GPTMTBPR).
1
0 R/W TBSNAPS 7
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GPTM Timer B Wait-on-Trigger
Description Value
Timer B begins counting as soon as it is enabled. 0
If Timer B is enabled (TBEN is set in the GPTMCTL register),
Timer B does not begin counting until it receives a trigger from
the timer in the previous position in the daisy chain, see Figure
10-9 on page 660. This function is valid for one-shot, periodic,
and PWM modes.
1
0 R/W TBWOT 6
GPTM Timer B Match Interrupt Enable
Description Value
The match interrupt is disabled for match events. Additionally,
triggers to the DMA and ADC on match events are prevented.
0
An interrupt is generated when the match value in the
GPTMTBMATCHR register is reached in the one-shot and
periodic modes.
1
0 R/W TBMIE 5
GPTM Timer B Count Direction
Description Value
The timer counts down. 0
The timer counts up. When counting up, the timer starts from a
value of 0x0.
1
When in PWMor RTCmode, the status of this bit is ignored. PWMmode
always counts down and RTC mode always counts up.
0 R/W TBCDIR 4
GPTM Timer B Alternate Mode Select
The TBAMS values are defined as follows:
Description Value
Capture or compare mode is enabled. 0
PWM mode is enabled. 1
Note: To enable PWMmode, you must also clear the TBCMR
bit and configure the TBMR field to 0x1 or 0x2.
0 R/W TBAMS 3
GPTM Timer B Capture Mode
The TBCMR values are defined as follows:
Description Value
Edge-Count mode 0
Edge-Time mode 1
0 R/W TBCMR 2
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GPTM Timer B Mode
The TBMR values are defined as follows:
Description Value
Reserved 0x0
One-Shot Timer mode 0x1
Periodic Timer mode 0x2
Capture mode 0x3
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
0x0 R/W TBMR 1:0
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
Important: Bits in this register should only be changed when the TnEN bit for the respective timer
is cleared.
GPTM Control (GPTMCTL)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x00C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TAEN TASTALL TAEVENT RTCEN TAOTE TAPWML reserved TBEN TBSTALL TBEVENT reserved TBOTE TBPWML reserved
R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO R/W R/W RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPTM Timer B PWM Output Level
The TBPWML values are defined as follows:
Description Value
Output is unaffected. 0
Output is inverted. 1
0 R/W TBPWML 14
GPTM Timer B Output Trigger Enable
The TBOTE values are defined as follows:
Description Value
The output Timer B ADC trigger is disabled. 0
The output Timer B ADC trigger is enabled. 1
In addition, the ADCmust be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 774).
0 R/W TBOTE 13
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0 RO reserved 12
GPTM Timer B Event Mode
The TBEVENT values are defined as follows:
Description Value
Positive edge 0x0
Negative edge 0x1
Reserved 0x2
Both edges 0x3
Note: If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
0x0 R/W TBEVENT 11:10
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
Description Value
Timer B continues counting while the processor is halted by the
debugger.
0
Timer B freezes counting while the processor is halted by the
debugger.
1
If the processor is executing normally, the TBSTALL bit is ignored.
0 R/W TBSTALL 9
GPTM Timer B Enable
The TBEN values are defined as follows:
Description Value
Timer B is disabled. 0
Timer B is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0 R/W TBEN 8
0 RO reserved 7
GPTM Timer A PWM Output Level
The TAPWML values are defined as follows:
Description Value
Output is unaffected. 0
Output is inverted. 1
0 R/W TAPWML 6
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GPTM Timer A Output Trigger Enable
The TAOTE values are defined as follows:
Description Value
The output Timer A ADC trigger is disabled. 0
The output Timer A ADC trigger is enabled. 1
In addition, the ADCmust be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 774).
0 R/W TAOTE 5
GPTM RTC Stall Enable
The RTCEN values are defined as follows:
Description Value
RTC counting freezes while the processor is halted by the
debugger.
0
RTC counting continues while the processor is halted by the
debugger.
1
If the RTCEN bit is set, it prevents the timer from stalling in all operating
modes, even if TnSTALL is set.
0 R/W RTCEN 4
GPTM Timer A Event Mode
The TAEVENT values are defined as follows:
Description Value
Positive edge 0x0
Negative edge 0x1
Reserved 0x2
Both edges 0x3
Note: If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
0x0 R/W TAEVENT 3:2
GPTM Timer A Stall Enable
The TASTALL values are defined as follows:
Description Value
Timer A continues counting while the processor is halted by the
debugger.
0
Timer A freezes counting while the processor is halted by the
debugger.
1
If the processor is executing normally, the TASTALL bit is ignored.
0 R/W TASTALL 1
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GPTM Timer A Enable
The TAEN values are defined as follows:
Description Value
Timer A is disabled. 0
Timer A is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0 R/W TAEN 0
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Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010
Note: This register is only implemented on GPTM Module 0 only.
This register allows software to synchronize a number of timers.
GPTM Synchronize (GPTMSYNC)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SYNCWT2 SYNCWT3 SYNCWT4 SYNCWT5 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SYNCT0 SYNCT1 SYNCT2 SYNCT3 SYNCT4 SYNCT5 SYNCWT0 SYNCWT1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Synchronize GPTM 32/64-Bit Timer 5
The SYNCWT5 values are defined as follows:
Description Value
GPTM 32/64-Bit Timer 5 is not affected. 0x0
A timeout event for Timer A of GPTM 32/64-Bit Timer 5 is
triggered.
0x1
A timeout event for Timer B of GPTM 32/64-Bit Timer 5 is
triggered.
0x2
A timeout event for both Timer A and Timer B of GPTM32/64-Bit
Timer 5 is triggered.
0x3
0x0 R/W SYNCWT5 23:22
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Description Value
triggered.
0x1
triggered.
0x2
0x3
Description Value
triggered.
0x1
triggered.
0x2
0x3
Description Value
triggered.
0x1
triggered.
0x2
0x3
Description Value
triggered.
0x1
triggered.
0x2
0x3
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Description Value
triggered.
0x1
triggered.
0x2
0x3
The SYNCT5 values are defined as follows:
Description Value
triggered.
0x1
triggered.
0x2
0x3
0x0 R/W SYNCT5 11:10
Description Value
triggered.
0x1
triggered.
0x2
0x3
0x0 R/W SYNCT4 9:8
Description Value
triggered.
0x1
triggered.
0x2
0x3
0x0 R/W SYNCT3 7:6
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Description Value
triggered.
0x1
triggered.
0x2
0x3
0x0 R/W SYNCT2 5:4
Description Value
triggered.
0x1
triggered.
0x2
0x3
0x0 R/W SYNCT1 3:2
Description Value
triggered.
0x1
triggered.
0x2
0x3
0x0 R/W SYNCT0 1:0
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Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTMcontroller-level interrupts. Setting a bit enables
the corresponding interrupt, while clearing a bit disables it.
GPTM Interrupt Mask (GPTMIMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WUEIM reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TATOIM CAMIM CAEIM RTCIM TAMIM reserved TBTOIM CBMIM CBEIM TBMIM reserved
R/W R/W R/W R/W R/W RO RO RO R/W R/W R/W R/W RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
32/64-Bit Wide GPTM Write Update Error Interrupt Mask
The WUEIM values are defined as follows:
Description Value
Interrupt is disabled. 0
Interrupt is enabled. 1
0 R/W WUEIM 16
0 RO reserved 15:12
GPTM Timer B Match Interrupt Mask
The TBMIM values are defined as follows:
Description Value
0 R/W TBMIM 11
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GPTM Timer B Capture Mode Event Interrupt Mask
The CBEIM values are defined as follows:
Description Value
0 R/W CBEIM 10
GPTM Timer B Capture Mode Match Interrupt Mask
The CBMIM values are defined as follows:
Description Value
0 R/W CBMIM 9
GPTM Timer B Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Description Value
0 R/W TBTOIM 8
0 RO reserved 7:5
GPTM Timer A Match Interrupt Mask
The TAMIM values are defined as follows:
Description Value
0 R/W TAMIM 4
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Description Value
0 R/W RTCIM 3
GPTM Timer A Capture Mode Event Interrupt Mask
The CAEIM values are defined as follows:
Description Value
0 R/W CAEIM 2
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GPTM Timer A Capture Mode Match Interrupt Mask
The CAMIM values are defined as follows:
Description Value
0 R/W CAMIM 1
GPTM Timer A Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Description Value
0 R/W TATOIM 0
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Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x01C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WUERIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TATORIS CAMRIS CAERIS RTCRIS TAMRIS reserved TBTORIS CBMRIS CBERIS TBMRIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
32/64-Bit Wide GPTM Write Update Error Raw Interrupt Status
Description Value
No error. 0
Either a Timer A register or a Timer B register was written twice
in a row or a Timer A register was written before the
corresponding Timer B register was written.
1
0 R/W WUERIS 16
0 RO reserved 15:12
GPTM Timer B Match Raw Interrupt
Description Value
The match value has not been reached. 0
The TBMIE bit is set in the GPTMTBMRregister, and the match
values in the GPTMTBMATCHRand (optionally) GPTMTBPMR
registers have been reached when configured in one-shot or
periodic mode.
1
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
0 RO TBMRIS 11
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GPTM Timer B Capture Mode Event Raw Interrupt
Description Value
The capture mode event for Timer B has not occurred. 0
A capture mode event has occurred for Timer B. This interrupt
asserts when the subtimer is configured in Input Edge-Time
mode or when configured in PWMmode with the PWMinterrupt
enabled by setting the TBPWMIE bit in the GPTMTBMR.
1
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
0 RO CBERIS 10
GPTM Timer B Capture Mode Match Raw Interrupt
Description Value
The capture mode match for Timer B has not occurred. 0
The capture mode match has occurred for Timer B. This interrupt
asserts when the values in the GPTMTBR and GPTMTBPR
match the values in the GPTMTBMATCHR and GPTMTBPMR
when configured in Input Edge-Time mode.
1
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR
register.
0 RO CBMRIS 9
GPTM Timer B Time-Out Raw Interrupt
Description Value
Timer B has not timed out. 0
Timer B has timed out. This interrupt is asserted when a
one-shot or periodic mode timer reaches it's count limit (0 or
the value loaded into GPTMTBILR, depending on the count
direction).
1
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR
register.
0 RO TBTORIS 8
0 RO reserved 7:5
GPTM Timer A Match Raw Interrupt
Description Value
The match value has not been reached. 0
The TAMIE bit is set in the GPTMTAMR register, and the match
value in the GPTMTAMATCHR and (optionally) GPTMTAPMR
registers have been reached when configured in one-shot or
periodic mode.
1
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR
register.
0 RO TAMRIS 4
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GPTM RTC Raw Interrupt
Description Value
The RTC event has not occurred. 0
The RTC event has occurred. 1
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR
register.
0 RO RTCRIS 3
GPTM Timer A Capture Mode Event Raw Interrupt
Description Value
The capture mode event for Timer A has not occurred. 0
A capture mode event has occurred for Timer A. This interrupt
asserts when the subtimer is configured in Input Edge-Time
mode or when configured in PWMmode with the PWMinterrupt
enabled by setting the TAPWMIE bit in the GPTMTAMR.
1
This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR
register.
0 RO CAERIS 2
GPTM Timer A Capture Mode Match Raw Interrupt
Description Value
The capture mode match for Timer A has not occurred. 0
A capture mode match has occurred for Timer A. This interrupt
asserts when the values in the GPTMTAR and GPTMTAPR
match the values in the GPTMTAMATCHR and GPTMTAPMR
when configured in Input Edge-Time mode.
1
This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR
register.
0 RO CAMRIS 1
GPTM Timer A Time-Out Raw Interrupt
Description Value
Timer A has not timed out. 0
Timer A has timed out. This interrupt is asserted when a
one-shot or periodic mode timer reaches it's count limit (0 or
the value loaded into GPTMTAILR, depending on the count
direction).
1
This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR
register.
0 RO TATORIS 0
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Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WUEMIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TATOMIS CAMMIS CAEMIS RTCMIS TAMMIS reserved TBTOMIS CBMMIS CBEMIS TBMMIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
32/64-Bit Wide GPTM Write Update Error Masked Interrupt Status
Description Value
An unmasked Write Update Error has not occurred. 0
An unmasked Write Update Error has occurred. 1
0 RO WUEMIS 16
0 RO reserved 15:12
GPTM Timer B Match Masked Interrupt
Description Value
A Timer B Mode Match interrupt has not occurred or is masked. 0
An unmasked Timer B Mode Match interrupt
has occurred.
1
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
0 RO TBMMIS 11
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GPTM Timer B Capture Mode Event Masked Interrupt
Description Value
A Capture B event interrupt has not occurred or is masked. 0
An unmasked Capture B event interrupt
has occurred.
1
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
0 RO CBEMIS 10
GPTM Timer B Capture Mode Match Masked Interrupt
Description Value
A Capture B Mode Match interrupt has not occurred or is
masked.
0
An unmasked Capture B Match interrupt
has occurred.
1
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR
register.
0 RO CBMMIS 9
GPTM Timer B Time-Out Masked Interrupt
Description Value
A Timer B Time-Out interrupt has not occurred or is masked. 0
An unmasked Timer B Time-Out interrupt
has occurred.
1
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR
register.
0 RO TBTOMIS 8
0 RO reserved 7:5
GPTM Timer A Match Masked Interrupt
Description Value
A Timer A Mode Match interrupt has not occurred or is masked. 0
An unmasked Timer A Mode Match interrupt
has occurred.
1
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR
register.
0 RO TAMMIS 4
GPTM RTC Masked Interrupt
Description Value
An RTC event interrupt has not occurred or is masked. 0
An unmasked RTC event interrupt
has occurred.
1
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR
register.
0 RO RTCMIS 3
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GPTM Timer A Capture Mode Event Masked Interrupt
Description Value
A Capture A event interrupt has not occurred or is masked. 0
An unmasked Capture A event interrupt
has occurred.
1
This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR
register.
0 RO CAEMIS 2
GPTM Timer A Capture Mode Match Masked Interrupt
Description Value
A Capture A Mode Match interrupt has not occurred or is
masked.
0
An unmasked Capture A Match interrupt
has occurred.
1
This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR
register.
0 RO CAMMIS 1
GPTM Timer A Time-Out Masked Interrupt
Description Value
A Timer A Time-Out interrupt has not occurred or is masked. 0
An unmasked Timer A Time-Out interrupt
has occurred.
1
This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR
register.
0 RO TATOMIS 0
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Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WUECINT reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TATOCINT CAMCINT CAECINT RTCCINT TAMCINT reserved TBTOCINT CBMCINT CBECINT TBMCINT reserved
W1C W1C W1C W1C W1C RO RO RO W1C W1C W1C W1C RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
32/64-Bit Wide GPTM Write Update Error Interrupt Clear
Writing a 1 to this bit clears the WUERIS bit in the GPTMRIS register
and the WUEMIS bit in the GPTMMIS register.
0 R/W WUECINT 16
0 RO reserved 15:12
GPTM Timer B Match Interrupt Clear
Writing a 1 to this bit clears the TBMRIS bit in the GPTMRIS register
and the TBMMIS bit in the GPTMMIS register.
0 W1C TBMCINT 11
GPTM Timer B Capture Mode Event Interrupt Clear
Writing a 1 to this bit clears the CBERIS bit in the GPTMRIS register
and the CBEMIS bit in the GPTMMIS register.
0 W1C CBECINT 10
GPTM Timer B Capture Mode Match Interrupt Clear
Writing a 1 to this bit clears the CBMRIS bit in the GPTMRIS register
and the CBMMIS bit in the GPTMMIS register.
0 W1C CBMCINT 9
GPTM Timer B Time-Out Interrupt Clear
Writing a 1 to this bit clears the TBTORIS bit in the GPTMRIS register
and the TBTOMIS bit in the GPTMMIS register.
0 W1C TBTOCINT 8
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0 RO reserved 7:5
GPTM Timer A Match Interrupt Clear
Writing a 1 to this bit clears the TAMRIS bit in the GPTMRIS register
and the TAMMIS bit in the GPTMMIS register.
0 W1C TAMCINT 4
GPTM RTC Interrupt Clear
Writing a 1 to this bit clears the RTCRIS bit in the GPTMRIS register
and the RTCMIS bit in the GPTMMIS register.
0 W1C RTCCINT 3
GPTM Timer A Capture Mode Event Interrupt Clear
Writing a 1 to this bit clears the CAERIS bit in the GPTMRIS register
and the CAEMIS bit in the GPTMMIS register.
0 W1C CAECINT 2
GPTM Timer A Capture Mode Match Interrupt Clear
Writing a 1 to this bit clears the CAMRIS bit in the GPTMRIS register
and the CAMMIS bit in the GPTMMIS register.
0 W1C CAMCINT 1
GPTM Timer A Time-Out Raw Interrupt
Writing a 1 to this bit clears the TATORIS bit in the GPTMRIS register
and the TATOMIS bit in the GPTMMIS register.
0 W1C TATOCINT 0
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Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028
When the timer is counting down, this register is used to load the starting count value into the timer.
When the timer is counting up, this register sets the upper bound for the timeout event.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit
register (the upper 16-bits correspond to the contents of the GPTM Timer B Interval Load
(GPTMTBILR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no
effect on the state of GPTMTBILR.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAILR contains bits
31:0 of the 64-bit count and the GPTM Timer B Interval Load (GPTMTBILR) register contains bits
63:32.
GPTM Timer A Interval Load (GPTMTAILR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x028
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TAILR
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TAILR
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
GPTM Timer A Interval Load Register
Writing this field loads the counter for Timer A. A read returns the current
value of GPTMTAILR.
0xFFFF.FFFF R/W TAILR 31:0
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Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C
When the timer is counting down, this register is used to load the starting count value into the timer.
When the timer is counting up, this register sets the upper bound for the timeout event.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this
register are loaded into the upper 16 bits of the GPTMTAILRregister. Reads fromthis register return
the current value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load
value. Bits 31:16 are reserved in both cases.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAILR contains bits
31:0 of the 64-bit count and the GPTMTBILR register contains bits 63:32.
GPTM Timer B Interval Load (GPTMTBILR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x02C
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TBILR
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TBILR
1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 Reset
GPTM Timer B Interval Load Register
Writing this field loads the counter for Timer B. A read returns the current
value of GPTMTBILR.
When a 16/32-bit GPTMis in 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
0x0000.FFFF
(for 16/32-bit)
0xFFFF.FFFF
(for 32/64-bit)
R/W TBILR 31:0
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Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030
This register is loaded with a match value. Interrupts can be generated when the timer value is equal
to the value in this register in one-shot or periodic mode.
In Edge-Count mode, this register along with GPTMTAILR, determines how many edge events are
counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this
value. Note that in edge-count mode, when executing an up-count, the value of GPTMTnPR and
GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR.
In PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM
signal.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAMATCHR appears as
a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Match
(GPTMTBMATCHR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and
have no effect on the state of GPTMTBMATCHR.
When a 32/64-bit Wide GPTMis configured to one of the 64-bit modes, GPTMTAMATCHRcontains
bits 31:0 of the 64-bit match value and the GPTM Timer B Match (GPTMTBMATCHR) register
contains bits 63:32.
GPTM Timer A Match (GPTMTAMATCHR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x030
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TAMR
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TAMR
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
GPTM Timer A Match Register
This value is compared to the GPTMTAR register to determine match
events.
0xFFFF.FFFF R/W TAMR 31:0
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Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034
This register is loaded with a match value. Interrupts can be generated when the timer value is equal
to the value in this register in one-shot or periodic mode.
In Edge-Count mode, this register along with GPTMTBILR determines how many edge events are
counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this
value. Note that in edge-count mode, when executing an up-count, the value of GPTMTnPR and
GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR.
In PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM
signal.
register are loaded into the upper 16 bits of the GPTMTAMATCHRregister. Reads fromthis register
return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are
used for the match value. Bits 31:16 are reserved in both cases.
When a 32/64-bit Wide GPTMis configured to one of the 64-bit modes, GPTMTAMATCHRcontains
bits 31:0 of the 64-bit match value and the GPTMTBMATCHR register contains bits 63:32.
GPTM Timer B Match (GPTMTBMATCHR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x034
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TBMR
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TBMR
1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 Reset
GPTM Timer B Match Register
This value is compared to the GPTMTBR register to determine match
events.
0x0000.FFFF
(for 16/32-bit)
0xFFFF.FFFF
(for 32/64-bit)
R/W TBMR 31:0
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Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer
counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the
GPTMTARand GPTMTAV registers are incremented. In all other individual/split modes, this register
is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes
of the 16/32-bit GPTM and bits 47:32 in the 32-bit modes of the 32/64-bit Wide GPTM.
GPTM Timer A Prescale (GPTMTAPR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x038
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TAPSR TAPSRH
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:16
GPTM Timer A Prescale High Byte
The register loads this value on a write. A read returns the current value
of the register.
For the 16/32-bit GPTM, this field is reserved. For the 32/64-bit Wide
GPTM, this field contains the upper 8-bits of the 16-bit prescaler.
Refer to Table 10-5 on page 651 for more details and an example.
0x00 R/W TAPSRH 15:8
GPTM Timer A Prescale
of the register.
For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler.
For the 32/64-bit Wide GPTM, this field contains the lower 8-bits of the
16-bit prescaler.
0x00 R/W TAPSR 7:0
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Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer
counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the
GPTMTBRand GPTMTBV registers are incremented. In all other individual/split modes, this register
is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes
of the 16/32-bit GPTM and bits 47:32 in the 32-bit modes of the 32/64-bit Wide GPTM.
GPTM Timer B Prescale (GPTMTBPR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x03C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TBPSR TBPSRH
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:16
GPTM Timer B Prescale High Byte
of the register.
GPTM, this field contains the upper 8-bits of the 16-bit prescaler.
0x00 R/W TBPSRH 15:8
GPTM Timer B Prescale
of this register.
For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler.
For the 32/64-bit Wide GPTM, this field contains the lower 8-bits of the
16-bit prescaler.
0x00 R/W TBPSR 7:0
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Register 16: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register allows software to extend the range of the GPTMTAMATCHR when the timers are
used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM and bits
47:32 in the 32-bit modes of the 32/64-bit Wide GPTM.
GPTM TimerA Prescale Match (GPTMTAPMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x040
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TAPSMR TAPSMRH
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPTM Timer A Prescale Match High Byte
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
GPTM, this field contains the upper 8-bits of the 16-bit prescale match
value.
0x00 R/W TAPSMRH 15:8
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler
match value. For the 32/64-bit Wide GPTM, this field contains the lower
8-bits of the 16-bit prescaler match value.
0x00 R/W TAPSMR 7:0
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Register 17: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register allows software to extend the range of the GPTMTBMATCHR when the timers are
used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM and bits
47:32 in the 32-bit modes of the 32/64-bit Wide GPTM.
GPTM TimerB Prescale Match (GPTMTBPMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x044
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TBPSMR TBPSMRH
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPTM Timer B Prescale Match High Byte
This value is used alongside GPTMTBMATCHR to detect timer match
GPTM, this field contains the upper 8-bits of the 16-bit prescale match
value.
0x00 R/W TBPSMRH 15:8
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler
match value. For the 32/64-bit Wide GPTM, this field contains the lower
8-bits of the 16-bit prescaler match value.
0x00 R/W TBPSMR 7:0
April 10, 2013 704
Register 18: GPTM Timer A (GPTMTAR), offset 0x048
This register shows the current value of the Timer A counter in all cases except for Input Edge Count
and Time modes. In the Input Edge Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this register contains the time at which the last edge
event took place.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAR appears as a 32-bit
register (the upper 16-bits correspond to the contents of the GPTM Timer B (GPTMTBR) register).
In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of
the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count.
Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic
modes, read bits [23:16] in the GPTMTAV register.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAR contains bits
31:0 of the 64-bit timer value and the GPTM Timer B (GPTMTBR) register contains bits 63:32. In
a 32-bit mode, the value of the prescaler is stored in the GPTM Timer A Prescale Snapshot
(GPTMTAPS) register.
GPTM Timer A (GPTMTAR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x048
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TAR
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TAR
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
GPTM Timer A Register
A read returns the current value of the GPTMTimer A Count Register,
in all cases except for Input Edge Count and Time modes. In the Input
Edge Count mode, this register contains the number of edges that have
occurred. In the Input Edge Time mode, this register contains the time
at which the last edge event took place.
0xFFFF.FFFF RO TAR 31:0
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Register 19: GPTM Timer B (GPTMTBR), offset 0x04C
This register shows the current value of the Timer B counter in all cases except for Input Edge Count
and Time modes. In the Input Edge Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this register contains the time at which the last edge
event took place.
register are loaded into the upper 16 bits of the GPTMTAR register. Reads from this register return
the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits
23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes,
which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler
in 16-bit One-Shot and Periodic modes, read bits [23:16] in the GPTMTBV register.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAR contains bits
31:0 of the 64-bit timer value and the GPTM Timer B (GPTMTBR) register contains bits 63:32. In
a 32-bit mode, the value of the prescaler is stored in the GPTM Timer B Prescale Snapshot
(GPTMTBPS) register.
GPTM Timer B (GPTMTBR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x04C
Type RO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TBR
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TBR
1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 Reset
GPTM Timer B Register
A read returns the current value of the GPTMTimer B Count Register,
in all cases except for Input Edge Count and Time modes. In the Input
Edge Count mode, this register contains the number of edges that have
occurred. In the Input Edge Time mode, this register contains the time
at which the last edge event took place.
0x0000.FFFF
(for 16/32-bit)
0xFFFF.FFFF
(for 32/64-bit)
RO TBR 31:0
April 10, 2013 706
Register 20: GPTM Timer A Value (GPTMTAV), offset 0x050
When read, this register shows the current, free-running value of Timer A in all modes. Software
can use this value to determine the time elapsed between an interrupt and the ISRentry when using
the snapshot feature with the periodic operating mode. When written, the value written into this
register is loaded into the GPTMTAR register on the next clock cycle.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAV appears as a 32-bit
register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (GPTMTBV)
register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the
current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge
Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic
down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down
before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAV contains bits
31:0 of the 64-bit timer value and the GPTM Timer B Value (GPTMTBV) register contains bits
63:32. In a 32-bit mode, the current, free-running value of the prescaler is stored in the GPTMTimer
A Prescale Value (GPTMTAPV) register.mint
GPTM Timer A Value (GPTMTAV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x050
Type RW, reset 0xFFFF.FFFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TAV
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TAV
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
GPTM Timer A Value
A read returns the current, free-running value of Timer A in all modes.
When written, the value written into this register is loaded into the
GPTMTAR register on the next clock cycle.
Note: In 16-bit mode, only the lower 16-bits of the GPTMTAV
register can be written with a new value. Writes to the
prescaler bits have no effect.
0xFFFF.FFFF RW TAV 31:0
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Register 21: GPTM Timer B Value (GPTMTBV), offset 0x054
When read, this register shows the current, free-running value of Timer B in all modes. Software
can use this value to determine the time elapsed between an interrupt and the ISR entry. When
written, the value written into this register is loaded into the GPTMTBR register on the next clock
cycle.
register are loaded into the upper 16 bits of the GPTMTAV register. Reads from this register return
the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter
and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of
the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes.
In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning
bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always
reads as 0.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTBV contains bits
63:32 of the 64-bit timer value and the GPTM Timer A Value (GPTMTAV) register contains bits
31:0. In a 32-bit mode, the current, free-running value of the prescaler is stored in the GPTM Timer
B Prescale Value (GPTMTBPV) register.
GPTM Timer B Value (GPTMTBV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x054
Type RW, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TBV
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TBV
1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 Reset
GPTM Timer B Value
A read returns the current, free-running value of Timer A in all modes.
When written, the value written into this register is loaded into the
GPTMTAR register on the next clock cycle.
Note: In 16-bit mode, only the lower 16-bits of the GPTMTBV
register can be written with a new value. Writes to the
prescaler bits have no effect.
0x0000.FFFF
(for 16/32-bit)
0xFFFF.FFFF
(for 32/64-bit)
RW TBV 31:0
April 10, 2013 708
Register 22: GPTM RTC Predivide (GPTMRTCPD), offset 0x058
This register provides the current RTC predivider value when the timer is operating in RTC mode.
Software must perform an atomic access with consecutive reads of the GPTMTAR, GPTMTBR,
and GPTMRTCPD registers, see Figure 10-2 on page 653 for more information.
GPTM RTC Predivide (GPTMRTCPD)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x058
Type RO, reset 0x0000.7FFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RTCPD
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Reset
RTC Predivide Counter Value
The current RTC predivider value when the timer is operating in RTC
mode. This field has no meaning in other timer modes.
0x0000.7FFF RO RTCPD 15:0
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Register 23: GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C
For the 32/64-bit Wide GPTM, this register shows the current value of the Timer A prescaler in the
32-bit modes. This register is ununsed in 16/32-bit GPTM mode.
GPTM Timer A Prescale Snapshot (GPTMTAPS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x05C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PSS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPTM Timer A Prescaler Snapshot
A read returns the current value of the GPTM Timer A Prescaler.
0x0000 RO PSS 15:0
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Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060
For the 32/64-bit Wide GPTM, this register shows the current value of the Timer B prescaler in the
32-bit modes. This register is ununsed in 16/32-bit GPTM mode.
GPTM Timer B Prescale Snapshot (GPTMTBPS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x060
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PSS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPTM Timer A Prescaler Value
A read returns the current value of the GPTM Timer A Prescaler.
0x0000 RO PSS 15:0
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Register 25: GPTM Timer A Prescale Value (GPTMTAPV), offset 0x064
For the 32/64-bit Wide GPTM, this register shows the current free-running value of the Timer A
prescaler in the 32-bit modes. Software can use this value in conjunction with the GPTMTAV register
to determine the time elapsed between an interrupt and the ISR entry. This register is ununsed in
16/32-bit GPTM mode.
GPTM Timer A Prescale Value (GPTMTAPV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x064
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PSV
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPTM Timer A Prescaler Value
A read returns the current, free-running value of the Timer A prescaler.
0x0000 RO PSV 15:0
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Register 26: GPTM Timer B Prescale Value (GPTMTBPV), offset 0x068
For the 32/64-bit Wide GPTM, this register shows the current free-running value of the Timer B
prescaler in the 32-bit modes. Software can use this value in conjunction with the GPTMTBV register
to determine the time elapsed between an interrupt and the ISR entry. This register is ununsed in
16/32-bit GPTM mode.
GPTM Timer B Prescale Value (GPTMTBPV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0x068
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PSV
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPTM Timer B Prescaler Value
A read returns the current, free-running value of the Timer A prescaler.
0x0000 RO PSV 15:0
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Register 27: GPTM Peripheral Properties (GPTMPP), offset 0xFC0
The GPTMPP register provides information regarding the properties of the General-Purpose Timer
module.
GPTM Peripheral Properties (GPTMPP)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
Offset 0xFC0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SIZE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
Count Size
Description Value
Timer A and Timer B counters are 16 bits each with an 8-bit
prescale counter.
0
Timer A and Timer B counters are 32 bits each with a 16-bit
prescale counter.
1
0x0 RO SIZE 3:0
April 10, 2013 714
11 Watchdog Timers
A watchdog timer can generate a non-maskable interrupt (NMI), a regular interrupt or a reset when
a time-out value is reached. The watchdog timer is used to regain control when a system has failed
due to a software error or due to the failure of an external device to respond in the expected way.
The TM4C123AH6PM microcontroller has two Watchdog Timer Modules, one module is clocked
by the system clock (Watchdog Timer 0) and the other (Watchdog Timer 1) is clocked by the PIOSC
The two modules are identical except that WDT1 is in a different clock domain, and therefore requires
synchronizers. As a result, WDT1 has a bit defined in the Watchdog Timer Control (WDTCTL)
register to indicate when a write to a WDT1 register is complete. Software can use this bit to ensure
that the previous access has completed before starting the next access.
The TM4C123AH6PM controller has two Watchdog Timer modules with the following features:
32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking and optional NMI function
Lock register protection from runaway software
Reset generation logic with an enable/disable
User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
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11.1 Block Diagram
Figure 11-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Down
Counter
0x0000.0000
Interrupt/NMI
System Clock/
PIOSC
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
The watchdog interrupt can be programmed to be a non-maskable interrupt (NMI) using the INTTYPE
bit in the WDTCTL register. After the first time-out event, the 32-bit counter is re-loaded with the
value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down
from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock
(WDTLOCK) register is written, which prevents the timer configuration from being inadvertently
altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled by setting the RESEN bit in the WDTCTL register, the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
April 10, 2013 716
Watchdog Timers
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
The watchdog timer is enabled during the boot process in hardware. Once the boot process is
completed, the watchdog timer is disabled. To achieve maximumwatchdog protection of the device,
the watchdog timer can be re-enabled at the start of the reset vector. This leaves the watchdog
timer disabled only for the amount of time it takes to re-enable it.
11.2.1 Register Access Timing
Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be
written with a timing gap between accesses. Software must guarantee that this delay is inserted
between back-to-back writes to WDT1 registers or between a write followed by a read to the registers.
The timing for back-to-back reads from the WDT1 module has no restrictions. The WRC bit in the
Watchdog Control (WDTCTL) register for WDT1 indicates that the required timing gap has elapsed.
This bit is cleared on a write operation and set once the write completes, indicating to software that
another write or read may be started safely. Software should poll WDTCTL for WRC=1 prior to
accessing another register. Note that WDT0 does not have this restriction as it runs off the system
clock.
To use the WDT, its peripheral clock must be enabled by setting the Rn bit in the Watchdog Timer
Run Mode Clock Gating Control (RCGCWD) register, see page 319.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If WDT1, wait for the WRC bit in the WDTCTL register to be set.
3. If the Watchdog is configured to trigger systemresets, set the RESEN bit in the WDTCTL register.
4. If WDT1, wait for the WRC bit in the WDTCTL register to be set.
5. Set the INTEN bit in the WDTCTL register to enable the Watchdog, enable interrupts, and lock
the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
To service the watchdog, periodically reload the count value into the WDTLOAD register to restart
the count. The interrupt can be enabled using the INTEN bit in the WDTCTL register to allow the
processor to attempt corrective action if the watchdog is not serviced often enough. The RESEN bit
in WDTCTL can be set so that the system resets if the failure is not recoverable using the ISR.
11.4 Register Map
Table 11-1 on page 718 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register's address, relative to the Watchdog Timer base address:
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WDT0: 0x4000.0000
WDT1: 0x4000.1000
Note that the Watchdog Timer module clock must be enabled before the registers can be programmed
(see page 319).
Table 11-1. Watchdog Timers Register Map
See
page
719 Watchdog Load 0xFFFF.FFFF R/W WDTLOAD 0x000
720 Watchdog Value 0xFFFF.FFFF RO WDTVALUE 0x004
721 Watchdog Control
0x0000.0000
(WDT0)
0x8000.0000
(WDT1)
R/W WDTCTL 0x008
723 Watchdog Interrupt Clear - WO WDTICR 0x00C
724 Watchdog Raw Interrupt Status 0x0000.0000 RO WDTRIS 0x010
725 Watchdog Masked Interrupt Status 0x0000.0000 RO WDTMIS 0x014
726 Watchdog Test 0x0000.0000 R/W WDTTEST 0x418
727 Watchdog Lock 0x0000.0000 R/W WDTLOCK 0xC00
728 Watchdog Peripheral Identification 4 0x0000.0000 RO WDTPeriphID4 0xFD0
731 Watchdog Peripheral Identification 7 0x0000.0000 RO WDTPeriphID7 0xFDC
732 Watchdog Peripheral Identification 0 0x0000.0005 RO WDTPeriphID0 0xFE0
735 Watchdog Peripheral Identification 3 0x0000.0001 RO WDTPeriphID3 0xFEC
736 Watchdog PrimeCell Identification 0 0x0000.000D RO WDTPCellID0 0xFF0
737 Watchdog PrimeCell Identification 1 0x0000.00F0 RO WDTPCellID1 0xFF4
738 Watchdog PrimeCell Identification 2 0x0000.0006 RO WDTPCellID2 0xFF8
739 Watchdog PrimeCell Identification 3 0x0000.00B1 RO WDTPCellID3 0xFFC
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
April 10, 2013 718
Watchdog Timers
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WDTLOAD
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WDTLOAD
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
Watchdog Load Value 0xFFFF.FFFF R/W WDTLOAD 31:0
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Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WDTVALUE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WDTVALUE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
Watchdog Value
Current value of the 32-bit down counter.
0xFFFF.FFFF RO WDTVALUE 31:0
April 10, 2013 720
Watchdog Timers
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled by setting the INTEN bit, all subsequent writes to
the INTEN bit are ignored. The only mechanism that can re-enable writes to this bit is a hardware
reset.
Important: Because the Watchdog Timer 1 module has an independent clocking domain, its
registers must be written with a timing gap between accesses. Software must guarantee
that this delay is inserted between back-to-back writes to WDT1 registers or between
a write followed by a read to the registers. The timing for back-to-back reads from the
WDT1 module has no restrictions. The WRC bit in the Watchdog Control (WDTCTL)
register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared
on a write operation and set once the write completes, indicating to software that another
write or read may be started safely. Software should poll WDTCTL for WRC=1 prior to
accessing another register. Note that WDT0 does not have this restriction as it runs off
the system clock and therefore does not have a WRC bit.
Watchdog Control (WDTCTL)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x008
Type R/W, reset 0x0000.0000 (WDT0) and 0x8000.0000 (WDT1)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved WRC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTEN RESEN INTTYPE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Write Complete
The WRC values are defined as follows:
Description Value
A write access to one of the WDT1 registers is in progress. 0
A write access is not in progress, and WDT1 registers can be
read or written.
1
Note: This bit is reserved for WDT0 and has a reset value of 0.
1 RO WRC 31
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Watchdog Interrupt Type
The INTTYPE values are defined as follows:
Description Value
Watchdog interrupt is a standard interrupt. 0
Watchdog interrupt is a non-maskable interrupt. 1
0 R/W INTTYPE 2
Watchdog Reset Enable
The RESEN values are defined as follows:
Description Value
Disabled. 0
Enable the Watchdog module reset output. 1
0 R/W RESEN 1
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Description Value
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
0
Interrupt event enabled. Once enabled, all writes are ignored.
Setting this bit enables the Watchdog Timer.
1
0 R/W INTEN 0
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Watchdog Timers
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Write to this register when a
watchdog time-out interrupt has occurred to properly service the Watchdog. Value for a read or
reset is indeterminate.
Watchdog Interrupt Clear (WDTICR)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x00C
Type WO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WDTINTCLR
- - - - - - - - - - - - - - - - Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WDTINTCLR
- - - - - - - - - - - - - - - - Reset
Watchdog Interrupt Clear - WO WDTINTCLR 31:0
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Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WDTRIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Watchdog Raw Interrupt Status
Description Value
A watchdog time-out event has occurred. 1
The watchdog has not timed out. 0
0 RO WDTRIS 0
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Watchdog Timers
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x014
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WDTMIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Watchdog Masked Interrupt Status
Description Value
A watchdog time-out event has been signalled to the interrupt
controller.
1
The watchdog has not timed out or the watchdog timer interrupt
is masked.
0
0 RO WDTMIS 0
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Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x418
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved STALL reserved
RO RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Watchdog Stall Enable
Description Value
If the microcontroller is stopped with a debugger, the watchdog
timer stops counting. Once the microcontroller is restarted, the
watchdog timer resumes counting.
1
The watchdog timer continues counting if the microcontroller is
stopped with a debugger.
0
0 R/W STALL 8
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Watchdog Timers
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers, except for the Watchdog Test (WDTTEST) register. The locked state will be enabled
after 2 clock cycles. Reading the WDTLOCK register returns the lock status rather than the 32-bit
value written. Therefore, when write accesses are disabled, reading the WDTLOCKregister returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xC00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WDTLOCK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WDTLOCK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates, except for the WDTTEST register. Avoid writes
to the WDTTEST register when the watchdog registers are locked.
A read of this register returns the following values:
Description Value
Locked 0x0000.0001
Unlocked 0x0000.0000
0x0000.0000 R/W WDTLOCK 31:0
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Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFD0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID4 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
WDT Peripheral ID Register [7:0] 0x00 RO PID4 7:0
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Watchdog Timers
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFD4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID5 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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0xFD8
value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFD8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID6 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
April 10, 2013 730
Watchdog Timers
0xFDC
value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFDC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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0xFE0
value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFE0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID0 reserved
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Watchdog Peripheral ID Register [7:0] 0x05 RO PID0 7:0
April 10, 2013 732
Watchdog Timers
0xFE4
value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFE4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID1 reserved
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Reset
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0xFE8
value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFE8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID2 reserved
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Reset
April 10, 2013 734
Watchdog Timers
0xFEC
value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFEC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID3 reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFF0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID0 reserved
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Watchdog PrimeCell ID Register [7:0] 0x0D RO CID0 7:0
April 10, 2013 736
Watchdog Timers
value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFF4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID1 reserved
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Reset
Watchdog PrimeCell ID Register [15:8] 0xF0 RO CID1 7:0
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value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFF8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID2 reserved
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Watchdog PrimeCell ID Register [23:16] 0x06 RO CID2 7:0
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Watchdog Timers
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
value.
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFFC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID3 reserved
1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset
Watchdog PrimeCell ID Register [31:24] 0xB1 RO CID3 7:0
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12 Analog-to-Digital Converter (ADC)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number. Two identical converter modules are included, which share 12 input channels.
The TM4C123AH6PM ADC module features 12-bit conversion resolution and supports 12 input
channels, plus an internal temperature sensor. Each ADC module contains four programmable
sequencers allowing the sampling of multiple analog input sources without controller intervention.
Each sample sequencer provides flexible programming with fully configurable input source, trigger
events, interrupt generation, and sequencer priority. In addition, the conversion value can optionally
be diverted to a digital comparator module. Each ADC module provides eight digital comparators.
Each digital comparator evaluates the ADC conversion value against its two user-defined values to
determine the operational range of the signal. The trigger source for ADC0 and ADC1 may be
independent or the two ADC modules may operate from the same trigger source and operate on
the same or different inputs. A phase shifter can delay the start of sampling by a specified phase
angle. When using both ADC modules, it is possible to configure the converters to start the
conversions coincidentally or within a relative phase from each other, see Sample Phase
Control on page 745.
The TM4C123AH6PM microcontroller provides two ADC modules with each having the following
features:
12 shared analog input channels
12-bit precision ADC
Single-ended and differential-input configurations
On-chip internal temperature sensor
Maximum sample rate of one million samples/second
Optional phase shift in sample time programmable from 22.5 to 337.5
Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
Flexible trigger control
Controller (software)
Timers
Analog Comparators
PWM
GPIO
Hardware averaging of up to 64 samples
Digital comparison unit providing eight digital comparators
Converter uses VDDA and GNDA as the voltage reference
April 10, 2013 740
Power and ground for the analog circuitry is separate from the digital power and ground
Dedicated channel for each sample sequencer
ADC module uses burst requests for DMA
12.1 Block Diagram
The TM4C123AH6PM microcontroller contains two identical Analog-to-Digital Converter modules.
These two modules, ADC0 and ADC1, share the same 12 analog input channels. Each ADCmodule
operates independently and can therefore execute different sample sequences, sample any of the
analog input channels at any time, and generate different interrupts and triggers. Figure
12-1 on page 741 shows how the two modules are connected to analog inputs and the system bus.
Figure 12-1. Implementation of Two ADC Blocks
Input
Channels
Triggers
Interrupts/
Triggers
ADC 0
ADC 1
Interrupts/
Triggers
Figure 12-2 on page 742 provides details on the internal configuration of the ADC controls and data
registers.
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Figure 12-2. ADC Module Block Diagram
Analog Inputs
(AINx)
Trigger Events
SS0 Interrupt
SS1 Interrupt
SS2 Interrupt
SS3 Interrupt
ADCISC
ADCRIS
ADCIM
Interrupt Control
ADCDCISC
SS0
SS1
SS2
SS3
Comparator
GPIO
Timer
PWM
Comparator
GPIO
Timer
PWM
Comparator
GPIO
Timer
PWM
Comparator
GPIO
Timer
PWM
ADCEMUX
ADCPSSI
Digital
Comparator
ADCSSOPn
ADCSSDCn
ADCDCCTLn
ADCDCCMPn
Analog-to-Digital
Converter
Hardware Averager
ADCSAC
ADCSSFSTAT0
ADCSSCTL0
ADCSSEMUX0
Sample
Sequencer 0
ADCSSFSTAT1
ADCSSCTL1
ADCSSEMUX1
Sample
Sequencer 1
ADCSSFSTAT2
ADCSSCTL2
ADCSSEMUX2
Sample
Sequencer 2
ADCSSFSTAT3
ADCSSCTL3
ADCSSEMUX3
Sample
Sequencer 3
PWM Trigger
DC Interrupts
VDDA/GNDA
FIFO Block
ADCSSFIFO0
ADCSSFIFO1
ADCSSFIFO2
ADCSSFIFO3
ADCDCRIC
ADCSSMUX0
ADCSSMUX3
ADCSSMUX1
ADCSSMUX2
Control/Status
ADCUSTAT
ADCOSTAT
ADCACTSS
ADCSSPRI
ADCSPC
ADCPP
ADCPC
ADCTSSEL
ADCCC
The following table lists the external signals of the ADC module and describes the function of each.
The AINx signals are analog functions for some GPIO signals. The column in the table below titled
"Pin Mux/Pin Assignment" lists the GPIO pin placement for the ADC signals. These signals are
configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register
and setting the corresponding AMSEL bit in the GPIOAnalog Mode Select (GPIOAMSEL) register.
For more information on configuring GPIOs, see General-Purpose Input/Outputs
Table 12-1. ADC Signals (64LQFP)
a
Assignment
Pin Number Pin Name
Analog-to-digital converter input 0. Analog I PE3 6 AIN0
Analog-to-digital converter input 4. Analog I PD3 64 AIN4
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Table 12-1. ADC Signals (64LQFP) (continued)
a
Assignment
Pin Number Pin Name
Analog-to-digital converter input 10. Analog I PB4 58 AIN10
The TM4C123AH6PMADCcollects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approaches found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the
ADC to collect data from multiple input sources without having to be re-configured or serviced by
the processor. The programming of each sample in the sample sequence includes parameters such
as the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence. In addition, the DMA can be
used to more efficiently move data from the sample sequencers without CPU intervention.
12.3.1 Sample Sequencers
The sampling control and data capture is handled by the sample sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 12-2 on page 743 shows the maximum number of samples that each sequencer
can capture and its corresponding FIFO depth. Each sample that is captured is stored in the FIFO.
In this implementation, each FIFO entry is a 32-bit word, with the lower 12 bits containing the
conversion result.
Table 12-2. Samples and FIFO Depth of Sequencers
Depth of FIFO Number of Samples Sequencer
1 1 SS3
4 4 SS2
4 4 SS1
8 8 SS0
For a given sample sequence, each sample is defined by bit fields in the ADC Sample Sequence
Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn)
registers, where "n" corresponds to the sequence number. The ADCSSMUXn fields select the input
pin, while the ADCSSCTLn fields contain the sample control bits corresponding to parameters such
as temperature sensor selection, interrupt enable, end of sequence, and differential input mode.
Sample sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample
Sequencer (ADCACTSS) register and should be configured before being enabled. Sampling is
then initiated by setting the SSn bit in the ADC Processor Sample Sequence Initiate (ADCPSSI)
register. In addition, sample sequences may be initiated on multiple ADC modules simultaneously
using the GSYNC and SYNCWAIT bits in the ADCPSSI register during the configuration of each ADC
module. For more information on using these bits, refer to page 786.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
are allowed. In the ADCSSCTLn register, the IEn bits can be set for any combination of samples,
allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END
bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END
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bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete
execution of the sample sequence after the fifth sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFOhead and tail pointers are visible in the ADCSample Sequence FIFOStatus (ADCSSFSTATn)
registers along with FULL and EMPTY status flags. If a write is attempted when the FIFO is full, the
write does not occur and an overflow condition is indicated. Overflow and underflow conditions are
monitored using the ADCOSTAT and ADCUSTAT registers.
12.3.2 Module Control
Outside of the sample sequencers, the remainder of the control logic is responsible for tasks such
as:
Interrupt generation
DMA operation
Sequence prioritization
Trigger configuration
Comparator configuration
Sample phase control
Module clocking
Most of the ADC control logic runs at the ADC clock rate of 16 MHz. The internal ADC divider is
configured for 16-MHz operation automatically by hardware when the systemXTAL is selected with
the PLL.
12.3.2.1 Interrupts
The register configurations of the sample sequencers and digital comparators dictate which events
generate raw interrupts, but do not have control over whether the interrupt is actually sent to the
interrupt controller. The ADC module's interrupt signals are controlled by the state of the MASK bits
in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the
ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of the various interrupt
signals; and the ADC Interrupt Status and Clear (ADCISC) register, which shows active interrupts
that are enabled by the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the
corresponding IN bit in ADCISC. Digital comparator interrupts are cleared by writing a 1 to the ADC
Digital Comparator Interrupt Status and Clear (ADCDCISC) register.
12.3.2.2 DMA Operation
DMAmay be used to increase efficiency by allowing each sample sequencer to operate independently
and transfer data without processor intervention or reconfiguration. The ADC module provides a
request signal from each sample sequencer to the associated dedicated channel of the DMA
controller. The ADC does not support single transfer requests. A burst transfer request is asserted
when the interrupt bit for the sample sequence is set (IE bit in the ADCSSCTLn register is set).
The arbitration size of the DMA transfer must be a power of 2, and the associated IE bits in the
ADCSSCTLn register must be set. For example, if the DMA channel of SS0 has an arbitration
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size of four, the IE3 bit (4th sample) and the IE7 bit (8th sample) must be set. Thus the DMA
request occurs every time 4 samples have been acquired. No other special steps are needed to
enable the ADC module for DMA operation.
Refer to the Micro Direct Memory Access (DMA) on page 527 for more details about programming
the DMA controller.
12.3.2.3 Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample
sequencer units with the same priority do not provide consistent results, so software must ensure
that all active sample sequencer units have a unique priority value.
12.3.2.4 Sampling Events
Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. Trigger sources include processor (default), analog comparators, an external
signal on a GPIO specified by the GPIO ADC Control (GPIOADCCTL) register, a GP Timer, a
PWM generator, and continuous sampling. The processor triggers sampling by setting the SSx bits
in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
Care must be taken when using the continuous sampling trigger. If a sequencer's priority is too high,
it is possible to starve other lower priority sequencers. Generally, a sample sequencer using
continuous sampling should be set to the lowest priority. Continuous sampling can be used with a
digital comparator to cause an interrupt when a particular voltage is seen on an input.
12.3.2.5 Sample Phase Control
The trigger source for ADC0 and ADC1 may be independent or the two ADC modules may operate
from the same trigger source and operate on the same or different inputs. If the converters are
running at the same sample rate, they may be configured to start the conversions coincidentally or
with one of 15 different discrete phases relative to each other. The sample time can be delayed
from the standard sampling time in 22.5 increments up to 337.5 using the ADC Sample Phase
Control (ADCSPC) register. Figure 12-3 on page 745 shows an example of various phase
relationships at a 1 Msps rate.
Figure 12-3. ADC Sample Phases
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ADC Sample Clock
PHASE 0x0 (0.0)
PHASE 0x1 (22.5)
PHASE 0xE (315.0)
PHASE 0xF (337.5)
.
.
.
.
.
.
.
.
.
.
.
.
19
This feature can be used to double the sampling rate of an input. Both ADC module 0 and ADC
module 1 can be programmed to sample the same input. ADCmodule 0 could sample at the standard
position (the PHASE field in the ADCSPCregister is 0x0). ADCmodule 1 can be configured to sample
at 180 (PHASE = 0x8). The two modules can be be synchronized using the GSYNC and SYNCWAIT
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bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. Software could then
combine the results from the two modules to create a sample rate of two million samples/second
at 16 MHz as shown in Figure 12-4 on page 746.
Figure 12-4. Doubling the ADC Sample Rate
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
ADC Sample Clock
GSYNC
ADC 0 PHASE 0x0 (0.0)
ADC 1 PHASE 0x8 (180.0)
18
Using the ADCSPC register, ADC0 and ADC1 may provide a number of interesting applications:
Coincident sampling of different signals. The sample sequence steps run coincidently in both
converters.
ADC Module 0, ADCSPC = 0x0, sampling AIN0
Skewed sampling of the same signal. The sample sequence steps are 1/2 of an ADC clock (500
s for a 1Ms/s ADC) out of phase with each other. This configuration doubles the conversion
bandwidth of a single input when software combines the results as shown in Figure
12-5 on page 746.
Figure 12-5. Skewed Sampling
S1
S2
S2
S3
S3
S4
S4
S5
S5
S6
S6
S7
S7
S8
S8
ADC0
ADC1
S1
April 10, 2013 746
12.3.2.6 Module Clocking
The module is clocked by a 16-MHz clock which can be sourced by a divided version of the PLL
output, the PIOSC or an external source connected to MOSC (with the PLL in bypass mode). When
the PLL is operating, the ADC clock is derived from the PLL 25 by default. However, the PIOSC
can be used for the module clock using the ADC Clock Configuration (ADCCC) register. To use
the PIOSC to clock the ADC, first power up the PLL and then enable the PIOSC in the CS bit field
in the ADCCC register, then disable the PLL. When the PLL is bypassed, the module clock source
clock attached to the MOSC must be 16 MHz unless the PIOSC is used for the clock source. To
use the MOSC to clock the ADC, first power up the PLL and then enable the clock to the ADC
module, then disable the PLL and switch to the MOSC for the system clock. The ADC module can
continue to operate in Deep-Sleep mode if the PIOSC is the ADC module clock source.
The system clock must be at the same frequency or higher than the ADC clock. All ADC modules
share the same clock source to facilitate the synchronization of data samples between conversion
units, the selection and programming of which is provided by ADC0's ADCCC register. The ADC
modules do not run at different conversion rates.
12.3.2.7 Busy Status
The BUSY bit of the ADCACTSS register is used to indicate when the ADC is busy with a current
conversion. When there are no triggers pending which may start a new conversion in the immediate
cycle or next few cycles, the BUSY bit reads as 0. Software must read the status of the BUSY bit as
clear before disabling the ADC clock by writing to the Analog-to-Digital Converter Run Mode
Clock Gating Control (RCGCADC) register.
12.3.2.8 Dither Enable
The ADCCTL register provides a dither enable bit to reduce random noise in ADC sampling. The
DITHER bit is disabled by default at reset. For dither accuracy, please refer to Electrical
Characteristics on page 1183.
12.3.3 Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off, and all data fromthe converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 788). A single averaging circuit has been implemented, thus all input channels
receive the same amount of averaging whether they are single-ended or differential.
Figure 12-6 shows an example in which the ADCSAC register is set to 0x2 for 4x hardware
oversampling and the IE1 bit is set for the sample sequence, resulting in an interrupt after the
second averaged value is stored in the FIFO.
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Figure 12-6. Sample Averaging Example
A+B+C+D
4
A+B+C+D
4
INT
12.3.4 Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR)
architecture to deliver a 12-bit, low-power, high-precision conversion value. The successive
approximation uses a switched capacitor array to performthe dual functions of sampling and holding
the signal as well as providing the 12-bit DAC operation. The ADC requires a 16-MHz clock. This
clock can be a divided version of the PLL output, the PIOSC or a 16-MHz clock source connected
to MOSC. The MOSC provides the best results, followed by the PLL divided down, and then the
PIOSC. Figure 12-7 shows the ADC input equivalency diagram; for parameter values, see
Analog-to-Digital Converter (ADC) on page 1210.
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Figure 12-7. ADC Input Equivalency Diagram
Rs
Cs
C
ADC
Pin
V
S
I
L
Zs
5VESD
Clamp
R
ADC
InputPAD
Equivalent
Circuit Z
ADC
InputPAD
Equivalent
Circuit
R
ADC
InputPAD
Equivalent
Circuit
R
ADC
12bit
SARADC
Converter
Pin
Pin
Tiva Microcontroller
12bit
Word
V
ADCIN
ESDclamps
toGNDonly
The ADC operates from both the 3.3-V analog and 1.2-V digital power supplies. The ADC clock can
be configured to reduce power consumption when ADC conversions are not required (see System
Control on page 214). The analog inputs are connected to the ADCthrough specially balanced input
paths to minimize the distortion and cross-talk on the inputs. Detailed information on the ADCpower
supplies and analog inputs can be found in Analog-to-Digital Converter (ADC) on page 1210.
12.3.4.1 Voltage Reference
The ADC uses internal signals VREFP and VREFN as references to produce a conversion value
from the selected analog input. VREFP is connected to VDDA and VREFN is connected to GNDA.
as shown in Figure 12-8.
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Figure 12-8. ADC Voltage Reference
VREFP
VDDA
VREFN
GNDA ADC
VDDA
GNDA
The range of this conversion value is from 0x000 to 0xFFF. In single-ended-input mode, the 0x000
value corresponds to the voltage level on VREFN; the 0xFFF value corresponds to the voltage level
on VREFP. This configuration results in a resolution that can be calculated using the following
equation:
mV per ADC code = (VREFP - VREFN) / 4096
While the analog input pads can handle voltages beyond this range, the ADC conversions saturate
in under-voltage and over-voltage cases. Analog input voltages above VREFP saturate at 0xFFF
while those below VREFN saturate at 0x000. Figure 12-9 on page 751 shows the ADC conversion
function of the analog inputs.
April 10, 2013 750
Figure 12-9. ADC Conversion Result
0xFFF
V
IN
0xC00
0x800
0x400
V
R
E
F
N
V
R
E
F
P
(
V
R
E
F
P
-
V
R
E
F
N
)
(
V
R
E
F
P
-
V
R
E
F
N
)
(
V
R
E
F
P
-
V
R
E
F
N
)
- Input Saturation
12.3.5 Differential Sampling
In addition to traditional single-ended sampling, the ADC module supports differential sampling of
two analog input channels. To enable differential sampling, software must set the Dn bit in the
ADCSSCTL0n register in a step's configuration nibble.
When a sequence step is configured for differential sampling, the input pair to sample must be
configured in the ADCSSMUXn register. Differential pair 0 samples analog inputs 0 and 1; differential
pair 1 samples analog inputs 2 and 3; and so on (see Table 12-3 on page 751). The ADC does not
support other differential pairings such as analog input 0 with analog input 3.
Table 12-3. Differential Sampling Pairs
Analog Inputs Differential Pair
0 and 1 0
2 and 3 1
4 and 5 2
6 and 7 3
8 and 9 4
10 and 11 5
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The voltage sampled in differential mode is the difference between the odd and even channels:
Input Positive Voltage: VIN+ = V
IN_EVEN
(even channel)
Input Negative Voltage: VIN- = V
IN_ODD
(odd channel)
The input differential voltage is defined as: VIN
D
= VIN+ - VIN-, therefore:
If VIN
D
= 0, then the conversion result = 0x800
If VIN
D
> 0, then the conversion result > 0x800 (range is 0x8000xFFF)
If VIN
D
< 0, then the conversion result < 0x800 (range is 00x800)
When using differential sampling, the following definitions are relevant:
Input Common Mode Voltage: VIN
CM
= (VIN+ + VIN-) / 2
Reference Positive Voltage: VREFP
Reference Negative Voltage: VREFN
Reference Differential Voltage: VREF
D
= VREFP - VREFN
Reference Common Mode Voltage: VREF
CM
= (VREFP + VREFN) / 2
The following conditions provide optimal results in differential mode:
Both V
IN_EVEN
and V
IN_ODD
must be in the range of (VREFP to VREFN) for a valid conversion
result
The maximum possible differential input swing, or the maximum differential range, is: -VREF
D
to
+VREF
D
, so the maximum peak-to-peak input differential signal is (+VREF
D
- -VREF
D
) = 2 *
VREF
D
= 2 * (VREFP - VREFN)
In order to take advantage of the maximum possible differential input swing, VIN
CM
should be
very close to VREF
CM
, see Table 22-29 on page 1210.
If VIN
CM
is not equal to VREF
CM
, the differential input signal may clip at either maximumor minimum
voltage, because either single ended input can never be larger than VREFP or smaller than VREFN,
and it is not possible to achieve full swing. Thus any difference in common mode between the input
voltage and the reference voltage limits the differential dynamic range of the ADC.
Because the maximum peak-to-peak differential signal voltage is 2 * (VREFP - VREFN), the ADC
codes are interpreted as:
mV per ADC code = (2 *(VREFP - VREFN)) / 4096
Figure 12-10 shows how the differential voltage, V, is represented in ADC codes.
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Figure 12-10. Differential Voltage Representation
0 VREFP - VREFN
V
0xFFF
0x800
- Input Saturation
-(VREFP - VREFN)
12.3.6 Internal Temperature Sensor
The temperature sensor's primary purpose is to notify the system that the internal temperature is
too high or low for reliable operation.
The temperature sensor does not have a separate enable, because it also contains the bandgap
reference and must always be enabled. The reference is supplied to other analog modules; not just
the ADC.
The internal temperature sensor converts a temperature measurement into a voltage. This voltage
value, V
TSENS
, is given by the following equation (where TEMP is the temperature in C):
V
TSENS
= 2.7 - ((TEMP + 55) / 75)
This relation is shown in Figure 12-11 on page 754.
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Figure 12-11. Internal Temperature Sensor Characteristic
V
TSENS
V
TSENS
= 2.7 V
(TEMP+55)
75
2.5 V
1.633 V
0.833 V
Temp 85 C -40 C 25 C
The temperature sensor reading can be sampled in a sample sequence by setting the TSn bit in
the ADCSSCTLn register. The temperature reading from the temperature sensor can also be given
as a function of the ADC value. The following formula calculates temperature (TEMP in ) based
on the ADC reading (ADC
CODE
, given as an unsigned decimal number from 0 to 4095) and the
maximum ADC voltage range (VREFP - VREFN):
TEMP = 147.5 - ((75 * (VREFP - VREFN) ADC
CODE
) / 4096)
12.3.7 Digital Comparator Unit
An ADC is commonly used to sample an external signal and to monitor its value to ensure that it
remains in a given range. To automate this monitoring procedure and reduce the amount of processor
overhead that is required, each module provides eight digital comparators.
Conversions from the ADC that are sent to the digital comparators are compared against the user
programmable limits in the ADC Digital Comparator Range (ADCDCCMPn) registers. The ADC
can be configured to generate an interrupt depending on whether the ADC is operating within the
low, mid or high-band region configured in the ADCDCCMPn bit fields. The digital comparators four
operational modes (Once, Always, Hysteresis Once, Hysteresis Always) can be additionally applied
to the interrupt configuration.
12.3.7.1 Output Functions
ADC conversions can either be stored in the ADC Sample Sequence FIFOs or compared using the
digital comparator resources as defined by the SnDCOP bits in the ADC Sample Sequence n
Operation (ADCSSOPn) register. These selected ADC conversions are used by their respective
April 10, 2013 754
digital comparator to monitor the external signal. Each comparator has two possible output functions:
processor interrupts and triggers.
Each function has its own state machine to track the monitored signal. Even though the interrupt
and trigger functions can be enabled individually or both at the same time, the same conversion
data is used by each function to determine if the right conditions have been met to assert the
associated output.
Interrupts
The digital comparator interrupt function is enabled by setting the CIE bit in the ADC Digital
Comparator Control (ADCDCCTLn) register. This bit enables the interrupt function state machine
to start monitoring the incoming ADC conversions. When the appropriate set of conditions is met,
and the DCONSSx bit is set in the ADCIM register, an interrupt is sent to the interrupt controller.
Note: Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
Triggers
The digital comparator trigger function is enabled by setting the CTE bit in the ADCDCCTLn register.
This bit enables the trigger function state machine to start monitoring the incoming ADCconversions.
When the appropriate set of conditions is met, the corresponding digital comparator trigger to the
PWM module is asserted
12.3.7.2 Operational Modes
Four operational modes are provided to support a broad range of applications and multiple possible
signaling requirements: Always, Once, Hysteresis Always, and Hysteresis Once. The operational
mode is selected using the CIM or CTM field in the ADCDCCTLn register.
Always Mode
In the Always operational mode, the associated interrupt or trigger is asserted whenever the ADC
conversion value meets its comparison criteria. The result is a string of assertions on the interrupt
or trigger while the conversions are within the appropriate range.
Once Mode
In the Once operational mode, the associated interrupt or trigger is asserted whenever the ADC
conversion value meets its comparison criteria, and the previous ADC conversion value did not.
The result is a single assertion of the interrupt or trigger when the conversions are within the
appropriate range.
Hysteresis-Always Mode
The Hysteresis-Always operational mode can only be used in conjunction with the low-band or
high-band regions because the mid-band region must be crossed and the opposite region entered
to clear the hysteresis condition. In the Hysteresis-Always mode, the associated interrupt or trigger
is asserted in the following cases: 1) the ADC conversion value meets its comparison criteria or 2)
a previous ADC conversion value has met the comparison criteria, and the hysteresis condition has
not been cleared by entering the opposite region. The result is a string of assertions on the interrupt
or trigger that continue until the opposite region is entered.
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Hysteresis-Once Mode
The Hysteresis-Once operational mode can only be used in conjunction with the low-band or
high-band regions because the mid-band region must be crossed and the opposite region entered
to clear the hysteresis condition. In the Hysteresis-Once mode, the associated interrupt or trigger
is asserted only when the ADC conversion value meets its comparison criteria, the hysteresis
condition is clear, and the previous ADC conversion did not meet the comparison criteria. The result
is a single assertion on the interrupt or trigger.
12.3.7.3 Function Ranges
The two comparison values, COMP0 and COMP1, in the ADC Digital Comparator Range
(ADCDCCMPn) register effectively break the conversion area into three distinct regions. These
regions are referred to as the low-band (less than COMP0), mid-band (greater than COMP0 but less
than or equal to COMP1), and high-band (greater than or equal to COMP1) regions. COMP0 and COMP1
may be programmed to the same value, effectively creating two regions, but COMP1 must always
be greater than or equal to the value of COMP0. A COMP1 value that is less than COMP0 generates
unpredictable results.
Low-Band Operation
To operate in the low-band region, the CIC field or the CTC field in the ADCDCCTLn register must
be programmed to 0x0. This setting causes interrupts or triggers to be generated in the low-band
region as defined by the programmed operational mode. An example of the state of the
interrupt/trigger signal in the low-band region for each of the operational modes is shown in Figure
12-12 on page 756. Note that a "0" in a column following the operational mode name (Always, Once,
Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is de-asserted
and a "1" indicates that the signal is asserted.
Figure 12-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Always
Once
Hysteresis Always
Hysteresis Once
COMP0
COMP1
April 10, 2013 756
Mid-Band Operation
To operate in the mid-band region, the CIC field or the CTC field in the ADCDCCTLn register must
be programmed to 0x1. This setting causes interrupts or triggers to be generated in the mid-band
region according the operation mode. Only the Always and Once operational modes are available
in the mid-band region. An example of the state of the interrupt/trigger signal in the mid-band region
for each of the allowed operational modes is shown in Figure 12-13 on page 757. Note that a "0" in
a column following the operational mode name (Always or Once) indicates that the interrupt or
trigger signal is de-asserted and a "1" indicates that the signal is asserted.
Figure 12-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1)
0
0
-
-
0
0
-
-
1
1
-
-
1
0
-
-
0
0
-
-
0
0
-
-
0
0
-
-
1
1
-
-
1
0
-
-
1
0
-
-
0
0
-
-
0
0
-
-
1
1
-
-
1
0
-
-
0
0
-
-
0
0
-
-
Always
Once
Hysteresis Always
Hysteresis Once
COMP0
COMP1
High-Band Operation
To operate in the high-band region, the CIC field or the CTC field in the ADCDCCTLn register must
be programmed to 0x3. This setting causes interrupts or triggers to be generated in the high-band
region according the operation mode. An example of the state of the interrupt/trigger signal in the
high-band region for each of the allowed operational modes is shown in Figure 12-14 on page 758.
Note that a "0" in a column following the operational mode name (Always, Once, Hysteresis Always,
and Hysteresis Once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates
that the signal is asserted.
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Figure 12-14. High-Band Operation (CIC=0x3 and/or CTC=0x3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
Always
Once
Hysteresis Always
Hysteresis Once
COMP0
COMP1
In order for the ADC module to be used, the PLL must be enabled and programmed to a supported
crystal frequency in the RCC register (see page 239). Using unsupported frequencies can cause
faulty operation in the ADC module.
12.4.1 Module Initialization
Initialization of the ADC module is a simple process with very few steps: enabling the clock to the
ADC, disabling the analog isolation circuit associated with all inputs that are to be used, and
reconfiguring the sample sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock using the RCGCADC register (see page 332).
2. Enable the clock to the appropriate GPIO modules via the RCGCGPIOregister (see page 322).
To find out which GPIO ports to enable, refer to Signal Description on page 742.
3. Set the GPIO AFSEL bits for the ADC input pins (see page 612). To determine which GPIOs to
configure, see Table 21-4 on page 1170.
4. Configure the AINx signals to be analog inputs by clearing the corresponding DEN bit in the
GPIO Digital Enable (GPIODEN) register (see page 623).
5. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to
the appropriate bits of the GPIOAMSEL register (see page 628) in the associated GPIO block.
April 10, 2013 758
6. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority and Sample
Sequencer 3 as the lowest priority.
12.4.2 Sample Sequencer Configuration
Configuration of the sample sequencers is slightly more complex than the module initialization
because each sample sequencer is completely programmable.
The configuration for each sample sequencer should be as follows:
1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the
ADCACTSS register. Programming of the sample sequencers is allowed without having them
enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger
event were to occur during the configuration process.
2. Configure the trigger event for the sample sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register.
6. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS
register.
12.5 Register Map
Table 12-4 on page 759 lists the ADC registers. The offset listed is a hexadecimal increment to the
registers address, relative to that ADC module's base address of:
ADC0: 0x4003.8000
ADC1: 0x4003.9000
Note that the ADC module clock must be enabled before the registers can be programmed (see
page 332). There must be a delay of 3 system clocks after the ADC module clock is enabled before
any ADC module registers are accessed.
Table 12-4. ADC Register Map
See
page
762 ADC Active Sample Sequencer 0x0000.0000 R/W ADCACTSS 0x000
764 ADC Raw Interrupt Status 0x0000.0000 RO ADCRIS 0x004
766 ADC Interrupt Mask 0x0000.0000 R/W ADCIM 0x008
769 ADC Interrupt Status and Clear 0x0000.0000 R/W1C ADCISC 0x00C
772 ADC Overflow Status 0x0000.0000 R/W1C ADCOSTAT 0x010
774 ADC Event Multiplexer Select 0x0000.0000 R/W ADCEMUX 0x014
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Table 12-4. ADC Register Map (continued)
See
page
779 ADC Underflow Status 0x0000.0000 R/W1C ADCUSTAT 0x018
780 ADC Trigger Source Select 0x0000.0000 R/W ADCTSSEL 0x01C
782 ADC Sample Sequencer Priority 0x0000.3210 R/W ADCSSPRI 0x020
784 ADC Sample Phase Control 0x0000.0000 R/W ADCSPC 0x024
786 ADC Processor Sample Sequence Initiate - R/W ADCPSSI 0x028
788 ADC Sample Averaging Control 0x0000.0000 R/W ADCSAC 0x030
789 ADC Digital Comparator Interrupt Status and Clear 0x0000.0000 R/W1C ADCDCISC 0x034
791 ADC Control 0x0000.0000 R/W ADCCTL 0x038
792 ADC Sample Sequence Input Multiplexer Select 0 0x0000.0000 R/W ADCSSMUX0 0x040
794 ADC Sample Sequence Control 0 0x0000.0000 R/W ADCSSCTL0 0x044
801 ADC Sample Sequence Result FIFO 0 - RO ADCSSFIFO0 0x048
802 ADC Sample Sequence FIFO 0 Status 0x0000.0100 RO ADCSSFSTAT0 0x04C
804 ADC Sample Sequence 0 Operation 0x0000.0000 R/W ADCSSOP0 0x050
806 ADC Sample Sequence 0 Digital Comparator Select 0x0000.0000 R/W ADCSSDC0 0x054
816 ADC Sample Sequence Input Multiplexer Select 3 0x0000.0000 R/W ADCSSMUX3 0x0A0
817 ADC Sample Sequence Control 3 0x0000.0000 R/W ADCSSCTL3 0x0A4
801 ADC Sample Sequence Result FIFO 3 - RO ADCSSFIFO3 0x0A8
802 ADC Sample Sequence FIFO 3 Status 0x0000.0100 RO ADCSSFSTAT3 0x0AC
819 ADC Sample Sequence 3 Operation 0x0000.0000 R/W ADCSSOP3 0x0B0
820 ADC Sample Sequence 3 Digital Comparator Select 0x0000.0000 R/W ADCSSDC3 0x0B4
April 10, 2013 760
Table 12-4. ADC Register Map (continued)
See
page
821 ADC Digital Comparator Reset Initial Conditions 0x0000.0000 WO ADCDCRIC 0xD00
826 ADC Digital Comparator Control 0 0x0000.0000 R/W ADCDCCTL0 0xE00
826 ADC Digital Comparator Control 3 0x0000.0000 R/W ADCDCCTL3 0xE0C
826 ADC Digital Comparator Control 7 0x0000.0000 R/W ADCDCCTL7 0xE1C
829 ADC Digital Comparator Range 0 0x0000.0000 R/W ADCDCCMP0 0xE40
829 ADC Digital Comparator Range 3 0x0000.0000 R/W ADCDCCMP3 0xE4C
829 ADC Digital Comparator Range 7 0x0000.0000 R/W ADCDCCMP7 0xE5C
830 ADC Peripheral Properties 0x00B0.20C7 RO ADCPP 0xFC0
832 ADC Peripheral Configuration 0x0000.0007 R/W ADCPC 0xFC4
833 ADC Clock Configuration 0x0000.0000 R/W ADCCC 0xFC8
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
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Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the sample sequencers. Each sample sequencer can be
enabled or disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BUSY reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ASEN0 ASEN1 ASEN2 ASEN3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:17
ADC Busy
Description Value
ADC is idle 0
ADC is busy 1
Note: In order to use the BUSY bit, the ADC Event Multiplexer
Select (ADCEMUX) register must be programmed such that
no trigger is selected (bit field encoding is 0xE). The NEVER
encoding in the ADCEMUX register allows the ADC to safely
be put in Deep-Sleep mode.
0 RO BUSY 16
0 RO reserved 15:4
ADC SS3 Enable
Description Value
Sample Sequencer 3 is disabled. 0
Sample Sequencer 3 is enabled. 1
0 R/W ASEN3 3
ADC SS2 Enable
Description Value
0 R/W ASEN2 2
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ADC SS1 Enable
Description Value
0 R/W ASEN1 1
ADC SS0 Enable
Description Value
0 R/W ASEN0 0
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Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each sample sequencer. These bits may
be polled by software to look for interrupt conditions without sending the interrupts to the interrupt
controller.
ADC Raw Interrupt Status (ADCRIS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INRDC reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INR0 INR1 INR2 INR3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Digital Comparator Raw Interrupt Status
Description Value
All bits in the ADCDCISC register are clear. 0
At least one bit in the ADCDCISC register is set, meaning that
a digital comparator interrupt has occurred.
1
0 RO INRDC 16
0 RO reserved 15:4
SS3 Raw Interrupt Status
Description Value
A sample has completed conversion and the respective
ADCSSCTL3 IEn bit is set, enabling a raw interrupt.
1
This bit is cleared by writing a 1 to the IN3 bit in the ADCISC register.
0 RO INR3 3
Description Value
1
0 RO INR2 2
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Description Value
1
0 RO INR1 1
Description Value
1
0 RO INR0 0
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Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the sample sequencer and digital comparator raw interrupt signals
are sent to the interrupt controller. Each raw interrupt signal can be masked independently.
Note: Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
ADC Interrupt Mask (ADCIM)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DCONSS0 DCONSS1 DCONSS2 DCONSS3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MASK0 MASK1 MASK2 MASK3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Digital Comparator Interrupt on SS3
Description Value
The status of the digital comparators does not affect the SS3
interrupt status.
0
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS3 interrupt line.
1
0 R/W DCONSS3 19
Description Value
interrupt status.
0
1
0 R/W DCONSS2 18
April 10, 2013 766
Description Value
interrupt status.
0
1
0 R/W DCONSS1 17
Description Value
interrupt status.
0
1
0 R/W DCONSS0 16
0 RO reserved 15:4
SS3 Interrupt Mask
Description Value
The status of Sample Sequencer 3 does not affect the SS3
interrupt status.
0
The raw interrupt signal from Sample Sequencer 3 (ADCRIS
register INR3 bit) is sent to the interrupt controller.
1
0 R/W MASK3 3
SS2 Interrupt Mask
Description Value
interrupt status.
0
1
0 R/W MASK2 2
SS1 Interrupt Mask
Description Value
interrupt status.
0
1
0 R/W MASK1 1
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SS0 Interrupt Mask
Description Value
interrupt status.
0
1
0 R/W MASK0 0
April 10, 2013 768
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanismfor clearing sample sequencer interrupt conditions and shows
the status of interrupts generated by the sample sequencers and the digital comparators which have
been sent to the interrupt controller. When read, each bit field is the logical AND of the respective
INR and MASK bits. Sample sequencer interrupts are cleared by writing a 1 to the corresponding
bit position. Digital comparator interrupts are cleared by writing a 1 to the appropriate bits in the
ADCDCISC register. If software is polling the ADCRIS instead of generating interrupts, the sample
sequence INRn bits are still cleared via the ADCISC register, even if the INn bit is not set.
ADC Interrupt Status and Clear (ADCISC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x00C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DCINSS0 DCINSS1 DCINSS2 DCINSS3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IN0 IN1 IN2 IN3 reserved
R/W1C R/W1C R/W1C R/W1C RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Digital Comparator Interrupt Status on SS3
Description Value
No interrupt has occurred or the interrupt is masked. 0
Both the INRDC bit in the ADCRIS register and the DCONSS3
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
1
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
0 RO DCINSS3 19
Description Value
1
0 RO DCINSS2 18
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Description Value
1
0 RO DCINSS1 17
Description Value
1
0 RO DCINSS0 16
0 RO reserved 15:4
SS3 Interrupt Status and Clear
Description Value
Both the INR3 bit in the ADCRIS register and the MASK3 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the INR3
bit in the ADCRIS register.
0 R/W1C IN3 3
Description Value
1
0 R/W1C IN2 2
April 10, 2013 770
Description Value
1
0 R/W1C IN1 1
Description Value
1
0 R/W1C IN0 0
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Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OV0 OV1 OV2 OV3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SS3 FIFO Overflow
Description Value
The FIFO has not overflowed. 0
The FIFOfor Sample Sequencer 3 has hit an overflowcondition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
1
This bit is cleared by writing a 1.
0 R/W1C OV3 3
SS2 FIFO Overflow
Description Value
1
0 R/W1C OV2 2
SS1 FIFO Overflow
Description Value
1
0 R/W1C OV1 1
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SS0 FIFO Overflow
Description Value
1
0 R/W1C OV0 0
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Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each
sample sequencer can be configured with a unique trigger source. When using a PWM generator
as the trigger source, use the ADCTrigger Source Select (ADCTSSEL) register to specify in which
PWM module the generator is located.
ADC Event Multiplexer Select (ADCEMUX)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x014
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EM0 EM1 EM2 EM3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
April 10, 2013 774
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
Event Value
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x0
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1050).
0x1
Analog Comparator 1
0x2
reserved 0x3
External (GPIO Pins)
This trigger is connected to the GPIO interrupt for the
corresponding GPIO(see ADCTrigger Source on page 597).
0x4
Note: GPIOs that have AINx signals as alternate
functions can be used to trigger the ADC. However,
the pin cannot be used as both a GPIO and an
analog input.
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 678).
0x5
PWM generator 0
The PWM generator 0 trigger can be configured with the
PWM0 Interrupt and Trigger Enable (PWM0INTEN) register
(page 1097).
0x6
PWM generator 1
PWM1INTEN register (page 1097).
0x7
PWM generator 2
0x8
PWM generator 3
0x9
reserved 0xA-0xE
Always (continuously sample) 0xF
0x0 R/W EM3 15:12
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SS2 Trigger Select
Event Value
Processor (default)
register.
0x0
Analog Comparator 0
0x1
Analog Comparator 1
0x2
reserved 0x3
0x4
analog input.
Timer
0x5
PWM generator 0
(page 1097).
0x6
PWM generator 1
0x7
PWM generator 2
0x8
PWM generator 3
0x9
reserved 0xA-0xE
0x0 R/W EM2 11:8
April 10, 2013 776
SS1 Trigger Select
Event Value
Processor (default)
register.
0x0
Analog Comparator 0
0x1
Analog Comparator 1
0x2
reserved 0x3
0x4
analog input.
Timer
0x5
PWM generator 0
(page 1097).
0x6
PWM generator 1
0x7
PWM generator 2
0x8
PWM generator 3
0x9
reserved 0xA-0xE
0x0 R/W EM1 7:4
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SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0
Event Value
Processor (default)
register.
0x0
Analog Comparator 0
0x1
Analog Comparator 1
0x2
reserved 0x3
0x4
analog input.
Timer
0x5
PWM generator 0
(page 1097).
0x6
PWM generator 1
0x7
PWM generator 2
0x8
PWM generator 3
0x9
reserved 0xA-0xE
0x0 R/W EM0 3:0
April 10, 2013 778
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding
underflow condition is cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
UV0 UV1 UV2 UV3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SS3 FIFO Underflow
The valid configurations for this field are shown below. This bit is cleared
by writing a 1.
Description Value
The FIFO has not underflowed. 0
The FIFO for the Sample Sequencer has hit an underflow
condition, meaning that the FIFO is empty and a read was
requested. The problematic read does not move the FIFO
pointers, and 0s are returned.
1
0 R/W1C UV3 3
SS2 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
0 R/W1C UV2 2
SS1 FIFO Underflow
0 R/W1C UV1 1
SS0 FIFO Underflow
0 R/W1C UV0 0
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Register 8: ADC Trigger Source Select (ADCTSSEL), offset 0x01C
The ADCTSSEL register specifies which PWM module is selected with the EMn bit field in the ADC
Event Multiplexer Select (ADCEMUX) register. The register resets to 0x0000.0000, which selects
PWM module 0 for all generators.
ADC Trigger Source Select (ADCTSSEL)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x01C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved PS2 reserved PS3 reserved
RO RO RO RO R/W R/W RO RO RO RO RO RO R/W R/W RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved PS0 reserved PS1 reserved
RO RO RO RO R/W R/W RO RO RO RO RO RO R/W R/W RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EM3 PWM Module Select
This field selects which PWM module signals are used in the
PWM0-PWM3 encodings of the ADCEMUX register EM3 bit field.
Description Value
PWM module 0 0x0
PWM module 1 0x1
reserved 0x2 - 0x3
0x0 R/W PS3 29:28
Description Value
PWM module 0 0x0
PWM module 1 0x1
reserved 0x2 - 0x3
0x0 R/W PS2 21:20
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Description Value
PWM module 0 0x0
PWM module 1 0x1
reserved 0x2 - 0x3
0x0 R/W PS1 13:12
Description Value
PWM module 0 0x0
PWM module 1 0x1
reserved 0x2 - 0x3
0x0 R/W PS0 5:4
0x0 RO reserved 3:0
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Register 9: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the
highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities,
each sequence must have a unique priority for the ADC to operate properly.
ADC Sample Sequencer Priority (ADCSSPRI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SS0 reserved SS1 reserved SS2 reserved SS3 reserved
R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO Type
0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 Reset
SS3 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
0x3 R/W SS3 13:12
SS2 Priority
fields are equal.
0x2 R/W SS2 9:8
0x0 RO reserved 7:6
SS1 Priority
fields are equal.
0x1 R/W SS1 5:4
0x0 RO reserved 3:2
April 10, 2013 782
SS0 Priority
fields are equal.
0x0 R/W SS0 1:0
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Register 10: ADC Sample Phase Control (ADCSPC), offset 0x024
This register allows the ADC module to sample at one of 16 different discrete phases from 0.0
through 337.5. For example, the sample rate could be effectively doubled by sampling a signal
using one ADC module configured with the standard sample time and the second ADC module
configured with a 180.0 phase lag.
Note: Care should be taken when the PHASE field is non-zero, as the resulting delay in sampling
the AINx input may result in undesirable system consequences. The time from ADC trigger
to sample is increased and could make the response time longer than anticipated. The
added latency could have ramifications in the system design. Designers should carefully
consider the impact of this delay.
ADC Sample Phase Control (ADCSPC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PHASE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
April 10, 2013 784
Phase Difference
This field selects the sample phase difference fromthe standard sample
time.
Description Value
ADC sample lags by 0.0 0x0
ADC sample lags by 225.0 0xA
ADC sample lags by 247.5 0xB
ADC sample lags by 270.0 0xC
ADC sample lags by 292.5 0xD
ADC sample lags by 315.0 0xE
ADC sample lags by 337.5 0xF
0x0 R/W PHASE 3:0
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Register 11: ADCProcessor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the sample
sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
This register also provides a means to configure and then initiate concurrent sampling on all ADC
modules. To do this, the first ADC module should be configured. The ADCPSSI register for that
module should then be written. The appropriate SS bits should be set along with the SYNCWAIT bit.
Additional ADC modules should then be configured following the same procedure. Once the final
ADC module is configured, its ADCPSSI register should be written with the appropriate SS bits set
along with the GSYNC bit. All of the ADC modules then begin concurrent sampling according to their
configuration.
ADC Processor Sample Sequence Initiate (ADCPSSI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x028
Type R/W, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved SYNCWAIT reserved GSYNC
RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SS0 SS1 SS2 SS3 reserved
WO WO WO WO RO RO RO RO RO RO RO RO RO RO RO RO Type
- - - - 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Global Synchronize
Description Value
This bit is cleared once sampling has been initiated. 0
This bit initiates sampling in multiple ADC modules at the same
time. Any ADC module that has been initialized by setting an
SSn bit and the SYNCWAIT bit starts sampling once this bit is
written.
1
0 R/W GSYNC 31
Synchronize Wait
Description Value
Sampling begins when a sample sequence has been initiated. 0
This bit allows the sample sequences to be initiated, but delays
sampling until the GSYNC bit is set.
1
0 R/W SYNCWAIT 27
April 10, 2013 786
SS3 Initiate
Description Value
No effect. 0
Begin sampling on Sample Sequencer 3, if the sequencer is
enabled in the ADCACTSS register.
1
Only a write by software is valid; a read of this register returns no
meaningful data.
- WO SS3 3
SS2 Initiate
Description Value
No effect. 0
1
meaningful data.
- WO SS2 2
SS1 Initiate
Description Value
No effect. 0
1
meaningful data.
- WO SS1 1
SS0 Initiate
Description Value
No effect. 0
1
meaningful data.
- WO SS0 0
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Register 12: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFOis averaged from2
AVG
consecutive ADCsamples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG=7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x030
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
AVG reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Description Value
No hardware oversampling 0x0
2x hardware oversampling 0x1
reserved 0x7
0x0 R/W AVG 2:0
April 10, 2013 788
Register 13: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC),
offset 0x034
This register provides status and acknowledgement of digital comparator interrupts. One bit is
provided for each comparator.
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x034
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DCINT0 DCINT1 DCINT2 DCINT3 DCINT4 DCINT5 DCINT6 DCINT7 reserved
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Digital Comparator 7 Interrupt Status and Clear
Description Value
No interrupt. 0
Digital Comparator 7 has generated an interrupt. 1
0 R/W1C DCINT7 7
Description Value
No interrupt. 0
0 R/W1C DCINT6 6
Description Value
No interrupt. 0
0 R/W1C DCINT5 5
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Description Value
No interrupt. 0
0 R/W1C DCINT4 4
Description Value
No interrupt. 0
0 R/W1C DCINT3 3
Description Value
No interrupt. 0
0 R/W1C DCINT2 2
Description Value
No interrupt. 0
0 R/W1C DCINT1 1
Description Value
No interrupt. 0
0 R/W1C DCINT0 0
April 10, 2013 790
Register 14: ADC Control (ADCCTL), offset 0x038
This register configures the voltage reference.
ADC Control (ADCCTL)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x038
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VREF reserved DITHER reserved
R/W R/W RO RO RO RO R/W RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Dither Mode Enable
Description Value
Dither mode disabled 0
Dither mode enabled 1
0 R/W DITHER 6
0 RO reserved 5:2
Voltage Reference Select
Description Value
VDDA and GNDA are the voltage references. 0x0
Reserved 0x1 - 0x3
0x0 R/W VREF 1:0
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Register 15: ADCSample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 0. This register is 32 bits wide and contains information for eight possible
samples.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x040
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MUX4 MUX5 MUX6 MUX7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MUX0 MUX1 MUX2 MUX3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 0x1 indicates the input
is AIN1.
0x0 R/W MUX7 31:28
The MUX6 field is used during the seventh sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
0x0 R/W MUX6 27:24
The MUX5 field is used during the sixth sample of a sequence executed
sampled for the analog-to-digital conversion.
0x0 R/W MUX5 23:20
The MUX4 field is used during the fifth sample of a sequence executed
0x0 R/W MUX4 19:16
The MUX3 field is used during the fourth sample of a sequence executed
0x0 R/W MUX3 15:12
3rd Sample Input Select
The MUX2 field is used during the third sample of a sequence executed
0x0 R/W MUX2 11:8
April 10, 2013 792
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
0x0 R/W MUX1 7:4
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
0x0 R/W MUX0 3:0
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Register 16: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
a sample sequencer. When configuring a sample sequence, the END bit must be set for the final
sample, whether it be after the first sample, eighth sample, or any sample in between. This register
is 32 bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x044
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
D4 END4 IE4 TS4 D5 END5 IE5 TS5 D6 END6 IE6 TS6 D7 END7 IE7 TS7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
8th Sample Temp Sensor Select
Description Value
The input pin specified by the ADCSSMUXn register is read
during the eighth sample of the sample sequence.
0
The temperature sensor is read during the eighth sample of the
sample sequence.
1
0 R/W TS7 31
8th Sample Interrupt Enable
Description Value
The raw interrupt is not asserted to the interrupt controller. 0
The raw interrupt signal (INR0 bit) is asserted at the end of the
eighth sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
1
It is legal to have multiple samples within a sequence generate interrupts.
0 R/W IE7 30
8th Sample is End of Sequence
Description Value
Another sample in the sequence is the final sample. 0
The eighth sample is the last sample of the sequence. 1
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
0 R/W END7 29
April 10, 2013 794
8th Sample Differential Input Select
Description Value
The analog inputs are not differentially sampled. 0
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
1
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS7 bit is set.
0 R/W D7 28
Description Value
during the seventh sample of the sample sequence.
0
The temperature sensor is read during the seventh sample of
the sample sequence.
1
0 R/W TS6 27
Description Value
seventh sample's conversion. If the MASK0 bit in the ADCIM
1
0 R/W IE6 26
Description Value
The seventh sample is the last sample of the sequence. 1
0 R/W END6 25
Description Value
1
0 R/W D6 24
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Description Value
during the sixth sample of the sample sequence.
0
The temperature sensor is read during the sixth sample of the
sample sequence.
1
0 R/W TS5 23
Description Value
sixth sample's conversion. If the MASK0 bit in the ADCIMregister
is set, the interrupt is promoted to the interrupt controller.
1
0 R/W IE5 22
Description Value
The sixth sample is the last sample of the sequence. 1
0 R/W END5 21
Description Value
1
0 R/W D5 20
Description Value
during the fifth sample of the sample sequence.
0
The temperature sensor is read during the fifth sample of the
sample sequence.
1
0 R/W TS4 19
April 10, 2013 796
Description Value
fifth sample's conversion. If the MASK0 bit in the ADCIMregister
1
0 R/W IE4 18
Description Value
The fifth sample is the last sample of the sequence. 1
0 R/W END4 17
Description Value
1
0 R/W D4 16
Description Value
during the fourth sample of the sample sequence.
0
The temperature sensor is read during the fourth sample of the
sample sequence.
1
0 R/W TS3 15
Description Value
fourth sample's conversion. If the MASK0 bit in the ADCIM
1
0 R/W IE3 14
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Description Value
The fourth sample is the last sample of the sequence. 1
0 R/W END3 13
Description Value
1
0 R/W D3 12
3rd Sample Temp Sensor Select
Description Value
during the third sample of the sample sequence.
0
The temperature sensor is read during the third sample of the
sample sequence.
1
0 R/W TS2 11
3rd Sample Interrupt Enable
Description Value
third sample's conversion. If the MASK0 bit in the ADCIMregister
1
0 R/W IE2 10
3rd Sample is End of Sequence
Description Value
The third sample is the last sample of the sequence. 1
0 R/W END2 9
April 10, 2013 798
3rd Sample Differential Input Select
Description Value
1
0 R/W D2 8
2nd Sample Temp Sensor Select
Description Value
during the second sample of the sample sequence.
0
The temperature sensor is read during the second sample of
1
0 R/W TS1 7
2nd Sample Interrupt Enable
Description Value
second sample's conversion. If the MASK0 bit in the ADCIM
1
0 R/W IE1 6
2nd Sample is End of Sequence
Description Value
The second sample is the last sample of the sequence. 1
0 R/W END1 5
2nd Sample Differential Input Select
Description Value
1
0 R/W D1 4
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1st Sample Temp Sensor Select
Description Value
during the first sample of the sample sequence.
0
The temperature sensor is read during the first sample of the
sample sequence.
1
0 R/W TS0 3
1st Sample Interrupt Enable
Description Value
first sample's conversion. If the MASK0 bit in the ADCIMregister
1
0 R/W IE0 2
1st Sample is End of Sequence
Description Value
The first sample is the last sample of the sequence. 1
0 R/W END0 1
1st Sample Differential Input Select
Description Value
1
0 R/W D0 0
April 10, 2013 800
Register 17: ADCSample Sequence Result FIFO0 (ADCSSFIFO0), offset 0x048
Register 20: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
Important: This register is read-sensitive. See the register description for details.
This register contains the conversion results for samples collected with the sample sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO n (ADCSSFIFOn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x048
Type RO, reset -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA reserved
- - - - - - - - - - - - 0 0 0 0 Reset
Conversion Result Data - RO DATA 11:0
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Register 21: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
0x06C
0x08C
0x0AC
This register provides a window into the sample sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO with the head and tail pointers both pointing to index 0. The ADCSSFSTAT0 register provides
status on FIFO0, which has 8 entries; ADCSSFSTAT1 on FIFO1, which has 4 entries;
ADCSSFSTAT2 on FIFO2, which has 4 entries; and ADCSSFSTAT3 on FIFO3 which has a single
entry.
ADC Sample Sequence FIFO n Status (ADCSSFSTATn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x04C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TPTR HPTR EMPTY reserved FULL reserved
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Reset
FIFO Full
Description Value
The FIFO is not currently full. 0
The FIFO is currently full. 1
0 RO FULL 12
FIFO Empty
Description Value
The FIFO is not currently empty. 0
The FIFO is currently empty. 1
1 RO EMPTY 8
April 10, 2013 802
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and
0x0 for FIFO3.
0x0 RO HPTR 7:4
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and
0x0 for FIFO3.
0x0 RO TPTR 3:0
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Register 25: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050
This register determines whether the sample from the given conversion on Sample Sequence 0 is
saved in the Sample Sequence FIFO0 or sent to the digital comparator unit.
ADC Sample Sequence 0 Operation (ADCSSOP0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x050
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
S4DCOP reserved S5DCOP reserved S6DCOP reserved S7DCOP reserved
R/W RO RO RO R/W RO RO RO R/W RO RO RO R/W RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Sample 7 Digital Comparator Operation
Description Value
The eighth sample is saved in Sample Sequence FIFO0. 0
The eighth sample is sent to the digital comparator unit specified
by the S7DCSEL bit in the ADCSSDC0 register, and the value
is not written to the FIFO.
1
0 R/W S7DCOP 28
Same definition as S7DCOP but used during the seventh sample.
0 R/W S6DCOP 24
Same definition as S7DCOP but used during the sixth sample.
0 R/W S5DCOP 20
Same definition as S7DCOP but used during the fifth sample.
0 R/W S4DCOP 16
April 10, 2013 804
Same definition as S7DCOP but used during the fourth sample.
0 R/W S3DCOP 12
Same definition as S7DCOP but used during the third sample.
0 R/W S2DCOP 8
0x0 RO reserved 7:5
Same definition as S7DCOP but used during the second sample.
0 R/W S1DCOP 4
0x0 RO reserved 3:1
Same definition as S7DCOP but used during the first sample.
0 R/W S0DCOP 0
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Register 26: ADCSample Sequence 0 Digital Comparator Select (ADCSSDC0),
offset 0x054
This register determines which digital comparator receives the sample from the given conversion
on Sample Sequence 0, if the corresponding SnDCOP bit in the ADCSSOP0 register is set.
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x054
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
S4DCSEL S5DCSEL S6DCSEL S7DCSEL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Sample 7 Digital Comparator Select
When the S7DCOP bit in the ADCSSOP0 register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the eighth sample from Sample Sequencer 0.
Note: Values not listed are reserved.
Description Value
Digital Comparator Unit 0 (ADCDCCMP0 and ADCDCCTL0) 0x0
0x0 R/W S7DCSEL 31:28
This field has the same encodings as S7DCSEL but is used during the
seventh sample.
sixth sample.
fifth sample.
fourth sample.
April 10, 2013 806
third sample.
second sample.
0x0 R/W S1DCSEL 7:4
first sample.
0x0 R/W S0DCSEL 3:0
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offset 0x060
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16 bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 792 for detailed bit descriptions. The ADCSSMUX1
register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2.
ADC Sample Sequence Input Multiplexer Select n (ADCSSMUXn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x060
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MUX0 MUX1 MUX2 MUX3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
4th Sample Input Select 0x0 R/W MUX3 15:12
3rd Sample Input Select 0x0 R/W MUX2 11:8
2nd Sample Input Select 0x0 R/W MUX1 7:4
1st Sample Input Select 0x0 R/W MUX0 3:0
April 10, 2013 808
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set for the
final sample, whether it be after the first sample, fourth sample, or any sample in between. These
registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0
register on page 794 for detailed bit descriptions. The ADCSSCTL1 register configures Sample
Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2.
ADC Sample Sequence Control n (ADCSSCTLn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x064
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Value
during the fourth sample of the sample sequence.
0
The temperature sensor is read during the fourth sample of the
sample sequence.
1
0 R/W TS3 15
Description Value
fourth sample's conversion. If the MASK0 bit in the ADCIM
1
0 R/W IE3 14
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Description Value
The fourth sample is the last sample of the sequence. 1
0 R/W END3 13
Description Value
1
0 R/W D3 12
3rd Sample Temp Sensor Select
Description Value
during the third sample of the sample sequence.
0
The temperature sensor is read during the third sample of the
sample sequence.
1
0 R/W TS2 11
3rd Sample Interrupt Enable
Description Value
third sample's conversion. If the MASK0 bit in the ADCIMregister
1
0 R/W IE2 10
3rd Sample is End of Sequence
Description Value
The third sample is the last sample of the sequence. 1
0 R/W END2 9
April 10, 2013 810
3rd Sample Differential Input Select
Description Value
1
0 R/W D2 8
2nd Sample Temp Sensor Select
Description Value
during the second sample of the sample sequence.
0
The temperature sensor is read during the second sample of
1
0 R/W TS1 7
2nd Sample Interrupt Enable
Description Value
second sample's conversion. If the MASK0 bit in the ADCIM
1
0 R/W IE1 6
2nd Sample is End of Sequence
Description Value
The second sample is the last sample of the sequence. 1
0 R/W END1 5
2nd Sample Differential Input Select
Description Value
1
0 R/W D1 4
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Description Value
0
sample sequence.
1
0 R/W TS0 3
1st Sample Interrupt Enable
Description Value
first sample's conversion. If the MASK0 bit in the ADCIMregister
1
0 R/W IE0 2
1st Sample is End of Sequence
Description Value
The first sample is the last sample of the sequence. 1
0 R/W END0 1
1st Sample Differential Input Select
Description Value
1
0 R/W D0 0
April 10, 2013 812
This register determines whether the sample from the given conversion on Sample Sequence n is
saved in the Sample Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1
register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2.
ADC Sample Sequence n Operation (ADCSSOPn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x070
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Value
The fourth sample is saved in Sample Sequence FIFOn. 0
The fourth sample is sent to the digital comparator unit specified
by the S3DCSEL bit in the ADCSSDC0n register, and the value
is not written to the FIFO.
1
0 R/W S3DCOP 12
Same definition as S3DCOP but used during the third sample.
0 R/W S2DCOP 8
0x0 RO reserved 7:5
Same definition as S3DCOP but used during the second sample.
0 R/W S1DCOP 4
0x0 RO reserved 3:1
Same definition as S3DCOP but used during the first sample.
0 R/W S0DCOP 0
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offset 0x074
offset 0x094
These registers determine which digital comparator receives the sample from the given conversion
on Sample Sequence n if the corresponding SnDCOP bit in the ADCSSOPn register is set. The
ADCSSDC1 register controls the selection for Sample Sequencer 1 and the ADCSSDC2 register
controls the selection for Sample Sequencer 2.
ADC Sample Sequence n Digital Comparator Select (ADCSSDCn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x074
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
When the S3DCOP bit in the ADCSSOPn register is set, this field
registers) receives the eighth sample from Sample Sequencer n.
Description Value
Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0) 0x0
third sample.
April 10, 2013 814
second sample.
0x0 R/W S1DCSEL 7:4
first sample.
0x0 R/W S0DCSEL 3:0
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offset 0x0A0
This register defines the analog input configuration for the sample executed with Sample Sequencer
3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSMUX0
register on page 792 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MUX0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
1st Sample Input Select 0 R/W MUX0 3:0
April 10, 2013 816
Register 36: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for a sample executed with Sample Sequencer
3. When configuring a sample sequence in this register, the END bit must be set for this sample.
This register is 4 bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 794 for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 END0 IE0 TS0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Value
0
sample sequence.
1
0 R/W TS0 3
Sample Interrupt Enable
Description Value
The raw interrupt signal (INR0 bit) is asserted at the end of this
sample's conversion. If the MASK0 bit in the ADCIM register is
set, the interrupt is promoted to the interrupt controller.
1
0 R/W IE0 2
End of Sequence
This bit must be set before initiating single sample sequence.
Description Value
Sampling and conversion continues. 0
This is the end of sequence. 1
0 R/W END0 1
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Sample Differential Input Select
Description Value
1
0 R/W D0 0
April 10, 2013 818
Register 37: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0
This register determines whether the sample from the given conversion on Sample Sequence 3 is
saved in the Sample Sequence 3 FIFO or sent to the digital comparator unit.
ADC Sample Sequence 3 Operation (ADCSSOP3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0DCOP reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Value
The sample is saved in Sample Sequence FIFO3. 0
The sample is sent to the digital comparator unit specified by
the S0DCSEL bit in the ADCSSDC03 register, and the value is
not written to the FIFO.
1
0 R/W S0DCOP 0
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offset 0x0B4
This register determines which digital comparator receives the sample from the given conversion
on Sample Sequence 3 if the corresponding SnDCOP bit in the ADCSSOP3 register is set.
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S0DCSEL reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
When the S0DCOP bit in the ADCSSOP3 register is set, this field
registers) receives the sample from Sample Sequencer 3.
Description Value
0x0 R/W S0DCSEL 3:0
April 10, 2013 820
Register 39: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC),
offset 0xD00
This register provides the ability to reset any of the digital comparator interrupt or trigger functions
back to their initial conditions. Resetting these functions ensures that the data that is being used by
the interrupt and trigger functions in the digital comparator unit is not stale.
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xD00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DCTRIG0 DCTRIG1 DCTRIG2 DCTRIG3 DCTRIG4 DCTRIG5 DCTRIG6 DCTRIG7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DCINT0 DCINT1 DCINT2 DCINT3 DCINT4 DCINT5 DCINT6 DCINT7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Digital Comparator Trigger 7
Description Value
No effect. 0
Resets the Digital Comparator 7 trigger unit to its initial
conditions.
1
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used. After setting this bit, software
should wait until the bit clears before continuing.
0 WO DCTRIG7 23
Description Value
No effect. 0
conditions.
1
sequence so that stale data is not used.
0 WO DCTRIG6 22
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Description Value
No effect. 0
conditions.
1
0 WO DCTRIG5 21
Description Value
No effect. 0
conditions.
1
0 WO DCTRIG4 20
Description Value
No effect. 0
conditions.
1
0 WO DCTRIG3 19
Description Value
No effect. 0
conditions.
1
0 WO DCTRIG2 18
April 10, 2013 822
Description Value
No effect. 0
conditions.
1
0 WO DCTRIG1 17
Description Value
No effect. 0
conditions.
1
0 WO DCTRIG0 16
Digital Comparator Interrupt 7
Description Value
No effect. 0
Resets the Digital Comparator 7 interrupt unit to its initial
conditions.
1
When the interrupt has been cleared, this bit is automatically cleared.
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
0 WO DCINT7 7
Description Value
No effect. 0
conditions.
1
0 WO DCINT6 6
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Description Value
No effect. 0
conditions.
1
0 WO DCINT5 5
Description Value
No effect. 0
conditions.
1
0 WO DCINT4 4
Description Value
No effect. 0
conditions.
1
0 WO DCINT3 3
Description Value
No effect. 0
conditions.
1
0 WO DCINT2 2
April 10, 2013 824
Description Value
No effect. 0
conditions.
1
0 WO DCINT1 1
Description Value
No effect. 0
conditions.
1
0 WO DCINT0 0
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Register 40: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00
Register 43: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C
Register 47: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C
This register provides the comparison encodings that generate an interrupt and/or PWM trigger.
See Interrupt/ADC-Trigger Selector on page 1060 for more information on using the ADC digital
comparators to trigger a PWM generator.
ADC Digital Comparator Control n (ADCDCCTLn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xE00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CIM CIC CIE reserved CTM CTC CTE reserved
R/W R/W R/W R/W R/W RO RO RO R/W R/W R/W R/W R/W RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Comparison Trigger Enable
Description Value
Disables the trigger function state machine. ADC conversion
data is ignored by the trigger function.
0
Enables the trigger function state machine. The ADCconversion
data is used to determine if a trigger should be generated
according to the programming of the CTC and CTM fields.
1
0 R/W CTE 12
April 10, 2013 826
Comparison Trigger Condition
This field specifies the operational region in which a trigger is generated
when the ADCconversion data is compared against the values of COMP0
and COMP1. The COMP0 and COMP1 fields are defined in the
ADCDCCMPx registers.
Description Value
Low Band
ADC Data < COMP0 COMP1
0x0
Mid Band
COMP0 < ADC Data COMP1
0x1
reserved 0x2
High Band
COMP0 COMP1 ADC Data
0x3
0x0 R/W CTC 11:10
Comparison Trigger Mode
This field specifies the mode by which the trigger comparison is made.
Description Value
Always
This mode generates a trigger every time the ADC conversion
data falls within the selected operational region.
0x0
Once
This mode generates a trigger the first time that the ADC
conversion data enters the selected operational region.
0x1
Hysteresis Always
This mode generates a trigger when the ADC conversion data
falls within the selected operational region and continues to
generate the trigger until the hysteresis condition is cleared by
entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3.
0x2
Hysteresis Once
This mode generates a trigger the first time that the ADC
conversion data falls within the selected operational region. No
additional triggers are generated until the hysteresis condition
is cleared by entering the opposite operational region.
0x3
0x0 R/W CTM 9:8
0x0 RO reserved 7:5
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Comparison Interrupt Enable
Description Value
Disables the comparison interrupt. ADC conversion data has
no effect on interrupt generation.
0
Enables the comparison interrupt. The ADC conversion data is
used to determine if an interrupt should be generated according
to the programming of the CIC and CIM fields.
1
0 R/W CIE 4
Comparison Interrupt Condition
This field specifies the operational region in which an interrupt is
generated when the ADC conversion data is compared against the
values of COMP0 and COMP1. The COMP0 and COMP1 fields are defined
in the ADCDCCMPx registers.
Description Value
Low Band
ADC Data < COMP0 COMP1
0x0
Mid Band
COMP0 ADC Data < COMP1
0x1
reserved 0x2
High Band
COMP0 < COMP1 ADC Data
0x3
0x0 R/W CIC 3:2
Comparison Interrupt Mode
This field specifies the mode by which the interrupt comparison is made.
Description Value
Always
This mode generates an interrupt every time the ADCconversion
data falls within the selected operational region.
0x0
Once
This mode generates an interrupt the first time that the ADC
conversion data enters the selected operational region.
0x1
Hysteresis Always
This mode generates an interrupt when the ADC conversion
data falls within the selected operational region and continues
to generate the interrupt until the hysteresis condition is cleared
by entering the opposite operational region.
0x2
Hysteresis Once
This mode generates an interrupt the first time that the ADC
conversion data falls within the selected operational region. No
additional interrupts are generated until the hysteresis condition
is cleared by entering the opposite operational region.
0x3
0x0 R/W CIM 1:0
April 10, 2013 828
Register 48: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40
Register 51: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C
Register 55: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C
This register defines the comparison values that are used to determine if the ADC conversion data
falls in the appropriate operating region.
Note: The value in the COMP1 field must be greater than or equal to the value in the COMP0 field
or unexpected results can occur.
ADC Digital Comparator Range n (ADCDCCMPn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xE40
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
COMP1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
COMP0 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Compare 1
The value in this field is compared against the ADC conversion data.
The result of the comparison is used to determine if the data lies within
the high-band region.
Note that the value of COMP1 must be greater than or equal to the value
of COMP0.
0x000 R/W COMP1 27:16
Compare 0
The value in this field is compared against the ADC conversion data.
The result of the comparison is used to determine if the data lies within
the low-band region.
0x000 R/W COMP0 11:0
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Register 56: ADC Peripheral Properties (ADCPP), offset 0xFC0
The ADCPP register provides information regarding the properties of the ADC module.
ADC Peripheral Properties (ADCPP)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC0
Type RO, reset 0x00B0.20C7
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TYPE RSL TS reserved
0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSR CH DC
1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 0 Reset
0 RO reserved 31:24
Temperature Sensor
Description Value
The ADC module does not have a temperature sensor. 0
The ADC module has a temperature sensor. 1
This field provides the similar information as the legacy DC1 register
TEMPSNS bit.
0x1 RO TS 23
Resolution
This field specifies the maximumnumber of binary bits used to represent
the converted sample. The field is encoded as a binary value, in the
range of 0 to 32 bits.
0xC RO RSL 22:18
ADC Architecture
Description Value
SAR 0x0
Reserved 0x1 - 0x3
0x0 RO TYPE 17:16
Digital Comparator Count
This field specifies the number of ADC digital comparators available to
the converter. The field is encoded as a binary value, in the range of 0
to 63.
This field provides similar information to the legacy DC9 register
ADCnDCn bits.
0x8 RO DC 15:10
April 10, 2013 830
ADC Channel Count
This field specifies the number of ADC input channels available to the
converter. This field is encoded as a binary value, in the range of 0 to
63.
This field provides similar information to the legacy DC3 and DC8 register
ADCnAINn bits.
0xC RO CH 9:4
Maximum ADC Sample Rate
This field specifies the maximum number of ADC conversions per
second. The MSR field is encoded as follows:
Description Value
Reserved 0x0
125 ksps 0x1
Reserved 0x2
250 ksps 0x3
Reserved 0x4
500 ksps 0x5
Reserved 0x6
1 Msps 0x7
Reserved 0x8 - 0xF
0x7 RO MSR 3:0
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Register 57: ADC Peripheral Configuration (ADCPC), offset 0xFC4
The ADCPC register provides information regarding the configuration of the peripheral.
ADC Peripheral Configuration (ADCPC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SR reserved
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x0000.0000 RO reserved 31:4
ADC Sample Rate
This field specifies the number of ADC conversions per second and is
used in Run, Sleep, and Deep-sleep modes. The field encoding is based
on the legacy RCGC0 register encoding. The programmed sample rate
cannot exceed the maximum sample rate specified by the MSR field in
the ADCPP register. The SR field is encoded as follows:
Description Value
Reserved 0x0
125 ksps 0x1
Reserved 0x2
250 ksps 0x3
Reserved 0x4
500 ksps 0x5
Reserved 0x6
1 Msps 0x7
Reserved 0x8 - 0xF
0x7 R/W SR 3:0
April 10, 2013 832
Register 58: ADC Clock Configuration (ADCCC), offset 0xFC8
The ADCCC register controls the clock source for the ADC module.
To use the PIOSC to clock the ADC, first power up the PLL and then enable the PIOSC in the CS
bit field, then disable the PLL.
To use the MOSC to clock the ADC, first power up the PLL and then enable the clock to the ADC
module, then disable the PLL and switch to the MOSC for the system clock.
ADC Clock Configuration (ADCCC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ADC Clock Source
The following table specifies the clock source that generates the ADC
clock input, see Figure 5-5 on page 210.
Description Value
Either the 16-MHz system clock (if the PLL bypass is in
effect) or the 16 MHz clock derived from PLL 25 (default).
Note that when the PLL is bypassed, the systemclock must
be at least 16 MHz.
0x0
PIOSC
The PIOSC provides a 16-MHz clock source for the ADC.
If the PIOSC is used as the clock source, the ADC module
can continue to operate in Deep-Sleep mode.
0x1
Reserved 0x2 - 0xF
0 R/W CS 3:0
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13 Universal Asynchronous Receivers/Transmitters
(UARTs)
The TM4C123AH6PMcontroller includes eight Universal Asynchronous Receiver/Transmitter (UART)
with the following features:
Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
Line-break generation and detection
Fully programmable serial interface characteristics
5, 6, 7, or 8 data bits
Even, odd, stick, or no-parity bit generation/detection
1 or 2 stop bit generation
IrDA serial-IR (SIR) encoder/decoder providing
Programmable use of IrDA Serial Infrared (SIR) or UART input/output
Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
Support of normal 3/16 and low-power (1.41-2.23 s) bit durations
Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
Support for communication with ISO 7816 smart cards
Modem flow control (on UART1)
EIA-485 9-bit support
Standard FIFO-level and End-of-Transmission interrupts
Receive single request asserted when data is in the FIFO; burst request asserted at
April 10, 2013 834
Universal Asynchronous Receivers/Transmitters (UARTs)
Transmit single request asserted when there is space in the FIFO; burst request asserted at
13.1 Block Diagram
Figure 13-1. UART Module Block Diagram
TxFIFO
16 x 8
.
.
.
RxFIFO
16 x 8
.
.
.
DMA Control
UARTDMACTL
DMA Request
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
UARTDR
Control/Status
Transmitter
(with SIR
Transmit
Encoder)
Baud Rate
Generator
UARTIBRD
UARTFBRD
Receiver
(with SIR
Receive
Decoder)
UnTx
UnRx
System Clock
Interrupt
Clock Control
UARTCTL
PIOSC
Baud Clock
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
UART9BITADDR
UART9BITAMASK
UARTPP
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTCC
The following table lists the external signals of the UART module and describes the function of each.
The UART signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset, with the exception of the U0Rx and U0Tx pins which default to the UART function. The column
in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these
UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register
(page 612) should be set to choose the UART function. The number in parentheses is the encoding
that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register
(page 629) to assign the UART signal to the specified GPIO port pin. For more information on
configuring GPIOs, see General-Purpose Input/Outputs (GPIOs) on page 591.
Table 13-1. UART Signals (64LQFP)
a
Assignment
Pin Number Pin Name
UART module 0 receive. TTL I PA0 (1) 17 U0Rx
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Table 13-1. UART Signals (64LQFP) (continued)
a
Assignment
Pin Number Pin Name
UART module 0 transmit. TTL O PA1 (1) 18 U0Tx
UART module 1 Clear To Send modemflowcontrol
input signal.
TTL I PC5 (8)
PF1 (1)
15
29
U1CTS
UART module 1 Request to Send modem flow
control output line.
TTL O PC4 (8)
PF0 (1)
16
28
U1RTS
UART module 1 receive. TTL I PC4 (2)
PB0 (1)
16
45
U1Rx
UART module 1 transmit. TTL O PC5 (2)
PB1 (1)
15
46
U1Tx
UART module 2 receive. TTL I PG4 (1)
PD6 (1)
33
53
U2Rx
UART module 2 transmit. TTL O PD7 (1)
PG5 (1)
10
32
U2Tx
UART module 3 receive. TTL I PC6 (1) 14 U3Rx
UART module 3 transmit. TTL O PC7 (1) 13 U3Tx
UART module 5 receive. TTL I PE4 (1) 59 U5Rx
UART module 5 transmit. TTL O PE5 (1) 60 U5Tx
UART module 6 receive. TTL I PD4 (1) 43 U6Rx
UART module 6 transmit. TTL O PD5 (1) 44 U6Tx
Each TM4C123AH6PM UART performs the functions of parallel-to-serial and serial-to-parallel
conversions. It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 859). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to
an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
13.3.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits
(LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 13-2 on page 837 for details.
April 10, 2013 836
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 13-2. UART Character Frame
1
0
5-8 data bits
LSB MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
13.3.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divisor allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 855) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 856). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE
in UARTCTL is clear) or 8 (if HSE is set). By default, this will be the main system clock described
in Clock Control on page 208. Alternatively, the UART may be clocked from the internal precision
oscillator (PIOSC), independent of the system clock selection. This will allow the UART clock to be
programmed indpendently of the system clock PLL settings. See the UARTCC register for more
details.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRDregister)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to
as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5) in UARTCTL). This reference
clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during
receive operations. Note that the state of the HSE bit has no effect on clock generation in ISO 7816
smart card mode (when the SMART bit in the UARTCTL register is set).
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 857), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
UARTIBRD write, UARTFBRD write, and UARTLCRH write
UARTFBRD write, UARTIBRD write, and UARTLCRH write
UARTIBRD write and UARTLCRH write
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UARTFBRD write and UARTLCRH write
13.3.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRHregister. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 852) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start
bit has been received), the receive counter begins running and data is sampled on the eighth cycle
of Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL
(described in Transmit/Receive Logic on page 836).
The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE
clear) or the fourth cycle of Baud 8 (HSE set), otherwise it is ignored. After a valid start bit is detected,
successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one
bit period later) according to the programmed length of the data characters and value of the HSE
bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO along with any error bits
associated with that word.
13.3.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream and a half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output and decoded input to the UART. When enabled, the SIR block
uses the UnTx and UnRx pins for the SIRprotocol. These signals should be connected to an infrared
transceiver to implement an IrDA SIR physical layer link. The SIR block can receive and transmit,
but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before
data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between
transmission and reception. The SIR block has two modes of operation:
In normal IrDA mode, a zero logic level is transmitted as a high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW and driving the UART input pin LOW.
In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 s, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register. See page 854 for more
information on IrDA low-power pulse-duration configuration.
Whether the device is in normal or low-power IrDA mode, a start bit is deemed valid if the decoder
is still Low, one period of IrLPBaud16 after the Low was first detected. This enables a normal-mode
April 10, 2013 838
UART to receive data from a low-power mode UART that can transmit pulses as small as 1.41 s.
Thus, for both low-power and normal mode operation, the ILPDVSR field in the UARTILPR register
must be programmed such that 1.42 MHz < F
IrLPBaud16
< 2.12 MHz, resulting in a low-power pulse
duration of 1.412.11 s (three times the period of IrLPBaud16). The minimum frequency of
IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but pulses
greater than 1.4 s are accepted as valid pulses.
Figure 13-3 on page 839 shows the UART transmit and receive signals, with and without IrDA
modulation.
Figure 13-3. IrDA Data Modulation
1 0 1 0 0 0 1 1 0 1
Data bits
1 0 1 0 0 0 1 1 0 1
Data bits Start
bit
Start Stop
Bit period
Bit period
3
16
UnTx
UnTx with IrDA
UnRx with IrDA
UnRx
Stop
bit
In both normal and low-power IrDA modes:
During transmission, the UART data bit is used as the base for encoding
During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10-ms
delay between transmission and reception. This delay must be generated by software because it
is not automatically supported by the UART. The delay is required because the infrared receiver
electronics might become biased or even saturated fromthe optical power coupled fromthe adjacent
transmitter LED. This delay is known as latency or receiver setup time.
13.3.5 ISO 7816 Support
The UART offers basic support to allow communication with an ISO 7816 smartcard. When bit 3
(SMART) of the UARTCTL register is set, the UnTx signal is used as a bit clock, and the UnRx signal
is used as the half-duplex communication line connected to the smartcard. A GPIO signal can be
used to generate the reset signal to the smartcard. The remaining smartcard signals should be
provided by the system design. The maximum clock rate in this mode is system clock / 16.
When using ISO 7816 mode, the UARTLCRH register must be set to transmit 8-bit words (WLEN
bits 6:5 configured to 0x3) with EVEN parity (PEN set and EPS set). In this mode, the UART
automatically uses 2 stop bits, and the STP2 bit of the UARTLCRH register is ignored.
If a parity error is detected during transmission, UnRx is pulled Low during the second stop bit. In
this case, the UART aborts the transmission, flushes the transmit FIFO and discards any data it
contains, and raises a parity error interrupt, allowing software to detect the problem and initiate
retransmission of the affected data. Note that the UART does not support automatic retransmission
in this case.
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13.3.6 Modem Handshake Support
This section describes how to configure and use the modem flow control signals for UART1 when
connected as a DTE (data terminal equipment) or as a DCE (data communications equipment). In
general, a modem is a DCE and a computing device that connects to a modem is the DTE.
13.3.6.1 Signaling
The status signals provided by UART1 differ based on whether the UART is used as a DTE or DCE.
When used as a DTE, the modem flow control signals are defined as:
U1CTS is Clear To Send
U1RTS is Request To Send
When used as a DCE, the the modem flow control signals are defined as:
U1CTS is Request To Send
U1RTS is Clear To Send
13.3.6.2 Flow Control
Flow control can be accomplished by either hardware or software. The following sections describe
the different methods.
Hardware Flow Control (RTS/CTS)
Hardware flow control between two devices is accomplished by connecting the U1RTS output to the
Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the
receiving device to the U1CTS input.
The U1CTS input controls the transmitter. The transmitter may only transmit data when the U1CTS
input is asserted. The U1RTS output signal indicates the state of the receive FIFO. U1CTS remains
asserted until the preprogrammed watermark level is reached, indicating that the Receive FIFOhas
no space to store additional characters.
The UARTCTL register bits 15 (CTSEN) and 14 (RTSEN) specify the flow control mode as shown in
Table 13-2 on page 840.
Table 13-2. Flow Control Mode
Description RTSEN CTSEN
RTS and CTS flow control enabled 1 1
Only CTS flow control enabled 0 1
Only RTS flow control enabled 1 0
Both RTS and CTS flow control disabled 0 0
Note that when RTSEN is 1, software cannot modify the U1RTS output value through the UARTCTL
register Request to Send (RTS) bit, and the status of the RTS bit should be ignored.
Software Flow Control (Modem Status Interrupts)
Software flowcontrol between two devices is accomplished by using interrupts to indicate the status
of the UART. Interrupts may be generated for the U1CTS signal using bit 3 of the UARTIM register.
The raw and masked interrupt status may be checked using the UARTRIS and UARTMIS register.
These interrupts may be cleared using the UARTICR register.
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13.3.7 9-Bit UART Mode
The UART provides a 9-bit mode that is enabled with the 9BITEN bit in the UART9BITADDR
register. This feature is useful in a multi-drop configuration of the UART where a single master
connected to multiple slaves can communicate with a particular slave through its address or set of
addresses along with a qualifier for an address byte. All the slaves check for the address qualifier
in the place of the parity bit and, if set, then compare the byte received with the preprogrammed
address. If the address matches, then it receives or sends further data. If the address does not
match, it drops the address byte and any subsequent data bytes. If the UART is in 9-bit mode, then
the receiver operates with no parity mode. The address can be predefined to match with the received
byte and it can be configured with the UART9BITADDR register. The matching can be extended
to a set of addresses using the address mask in the UART9BITAMASK register. By default, the
UART9BITAMASK is 0xFF, meaning that only the specified address is matched.
When not finding a match, the rest of the data bytes with the 9th bit cleared are dropped. If a match
is found, then an interrupt is generated to the NVIC for further action. The subsequent data bytes
with the cleared 9th bit are stored in the FIFO. Software can mask this interrupt in case DMA and/or
FIFO operations are enabled for this instance and processor intervention is not required. All the
send transactions with 9-bit mode are data bytes and the 9th bit is cleared. Software can override
the 9th bit to be set (to indicate address) by overriding the parity settings to sticky parity with odd
parity enabled for a particular byte. To match the transmission time with correct parity settings, the
address byte can be transmitted as a single then a burst transfer. The Transmit FIFO does not hold
the address/data bit, hence software should take care of enabling the address bit appropriately.
13.3.8 FIFO Operation
The UART has two 16x8 FIFOs; one for transmit and one for receive. Both FIFOs are accessed via
the UART Data (UARTDR) register (see page 847). Read operations of the UARTDRregister return
a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in
the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 857).
FIFOstatus can be monitored via the UART Flag (UARTFR) register (see page 852) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the
UARTRSR register shows overrun status via the OE bit. If the FIFOs are disabled, the empty and
full flags are set according to the status of the 1-byte-deep holding registers.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 863). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include , , , , and . For example,
if the option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data
bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the mark.
13.3.9 Interrupts
The UART can generate interrupts when the following conditions are observed:
Overrun Error
Break Error
Parity Error
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Framing Error
Receive Timeout
Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the
EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 871).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM) register (see page 865) by setting the corresponding IM bits. If interrupts are not
used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 868).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a 1 to the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 874).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period when the HSE bit is clear or over a 64-bit period when the HSE bit
is set. The receive timeout interrupt is cleared either when the FIFObecomes empty through reading
all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the
UARTICR register.
The receive interrupt changes state when one of the following events occurs:
If the FIFOs are enabled and the receive FIFOreaches the programmed trigger level, the RXRIS
bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes
less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit.
If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the
location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the
receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit.
The transmit interrupt changes state when one of the following events occurs:
If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger
level, the TXRIS bit is set. The transmit interrupt is based on a transition through level, therefore
the FIFOmust be written past the programmed trigger level otherwise no further transmit interrupts
will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit.
If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.
13.3.10 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work by setting
the LBE bit in the UARTCTL register (see page 859). In loopback mode, data transmitted on the
UnTx output is received on the UnRx input. Note that the LBE bit should be set before the UART is
enabled.
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The UART provides an interface to the DMA controller with separate channels for transmit and
receive. The DMA operation of the UART is enabled through the UART DMA Control
(UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on
the receive or transmit channel when the associated FIFOcan transfer data. For the receive channel,
a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer
request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger
level configured in the UARTIFLS register. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The
single and burst DMA transfer requests are handled automatically by the DMA controller depending
on how the DMA channel is configured.
To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control
(UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit
of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive
channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive
error occurs, the DMA receive requests are automatically disabled. This error condition can be
cleared by clearing the appropriate UART error interrupt.
If DMA is enabled, then the DMA controller triggers an interrupt when a transfer is complete. The
interrupt occurs on the UART interrupt vector. Therefore, if interrupts are used for UART operation
and DMA is enabled, the UART interrupt handler must be designed to handle the DMA completion
interrupt.
See Micro Direct Memory Access (DMA) on page 527 for more details about programming the
DMA controller.
To enable and initialize the UART, the following steps are necessary:
1. Enable the UART module using the RCGCUART register (see page 325).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 322).
To find out which GPIO port to enable, refer to Table 21-5 on page 1176.
3. Set the GPIOAFSEL bits for the appropriate pins (see page 612). To determine which GPIOs to
4. Configure the GPIO current level and/or slew rate as specified for the mode selected (see
page 614 and page 622).
5. Configure the PMCn fields in the GPIOPCTL register to assign the UART signals to the appropriate
pins (see page 629 and Table 21-5 on page 1176).
To use the UART, the peripheral clock must be enabled by setting the appropriate bit in the
RCGCUART register (page 325). In addition, the clock to the appropriate GPIO module must be
enabled via the RCGCGPIO register (page 322) in the System Control module. To find out which
GPIO port to enable, refer to Table 21-5 on page 1176.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz, and the desired UART configuration is:
115200 baud rate
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Data length of 8 bits
One stop bit
No parity
FIFOs disabled
No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), because
the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using
the equation described in Baud-Rate Generation on page 837, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 855) should be set to 10
decimal or 0xA. The value to be loaded into the UARTFBRD register (see page 856) is calculated
by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Configure the UART clock source by writing to the UARTCC register.
6. Optionally, configure the DMAchannel (see Micro Direct Memory Access (DMA) on page 527)
and enable the DMA option(s) in the UARTDMACTL register.
7. Enable the UART by setting the UARTEN bit in the UARTCTL register.
13.5 Register Map
Table 13-3 on page 845 lists the UART registers. The offset listed is a hexadecimal increment to the
registers address, relative to that UARTs base address:
UART0: 0x4000.C000
UART1: 0x4000.D000
UART2: 0x4000.E000
UART3: 0x4000.F000
UART4: 0x4001.0000
UART5: 0x4001.1000
UART6: 0x4001.2000
UART7: 0x4001.3000
The UART module clock must be enabled before the registers can be programmed (see page 325).
There must be a delay of 3 systemclocks after the UART module clock is enabled before any UART
module registers are accessed.
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The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 859) before any
of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation,
the current transaction is completed prior to the UART stopping.
Table 13-3. UART Register Map
See
page
847 UART Data 0x0000.0000 R/W UARTDR 0x000
849 UART Receive Status/Error Clear 0x0000.0000 R/W UARTRSR/UARTECR 0x004
852 UART Flag 0x0000.0090 RO UARTFR 0x018
854 UART IrDA Low-Power Register 0x0000.0000 R/W UARTILPR 0x020
855 UART Integer Baud-Rate Divisor 0x0000.0000 R/W UARTIBRD 0x024
856 UART Fractional Baud-Rate Divisor 0x0000.0000 R/W UARTFBRD 0x028
857 UART Line Control 0x0000.0000 R/W UARTLCRH 0x02C
859 UART Control 0x0000.0300 R/W UARTCTL 0x030
863 UART Interrupt FIFO Level Select 0x0000.0012 R/W UARTIFLS 0x034
865 UART Interrupt Mask 0x0000.0000 R/W UARTIM 0x038
868 UART Raw Interrupt Status 0x0000.0000 RO UARTRIS 0x03C
871 UART Masked Interrupt Status 0x0000.0000 RO UARTMIS 0x040
874 UART Interrupt Clear 0x0000.0000 W1C UARTICR 0x044
876 UART DMA Control 0x0000.0000 R/W UARTDMACTL 0x048
877 UART 9-Bit Self Address 0x0000.0000 R/W UART9BITADDR 0x0A4
878 UART 9-Bit Self Address Mask 0x0000.00FF R/W UART9BITAMASK 0x0A8
879 UART Peripheral Properties 0x0000.0003 RO UARTPP 0xFC0
880 UART Clock Configuration 0x0000.0000 R/W UARTCC 0xFC8
881 UART Peripheral Identification 4 0x0000.0000 RO UARTPeriphID4 0xFD0
884 UART Peripheral Identification 7 0x0000.0000 RO UARTPeriphID7 0xFDC
885 UART Peripheral Identification 0 0x0000.0060 RO UARTPeriphID0 0xFE0
888 UART Peripheral Identification 3 0x0000.0001 RO UARTPeriphID3 0xFEC
889 UART PrimeCell Identification 0 0x0000.000D RO UARTPCellID0 0xFF0
890 UART PrimeCell Identification 1 0x0000.00F0 RO UARTPCellID1 0xFF4
891 UART PrimeCell Identification 2 0x0000.0005 RO UARTPCellID2 0xFF8
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Table 13-3. UART Register Map (continued)
See
page
892 UART PrimeCell Identification 3 0x0000.00B1 RO UARTPCellID3 0xFFC
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
April 10, 2013 846
Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit
FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of
the transmit FIFO). A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and
status are stored in the receiving holding register (the bottomword of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA FE PE BE OE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART Overrun Error
Description Value
No data has been lost due to a FIFO overrun. 0
New data was received when the FIFO was full, resulting in
data loss.
1
0 RO OE 11
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UART Break Error
Description Value
No break condition has occurred 0
A break condition has been detected, indicating that the receive
data input was held Lowfor longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
1
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state), and the next valid start bit is received.
0 RO BE 10
UART Parity Error
Description Value
No parity error has occurred 0
The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
1
the FIFO.
0 RO PE 9
UART Framing Error
Description Value
No framing error has occurred 0
The received character does not have a valid stop bit (a valid
stop bit is 1).
1
0 RO FE 8
Data Transmitted or Received
Data that is to be transmitted via the UART is written to this field.
When read, this field contains the data that was received by the UART.
0x00 R/W DATA 7:0
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared on reset.
Read-Only Status Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FE PE BE OE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART Overrun Error
Description Value
No data has been lost due to a FIFO overrun. 0
New data was received when the FIFO was full, resulting in
data loss.
1
This bit is cleared by a write to UARTECR.
The FIFOcontents remain valid because no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must read the data in order to empty the FIFO.
0 RO OE 3
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UART Break Error
Description Value
No break condition has occurred 0
A break condition has been detected, indicating that the receive
data input was held Lowfor longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
1
This bit is cleared to 0 by a write to UARTECR.
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
0 RO BE 2
UART Parity Error
Description Value
No parity error has occurred 0
The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
1
0 RO PE 1
UART Framing Error
Description Value
No framing error has occurred 0
The received character does not have a valid stop bit (a valid
stop bit is 1).
1
the FIFO.
0 RO FE 0
Write-Only Error Clear Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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0x0000.00 WO reserved 31:8
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
0x00 WO DATA 7:0
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1. The CTS bit indicate the modem flow control. Note that the modem bits
are only implemented on UART1 and are reserved on UART0 and UART2.
UART Flag (UARTFR)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CTS reserved BUSY RXFE TXFF RXFF TXFE reserved
0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Reset
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Description Value
The transmitter has data to transmit. 0
If the FIFO is disabled (FEN is 0), the transmit holding register
is empty.
If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
1
1 RO TXFE 7
UART Receive FIFO Full
UARTLCRH register.
Description Value
The receiver can receive data. 0
If the FIFO is disabled (FEN is 0), the receive holding register
is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.
1
0 RO RXFF 6
April 10, 2013 852
UART Transmit FIFO Full
UARTLCRH register.
Description Value
The transmitter is not full. 0
If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
1
0 RO TXFF 5
UART Receive FIFO Empty
UARTLCRH register.
Description Value
The receiver is not empty. 0
If the FIFO is disabled (FEN is 0), the receive holding register
is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
1
1 RO RXFE 4
UART Busy
Description Value
The UART is not busy. 0
The UART is busy transmitting data. This bit remains set until
the complete byte, including all stop bits, has been sent from
the shift register.
1
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
0 RO BUSY 3
0 RO reserved 2:1
Clear To Send
Description Value
The U1CTS signal is not asserted. 0
The U1CTS signal is asserted. 1
0 RO CTS 0
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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPRregister stores the 8-bit low-power counter divisor value used to derive the low-power
SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when
reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / F
IrLPBaud16
where F
IrLPBaud16
is nominally 1.8432 MHz.
Because the IrLPBaud16 clock is used to sample transmitted data irrespective of mode, the
ILPDVSR field must be programmed in both low power and normal mode,such that 1.42 MHz <
F
IrLPBaud16
< 2.12 MHz, resulting in a low-power pulse duration of 1.412.11 s (three times the
period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than
one period of IrLPBaud16 are rejected, but pulses greater than 1.4 s are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ILPDVSR reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IrDA Low-Power Divisor
This field contains the 8-bit low-power divisor value.
0x00 R/W ILPDVSR 7:0
April 10, 2013 854
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimumpossible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See Baud-Rate Generation on page 837
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIVINT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Integer Baud-Rate Divisor 0x0000 R/W DIVINT 15:0
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Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See Baud-Rate Generation on page 837
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x028
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIVFRAC reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Fractional Baud-Rate Divisor 0x0 R/W DIVFRAC 5:0
April 10, 2013 856
Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x02C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BRK PEN EPS STP2 FEN WLEN SPS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRHare set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
0 R/W SPS 7
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Description Value
5 bits (default) 0x0
6 bits 0x1
7 bits 0x2
8 bits 0x3
0x0 R/W WLEN 6:5
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UART Enable FIFOs
Description Value
The FIFOs are disabled (Character mode). The FIFOs become
1-byte-deep holding registers.
0
The transmit and receive FIFObuffers are enabled (FIFOmode). 1
0 R/W FEN 4
UART Two Stop Bits Select
Description Value
One stop bit is transmitted at the end of a frame. 0
Two stop bits are transmitted at the end of a frame. The receive
logic does not check for two stop bits being received.
When in 7816 smartcard mode (the SMART bit is set in the
UARTCTL register), the number of stop bits is forced to 2.
1
0 R/W STP2 3
UART Even Parity Select
Description Value
Odd parity is performed, which checks for an odd number of 1s. 0
Even parity generation and checking is performed during
transmission and reception, which checks for an even number
of 1s in data and parity bits.
1
This bit has no effect when parity is disabled by the PEN bit.
0 R/W EPS 2
UART Parity Enable
Description Value
Parity is disabled and no parity bit is added to the data frame. 0
Parity checking and generation is enabled. 1
0 R/W PEN 1
UART Send Break
Description Value
Normal use. 0
A Low level is continually output on the UnTx signal, after
completing transmission of the current character. For the proper
execution of the break command, software must set this bit for
at least two frames (character periods).
1
0 R/W BRK 0
April 10, 2013 858
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit
Enable (TXE) and Receive Enable (RXE) bits, which are set.
To enable the UART module, the UARTEN bit must be set. If software requires a configuration change
in the module, the UARTEN bit must be cleared before the configuration changes are written. If the
UART is disabled during a transmit or receive operation, the current transaction is completed prior
to the UART stopping.
Note: The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFOby clearing bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x030
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
UARTEN SIREN SIRLP SMART EOT HSE reserved LBE TXE RXE reserved RTS reserved RTSEN CTSEN
R/W R/W R/W R/W R/W R/W RO R/W R/W R/W RO R/W RO RO R/W R/W Type
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Reset
Enable Clear To Send
Description Value
CTS hardware flow control is disabled. 0
CTS hardware flow control is enabled. Data is only transmitted
when the U1CTS signal is asserted.
1
0 R/W CTSEN 15
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Enable Request to Send
Description Value
RTS hardware flow control is disabled. 0
RTS hardware flow control is enabled. Data is only requested
(by asserting U1RTS) when the receive FIFO has available
entries.
1
0 R/W RTSEN 14
0 RO reserved 13:12
Request to Send
When RTSEN is clear, the status of this bit is reflected on the U1RTS
signal. If RTSEN is set, this bit is ignored on a write and should be ignored
on read.
0 R/W RTS 11
0 RO reserved 10
UART Receive Enable
Description Value
The receive section of the UART is disabled. 0
The receive section of the UART is enabled. 1
If the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
1 R/W RXE 9
UART Transmit Enable
Description Value
The transmit section of the UART is disabled. 0
The transmit section of the UART is enabled. 1
If the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
1 R/W TXE 8
UART Loop Back Enable
Description Value
Normal operation. 0
The UnTx path is fed through the UnRx path. 1
0 R/W LBE 7
0 RO reserved 6
April 10, 2013 860
High-Speed Enable
Description Value
The UART is clocked using the system clock divided by 16. 0
The UART is clocked using the system clock divided by 8. 1
Note: Systemclock used is also dependent on the baud-rate divisor
configuration (see page 855) and page 856).
The state of this bit has no effect on clock generation in ISO
7816 smart card mode (the SMART bit is set).
0 R/W HSE 5
End of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS
register.
Description Value
The TXRIS bit is set when the transmit FIFOcondition specified
in UARTIFLS is met.
0
The TXRIS bit is set only after all transmitted data, including
stop bits, have cleared the serializer.
1
0 R/W EOT 4
ISO 7816 Smart Card Support
Description Value
Normal operation. 0
The UART operates in Smart Card mode. 1
The application must ensure that it sets 8-bit word length (WLEN set to
0x3) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in
UARTLCRH when using ISO 7816 mode.
In this mode, the value of the STP2 bit in UARTLCRH is ignored and
the number of stop bits is forced to 2. Note that the UART does not
support automatic retransmission on parity errors. If a parity error is
detected on transmission, all further transmit operations are aborted
and software must handle retransmission of the affected byte or
message.
0 R/W SMART 3
UART SIR Low-Power Mode
This bit selects the IrDA encoding mode.
Description Value
Low-level bits are transmitted as an active High pulse with a
width of 3/16th of the bit period.
0
The UART operates in SIR Low-Power mode. Low-level bits
are transmitted with a pulse width which is 3 times the period
of the IrLPBaud16 input signal, regardless of the selected bit
rate.
1
Setting this bit uses less power, but might reduce transmission distances.
See page 854 for more information.
0 R/W SIRLP 2
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UART SIR Enable
Description Value
Normal operation. 0
The IrDA SIR block is enabled, and the UART will transmit and
receive data using SIR protocol.
1
0 R/W SIREN 1
UART Enable
Description Value
The UART is disabled. 0
The UART is enabled. 1
If the UART is disabled in the middle of transmission or reception, it
completes the current character before stopping.
0 R/W UARTEN 0
April 10, 2013 862
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFOlevel select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x034
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXIFLSEL RXIFLSEL reserved
0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Reset
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Description Value
RX FIFO full 0x0
RX FIFO full 0x1
RX FIFO full (default) 0x2
RX FIFO full 0x3
RX FIFO full 0x4
Reserved 0x5-0x7
0x2 R/W RXIFLSEL 5:3
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UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Description Value
TX FIFO empty 0x0
TX FIFO empty 0x1
TX FIFO empty (default) 0x2
TX FIFO empty 0x3
TX FIFO empty 0x4
Reserved 0x5-0x7
Note: If the EOT bit in UARTCTL is set (see page 859), the transmit
interrupt is generated once the FIFOis completely empty and
all data including stop bits have left the transmit serializer. In
this case, the setting of TXIFLSEL is ignored.
0x2 R/W TXIFLSEL 2:0
April 10, 2013 864
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x038
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved CTSIM reserved RXIM TXIM RTIM FEIM PEIM BEIM OEIM reserved 9BITIM reserved
RO R/W RO RO R/W R/W R/W R/W R/W R/W R/W RO R/W RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:13
9-Bit Mode Interrupt Mask
Description Value
The 9BITRIS interrupt is suppressed and not sent to the
0
An interrupt is sent to the interrupt controller when the 9BITRIS
bit in the UARTRIS register is set.
1
0 R/W 9BITIM 12
0 RO reserved 11
UART Overrun Error Interrupt Mask
Description Value
The OERIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the OERIS
1
0 R/W OEIM 10
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UART Break Error Interrupt Mask
Description Value
The BERIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the BERIS
1
0 R/W BEIM 9
UART Parity Error Interrupt Mask
Description Value
The PERIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the PERIS
1
0 R/W PEIM 8
UART Framing Error Interrupt Mask
Description Value
The FERIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the FERIS
1
0 R/W FEIM 7
UART Receive Time-Out Interrupt Mask
Description Value
The RTRIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the RTRIS
1
0 R/W RTIM 6
UART Transmit Interrupt Mask
Description Value
The TXRIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the TXRIS
1
0 R/W TXIM 5
UART Receive Interrupt Mask
Description Value
The RXRIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the RXRIS
1
0 R/W RXIM 4
April 10, 2013 866
0 RO reserved 3:2
UART Clear to Send Modem Interrupt Mask
Description Value
The CTSRIS interrupt is suppressed and not sent to the interrupt
controller.
0
An interrupt is sent to the interrupt controller when the CTSRIS
1
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0 R/W CTSIM 1
0 RO reserved 0
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Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x03C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved CTSRIS reserved RXRIS TXRIS RTRIS FERIS PERIS BERIS OERIS reserved 9BITRIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:13
9-Bit Mode Raw Interrupt Status
Description Value
No interrupt 0
A receive address match has occurred. 1
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR
register.
0 RO 9BITRIS 12
0 RO reserved 11
UART Overrun Error Raw Interrupt Status
Description Value
No interrupt 0
An overrun error has occurred. 1
This bit is cleared by writing a 1 to the OEIC bit in the UARTICRregister.
0 RO OERIS 10
UART Break Error Raw Interrupt Status
Description Value
No interrupt 0
A break error has occurred. 1
This bit is cleared by writing a 1 to the BEIC bit in the UARTICRregister.
0 RO BERIS 9
April 10, 2013 868
UART Parity Error Raw Interrupt Status
Description Value
No interrupt 0
A parity error has occurred. 1
This bit is cleared by writing a 1 to the PEIC bit in the UARTICRregister.
0 RO PERIS 8
UART Framing Error Raw Interrupt Status
Description Value
No interrupt 0
A framing error has occurred. 1
This bit is cleared by writing a 1 to the FEIC bit in the UARTICRregister.
0 RO FERIS 7
UART Receive Time-Out Raw Interrupt Status
Description Value
No interrupt 0
A receive time out has occurred. 1
This bit is cleared by writing a 1 to the RTIC bit in the UARTICRregister.
0 RO RTRIS 6
UART Transmit Raw Interrupt Status
Description Value
No interrupt 0
If the EOT bit in the UARTCTL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
If the EOT bit is set, the last bit of all transmitted data and flags
has left the serializer.
1
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFOis enabled, or by writing a single byte if the FIFO
is disabled.
0 RO TXRIS 5
UART Receive Raw Interrupt Status
Description Value
No interrupt 0
The receive FIFOlevel has passed through the condition defined
in the UARTIFLS register.
1
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
0 RO RXRIS 4
0 RO reserved 3:2
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UART Clear to Send Modem Raw Interrupt Status
Description Value
No interrupt 0
Clear to Send used for software flow control. 1
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
UART2.
0 RO CTSRIS 1
0 RO reserved 0
April 10, 2013 870
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x040
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved CTSMIS reserved RXMIS TXMIS RTMIS FEMIS PEMIS BEMIS OEMIS reserved 9BITMIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:13
9-Bit Mode Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to a receive address
match.
1
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR
register.
0 RO 9BITMIS 12
0 RO reserved 11
UART Overrun Error Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to an overrun error. 1
This bit is cleared by writing a 1 to the OEIC bit in the UARTICRregister.
0 RO OEMIS 10
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UART Break Error Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to a break error. 1
This bit is cleared by writing a 1 to the BEIC bit in the UARTICRregister.
0 RO BEMIS 9
UART Parity Error Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to a parity error. 1
This bit is cleared by writing a 1 to the PEIC bit in the UARTICRregister.
0 RO PEMIS 8
UART Framing Error Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to a framing error. 1
This bit is cleared by writing a 1 to the FEIC bit in the UARTICRregister.
0 RO FEMIS 7
UART Receive Time-Out Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to a receive time out. 1
This bit is cleared by writing a 1 to the RTIC bit in the UARTICRregister.
0 RO RTMIS 6
UART Transmit Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to passing through
the specified transmit FIFO level (if the EOT bit is clear) or due
to the transmission of the last data bit (if the EOT bit is set).
1
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFOis enabled, or by writing a single byte if the FIFO
is disabled.
0 RO TXMIS 5
April 10, 2013 872
UART Receive Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
1
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
0 RO RXMIS 4
0 RO reserved 3:2
UART Clear to Send Modem Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to Clear to Send. 1
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
UART2.
0 RO CTSMIS 1
0 RO reserved 0
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Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x044
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved CTSMIC reserved RXIC TXIC RTIC FEIC PEIC BEIC OEIC reserved 9BITIC reserved
RO W1C RO RO W1C W1C W1C W1C W1C W1C W1C RO R/W RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:13
9-Bit Mode Interrupt Clear
Writing a 1 to this bit clears the 9BITRIS bit in the UARTRIS register
and the 9BITMIS bit in the UARTMIS register.
0 R/W 9BITIC 12
0 RO reserved 11
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and
the OEMIS bit in the UARTMIS register.
0 W1C OEIC 10
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and
the BEMIS bit in the UARTMIS register.
0 W1C BEIC 9
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and
the PEMIS bit in the UARTMIS register.
0 W1C PEIC 8
Framing Error Interrupt Clear
Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and
the FEMIS bit in the UARTMIS register.
0 W1C FEIC 7
Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and
the RTMIS bit in the UARTMIS register.
0 W1C RTIC 6
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Transmit Interrupt Clear
Writing a 1 to this bit clears the TXRIS bit in the UARTRIS register and
the TXMIS bit in the UARTMIS register.
0 W1C TXIC 5
Receive Interrupt Clear
Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and
the RXMIS bit in the UARTMIS register.
0 W1C RXIC 4
0 RO reserved 3:2
UART Clear to Send Modem Interrupt Clear
Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register
and the CTSMIS bit in the UARTMIS register.
UART2.
0 W1C CTSMIC 1
0 RO reserved 0
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Register 14: UART DMA Control (UARTDMACTL), offset 0x048
The UARTDMACTL register is the DMA control register.
UART DMA Control (UARTDMACTL)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x048
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RXDMAE TXDMAE DMAERR reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00000.000 RO reserved 31:3
DMA on Error
Description Value
DMA receive requests are unaffected when a receive error
occurs.
0
DMA receive requests are automatically disabled when a
receive error occurs.
1
0 R/W DMAERR 2
Transmit DMA Enable
Description Value
DMA for the transmit FIFO is disabled. 0
DMA for the transmit FIFO is enabled. 1
0 R/W TXDMAE 1
Receive DMA Enable
Description Value
DMA for the receive FIFO is disabled. 0
DMA for the receive FIFO is enabled. 1
0 R/W RXDMAE 0
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Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4
The UART9BITADDR register is used to write the specific address that should be matched with the
receiving byte when the 9-bit Address Mask (UART9BITAMASK) is set to 0xFF. This register is
used in conjunction with UART9BITAMASK to form a match for address-byte received.
UART 9-Bit Self Address (UART9BITADDR)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x0A4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADDR reserved 9BITEN
R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Enable 9-Bit Mode
Description Value
9-bit mode is disabled. 0
9-bit mode is enabled. 1
0 R/W 9BITEN 15
Self Address for 9-Bit Mode
This field contains the address that should be matched when
UART9BITAMASK is 0xFF.
0x00 R/W ADDR 7:0
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Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8
The UART9BITAMASK register is used to enable the address mask for 9-bit mode. The address
bits are masked to create a set of addresses to be matched with the received address byte.
UART 9-Bit Self Address Mask (UART9BITAMASK)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x0A8
Type R/W, reset 0x0000.00FF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MASK reserved
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Reset
Self Address Mask for 9-Bit Mode
This field contains the address mask that creates a set of addresses
that should be matched.
0xFF R/W MASK 7:0
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Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0
The UARTPP register provides information regarding the properties of the UART module.
UART Peripheral Properties (UARTPP)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFC0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SC NB reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
9-Bit Support
Description Value
The UART module does not provide support for the transmission
of 9-bit data for RS-485 support.
0
The UART module provides support for the transmission of 9-bit
data for RS-485 support.
1
0x1 RO NB 1
Smart Card Support
Description Value
The UART module does not provide smart card support. 0
The UART module provides smart card support. 1
0x1 RO SC 0
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Register 18: UART Clock Configuration (UARTCC), offset 0xFC8
The UARTCC register controls the baud clock source for the UART module. For more information,
see the section called Communication Clock Sources on page 211.
Note: If the PIOSC is used for the UART baud clock, the system clock frequency must be at least
9 MHz in Run mode.
UART Clock Configuration (UARTCC)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFC8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART Baud Clock Source
The following table specifies the source that generates for the UART
baud clock:
Description Value
System clock (based on clock source and divisor factor) 0x0
reserved 0x1-0x4
PIOSC 0x5
Reserved 0x5-0xF
0 R/W CS 3:0
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Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFD0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID4 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART Peripheral ID Register [7:0]
0x00 RO PID4 7:0
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reset values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFD4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID5 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID5 7:0
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reset values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFD8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID6 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID6 7:0
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Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
reset values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFDC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID7 7:0
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Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
reset values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFE0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID0 reserved
0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Reset
0x60 RO PID0 7:0
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reset values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFE4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID1 7:0
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reset values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFE8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID2 reserved
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Reset
0x18 RO PID2 7:0
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Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
reset values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFEC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID3 reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x01 RO PID3 7:0
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Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFF0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID0 reserved
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART PrimeCell ID Register [7:0]
0x0D RO CID0 7:0
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values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFF4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID1 reserved
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Reset
0xF0 RO CID1 7:0
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values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFF8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID2 reserved
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x05 RO CID2 7:0
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Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
values.
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFFC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID3 reserved
1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset
0xB1 RO CID3 7:0
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14 Synchronous Serial Interface (SSI)
The TM4C123AH6PM microcontroller includes four Synchronous Serial Interface (SSI) modules.
Each SSI module is a master or slave interface for synchronous serial communication with peripheral
devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial
interfaces.
The TM4C123AH6PM SSI modules have the following features:
Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
Master or slave operation
Programmable clock bit rate and prescaler
Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
Programmable data frame size from 4 to 16 bits
Internal loopback test mode for diagnostic/debug testing
Standard FIFO-based interrupts and End-of-Transmission interrupt
Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
Transmit single request asserted when there is space in the FIFO; burst request asserted
when four or more entries are available to be written in the FIFO
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14.1 Block Diagram
Figure 14-1. SSI Module Block Diagram
SSIPCellID0
SSIPCellID1
SSIPCellID2
SSIPCellID3
SSIPeriphID0
SSIPeriphID1
SSIPeriphID2
SSIPeriphID3
SSIPeriphID4
SSIPeriphID5
SSIPeriphID6
SSIPeriphID7
Clock Prescaler
SSICPSR
Control/Status
Interrupt Control
SSIDR
TxFIFO
8 x 16
.
.
.
RxFIFO
8 x 16
.
.
.
Transmit/
Receive
Logic
SSITx
SSIRx
SSIClk
SSIFss
DMA Control
SSIDMACTL
DMA Request
Interrupt
System Clock
SSISR
SSICR1
SSICR0
SSIRIS
SSIMIS
SSIIM
SSIICR
Clock Control
SSICC
SSI Baud Clock
PIOSC
The following table lists the external signals of the SSI module and describes the function of each.
Most SSI signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset. The exceptions to this rule are the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins, which
default to the SSI function. The "Pin Mux/Pin Assignment" column in the following table lists the
possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 612) should be set to choose the SSI function. The number in
(GPIOPCTL) register (page 629) to assign the SSI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see General-Purpose Input/Outputs (GPIOs) on page 591.
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Synchronous Serial Interface (SSI)
Table 14-1. SSI Signals (64LQFP)
a
Assignment
Pin Number Pin Name
SSI module 0 clock TTL I/O PA2 (2) 19 SSI0Clk
SSI module 0 frame signal TTL I/O PA3 (2) 20 SSI0Fss
SSI module 0 receive TTL I PA4 (2) 21 SSI0Rx
SSI module 0 transmit TTL O PA5 (2) 22 SSI0Tx
SSI module 1 clock. TTL I/O PF2 (2)
PD0 (2)
30
61
SSI1Clk
SSI module 1 frame signal. TTL I/O PF3 (2)
PD1 (2)
31
62
SSI1Fss
SSI module 1 receive. TTL I PF0 (2)
PD2 (2)
28
63
SSI1Rx
SSI module 1 transmit. TTL O PF1 (2)
PD3 (2)
29
64
SSI1Tx
SSI module 2 clock. TTL I/O PB4 (2) 58 SSI2Clk
SSI module 2 frame signal. TTL I/O PB5 (2) 57 SSI2Fss
SSI module 2 receive. TTL I PB6 (2) 1 SSI2Rx
SSI module 2 transmit. TTL O PB7 (2) 4 SSI2Tx
SSI module 3 clock. TTL I/O PD0 (1) 61 SSI3Clk
SSI module 3 frame signal. TTL I/O PD1 (1) 62 SSI3Fss
SSI module 3 receive. TTL I PD2 (1) 63 SSI3Rx
SSI module 3 transmit. TTL O PD3 (1) 64 SSI3Tx
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFOmemories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes. The SSI also supports the DMA interface. The transmit and receive FIFOs
can be programmed as destination/source addresses in the DMA module. DMA operation is
enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 922).
14.3.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 915). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register (see page 908).
The frequency of the output clock SSIClk is defined by:
SSIClk = SysClk / (CPSDVSR * (1 + SCR))
Note: The PIOSC is used as the source for the SSIClk when the CS field in the SSI Clock
Configuration (SSICC) register is configured to 0x5. For master mode, the system clock
or the PIOSC must be at least two times faster than the SSIClk, with the restriction that
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SSIClk cannot be faster than 25 MHz. For slave mode, the system clock or the PIOSC
must be at least 6 times faster than the SSIClk.
See Synchronous Serial Interface (SSI) on page 1213 to view SSI timing parameters.
14.3.2 FIFO Operation
14.3.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 912), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the Rn bit in the RCGCSSI register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a DMA request when the FIFO is empty.
14.3.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
14.3.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
Transmit FIFO service (when the transmit FIFO is half full or less)
Receive FIFO service (when the receive FIFO is half full or more)
Receive FIFO time-out
Receive FIFO overrun
End of transmission
Receive DMA transfer complete
Transmit DMA transfer complete
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
generates a single interrupt request to the controller regardless of the number of active interrupts.
Each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the
SSI Interrupt Mask (SSIIM) register (see page 916). Setting the appropriate mask bit enables the
interrupt.
The individual outputs, along with a combined interrupt output, allow use of either a global interrupt
service routine or modular device drivers to handle interrupts. The transmit and receive dynamic
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dataflowinterrupts have been separated fromthe status interrupts so that data can be read or written
in response to the FIFO trigger levels. The status of the individual interrupt sources can be read
from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers
(see page 917 and page 919, respectively).
The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not
SSIClk is currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If
the RX FIFO is emptied before 32 clocks have passed, the time-out period is reset. As a result, the
ISR should clear the Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing
a 1 to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared
so late that the ISR returns before the interrupt is actually cleared, or the ISR may be re-activated
unnecessarily.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely
and is only valid for Master mode devices/operations. This interrupt can be used to indicate when
it is safe to turn off the SSI module clock or enter sleep mode. In addition, because transmitted data
and received data complete at exactly the same time, the interrupt can also indicate that read data
is ready immediately, without waiting for the receive FIFO time-out period to complete.
Note: In Freescale SPI mode only, a condition can be created where an EOT interrupt is generated
for every byte transferred even if the FIFO is full. If the EOT bit has been set to 0 in an
integrated slave SSI and the DMA has been configured to transfer data from this SSI to
a Master SSI on the device using external loopback, an EOT interrupt is generated by the
SSI slave for every byte even if the FIFO is full.
14.3.4 Frame Formats
Each data frame is between 4 and 16 bits long depending on the size of data programmed and is
transmitted starting with the MSB. There are three basic frame types that can be selected by
programming the FRF bit in the SSICR0 register:
Texas Instruments synchronous serial
Freescale SPI
MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
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responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
14.3.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 14-2 on page 898 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
SSIFss
SSITx/SSIRx
MSB LSB
4 to 16 bits
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred fromthe transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
each falling edge of SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 14-3 on page 898 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer)
MSB LSB
SSIClk
SSIFss
SSITx/SSIRx
4 to 16 bits
14.3.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits in the SSICR0 control register.
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SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is set, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing
a clock transition before the first data capture edge. When the SPH phase control bit is clear, data
is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second
clock edge transition.
14.3.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 14-4 on page 899 and Figure 14-5 on page 899.
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx
Q
SSITx
MSB
MSB
LSB
LSB
4 to 16 bits
Note: Q is undefined.
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx
LSB
SSITx MSB LSB
LSB
MSB
MSB
MSB
LSB
4 to16 bits
In this configuration, during idle periods:
SSIClk is forced Low
SSIFss is forced High
The transmit data line SSITx is arbitrarily forced Low
When the SSI is configured as a master, it enables the SSIClk pad
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When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSIFss master signal being driven Low, causing slave data to be enabled onto the SSIRx input
line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Once both the
master and slave data have been set, the SSIClk master clock pin goes High after one additional
half SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSIFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned
to its idle state one SSIClk period after the last bit has been captured.
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
14-6 on page 900, which covers both single and continuous transfers.
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
Q MSB
LSB
LSB
4 to 16 bits
Q
the SSIFss master signal being driven Low. The master SSITx output is enabled. After an additional
one-half SSIClk period, both master and slave valid data are enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
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Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Lowbetween successive data words,
and termination is the same as that of the single word transfer.
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 14-7 on page 901 and Figure 14-8 on page 901.
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
Q MSB
MSB LSB
LSB
4 to 16 bits
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx
MSB LSB LSB MSB
4 to 16 bits
SSIClk is forced High
the SSIFss master signal being driven Low, causing slave data to be immediately transferred onto
the SSIRx line of the master. The master SSITx output pad is enabled.
One-half period later, valid master data is transferred to the SSITx line. Once both the master and
slave data have been set, the SSIClk master clock pin becomes Low after one additional half
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SSIClk period, meaning that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSIFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned
to its idle state one SSIClk period after the last bit has been captured.
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
14-9 on page 902, which covers both single and continuous transfers.
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
MSB
LSB
LSB
4 to 16 bits
Q
SSIClk is forced High
the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After an
additional one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state until the
final bit of the last word has been captured and then returns to its idle state as described above.
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For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
14.3.4.7 MICROWIRE Frame Format
Figure 14-10 on page 903 shows the MICROWIRE frame format for a single frame. Figure
14-11 on page 904 shows the same format when back-to-back frames are transmitted.
Figure 14-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSIRx 0
SSITx
8-bit control
4 to 16 bits
output data
LSB
MSB
MSB
LSB
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex and uses a master-slave message passing technique. Each serial transmission begins
with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Lowfor the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of
SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one
clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto
the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge
of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock
period after the last bit has been latched in the receive serial shifter, causing the data to be transferred
to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
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from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
LSB MSB SSIRx 0
SSITx LSB LSB
MSB
4 to 16 bits
output data
8-bit control
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 14-12 on page 904 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
t
Hold
=t
SSIClk
t
Setup
=(2*t
SSIClk
)
The SSI peripheral provides an interface to the DMA controller with separate channels for transmit
and receive. The DMA operation of the SSI is enabled through the SSI DMAControl (SSIDMACTL)
register. When DMA operation is enabled, the SSI asserts a DMA request on the receive or
transmit channel when the associated FIFO can transfer data. For the receive channel, a single
transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is
asserted whenever the amount of data in the receive FIFO is 4 or more items. For the transmit
channel, a single transfer request is asserted whenever at least one empty location is in the transmit
FIFO. The burst request is asserted whenever the transmit FIFO has 4 or more empty slots. The
single and burst DMAtransfer requests are handled automatically by the DMAcontroller depending
how the DMA channel is configured. To enable DMA operation for the receive channel, the
RXDMAE bit of the DMA Control (SSIDMACTL) register should be set. To enable DMA operation
for the transmit channel, the TXDMAE bit of SSIDMACTL should be set. If DMA is enabled, then
the DMA controller triggers an interrupt when a transfer is complete. The interrupt occurs on the
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SSI interrupt vector. Therefore, if interrupts are used for SSI operation and DMA is enabled, the
SSI interrupt handler must be designed to handle the DMA completion interrupt.
See Micro Direct Memory Access (DMA) on page 527 for more details about programming the
DMA controller.
To enable and initialize the SSI, the following steps are necessary:
1. Enable the SSI module using the RCGCSSI register (see page 327).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 322).
To find out which GPIO port to enable, refer to Table 21-5 on page 1176.
3. Set the GPIOAFSEL bits for the appropriate pins (see page 612). To determine which GPIOs to
4. Configure the PMCn fields in the GPIOPCTL register to assign the SSI signals to the appropriate
pins. See page 629 and Table 21-5 on page 1176.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the SSI clock source by writing to the SSICC register.
4. Configure the clock prescale divisor by writing the SSICPSR register.
5. Write the SSICR0 register with the following configuration:
Serial clock rate (SCR)
Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
The data size (DSS)
6. Optionally, configure the DMAchannel (see Micro Direct Memory Access (DMA) on page 527)
and enable the DMA option(s) in the SSIDMACTL register.
7. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
Master operation
Freescale SPI mode (SPO=1, SPH=1)
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1 Mbps bit rate
8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
1x10
6
= 20x10
6
/ (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=0x2, SCR must be 0x9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is clear.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register.
14.5 Register Map
Table 14-2 on page 906 lists the SSI registers. The offset listed is a hexadecimal increment to the
registers address, relative to that SSI modules base address:
SSI0: 0x4000.8000
SSI1: 0x4000.9000
SSI2: 0x4000.A000
SSI3: 0x4000.B000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 327). There must be a delay of 3 system clocks after the SSI module clock is enabled before
any SSI module registers are accessed.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 14-2. SSI Register Map
See
page
908 SSI Control 0 0x0000.0000 R/W SSICR0 0x000
910 SSI Control 1 0x0000.0000 R/W SSICR1 0x004
912 SSI Data 0x0000.0000 R/W SSIDR 0x008
913 SSI Status 0x0000.0003 RO SSISR 0x00C
915 SSI Clock Prescale 0x0000.0000 R/W SSICPSR 0x010
916 SSI Interrupt Mask 0x0000.0000 R/W SSIIM 0x014
917 SSI Raw Interrupt Status 0x0000.0008 RO SSIRIS 0x018
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Table 14-2. SSI Register Map (continued)
See
page
919 SSI Masked Interrupt Status 0x0000.0000 RO SSIMIS 0x01C
921 SSI Interrupt Clear 0x0000.0000 W1C SSIICR 0x020
922 SSI DMA Control 0x0000.0000 R/W SSIDMACTL 0x024
923 SSI Clock Configuration 0x0000.0000 R/W SSICC 0xFC8
924 SSI Peripheral Identification 4 0x0000.0000 RO SSIPeriphID4 0xFD0
927 SSI Peripheral Identification 7 0x0000.0000 RO SSIPeriphID7 0xFDC
928 SSI Peripheral Identification 0 0x0000.0022 RO SSIPeriphID0 0xFE0
931 SSI Peripheral Identification 3 0x0000.0001 RO SSIPeriphID3 0xFEC
932 SSI PrimeCell Identification 0 0x0000.000D RO SSIPCellID0 0xFF0
933 SSI PrimeCell Identification 1 0x0000.00F0 RO SSIPCellID1 0xFF4
934 SSI PrimeCell Identification 2 0x0000.0005 RO SSIPCellID2 0xFF8
935 SSI PrimeCell Identification 3 0x0000.00B1 RO SSIPCellID3 0xFFC
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
The SSICR0 register contains bit fields that control various functions within the SSI module.
Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DSS FRF SPO SPH SCR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SSI Serial Clock Rate
This bit field is used to generate the transmit and receive bit rate of the
SSI. The bit rate is:
BR=SysClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
0x00 R/W SCR 15:8
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. This bit has the most impact on the first bit transmitted
by either allowing or not allowing a clock transition before the first data
capture edge.
Description Value
Data is captured on the first clock edge transition. 0
Data is captured on the second clock edge transition. 1
0 R/W SPH 7
SSI Serial Clock Polarity
Description Value
A steady state Low value is placed on the SSIClk pin. 0
A steady state High value is placed on the SSIClk pin when
data is not being transferred.
1
0 R/W SPO 6
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SSI Frame Format Select
Frame Format Value
Freescale SPI Frame Format 0x0
Texas Instruments Synchronous Serial Frame Format 0x1
MICROWIRE Frame Format 0x2
Reserved 0x3
0x0 R/W FRF 5:4
SSI Data Size Select
Data Size Value
Reserved 0x0-0x2
4-bit data 0x3
5-bit data 0x4
6-bit data 0x5
7-bit data 0x6
8-bit data 0x7
9-bit data 0x8
10-bit data 0x9
11-bit data 0xA
12-bit data 0xB
13-bit data 0xC
14-bit data 0xD
15-bit data 0xE
16-bit data 0xF
0x0 R/W DSS 3:0
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Register 2: SSI Control 1 (SSICR1), offset 0x004
The SSICR1 register contains bit fields that control various functions within the SSI module. Master
and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LBM SSE MS SOD EOT reserved
R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
End of Transmission
This bit is only valid for Master mode devices and operations (MS = 0x0).
Description Value
The TXRIS interrupt indicates that the transmit FIFO is half full
or less.
0
The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.
1
Note: In Freescale SPI mode only, a condition can be created where
an EOT interrupt is generated for every byte transferred even
if the FIFO is full. If the EOT bit has been set to 0 in an
integrated slave SSI and the DMA has been configured to
transfer data fromthis SSI to a Master SSI on the device using
external loopback, an EOT interrupt is generated by the SSI
slave for every byte even if the FIFO is full.
0 R/W EOT 4
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the systemwhile ensuring that only one slave drives data onto
the serial output line. In such systems, the TXDlines frommultiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
Description Value
SSI can drive the SSITx output in Slave mode. 0
SSI must not drive the SSITx output in Slave mode. 1
0 R/W SOD 3
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SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
the SSI is disabled (SSE=0).
Description Value
The SSI is configured as a master. 0
The SSI is configured as a slave. 1
0 R/W MS 2
SSI Synchronous Serial Port Enable
Description Value
SSI operation is disabled. 0
SSI operation is enabled. 1
Note: This bit must be cleared before any control registers
are reprogrammed.
0 R/W SSE 1
SSI Loopback Mode
Description Value
Normal serial port operation enabled. 0
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
1
0 R/W LBM 0
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Register 3: SSI Data (SSIDR), offset 0x008
The SSIDR register is 16-bits wide. When the SSIDR register is read, the entry in the receive FIFO
that is pointed to by the current FIFO read pointer is accessed. When a data value is removed by
the SSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO
pointed to by the current FIFO write pointer.
When the SSIDR register is written to, the entry in the transmit FIFO that is pointed to by the write
pointer is written to. Data values are removed from the transmit FIFO one value at a time by the
transmit logic. Each data value is loaded into the transmit serial shifter, then serially shifted out onto
the SSITx pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is cleared, allowing the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
0x0000 R/W DATA 15:0
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Register 4: SSI Status (SSISR), offset 0x00C
The SSISR register contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x00C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TFE TNF RNE RFF BSY reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SSI Busy Bit
Description Value
The SSI is idle. 0
The SSI is currently transmitting and/or receiving a frame, or
the transmit FIFO is not empty.
1
0 RO BSY 4
SSI Receive FIFO Full
Description Value
The receive FIFO is not full. 0
The receive FIFO is full. 1
0 RO RFF 3
SSI Receive FIFO Not Empty
Description Value
The receive FIFO is empty. 0
The receive FIFO is not empty. 1
0 RO RNE 2
SSI Transmit FIFO Not Full
Description Value
The transmit FIFO is full. 0
The transmit FIFO is not full. 1
1 RO TNF 1
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SSI Transmit FIFO Empty
Description Value
The transmit FIFO is not empty. 0
The transmit FIFO is empty. 1
1 RO TFE 0
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Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
The SSICPSR register specifies the division factor which is used to derive the SSIClk from the
system clock. The clock is further divided by a value from 1 to 256, which is 1 + SCR. SCR is
programmed in the SSICR0 register. The frequency of the SSIClk is defined by:
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CPSDVSR reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
0x00 R/W CPSDVSR 7:0
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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared on reset.
On a read, this register gives the current value of the mask on the corresponding interrupt. Setting
a bit sets the mask, preventing the interrupt from being signaled to the interrupt controller. Clearing
a bit clears the corresponding mask, enabling the interrupt to be sent to the interrupt controller.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x014
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RORIM RTIM RXIM TXIM reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
SSI Transmit FIFO Interrupt Mask
Description Value
The transmit FIFO interrupt is masked. 0
The transmit FIFO interrupt is not masked. 1
0 R/W TXIM 3
SSI Receive FIFO Interrupt Mask
Description Value
The receive FIFO interrupt is masked. 0
The receive FIFO interrupt is not masked. 1
0 R/W RXIM 2
SSI Receive Time-Out Interrupt Mask
Description Value
The receive FIFO time-out interrupt is masked. 0
The receive FIFO time-out interrupt is not masked. 1
0 R/W RTIM 1
SSI Receive Overrun Interrupt Mask
Description Value
The receive FIFO overrun interrupt is masked. 0
The receive FIFO overrun interrupt is not masked. 1
0 R/W RORIM 0
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Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RORRIS RTRIS RXRIS TXRIS reserved
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
SSI Transmit FIFO Raw Interrupt Status
Description Value
No interrupt. 0
If the EOT bit in the SSICR1 register is clear, the transmit FIFO
is half empty or less.
If the EOT bit is set, the transmit FIFO is empty, and the last bit
has been transmitted out of the serializer.
1
This bit is cleared when the transmit FIFO is more than half full (if the
EOT bit is clear) or when it has any data in it (if the EOT bit is set).
1 RO TXRIS 3
SSI Receive FIFO Raw Interrupt Status
Description Value
No interrupt. 0
The receive FIFO is half full or more. 1
This bit is cleared when the receive FIFO is less than half full.
0 RO RXRIS 2
SSI Receive Time-Out Raw Interrupt Status
Description Value
No interrupt. 0
The receive time-out has occurred. 1
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
0 RO RTRIS 1
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SSI Receive Overrun Raw Interrupt Status
Description Value
No interrupt. 0
The receive FIFO has overflowed 1
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
0 RO RORRIS 0
April 10, 2013 918
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x01C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RORMIS RTMIS RXMIS TXMIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
SSI Transmit FIFO Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to the transmit FIFO
being half empty or less (if the EOT bit is clear) or due to the
transmission of the last data bit (if the EOT bit is set).
1
This bit is cleared when the transmit FIFO is more than half empty (if
the EOT bit is clear) or when it has any data in it (if the EOT bit is set).
0 RO TXMIS 3
SSI Receive FIFO Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to the receive FIFO
being half full or more.
1
This bit is cleared when the receive FIFO is less than half full.
0 RO RXMIS 2
SSI Receive Time-Out Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to the receive time
out.
1
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
0 RO RTMIS 1
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SSI Receive Overrun Masked Interrupt Status
Description Value
An unmasked interrupt was signaled due to the receive FIFO
overflowing.
1
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
0 RO RORMIS 0
April 10, 2013 920
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RORIC RTIC reserved
W1C W1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
SSI Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and
the RTMIS bit in the SSIMIS register.
0 W1C RTIC 1
SSI Receive Overrun Interrupt Clear
Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register and
the RORMIS bit in the SSIMIS register.
0 W1C RORIC 0
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Register 10: SSI DMA Control (SSIDMACTL), offset 0x024
The SSIDMACTL register is the DMA control register.
SSI DMA Control (SSIDMACTL)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RXDMAE TXDMAE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Transmit DMA Enable
Description Value
DMA for the transmit FIFO is disabled. 0
DMA for the transmit FIFO is enabled. 1
0 R/W TXDMAE 1
Receive DMA Enable
Description Value
DMA for the receive FIFO is disabled. 0
DMA for the receive FIFO is enabled. 1
0 R/W RXDMAE 0
April 10, 2013 922
Register 11: SSI Clock Configuration (SSICC), offset 0xFC8
The SSICC register controls the baud clock source for the SSI module.
Note: If the PIOSC is used for the SSI baud clock, the system clock frequency must be at least
16 MHz in Run mode.
SSI Clock Configuration (SSICC)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFC8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SSI Baud Clock Source
The following table specifies the source that generates for the SSI baud
clock:
Description Value
System clock (based on clock source and divisor factor) 0x0
reserved 0x1-0x4
PIOSC 0x5
Reserved 0x6 - 0xF
0 R/W CS 3:0
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Register 12: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID4 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SSI Peripheral ID Register [7:0]
0x00 RO PID4 7:0
April 10, 2013 924
value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID5 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID5 7:0
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value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID6 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID6 7:0
April 10, 2013 926
Register 15: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFDC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID7 7:0
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Register 16: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID0 reserved
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Reset
0x22 RO PID0 7:0
April 10, 2013 928
value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x00 RO PID1 7:0
929 April 10, 2013
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value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID2 reserved
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Reset
0x18 RO PID2 7:0
April 10, 2013 930
Register 19: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFEC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PID3 reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x01 RO PID3 7:0
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Register 20: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID0 reserved
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SSI PrimeCell ID Register [7:0]
0x0D RO CID0 7:0
April 10, 2013 932
value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID1 reserved
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Reset
0xF0 RO CID1 7:0
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value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID2 reserved
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0x05 RO CID2 7:0
April 10, 2013 934
Register 23: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
value.
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFFC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CID3 reserved
1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset
0xB1 RO CID3 7:0
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15 Inter-Integrated Circuit (I
2
C) Interface
The Inter-Integrated Circuit (I
2
C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I
2
C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I
2
C
bus may also be used for system testing and diagnostic purposes in product development and
manufacturing. The TM4C123AH6PM microcontroller includes providing the ability to communicate
(both transmit and receive) with other I
2
C devices on the bus.
The TM4C123AH6PM controller includes I
2
C modules with the following features:
Devices on the I
2
C bus can be designated as either a master or a slave
Supports both transmitting and receiving data as either a master or a slave
Supports simultaneous master and slave operation
Four I
2
C modes
Master transmit
Master receive
Slave transmit
Slave receive
Four transmission speeds:
Standard (100 Kbps)
Fast-mode (400 Kbps)
Fast-mode plus (1 Mbps)
High-speed mode (3.33 Mbps)
Clock low timeout interrupt
Dual slave address capability
Glitch suppression
Master and slave interrupt generation
Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
April 10, 2013 936
2
C) Interface
15.1 Block Diagram
Figure 15-1. I
2
C Block Diagram
I
2
C I/O Select
I
2
C Master Core
Interrupt
I
2
C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIMR
I2CSRIS
I2CSMIS
I2CSICR I2CMMIS
I
2
C Control
I2CPP
The following table lists the external signals of the I
2
C interface and describes the function of each.
The I
2
C interface signals are alternate functions for some GPIO signals and default to be GPIO
signals at reset, with the exception of the I2C0SCL and I2CSDA pins which default to the I
2
C
function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for the I
2
Csignals. The AFSEL bit in the GPIOAlternate Function Select (GPIOAFSEL)
register (page 612) should be set to choose the I
2
C function. The number in parentheses is the
encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL)
register (page 629) to assign the I
2
C signal to the specified GPIOport pin. Note that the I2CSDA pin
should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more
Table 15-1. I2C Signals (64LQFP)
a
Assignment
Pin Number Pin Name
I
2
C module 0 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
OD I/O PB2 (3) 47 I2C0SCL
I
2
C module 0 data. OD I/O PB3 (3) 48 I2C0SDA
I
2
OD I/O PA6 (3)
PG4 (3)
23
33
I2C1SCL
I
2
C module 1 data. OD I/O PA7 (3)
PG5 (3)
24
32
I2C1SDA
I
2
OD I/O PE4 (3) 59 I2C2SCL
I
2
C module 2 data. OD I/O PE5 (3) 60 I2C2SDA
I
2
OD I/O PG0 (3)
PD0 (3)
37
61
I2C3SCL
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Table 15-1. I2C Signals (64LQFP) (continued)
a
Assignment
Pin Number Pin Name
I
2
C module 3 data. OD I/O PG1 (3)
PD1 (3)
36
62
I2C3SDA
I
2
OD I/O PG2 (3) 35 I2C4SCL
I
2
C module 4 data. OD I/O PG3 (3) 34 I2C4SDA
I
2
I
2
Each I
2
C module is comprised of both master and slave functions and is identified by a unique
address. A master-initiated communication generates the clock signal, SCL. For proper operation,
the SDA pin must be configured as an open-drain signal. Due to the internal circuitry that supports
high-speed operation, the SCL pin must not be configured as an open-drain signal, although the
internal circuitry causes it to act as if it were an open drain signal. Both SDA and SCL signals must
be connected to a positive supply voltage using a pull-up resistor. A typical I
2
C bus configuration is
shown in Figure 15-2. Refer to the I2C-bus specification and user manual to determine the size of
the pull-ups needed for proper operation.
See Inter-Integrated Circuit (I
2
C) Interface on page 1215 for I
2
C timing diagrams.
Figure 15-2. I
2
C Bus Configuration
R
PUP
Tiva
Microcontroller
I2CSCL I2CSDA
R
PUP
3rd Party Device
with I
2
C Interface
SCL SDA
I
2
C Bus
SCL
SDA
SCL SDA
3rd Party Device
with I
2
C Interface
15.3.1 I
2
C Bus Functional Overview
The I
2
Cbus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on TM4C123AH6PM
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I
2
C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in START and STOP Conditions on page 939) is unrestricted, but
each data byte has to be followed by an acknowledge bit, and data must be transferred MSB first.
When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force
the transmitter into a wait state. The data transfer continues when the receiver releases the clock
SCL.
April 10, 2013 938
2
C) Interface
15.3.1.1 START and STOP Conditions
The protocol of the I
2
C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
15-3.
Figure 15-3. START and STOP Conditions
START
condition
SDA
SCL
STOP
condition
SDA
SCL
The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated
START condition. To generate a single transmit cycle, the I
2
C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and the Control register is written
with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the
operation is completed (or aborted due an error), the interrupt pin becomes active and the data may
be read from the I
2
C Master Data (I2CMDR) register. When the I
2
C module operates in Master
receiver mode, the ACK bit is normally set causing the I
2
C bus controller to transmit an acknowledge
automatically after each byte. This bit must be cleared when the I
2
Cbus controller requires no further
data to be transmitted from the slave transmitter.
When operating in slave mode, the STARTRIS and STOPRIS bits in the I
2
C Slave Raw Interrupt
Status (I2CSRIS) register indicate detection of start and stop conditions on the bus and the I
2
C
Slave Masked Interrupt Status (I2CSMIS) register can be configured to allow STARTRIS and
STOPRIS to be promoted to controller interrupts (when interrupts are enabled).
15.3.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 15-4. After the START condition, a slave address
is transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S
bit in the I2CMSA register). If the R/S bit is clear, it indicates a transmit operation (send), and if it
is set, it indicates a request for data (receive). A data transfer is always terminated by a STOP
condition generated by the master, however, a master can initiate communications with another
device on the bus by generating a repeated START condition and addressing another slave without
first generating a STOP condition. Various combinations of receive/transmit formats are then possible
within a single transfer.
Figure 15-4. Complete Data Transfer with a 7-Bit Address
Data Slave address
ACK LSB MSB ACK R/S LSB MSB
SDA
SCL 1 2 7 8 9 1 2 7 8 9
Stop Start
The first seven bits of the first byte make up the slave address (see Figure 15-5). The eighth bit
determines the direction of the message. A zero in the R/S position of the first byte means that the
939 April 10, 2013
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master transmits (sends) data to the selected slave, and a one in this position means that the master
receives data from the slave.
Figure 15-5. R/S Bit in First Byte
R/S
LSB
Slave address
MSB
15.3.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 15-6).
Figure 15-6. Data Validity During Bit Transfer on the I
2
C Bus
Change
of data
allowed
Data line
stable
SDA
SCL
15.3.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data transmitted out by the receiver during the acknowledge cycle must comply with the
data validity requirements described in Data Validity on page 940.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Because the master controls the number of bytes in the transfer, it signals the
end of data to the slave transmitter by not generating an acknowledge on the last data byte. The
slave transmitter must then release SDA to allow the master to generate the STOP or a repeated
START condition.
If the slave is required to provide a manual ACK or NACK, the I
2
C Slave ACK Control
(I2CSACKCTL) register allows the slave to NACK for invalid data or command or ACK for valid
data or command. When this operation is enabled, the MCU slave module I
2
C clock is pulled low
after the last data bit until this register is written with the indicated response.
15.3.1.5 Repeated Start
The I
2
C master module has the capability of executing a repeated START (transmit or receive) after
an initial transfer has occurred.
A repeated start sequence for a Master transmit is as follows:
1. When the device is in the idle state, the Master writes the slave address to the I2CMSA register
and configures the R/S bit for the desired transfer type.
April 10, 2013 940
2
C) Interface
2. Data is written to the I2CMDR register.
3. When the BUSY bit in the I2CMCS register is '0' , the Master writes 0x3 to the I2CMCS register
to initiate a transfer.
4. The Master does not generate a STOP condition but instead writes another slave address to
the I2CMSA register and then writes 0x3 to initiate the repeated START.
A repeated start sequence for a Master receive is similar:
1. When the device is in idle, the Master writes the slave address to the I2CMSA register and
configures the R/S bit for the desired transfer type.
2. The master reads data from the I2CMDR register.
3. When the BUSY bit in the I2CMCS register is '0' , the Master writes 0x3 to the I2CMCS register
to initiate a transfer.
4. The Master does not generate a STOP condition but instead writes another slave address to
the I2CMSA register and then writes 0x3 to initiate the repeated START.
For more information on repeated START, refer to Figure 15-12 on page 951 and Figure
15-13 on page 952.
15.3.1.6 Clock Low Timeout (CLTO)
The I
2
C slave can extend the transaction by pulling the clock low periodically to create a slow bit
transfer rate. The I
2
C module has a 12-bit programmable counter that is used to track how long the
clock has been held low. The upper 8 bits of the count value are software programmable through
the I
2
C Master Clock Low Timeout Count (I2CMCLKOCNT) register. The lower four bits are not
user visible and are 0x0. The CNTL value programmed in the I2CMCLKOCNT register has to be
greater than 0x01. The application can program the eight most significant bits of the counter to
reflect the acceptable cumulative low period in transaction. The count is loaded at the START
condition and counts down on each falling edge of the internal bus clock of the Master. Note that
the internal bus clock generated for this counter keeps running at the programmed I
2
C speed even
if SCL is held lowon the bus. Upon reaching terminal count, the master state machine forces ABORT
on the bus by issuing a STOP condition at the instance of SCL and SDA release.
As an example, if an I
2
Cmodule was operating at 100 kHz speed, programming the I2CMCLKOCNT
register to 0xDA would translate to the value 0xDA0 since the lower four bits are set to 0x0. This
would translate to a decimal value of 3488 clocks or a cumulative clock low period of 34.88 ms at
100 kHz.
The CLKRIS bit in the I
2
C Master Raw Interrupt Status (I2CMRIS) register is set when the clock
timeout period is reached, allowing the master to start corrective action to resolve the remote slave
state. In addition, the CLKTO bit in the I
2
C Master Control/Status (I2CMCS) register is set; this bit
is cleared when a STOP condition is sent or during the I
2
C master reset. The status of the raw SDA
and SCL signals are readable by software through the SDA and SCL bits in the I
2
C Master Bus
Monitor (I2CMBMON) register to help determine the state of the remote slave.
In the event of a CLTO condition, application software must choose how it intends to attempt bus
recovery. Most applications may attempt to manually toggle the I
2
C pins to force the slave to let go
of the clock signal (a common solution is to attempt to force a STOP on the bus). If a CLTO is
detected before the end of a burst transfer, and the bus is successfully recovered by the master,
the master hardware attempts to finish the pending burst operation. Depending on the state of the
941 April 10, 2013
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slave after bus recovery, the actual behavior on the bus varies. If the slave resumes in a state where
it can acknowledge the master (essentially where it was before the bus hang), it continues where
it left off. However, if the slave resumes in a reset state (or if a forced STOP by the master causes
the slave to enter the idle state), it may ignore the master's attempt to complete the burst operation
and NAK the first data byte that the master sends or requests.
Since the behavior of slaves cannot always be predicted, it is suggested that application software
always write the STOP bit in the I
2
C Master Configuration (I2CMCR) register during the CLTO
interrupt service routine. This limits the amount of data the master attempts to send or receive upon
bus recovery to a single byte, and after the single byte is on the wire, the master issues a STOP.
An alternative solution is to have the application software reset the I
2
C peripheral before attempting
to manually recover the bus. This solution allows the I
2
Cmaster hardware to be returned to a known
good (and idle) state before attempting to recover a stuck bus and prevents any unwanted data
from appearing on the wire."
Note: The Master Clock Low Timeout counter counts for the entire time SCL is held Low
continuously. If SCL is de-asserted at any point, the Master Clock Low Timeout Counter is
reloaded with the value in the I2CMCLKOCNT register and begins counting down from this
value.
15.3.1.7 Dual Address
The I
2
C interface supports dual address capability for the slave. The additional programmable
address is provided and can be matched if enabled. In legacy mode with dual address disabled,
the I
2
C slave provides an ACK on the bus if the address matches the OAR field in the I2CSOAR
register. In dual address mode, the I
2
C slave provides an ACK on the bus if either the OAR field in
the I2CSOAR register or the OAR2 field in the I2CSOAR2 register is matched. The enable for dual
address is programmable through the OAR2EN bit in the I2CSOAR2 register and there is no disable
on the legacy address.
The OAR2SEL bit in the I2CSCSR register indicates if the address that was ACKed is the alternate
address or not. When this bit is clear, it indicates either legacy operation or no address match.
15.3.1.8 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a '1' (High) on SDA, while another master transmits a '0'
(Low), switches off its data output stage and retires until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
15.3.1.9 Glitch Suppression in Multi-Master Configuration
When a multi-master configuration is being used, the GFE bit in the I
2
C Master Configuration
(I2CMCR) register can be set to enable glitch suppression on the SCL and SDA lines and assure
proper signal values. The filter can be programmed to different filter widths using the GFPW bit in
the I
2
C Master Configuration 2 (I2CMCR2) register. The glitch suppression value is in terms of
buffered system clocks. Note that all signals will be delayed internally when glitch suppression is
nonzero. For example, if GFPW is set to 0x7, 31 clocks should be added onto the calculation for the
expected transaction time.
April 10, 2013 942
2
C) Interface
15.3.2 Available Speed Modes
The I
2
C bus can run in Standard mode (100 kbps), Fast mode (400 kbps), Fast mode plus (1 Mbps)
or High-Speed mode (3.33 Mbps). The selected mode should match the speed of the other I
2
C
devices on the bus.
15.3.2.1 Standard, Fast, and Fast Plus Modes
Standard, Fast, and Fast Plus modes are selected using a value in the I
2
C Master Timer Period
(I2CMTPR) register that results in an SCL frequency of 100 kbps for Standard mode, 400 kbps for
Fast mode, or 1 Mbps for Fast mode plus.
The I
2
C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2CMTPR register (see page 965). This value is
determined by replacing the known variables in the equation below and solving for TIMER_PRD.
The I
2
C clock period is calculated as follows:
SCL_PERIOD = 2 (1 + TIMER_PRD) (SCL_LP + SCL_HP) CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/SCL_PERIOD = 333 Khz
Table 15-2 gives examples of the timer periods that should be used to generate Standard, Fast
mode, and Fast mode plus SCL frequencies based on various system clock frequencies.
2
C Master Timer Period versus Speed Mode
Fast Mode
Plus
Timer
Period
Fast Mode Timer Period Standard Mode Timer Period System Clock
- - - - 100 Kbps 0x01 4 MHz
- - - - 100 Kbps 0x02 6 MHz
- - 312 Kbps 0x01 89 Kbps 0x06 12.5 MHz
- - 278 Kbps 0x02 93 Kbps 0x08 16.7 MHz
- - 333 Kbps 0x02 100 Kbps 0x09 20 MHz
- - 312 Kbps 0x03 96.2 Kbps 0x0C 25 MHz
- - 330 Kbps 0x04 97.1 Kbps 0x10 33 MHz
1000 Kbps 0x01 400 Kbps 0x04 100 Kbps 0x13 40 MHz
943 April 10, 2013
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15.3.2.2 High-Speed Mode
The TM4C123AH6PM I
2
C peripheral has support for High-speed operation as both a master and
slave. High-Speed mode is configured by setting the HS bit in the I
2
C Master Control/Status
(I2CMCS) register. High-Speed mode transmits data at a high bit rate with a 66.6%/33.3% duty
cycle, but communication and arbitration are done at Standard, Fast mode, or Fast-mode plus
speed, depending on which is selected by the user. When the HS bit in the I2CMCS register is set,
current mode pull-ups are enabled.
The clock period can be selected using the equation below, but in this case, SCL_LP=2 and
SCL_HP=1.
SCL_PERIOD = 2 (1 + TIMER_PRD) (SCL_LP + SCL_HP) CLK_PRD
So for example:
CLK_PRD = 25 ns
TIMER_PRD = 1
SCL_LP=2
SCL_HP=1
yields a SCL frequency of:
1/T = 3.33 Mhz
Table 15-3 on page 944 gives examples of timer period and systemclock in High-Speed mode. Note
that the HS bit in the I2CMTPR register needs to be set for the TPR value to be used in High-Speed
mode.
2
C Master Timer Period in High-Speed Mode
Transmission Mode Timer Period System Clock
3.33 Mbps 0x01 40 MHz
2.77 Mbps 0x02 50 MHz
3.33 Mbps 0x03 80 MHz
When operating as a master, the protocol is shown in Figure 15-7. The master is responsible for
sending a master code byte in either Standard (100 Kbps) or Fast-mode (400 Kbps) before it begins
transferring in High-speed mode. The master code byte must contain data in the formof 0000.1XXX
and is used to tell the slave devices to prepare for a High-speed transfer. The master code byte
should never be acknowledged by a slave since it is only used to indicate that the upcoming data
is going to be transferred at a higher data rate. To send the master code byte, software should place
the value of the master code byte into the I2CMSA register and write the I2CMCS register with a
value of 0x13. This places the I
2
C master peripheral in High-speed mode, and all subsequent
transfers (until STOP) are carried out at High-speed data rate using the normal I2CMCS command
bits, without setting the HS bit in the I2CMCS register. Again, setting the HS bit in the I2CMCS register
is only necessary during the master code byte.
When operating as a High-speed slave, there is no additional software required.
April 10, 2013 944
2
C) Interface
Figure 15-7. High-Speed Data Format
SDA
SCL
Device-Specific NAK Address
R/W
Data
Standard (100 KHz) or Fast Mode (400 KHz) High Speed
(3.3 Mbps)
Note: High-Speed mode is 3.4 Mbps, provided correct system clock frequency is set and there is
appropriate pull strength on SCL and SDA lines.
15.3.3 Interrupts
The I
2
C can generate interrupts when the following conditions are observed:
Master transaction completed
Master arbitration lost
Master transaction error
Master bus timeout
Slave transaction received
Slave transaction requested
Stop condition on bus detected
Start condition on bus detected
The I
2
C master and I
2
C slave modules have separate interrupt signals. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
15.3.3.1 I
2
C Master Interrupts
The I
2
C master module generates an interrupt when a transaction completes (either transmit or
receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I
2
C
master interrupt, software must set the IM bit in the I
2
C Master Interrupt Mask (I2CMIMR) register.
When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I
2
C
Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction
and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction
wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration,
the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in
the I
2
C Master Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I
2
C Master Raw Interrupt Status (I2CMRIS) register.
15.3.3.2 I
2
C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by setting the DATAIM bit in the I
2
C Slave Interrupt Mask (I2CSIMR) register. Software
945 April 10, 2013
Tiva
determines whether the module should write (transmit) or read (receive) data from the I
2
C Slave
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I
2
C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by setting the DATAIC bit in the
I
2
C Slave Interrupt Clear (I2CSICR) register.
In addition, the slave module can generate an interrupt when a start and stop condition is detected.
These interrupts are enabled by setting the STARTIM and STOPIM bits of the I
2
C Slave Interrupt
Mask (I2CSIMR) register and cleared by writing a 1 to the STOPIC and STARTIC bits of the I
2
C
Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I
2
C Slave Raw Interrupt Status (I2CSRIS) register.
15.3.4 Loopback Operation
The I
2
C modules can be placed into an internal loopback mode for diagnostic or debug work by
setting the LPBK bit in the I
2
C Master Configuration (I2CMCR) register. In loopback mode, the
SDA and SCL signals from the master and are tied to the SDA and SCL signals of the slave module
to allow internal testing of the device without having to go through I/O.
15.3.5 Command Sequence Flow Charts
This section details the steps required to perform the various I
2
C transfer types in both master and
slave mode.
15.3.5.1 I
2
C Master Command Sequences
The figures that follow show the command sequences available for the I
2
C master.
April 10, 2013 946
2
C) Interface
Figure 15-8. Master Single TRANSMIT
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
Sequence
may be
omitted in a
Single Master
system
BUSBSY bit=0?
NO
Write ---0-111
to I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
YES
NO
NO
947 April 10, 2013
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Figure 15-9. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
Sequence may be
omitted in a Single
Master system
BUSBSY bit=0?
NO
Write ---00111
to I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
NO
NO
Read data from
I2CMDR
YES
April 10, 2013 948
2
C) Interface
Figure 15-10. Master TRANSMIT of Multiple Data Bytes
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
BUSBSY bit=0?
YES
Write ---0-011
to I2CMCS
NO
Read I2CMCS
BUSY bit=0?
YES
ERROR bit=0?
YES
ARBLST bit=1?
Write data to
I2CMDR
Write ---0-100
to I2CMCS
Index=n?
NO
Error Service
Idle
YES
Write ---0-001
to I2CMCS
Write ---0-101
to I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
NO
Idle
YES
Error Service
NO
NO
NO
NO
Sequence
may be
omitted in a
Single Master
system
949 April 10, 2013
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Figure 15-11. Master RECEIVE of Multiple Data Bytes
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
BUSBSY bit=0?
NO
Write ---01011
to I2CMCS
YES
Read I2CMCS
BUSY bit=0?
NO
ERROR bit=0?
YES
ARBLST bit=1?
Write ---0-100
to I2CMCS
NO
Error Service
YES
Idle
Read data from
I2CMDR
Index=m-1?
Write ---00101
to I2CMCS
YES
Idle
Read data from
I2CMDR
Error Service
ERROR bit=0?
YES
Write ---01001
to I2CMCS
Read I2CMCS
BUSY bit=0?
NO
YES
Sequence
may be
omitted in a
Single Master
system
NO
NO
NO
April 10, 2013 950
2
C) Interface
Figure 15-12. Master RECEIVE with Repeated START after Master TRANSMIT
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011
to I2CMCS
Master operates in
Master Receive mode
Idle
Repeated START
condition is generated
with changing data
direction
951 April 10, 2013
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Figure 15-13. Master TRANSMIT with Repeated START after Master RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011
to I2CMCS
Master operates in
Master Transmit mode
Idle
Repeated START
condition is generated
with changing data
direction
April 10, 2013 952
2
C) Interface
Figure 15-14. Standard High Speed Mode Master Transmit
IDLE
write slave address
to I2CMSA register
write ---10011
to I2CMCS register
read I2CMCS register
Busy=0'
Error=0'
IDLE
write Slave Address
to I2MSA register
write Data
to I2CMDR register
yes
yes
no
no
Normal sequence starts here. The
sequence below covers SINGLE send
write ---0-111
to I2CMCS register
read I2CMCS register
Busy=0'
Error=0'
IDLE
yes
yes
no
Error service
IDLE
no
Master code and
arbitration is always
done in FAST or
STANDARD mode
953 April 10, 2013
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15.3.5.2 I
2
C Slave Command Sequences
Figure 15-15 on page 954 presents the command sequence available for the I
2
C slave.
Figure 15-15. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1
to I2CSCSR
Read I2CSCSR
RREQ bit=1?
Read data from
I2CSDR
YES
TREQ bit=1?
NO
Write data to
I2CSDR
YES
NO
FBR is
also valid
The following example shows how to configure the I
2
C module to transmit a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I
2
Cclock using the RCGCI2Cregister in the SystemControl module (see page 329).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register in the System
Control module (see page 322). To find out which GPIO port to enable, refer to Table
21-5 on page 1176.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 612). To determine which GPIOs to configure, see Table
21-4 on page 1170.
4. Enable the I2CSDA pin for open-drain operation. See page 617.
April 10, 2013 954
2
C) Interface
5. Configure the PMCn fields in the GPIOPCTL register to assign the I
2
C signals to the appropriate
6. Initialize the I
2
C Master by writing the I2CMCR register with a value of 0x0000.0010.
7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPRregister represents the number of systemclock periods
in one SCL clock period. The TPR value is determined by the following equation:
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (20MHz/(2*(6+4)*100000))-1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
8. Specify the slave address of the master and that the next operation is a Transmit by writing the
I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
9. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the
desired data.
10. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register
with a value of 0x0000.0007 (STOP, START, RUN).
11. Wait until the transmission completes by polling the I2CMCS registers BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
To configure the I
2
C master to High Speed mode:
1. Enable the I
2
Cclock using the RCGCI2Cregister in the SystemControl module (see page 329).
Control module (see page 322). To find out which GPIO port to enable, refer to Table
21-5 on page 1176.
GPIOAFSEL register (see page 612). To determine which GPIOs to configure, see Table
21-4 on page 1170.
4. Enable the I2CSDA pin for open-drain operation. See page 617.
5. Configure the PMCn fields in the GPIOPCTL register to assign the I
2
C signals to the appropriate
6. Initialize the I
2
C Master by writing the I2CMCR register with a value of 0x0000.0010.
7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPRregister represents the number of systemclock periods
in one SCL clock period. The TPR value is determined by the following equation:
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (80 MHz/(2*(2+1)*3330000))-1;
TPR = 3
955 April 10, 2013
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Write the I2CMTPR register with the value of 0x0000.0003.
8. To send the master code byte, software should place the value of the master code byte into the
I2CMSA register and write the I2CMCS register with a value of 0x13.
9. This places the I2C master peripheral in High-speed mode, and all subsequent transfers (until
STOP) are carried out at High-speed data rate using the normal I2CMCS command bits, without
setting the HS bit in the I2CMCS register.
10. The transaction is ended by setting the STOP bit in the I2CMCS register.
11. Wait until the transmission completes by polling the I2CMCS registers BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
15.5 Register Map
Table 15-4 on page 956 lists the I
2
Cregisters. All addresses given are relative to the I
2
Cbase address:
I
2
C 0: 0x4002.0000
I
2
C 1: 0x4002.1000
I
2
C 2: 0x4002.2000
I
2
C 3: 0x4002.3000
I
2
C 4: 0x400C.0000
I
2
C 5: 0x400C.1000
Note that the I
2
C module clock must be enabled before the registers can be programmed (see
page 329). There must be a delay of 3 system clocks after the I
2
C module clock is enabled before
any I
2
C module registers are accessed.
The hw_i2c.h file in the TivaWare
Driver Library uses a base address of 0x800 for the I

2
C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that TivaWare
for C Series uses an offset between 0x000 and 0x018 with the slave base address.
2
C) Interface Register Map
See
page
I
2
C Master
958 I2C Master Slave Address 0x0000.0000 R/W I2CMSA 0x000
959 I2C Master Control/Status 0x0000.0020 R/W I2CMCS 0x004
964 I2C Master Data 0x0000.0000 R/W I2CMDR 0x008
965 I2C Master Timer Period 0x0000.0001 R/W I2CMTPR 0x00C
966 I2C Master Interrupt Mask 0x0000.0000 R/W I2CMIMR 0x010
967 I2C Master Raw Interrupt Status 0x0000.0000 RO I2CMRIS 0x014
968 I2C Master Masked Interrupt Status 0x0000.0000 RO I2CMMIS 0x018
969 I2C Master Interrupt Clear 0x0000.0000 WO I2CMICR 0x01C
970 I2C Master Configuration 0x0000.0000 R/W I2CMCR 0x020
April 10, 2013 956
2
C) Interface
2
C) Interface Register Map (continued)
See
page
972 I2C Master Clock Low Timeout Count 0x0000.0000 R/W I2CMCLKOCNT 0x024
973 I2C Master Bus Monitor 0x0000.0003 RO I2CMBMON 0x02C
974 I2C Master Configuration 2 0x0000.0000 R/W I2CMCR2 0x038
I
2
C Slave
975 I2C Slave Own Address 0x0000.0000 R/W I2CSOAR 0x800
976 I2C Slave Control/Status 0x0000.0000 RO I2CSCSR 0x804
978 I2C Slave Data 0x0000.0000 R/W I2CSDR 0x808
979 I2C Slave Interrupt Mask 0x0000.0000 R/W I2CSIMR 0x80C
980 I2C Slave Raw Interrupt Status 0x0000.0000 RO I2CSRIS 0x810
981 I2C Slave Masked Interrupt Status 0x0000.0000 RO I2CSMIS 0x814
982 I2C Slave Interrupt Clear 0x0000.0000 WO I2CSICR 0x818
983 I2C Slave Own Address 2 0x0000.0000 R/W I2CSOAR2 0x81C
984 I2C Slave ACK Control 0x0000.0000 R/W I2CSACKCTL 0x820
I
2
C Status and Control
985 I2C Peripheral Properties 0x0000.0001 RO I2CPP 0xFC0
986 I2C Peripheral Configuration 0x0000.0001 RO I2CPC 0xFC4
2
C Master)
The remainder of this section lists and describes the I
2
C master registers, in numerical order by
address offset.
957 April 10, 2013
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Register 1: I
2
C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Transmit (Low).
I2C Master Slave Address (I2CMSA)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R/S SA reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I
2
C Slave Address
This field specifies bits A6 through A0 of the slave address.
0x00 R/W SA 7:1
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Transmit
(Low).
Description Value
Transmit 0
Receive 1
0 R/W R/S 0
April 10, 2013 958
2
C) Interface
Register 2: I
2
C Master Control/Status (I2CMCS), offset 0x004
This register accesses status bits when read and control bits when written. When read, the status
register indicates the state of the I
2
C bus controller. When written, the control register configures
the I
2
C controller operation.
The START bit generates the START or REPEATED START condition. The STOP bit determines if
the cycle stops at the end of the data cycle or continues to the next transfer cycle, which could be
a repeated START. To generate a single transmit cycle, the I
2
C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and this register is written with
ACK=X(0 or 1), STOP=1, START=1, and RUN=1 to performthe operation and stop. When the operation
is completed (or aborted due an error), an interrupt becomes active and the data may be read from
the I2CMDRregister. When the I
2
Cmodule operates in Master receiver mode, the ACK bit is normally
set, causing the I
2
C bus controller to transmit an acknowledge automatically after each byte. This
bit must be cleared when the I
2
C bus controller requires no further data to be transmitted from the
slave transmitter.
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BUSY ERROR ADRACK DATACK ARBLST IDLE BUSBSY CLKTO reserved
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Reset
Clock Timeout Error
Description Value
No clock timeout error. 0
The clock timeout error has occurred. 1
This bit is cleared when the master sends a STOP condition or if the
I
2
C master is reset.
0 RO CLKTO 7
959 April 10, 2013
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Bus Busy
Description Value
The I
2
C bus is idle. 0
The I
2
C bus is busy. 1
The bit changes based on the START and STOP conditions.
0 RO BUSBSY 6
I
2
C Idle
Description Value
The I
2
C controller is not idle. 0
The I
2
C controller is idle. 1
1 RO IDLE 5
Arbitration Lost
Description Value
The I
2
C controller won arbitration. 0
The I
2
C controller lost arbitration. 1
0 RO ARBLST 4
Acknowledge Data
Description Value
The transmitted data was acknowledged 0
The transmitted data was not acknowledged. 1
0 RO DATACK 3
Acknowledge Address
Description Value
The transmitted address was acknowledged 0
The transmitted address was not acknowledged. 1
0 RO ADRACK 2
Error
Description Value
No error was detected on the last operation. 0
An error occurred on the last operation. 1
The error can be fromthe slave address not being acknowledged or the
transmit data not being acknowledged.
0 RO ERROR 1
I
2
C Busy
Description Value
The controller is idle. 0
The controller is busy. 1
When the BUSY bit is set, the other status bits are not valid.
0 RO BUSY 0
April 10, 2013 960
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C) Interface
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RUN START STOP ACK HS reserved
WO WO WO WO WO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:5
High-Speed Enable
Description Value
The master operates in Standard, Fast mode, or Fast mode
plus as selected by using a value in the I2CMTPR register that
results in an SCL frequency of 100 kbps for Standard mode,
400 kbps for Fast mode, or 1 Mpbs for Fast mode plus.
0
The master operates in High-Speed mode with transmission
speeds up to 3.33 Mbps.
1
0 WO HS 4
Data Acknowledge Enable
Description Value
The received data byte is not acknowledged automatically by
the master.
0
The received data byte is acknowledged automatically by the
master. See field decoding in Table 15-5 on page 962.
1
0 WO ACK 3
Generate STOP
Description Value
The controller does not generate the STOP condition. 0
The controller generates the STOPcondition. See field decoding
1
0 WO STOP 2
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Generate START
Description Value
The controller does not generate the START condition. 0
The controller generates the START or repeated START
condition. See field decoding in Table 15-5 on page 962.
1
0 WO START 1
I
2
C Master Enable
Description Value
This encoding means the master is unable to transmit or receive
data.
0
The master is able to transmit or receive data.
See field decoding in Table 15-5 on page 962.
1
0 WO RUN 0
Table 15-5. Write Field Decoding for I2CMCS[3:0] Field
Description
I2CMCS[3:0] I2CMSA[0]
Current
State
RUN START STOP ACK R/S
START condition followed by TRANSMIT (master goes
to the Master Transmit state).
1 1 0 X
a
0
Idle
START condition followed by a TRANSMIT and STOP
condition (master remains in Idle state).
1 1 1 X 0
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1 1 0 0 1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1 1 1 0 1
START condition followed by RECEIVE (master goes to
the Master Receive state).
1 1 0 1 1
Illegal 1 1 1 1 1
NOP All other combinations not listed are non-operations.
April 10, 2013 962
2
C) Interface
Table 15-5. Write Field Decoding for I2CMCS[3:0] Field (continued)
Description
I2CMCS[3:0] I2CMSA[0]
Current
State
RUN START STOP ACK R/S
TRANSMIT operation (master remains in Master
Transmit state).
1 0 0 X X
Master
Transmit
STOP condition (master goes to Idle state). 0 0 1 X X
TRANSMIT followed by STOP condition (master goes
to Idle state).
1 0 1 X X
Repeated START condition followed by a TRANSMIT
(master remains in Master Transmit state).
1 1 0 X 0
Repeated START condition followed by TRANSMIT and
STOP condition (master goes to Idle state).
1 1 1 X 0
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1 1 0 0 1
Repeated START condition followed by a TRANSMIT
and STOP condition (master goes to Idle state).
1 1 1 0 1
Repeated START condition followed by RECEIVE
(master goes to Master Receive state).
1 1 0 1 1
Illegal. 1 1 1 1 1
NOP. All other combinations not listed are non-operations.
RECEIVE operation with negative ACK (master remains
in Master Receive state).
1 0 0 0 X
Master
Receive
b
0 0 1 X X
RECEIVE followed by STOP condition (master goes to
Idle state).
1 0 1 0 X
RECEIVE operation (master remains in Master Receive
state).
1 0 0 1 X
Illegal. 1 0 1 1 X
operation with a negative ACK(master remains in Master
Receive state).
1 1 0 0 1
Repeated START condition followed by RECEIVE and
1 1 1 0 1
(master remains in Master Receive state).
1 1 0 1 1
Repeated START condition followed by TRANSMIT
(master goes to Master Transmit state).
1 1 0 X 0
Repeated START condition followed by TRANSMIT and
1 1 1 X 0
NOP. All other combinations not listed are non-operations.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Register 3: I
2
C Master Data (I2CMDR), offset 0x008
This register contains the data to be transmitted when in the Master Transmit state and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
This byte contains the data transferred during a transaction. 0x00 R/W DATA 7:0
April 10, 2013 964
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C) Interface
Register 4: I
2
C Master Timer Period (I2CMTPR), offset 0x00C
This register is programmed to set the timer period for the SCL clock and assign the SCL clock to
either standard or high-speed mode.
I2C Master Timer Period (I2CMTPR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x00C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TPR HS reserved
R/W R/W R/W R/W R/W R/W R/W WO RO RO RO RO RO RO RO RO Type
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
High-Speed Enable
Description Value
The SCL Clock Period set by TPR applies to Standard mode
(100 Kbps), Fast-mode (400 Kbps), or Fast-mode plus (1 Mbps).
0
The SCL Clock Period set by TPR applies to High-speed mode
(3.33 Mbps).
1
0x0 WO HS 7
Timer Period
This field is used in the equation to configure SCL_PERIOD:
SCL_PERIOD = 2(1 + TPR)(SCL_LP + SCL_HP)CLK_PRD
where:
SCL_PRD is the SCL line period (I
2
C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
CLK_PRD is the system clock period in ns.
0x1 R/W TPR 6:0
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Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IM CLKIM reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Clock Timeout Interrupt Mask
Description Value
The CLKRIS interrupt is suppressed and not sent to the interrupt
controller.
0
The clock timeout interrupt is sent to the interrupt controller
when the CLKRIS bit in the I2CMRIS register is set.
1
0 R/W CLKIM 1
Master Interrupt Mask
Description Value
The RIS interrupt is suppressed and not sent to the interrupt
controller.
0
The master interrupt is sent to the interrupt controller when the
RIS bit in the I2CMRIS register is set.
1
0 R/W IM 0
April 10, 2013 966
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C) Interface
Register 6: I
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x014
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RIS CLKRIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Clock Timeout Raw Interrupt Status
Description Value
No interrupt. 0
The clock timeout interrupt is pending. 1
This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICRregister.
0 RO CLKRIS 1
Master Raw Interrupt Status
Description Value
No interrupt. 0
A master interrupt is pending. 1
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
0 RO RIS 0
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Register 7: I
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MIS CLKMIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Clock Timeout Masked Interrupt Status
Description Value
No interrupt. 0
An unmasked clock timeout interrupt was signaled and is
pending.
1
This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICRregister.
0 RO CLKMIS 1
Masked Interrupt Status
Description Value
An unmasked master interrupt was signaled and is pending. 1
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
0 RO MIS 0
April 10, 2013 968
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C) Interface
Register 8: I
2
C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw and masked interrupts.
I2C Master Interrupt Clear (I2CMICR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x01C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IC CLKIC reserved
WO WO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:2
Clock Timeout Interrupt Clear
Writing a 1 to this bit clears the CLKRIS bit in the I2CMRIS register and
the CLKMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
0 WO CLKIC 1
Master Interrupt Clear
Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the
MIS bit in the I2CMMIS register.
0 WO IC 0
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Register 9: I
2
C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave), enables the glitch filter, and sets the interface
for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LPBK reserved MFE SFE GFE reserved
R/W RO RO RO R/W R/W R/W RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I
2
C Glitch Filter Enable
Description Value
I
2
C glitch filter is disabled. 0
I
2
C glitch filter is enabled. 1
Use the GFPW bit in the I
2
CMaster Configuration 2 (I2CMCR2) register
to program the pulse width.
0 R/W GFE 6
I
2
C Slave Function Enable
Description Value
Slave mode is disabled. 0
Slave mode is enabled. 1
0 R/W SFE 5
I
2
C Master Function Enable
Description Value
Master mode is disabled. 0
Master mode is enabled. 1
0 R/W MFE 4
0x0 RO reserved 3:1
April 10, 2013 970
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C) Interface
I
2
C Loopback
Description Value
Normal operation. 0
The controller in a test mode loopback configuration. 1
0 R/W LPBK 0
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Register 10: I
2
C Master Clock Low Timeout Count (I2CMCLKOCNT), offset
0x024
This register contains the upper 8 bits of a 12-bit counter that can be used to keep the timeout limit
for clock stretching by a remote slave. The lower four bits of the counter are not user visible and
are always 0x0.
Note: The Master Clock Low Timeout counter counts for the entire time SCL is held Low
continuously. If SCL is de-asserted at any point, the Master Clock Low Timeout Counter is
reloaded with the value in the I2CMCLKOCNT register and begins counting down from this
value.
I2C Master Clock Low Timeout Count (I2CMCLKOCNT)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CNTL reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I
2
C Master Count
This field contains the upper 8 bits of a 12-bit counter for the clock low
timeout count.
Note: The value of CNTL must be greater than 0x1.
0 R/W CNTL 7:0
April 10, 2013 972
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C) Interface
Register 11: I
2
C Master Bus Monitor (I2CMBMON), offset 0x02C
This register is used to determine the SCL and SDA signal status.
I2C Master Bus Monitor (I2CMBMON)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x02C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCL SDA reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I
2
C SDA Status
Description Value
The I2CSDA signal is low. 0
The I2CSDA signal is high. 1
1 RO SDA 1
I
2
C SCL Status
Description Value
The I2CSCL signal is low. 0
The I2CSCL signal is high. 1
1 RO SCL 0
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Register 12: I
2
C Master Configuration 2 (I2CMCR2), offset 0x038
This register can be programmed to select the pulse width for glitch suppression, measured in
system clocks.
I2C Master Configuration 2 (I2CMCR2)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x038
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved GFPW reserved
RO RO RO RO R/W R/W R/W RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:7
I
2
C Glitch Filter Pulse Width
This field controls the pulse width select for glitch suppression on the
SCL and SDA lines. Glitch suppression values can be programmed
relative to system clocks.
Description Value
Bypass 0x0
1 clock 0x1
2 clocks 0x2
3 clocks 0x3
4 clocks 0x4
8 clocks 0x5
16 clocks 0x6
31 clocks 0x7
0 R/W GFPW 6:4
0 RO reserved 3:0
2
C Slave)
2
C slave registers, in numerical order by
address offset.
April 10, 2013 974
2
C) Interface
Register 13: I
2
C Slave Own Address (I2CSOAR), offset 0x800
This register consists of seven address bits that identify the TM4C123AH6PM I
2
C device on the I
2
C
bus.
I2C Slave Own Address (I2CSOAR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x800
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OAR reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I
2
C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
0x00 R/W OAR 6:0
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Register 14: I
2
C Slave Control/Status (I2CSCSR), offset 0x804
This register functions as a control register when written, and a status register when read.
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x804
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RREQ TREQ FBR OAR2SEL reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
OAR2 Address Matched
Description Value
Either the address is not matched or the match is in legacy
mode.
0
OAR2 address matched and ACKed by the slave. 1
This bit gets reevaluated after every address comparison.
0 RO OAR2SEL 3
First Byte Received
Description Value
The first byte has not been received. 0
The first byte following the slaves own address has been
received.
1
This bit is only valid when the RREQ bit is set and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
0 RO FBR 2
April 10, 2013 976
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C) Interface
Transmit Request
Description Value
No outstanding transmit request. 0
The I
2
C controller has been addressed as a slave transmitter
and is using clock stretching to delay the master until data has
been written to the I2CSDR register.
1
0 RO TREQ 1
Receive Request
Description Value
No outstanding receive data. 0
The I
2
C controller has outstanding receive data from the I
2
C
master and is using clock stretching to delay the master until
the data has been read from the I2CSDR register.
1
0 RO RREQ 0
Write-Only Control Register
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x804
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DA reserved
WO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Device Active
Description Value
Disables the I
2
C slave operation. 0
Enables the I
2
C slave operation. 1
Once this bit has been set, it should not be set again unless it has been
cleared by writing a 0 or by a reset, otherwise transfer failures may
occur.
0 WO DA 0
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Register 15: I
2
C Slave Data (I2CSDR), offset 0x808
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x808
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
0x00 R/W DATA 7:0
April 10, 2013 978
2
C) Interface
Register 16: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x80C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x80C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATAIM STARTIM STOPIM reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:3
Stop Condition Interrupt Mask
Description Value
The STOPRIS interrupt is suppressed and not sent to the
0
The STOP condition interrupt is sent to the interrupt controller
when the STOPRIS bit in the I2CSRIS register is set.
1
0 R/W STOPIM 2
Start Condition Interrupt Mask
Description Value
The STARTRIS interrupt is suppressed and not sent to the
0
The START condition interrupt is sent to the interrupt controller
when the STARTRIS bit in the I2CSRIS register is set.
1
0 R/W STARTIM 1
Data Interrupt Mask
Description Value
The DATARIS interrupt is suppressed and not sent to the
0
The data received or data requested interrupt is sent to the
interrupt controller when the DATARIS bit in the I2CSRISregister
is set.
1
0 R/W DATAIM 0
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Register 17: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x810
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x810
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATARIS STARTRIS STOPRIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:3
Stop Condition Raw Interrupt Status
Description Value
No interrupt. 0
A STOP condition interrupt is pending. 1
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
0 RO STOPRIS 2
Start Condition Raw Interrupt Status
Description Value
No interrupt. 0
A START condition interrupt is pending. 1
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0 RO STARTRIS 1
Data Raw Interrupt Status
Description Value
No interrupt. 0
A data received or data requested interrupt is pending. 1
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
0 RO DATARIS 0
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C) Interface
Register 18: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x814
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x814
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATAMIS STARTMIS STOPMIS reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:3
Stop Condition Masked Interrupt Status
Description Value
An unmasked STOPcondition interrupt was signaled is pending. 1
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
0 RO STOPMIS 2
Start Condition Masked Interrupt Status
Description Value
An unmasked START condition interrupt was signaled is
pending.
1
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0 RO STARTMIS 1
Data Masked Interrupt Status
Description Value
An unmasked data received or data requested interrupt was
signaled is pending.
1
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
0 RO DATAMIS 0
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Register 19: I
2
C Slave Interrupt Clear (I2CSICR), offset 0x818
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x818
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATAIC STARTIC STOPIC reserved
WO WO WO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:3
Stop Condition Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register
and the STOPMIS bit in the I2CSMIS register.
0 WO STOPIC 2
Start Condition Interrupt Clear
Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register
and the STARTMIS bit in the I2CSMIS register.
0 WO STARTIC 1
Data Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register
and the STOPMIS bit in the I2CSMIS register.
0 WO DATAIC 0
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Register 20: I
2
C Slave Own Address 2 (I2CSOAR2), offset 0x81C
This register consists of seven address bits that identify the alternate address for the I
2
C device on
the I
2
C bus.
I2C Slave Own Address 2 (I2CSOAR2)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x81C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OAR2 OAR2EN reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I
2
C Slave Own Address 2 Enable
Description Value
The alternate address is disabled. 0
Enables the use of the alternate address in the OAR2 field. 1
0 R/W OAR2EN 7
I
2
C Slave Own Address 2
This field specifies the alternate OAR2 address.
0x00 R/W OAR2 6:0
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Register 21: I
2
C Slave ACK Control (I2CSACKCTL), offset 0x820
This register enables the I
2
C slave to NACK for invalid data or command or ACK for valid data or
command. The I
2
C clock is pulled low after the last data bit until this register is written.
I2C Slave ACK Control (I2CSACKCTL)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x820
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ACKOEN ACKOVAL reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I
2
C Slave ACK Override Value
Description Value
An ACK is sent indicating valid data or command. 0
A NACK is sent indicating invalid data or command. 1
0 R/W ACKOVAL 1
I
2
C Slave ACK Override Enable
Description Value
A response in not provided. 0
An ACK or NACK is sent according to the value written to the
ACKOVAL bit.
1
0 R/W ACKOEN 0
2
C Status and Control)
2
C status and control registers, in numerical
order by address offset.
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C) Interface
Register 22: I
2
C Peripheral Properties (I2CPP), offset 0xFC0
The I2CPP register provides information regarding the properties of the I
2
C module.
I2C Peripheral Properties (I2CPP)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0xFC0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
HS reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
High-Speed Capable
Description Value
The interface is capable of Standard, Fast, or Fast mode plus
operation.
0
The interface is capable of High-Speed operation. 1
0x1 RO HS 0
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Register 23: I
2
C Peripheral Configuration (I2CPC), offset 0xFC4
The I2CPC register allows software to enable features present in the I
2
C module.
I2C Peripheral Configuration (I2CPC)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0xFC4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
HS reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:1
High-Speed Capable
Description Value
The interface is set to Standard, Fast or Fast mode plus
operation.
0
The interface is set to High-Speed operation. Note that this
encoding may only be used if the HS bit in the I2CPP register
is set. Otherwise, this encoding is not available.
1
1 R/W HS 0
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C) Interface
16 Controller Area Network (CAN) Module
Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, it is also used in many embedded control
applications (such as industrial and medical). Bit rates up to 1 Mbps are possible at network lengths
less than 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at
500 meters).
The TM4C123AH6PM microcontroller includes two CAN units with the following features:
CAN protocol version 2.0 part A/B
Bit rates up to 1 Mbps
32 message objects with individual identifier masks
Maskable interrupt
Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
Programmable loopback mode for self-test operation
Programmable FIFO mode enables storage of multiple message objects
Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
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16.1 Block Diagram
Figure 16-1. CAN Controller Block Diagram
CAN Control
CAN Core
CANIF2CRQ
CANIF2CMSK
CANIF2MSK1
CANIF2MSK2
CANIF2ARB1
CANIF2ARB2
CANIF2MCTL
CANIF2DA1
Message Object
Registers
CANNWDA1
CANTXRQ1
CANTXRQ2
CANNWDA2
CANMSG1INT
CANMSG2INT
CANMSG1VAL
CANMSG2VAL
CAN Tx
CANINT
CANTST
CANBRPE
CANERR
CANCTL
CANSTS
CANBIT
CAN Interface 1
CANIF1CRQ
CANIF1CMSK
CANIF1MSK1
CANIF1MSK2
CANIF1ARB1
CANIF1ARB2
CANIF1MCTL
CANIF1DA1
CANIF1DA2
CANIF1DB1
CANIF1DB2
CAN Interface 2
APB
Interface
APB Pins
Message RAM
32 Message Objects
CAN Rx
CANIF2DA2
CANIF2DB1
CANIF2DB2
The following table lists the external signals of the CAN controller and describes the function of
each. The CAN controller signals are alternate functions for some GPIO signals and default to be
GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the
possible GPIO pin placements for the CAN signals. The AFSEL bit in the GPIOAlternate Function
Select (GPIOAFSEL) register (page 612) should be set to choose the CAN controller function. The
number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO
Port Control (GPIOPCTL) register (page 629) to assign the CAN signal to the specified GPIO port
pin. For more information on configuring GPIOs, see General-Purpose Input/Outputs
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Controller Area Network (CAN) Module
Table 16-1. Controller Area Network Signals (64LQFP)
a
Assignment
Pin Number Pin Name
CAN module 0 receive. TTL I PF0 (3)
PB4 (8)
PE4 (8)
28
58
59
CAN0Rx
CAN module 0 transmit. TTL O PF3 (3)
PB5 (8)
PE5 (8)
31
57
60
CAN0Tx
CAN module 1 receive. TTL I PA0 (8) 17 CAN1Rx
CAN module 1 transmit. TTL O PA1 (8) 18 CAN1Tx
The TM4C123AH6PM CAN controller conforms to the CAN protocol version 2.0 (parts A and B).
Message transfers that include data, remote, error, and overload frames with an 11-bit identifier
(standard) or a 29-bit identifier (extended) are supported. Transfer rates can be programmed up to
1 Mbps.
The CAN module consists of three major parts:
CAN protocol controller and message handler
Message memory
CAN register interface
A data frame contains data for transmission, whereas a remote frame contains no data and is used
to request the transmission of a specific message object. The CANdata/remote frame is constructed
as shown in Figure 16-2.
Figure 16-2. CAN Data/Remote Frame
Number
Of Bits
S
O
F
EOP IFS
Bus
Idle
1 1 6 1 11 or 29 0 . . . 64 15 7 3 1 1
A
C
K
Data Field
Control
Field
R
T
R
Message Delimiter
Bus
Idle
Bit Stuffing
CAN Data Frame
Arbitration Field
CRC Sequence
CRC
Field
Acknowledgement
Field
End of
Frame
Field
Interframe
Field
Start
Of Frame
Remote
Transmission
Request
Delimiter
Bits
CRC
Sequence
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The protocol controller transfers and receives the serial data fromthe CAN bus and passes the data
on to the message handler. The message handler then loads this information into the appropriate
message object based on the current filtering and identifiers in the message object memory. The
message handler is also responsible for generating interrupts based on events on the CAN bus.
The message object memory is a set of 32 identical memory blocks that hold the current configuration,
status, and actual data for each message object. These memory blocks are accessed via either of
the CAN message object register interfaces.
The message memory is not directly accessible in the TM4C123AH6PM memory map, so the
TM4C123AH6PM CAN controller provides an interface to communicate with the message memory
via two CANinterface register sets for communicating with the message objects. These two interfaces
must be used to read or write to each message object. The two message object interfaces allow
parallel access to the CAN controller message objects when multiple objects may have new
information that must be processed. In general, one interface is used for transmit data and one for
receive data.
16.3.1 Initialization
To use the CAN controller, the peripheral clock must be enabled using the RCGC0 register (see
page 430). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2
register (see page 438). To find out which GPIOport to enable, refer to Table 21-4 on page 1170. Set
the GPIO AFSEL bits for the appropriate pins (see page 612). Configure the PMCn fields in the
GPIOPCTL register to assign the CAN signals to the appropriate pins. See page 629 and Table
21-5 on page 1176.
Software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register (with
software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error
counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus
are stopped and the CANnTX signal is held High. Entering the initialization state does not change
the configuration of the CAN controller, the message objects, or the error counters. However, some
configuration registers are only accessible while in the initialization state.
To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each
message object. If a message object is not needed, label it as not valid by clearing the MSGVAL bit
in the CAN IFn Arbitration 2 (CANIFnARB2) register. Otherwise, the whole message object must
be initialized, as the fields of the message object may not have valid information, causing unexpected
results. Both the INIT and CCE bits in the CANCTL register must be set in order to access the
CANBIT register and the CAN Baud Rate Prescaler Extension (CANBRPE) register to configure
the bit timing. To leave the initialization state, the INIT bit must be cleared. Afterwards, the internal
Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for
the occurrence of a sequence of 11 consecutive recessive bits (indicating a bus idle condition)
before it takes part in bus activities and starts message transfers. Message object initialization does
not require the CAN to be in the initialization state and can be done on the fly. However, message
objects should all be configured to particular identifiers or set to not valid before message transfer
starts. To change the configuration of a message object during normal operation, clear the MSGVAL
bit in the CANIFnARB2 register to indicate that the message object is not valid during the change.
When the configuration is completed, set the MSGVAL bit again to indicate that the message object
is once again valid.
16.3.2 Operation
Two sets of CAN Interface Registers (CANIF1x and CANIF2x) are used to access the message
objects in the Message RAM. The CAN controller coordinates transfers to and from the Message
RAM to and from the registers. The two sets are independent and identical and can be used to
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queue transactions. Generally, one interface is used to transmit data and one is used to receive
data.
Once the CAN module is initialized and the INIT bit in the CANCTL register is cleared, the CAN
module synchronizes itself to the CAN bus and starts the message transfer. As each message is
received, it goes through the message handler's filtering process, and if it passes through the filter,
is stored in the message object specified by the MNUM bit in the CAN IFn Command Request
(CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and
eight data bytes) is stored in the message object. If the Identifier Mask (the MSK bits in the CAN IFn
Mask 1 and CANIFn Mask 2 (CANIFnMSKn) registers) is used, the arbitration bits that are masked
to "don't care" may be overwritten in the message object.
The CPUmay read or write each message at any time via the CANInterface Registers. The message
handler guarantees data consistency in case of concurrent accesses.
The transmission of message objects is under the control of the software that is managing the CAN
hardware. Message objects can be used for one-time data transfers or can be permanent message
objects used to respond in a more periodic manner. Permanent message objects have all arbitration
and control set up, and only the data bytes are updated. At the start of transmission, the appropriate
TXRQST bit in the CAN Transmission Request n (CANTXRQn) register and the NEWDAT bit in the
CAN New Data n (CANNWDAn) register are set. If several transmit messages are assigned to the
same message object (when the number of message objects is not sufficient), the whole message
object has to be configured before the transmission of this message is requested.
The transmission of any number of message objects may be requested at the same time; they are
transmitted according to their internal priority, which is based on the message identifier (MNUM) for
the message object, with 1 being the highest priority and 32 being the lowest priority. Messages
may be updated or set to not valid any time, even when their requested transmission is still pending.
The old data is discarded when a message is updated before its pending transmission has started.
Depending on the configuration of the message object, the transmission of a message may be
requested autonomously by the reception of a remote frame with a matching identifier.
Transmission can be automatically started by the reception of a matching remote frame. To enable
this mode, set the RMTEN bit in the CANIFn Message Control (CANIFnMCTL) register. A matching
received remote frame causes the TXRQST bit to be set, and the message object automatically
transfers its data or generates an interrupt indicating a remote frame was requested. A remote frame
can be strictly a single message identifier, or it can be a range of values specified in the message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are identified
as remote frame requests. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are identified as a remote frame request. The MXTD
bit in the CANIFnMSK2 register should be set if a remote frame request is expected to be triggered
by 29-bit extended identifiers.
16.3.3 Transmitting Message Objects
If the internal transmit shift register of the CAN module is ready for loading, and if a data transfer is
not occurring between the CAN Interface Registers and message RAM, the valid message object
with the highest priority that has a pending transmission request is loaded into the transmit shift
register by the message handler and the transmission is started. The message object's NEWDAT bit
in the CANNWDAn register is cleared. After a successful transmission, and if no new data was
written to the message object since the start of the transmission, the TXRQST bit in the CANTXRQn
register is cleared. If the CAN controller is configured to interrupt on a successful transmission of a
message object, (the TXIE bit in the CAN IFn Message Control (CANIFnMCTL) register is set),
the INTPND bit in the CANIFnMCTL register is set after a successful transmission. If the CAN
module has lost the arbitration or if an error occurred during the transmission, the message is
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re-transmitted as soon as the CAN bus is free again. If, meanwhile, the transmission of a message
with higher priority has been requested, the messages are transmitted in the order of their priority.
16.3.4 Configuring a Transmit Message Object
The following steps illustrate how to configure a transmit message object.
1. In the CAN IFn Command Mask (CANIFnCMASK) register:
Set the WRNRD bit to specify a write to the CANIFnCMASK register; specify whether to
transfer the IDMASK, DIR, and MXTD of the message object into the CAN IFn registers using
the MASK bit
Specify whether to transfer the ID, DIR, XTD, and MSGVAL of the message object into the
interface registers using the ARB bit
Specify whether to transfer the control bits into the interface registers using the CONTROL
bit
Specify whether to clear the INTPND bit in the CANIFnMCTL register using the CLRINTPND
bit
Specify whether to clear the NEWDAT bit in the CANNWDAn register using the NEWDAT bit
Specify which bits to transfer using the DATAA and DATAB bits
2. In the CANIFnMSK1 register, use the MSK[15:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[15:0] in this
register are used for bits [15:0] of the 29-bit message identifier and are not used for an 11-bit
identifier. A value of 0x00 enables all messages to pass through the acceptance filtering. Also
note that in order for these bits to be used for acceptance filtering, they must be enabled by
setting the UMASK bit in the CANIFnMCTL register.
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. For a 29-bit identifier, configure ID[15:0] in the CANIFnARB1 register for bits [15:0] of the
message identifier and ID[12:0] in the CANIFnARB2 register for bits [28:16] of the message
identifier. Set the XTD bit to indicate an extended identifier; set the DIR bit to indicate transmit;
and set the MSGVAL bit to indicate that the message object is valid.
5. For an 11-bit identifier, disregard the CANIFnARB1 register and configure ID[12:2] in the
CANIFnARB2 register for bits [10:0] of the message identifier. Clear the XTD bit to indicate a
standard identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to indicate that
the message object is valid.
6. In the CANIFnMCTL register:
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Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
Optionally set the TXIE bit to enable the INTPND bit to be set after a successful transmission
Optionally set the RMTEN bit to enable the TXRQST bit to be set on the reception of a matching
remote frame allowing automatic transmission
Set the EOB bit for a single message object
Configure the DLC[3:0] field to specify the size of the data frame. Take care during this
configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
7. Load the data to be transmitted into the CANIFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1,
CANIFnDB2) registers. Byte 0 of the CANdata frame is stored in DATA[7:0] in the CANIFnDA1
register.
8. Program the number of the message object to be transmitted in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register.
9. When everything is properly configured, set the TXRQST bit in the CANIFnMCTL register. Once
this bit is set, the message object is available to be transmitted, depending on priority and bus
availability. Note that setting the RMTEN bit in the CANIFnMCTL register can also start message
transmission if a matching remote frame has been received.
16.3.5 Updating a Transmit Message Object
The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface
Registers and neither the MSGVAL bit in the CANIFnARB2 register nor the TXRQST bits in the
CANIFnMCTL register have to be cleared before the update.
Even if only some of the data bytes are to be updated, all four bytes of the corresponding
CANIFnDAn/CANIFnDBn register have to be valid before the content of that register is transferred
to the message object. Either the CPU must write all four bytes into the CANIFnDAn/CANIFnDBn
register or the message object is transferred to the CANIFnDAn/CANIFnDBn register before the
CPU writes the new data bytes.
In order to only update the data in a message object, the WRNRD, DATAA and DATAB bits in the
CANIFnMSKn register are set, followed by writing the updated data into CANIFnDA1, CANIFnDA2,
CANIFnDB1, and CANIFnDB2 registers, and then the number of the message object is written to
the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. To begin transmission
of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register.
To prevent the clearing of the TXRQST bit in the CANIFnMCTL register at the end of a transmission
that may already be in progress while the data is updated, the NEWDAT and TXRQST bits have to be
set at the same time in the CANIFnMCTL register. When these bits are set at the same time, NEWDAT
is cleared as soon as the new transmission has started.
16.3.6 Accepting Received Message Objects
When the arbitration and control field (the ID and XTD bits in the CANIFnARB2 and the RMTEN and
DLC[3:0] bits of the CANIFnMCTL register) of an incoming message is completely shifted into
the CAN controller, the message handling capability of the controller starts scanning the message
RAM for a matching valid message object. To scan the message RAM for a matching message
object, the controller uses the acceptance filtering programmed through the mask bits in the
CANIFnMSKn register and enabled using the UMASK bit in the CANIFnMCTL register. Each valid
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message object, starting with object 1, is compared with the incoming message to locate a matching
message object in the message RAM. If a match occurs, the scanning is stopped and the message
handler proceeds depending on whether it is a data frame or remote frame that was received.
16.3.7 Receiving a Data Frame
The message handler stores the message from the CAN controller receive shift register into the
matching message object in the message RAM. The data bytes, all arbitration bits, and the DLC bits
are all stored into the corresponding message object. In this manner, the data bytes are connected
with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register
is set to indicate that new data has been received. The CPU should clear this bit when it reads the
message object to indicate to the controller that the message has been received, and the buffer is
free to receive more messages. If the CAN controller receives a message and the NEWDAT bit is
already set, the MSGLST bit in the CANIFnMCTL register is set to indicate that the previous data
was lost. If the system requires an interrupt on successful reception of a frame, the RXIE bit of the
CANIFnMCTL register should be set. In this case, the INTPND bit of the same register is set, causing
the CANINT register to point to the message object that just received a message. The TXRQST bit
of this message object should be cleared to prevent the transmission of a remote frame.
16.3.8 Receiving a Remote Frame
A remote frame contains no data, but instead specifies which object should be transmitted. When
a remote frame is received, three different configurations of the matching message object have to
be considered:
Table 16-2. Message Object Configurations
Description Configuration in CANIFnMCTL
At the reception of a matching remote frame, the TXRQST bit of this
message object is set. The rest of the message object remains
unchanged, and the controller automatically transfers the data in
the message object as soon as possible.
DIR = 1 (direction = transmit); programmed in the
CANIFnARB2 register
RMTEN = 1 (set the TXRQST bit of the
CANIFnMCTL register at reception of the frame
to enable transmission)
UMASK = 1 or 0
message object remains unchanged, and the remote frame is
ignored. This remote frame is disabled, the data is not transferred
and nothing indicates that the remote frame ever happened.
CANIFnARB2 register
RMTEN = 0 (do not change the TXRQST bit of the
CANIFnMCTL register at reception of the frame)
UMASK = 0 (ignore mask in the CANIFnMSKn
register)
message object is cleared. The arbitration and control field (ID +
XTD + RMTEN + DLC) fromthe shift register is stored into the message
object in the message RAM, and the NEWDAT bit of this message
object is set. The data field of the message object remains
unchanged; the remote frame is treated similar to a received data
frame. This mode is useful for a remote data request from another
CANdevice for which the TM4C123AH6PMcontroller does not have
readily available data. The software must fill the data and answer
the frame manually.
CANIFnARB2 register
RMTEN = 0 (do not change the TXRQST bit of the
CANIFnMCTL register at reception of the frame)
UMASK = 1 (use mask (MSK, MXTD, and MDIR in
the CANIFnMSKn register) for acceptance filtering)
April 10, 2013 994
16.3.9 Receive/Transmit Priority
The receive/transmit priority for the message objects is controlled by the message number. Message
object 1 has the highest priority, while message object 32 has the lowest priority. If more than one
transmission request is pending, the message objects are transmitted in order based on the message
object with the lowest message number. This prioritization is separate from that of the message
identifier which is enforced by the CAN bus. As a result, if message object 1 and message object
2 both have valid messages to be transmitted, message object 1 is always transmitted first regardless
of the message identifier in the message object itself.
16.3.10 Configuring a Receive Message Object
The following steps illustrate how to configure a receive message object.
1. Program the CAN IFn Command Mask (CANIFnCMASK) register as described in the
Configuring a Transmit Message Object on page 992 section, except that the WRNRD bit is set
to specify a write to the message RAM.
2. Program the CANIFnMSK1and CANIFnMSK2 registers as described in the Configuring a
Transmit Message Object on page 992 section to configure which bits are used for acceptance
filtering. Note that in order for these bits to be used for acceptance filtering, they must be enabled
by setting the UMASK bit in the CANIFnMCTL register.
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. Program the CANIFnARB1 and CANIFnARB2 registers as described in the Configuring a
Transmit Message Object on page 992 section to program XTD and ID bits for the message
identifier to be received; set the MSGVAL bit to indicate a valid message; and clear the DIR bit
to specify receive.
5. In the CANIFnMCTL register:
Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
Optionally set the RXIE bit to enable the INTPND bit to be set after a successful reception
Clear the RMTEN bit to leave the TXRQST bit unchanged
Set the EOB bit for a single message object
Configure the DLC[3:0] field to specify the size of the data frame
Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
6. Program the number of the message object to be received in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register. Reception of the message object begins as soon
as a matching frame is available on the CAN bus.
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When the message handler stores a data frame in the message object, it stores the received Data
Length Code and eight data bytes in the CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2
register. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. If the
Data Length Code is less than 8, the remaining bytes of the message object are overwritten by
unspecified values.
The CAN mask registers can be used to allow groups of data frames to be received by a message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by
a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register
should be set if only 29-bit extended identifiers are expected by this message object.
16.3.11 Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CANIFnCMSK register and then writes the number of
the message object to the CANIFnCRQ register. That combination transfers the whole received
message fromthe message RAMinto the Message Buffer registers (CANIFnMSKn, CANIFnARBn,
and CANIFnMCTL). Additionally, the NEWDAT and INTPND bits are cleared in the message RAM,
acknowledging that the message has been read and clearing the pending interrupt generated by
this message object.
If the message object uses masks for acceptance filtering, the CANIFnARBn registers show the
full, unmasked ID for the received message.
The NEWDAT bit in the CANIFnMCTL register shows whether a new message has been received
since the last time this message object was read. The MSGLST bit in the CANIFnMCTL register
shows whether more than one message has been received since the last time this message object
was read. MSGLST is not automatically cleared, and should be cleared by software after reading its
status.
Using a remote frame, the CPU may request new data from another CAN node on the CAN bus.
Setting the TXRQST bit of a receive object causes the transmission of a remote frame with the receive
object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be
transmitted, the TXRQST bit is automatically reset. This prevents the possible loss of data when the
other device on the CAN bus has already transmitted the data slightly earlier than expected.
16.3.11.1 Configuration of a FIFO Buffer
With the exception of the EOB bit in the CANIFnMCTL register, the configuration of receive message
objects belonging to a FIFO buffer is the same as the configuration of a single receive message
object (see Configuring a Receive Message Object on page 995). To concatenate two or more
message objects into a FIFO buffer, the identifiers and masks (if used) of these message objects
have to be programmed to matching values. Due to the implicit priority of the message objects, the
message object with the lowest message object number is the first message object in a FIFObuffer.
The EOB bit of all message objects of a FIFO buffer except the last one must be cleared. The EOB
bit of the last message object of a FIFO buffer is set, indicating it is the last entry in the buffer.
16.3.11.2 Reception of Messages with FIFO Buffers
Received messages with identifiers matching to a FIFO buffer are stored starting with the message
object with the lowest message number. When a message is stored into a message object of a
FIFO buffer, the NEWDAT of the CANIFnMCTL register bit of this message object is set. By setting
April 10, 2013 996
NEWDAT while EOB is clear, the message object is locked and cannot be written to by the message
handler until the CPU has cleared the NEWDAT bit. Messages are stored into a FIFO buffer until the
last message object of this FIFO buffer is reached. Until all of the preceding message objects have
been released by clearing the NEWDAT bit, all further messages for this FIFO buffer are written into
the last message object of the FIFO buffer and therefore overwrite previous messages.
16.3.11.3 Reading from a FIFO Buffer
When the CPU transfers the contents of a message object from a FIFO buffer by writing its number
to the CANIFnCRQregister, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should
be set such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the
read. The values of these bits in the CANIFnMCTL register always reflect the status of the message
object before the bits are cleared. To assure the correct function of a FIFO buffer, the CPU should
read out the message objects starting with the message object with the lowest message number.
When reading from the FIFO buffer, the user should be aware that a new received message is
placed in the message object with the lowest message number for which the NEWDAT bit of the
CANIFnMCTL register is clear. As a result, the order of the received messages in the FIFO is not
guaranteed. Figure 16-3 on page 998 shows how a set of message objects which are concatenated
to a FIFO Buffer can be handled by the CPU.
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Figure 16-3. Message Objects in a FIFO Buffer
START
No
Yes
Write MNUM to IFn Command Request
(Read Message to IFn Registers,
Reset NEWDAT = 0,
Reset INTPND = 0
MNUM = Interrupt Pointer
Read IFn Message Control
Read Data from IFn Data A,B
NEWDAT = 1
EOB = 1
Read Interrupt Pointer
Status Change
Interrupt Handling
END
Message Interrupt
Yes
MNUM = MNUM + 1
Case Interrupt Pointer else
0x0000 0x8000
No
16.3.12 Handling of Interrupts
If several interrupts are pending, the CANInterrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. The status interrupt has the highest
April 10, 2013 998
priority. Among the message interrupts, the message object's interrupt with the lowest message
number has the highest priority. A message interrupt is cleared by clearing the message object's
INTPND bit in the CANIFnMCTL register or by reading the CAN Status (CANSTS) register. The
status Interrupt is cleared by reading the CANSTS register.
The interrupt identifier INTID in the CANINT register indicates the cause of the interrupt. When no
interrupt is pending, the register reads as 0x0000. If the value of the INTID field is different from 0,
then an interrupt is pending. If the IE bit is set in the CANCTL register, the interrupt line to the
interrupt controller is active. The interrupt line remains active until the INTID field is 0, meaning
that all interrupt sources have been cleared (the cause of the interrupt is reset), or until IE is cleared,
which disables interrupts from the CAN controller.
The INTID field of the CANINT register points to the pending message interrupt with the highest
interrupt priority. The SIE bit in the CANCTL register controls whether a change of the RXOK, TXOK,
and LEC bits in the CANSTS register can cause an interrupt. The EIE bit in the CANCTLregister
controls whether a change of the BOFF and EWARN bits in the CANSTS register can cause an
interrupt. The IE bit in the CANCTL register controls whether any interrupt from the CAN controller
actually generates an interrupt to the interrupt controller. The CANINT register is updated even
when the IE bit in the CANCTL register is clear, but the interrupt is not indicated to the CPU.
A value of 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN
module has updated, but not necessarily changed, the CANSTS register, indicating that either an
error or status interrupt has been generated. A write access to the CANSTS register can clear the
RXOK, TXOK, and LEC bits in that same register; however, the only way to clear the source of a
status interrupt is to read the CANSTS register.
The source of an interrupt can be determined in two ways during interrupt handling. The first is to
read the INTID bit in the CANINT register to determine the highest priority interrupt that is pending,
and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see
all of the message objects that have pending interrupts.
An interrupt service routine reading the message that is the source of the interrupt may read the
message and clear the message object's INTPND bit at the same time by setting the CLRINTPND
bit in the CANIFnCMSK register. Once the INTPND bit has been cleared, the CANINT register
contains the message number for the next message object with a pending interrupt.
16.3.13 Test Mode
A Test Mode is provided which allows various diagnostics to be performed. Test Mode is entered
by setting the TEST bit in the CANCTL register. Once in Test Mode, the TX[1:0], LBACK, SILENT
and BASIC bits in the CAN Test (CANTST) register can be used to put the CAN controller into the
various diagnostic modes. The RX bit in the CANTST register allows monitoring of the CANnRX
signal. All CANTST register functions are disabled when the TEST bit is cleared.
16.3.13.1 Silent Mode
Silent Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission
of dominant bits (Acknowledge Bits, Error Frames). The CAN Controller is put in Silent Mode setting
the SILENT bit in the CANTST register. In Silent Mode, the CAN controller is able to receive valid
data frames and valid remote frames, but it sends only recessive bits on the CAN bus and cannot
start a transmission. If the CAN Controller is required to send a dominant bit (ACK bit, overload flag,
or active error flag), the bit is rerouted internally so that the CAN Controller monitors this dominant
bit, although the CAN bus remains in recessive state.
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16.3.13.2 Loopback Mode
Loopback mode is useful for self-test functions. In Loopback Mode, the CAN Controller internally
routes the CANnTX signal on to the CANnRX signal and treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into the message buffer. The
CAN Controller is put in Loopback Mode by setting the LBACK bit in the CANTST register. To be
independent fromexternal stimulation, the CAN Controller ignores acknowledge errors (a recessive
bit sampled in the acknowledge slot of a data/remote frame) in Loopback Mode. The actual value
of the CANnRX signal is disregarded by the CAN Controller. The transmitted messages can be
monitored on the CANnTX signal.
16.3.13.3 Loopback Combined with Silent Mode
Loopback Mode and Silent Mode can be combined to allow the CAN Controller to be tested without
affecting a running CAN system connected to the CANnTX and CANnRX signals. In this mode, the
CANnRX signal is disconnected from the CAN Controller and the CANnTX signal is held recessive.
This mode is enabled by setting both the LBACK and SILENT bits in the CANTST register.
16.3.13.4 Basic Mode
Basic Mode allows the CAN Controller to be operated without the Message RAM. In Basic Mode,
The CANIF1 registers are used as the transmit buffer. The transmission of the contents of the IF1
registers is requested by setting the BUSY bit of the CANIF1CRQ register. The CANIF1 registers
are locked while the BUSY bit is set. The BUSY bit indicates that a transmission is pending. As soon
the CAN bus is idle, the CANIF1 registers are loaded into the shift register of the CAN Controller
and transmission is started. When the transmission has completed, the BUSY bit is cleared and the
locked CANIF1 registers are released. A pending transmission can be aborted at any time by clearing
the BUSY bit in the CANIF1CRQ register while the CANIF1 registers are locked. If the CPU has
cleared the BUSY bit, a possible retransmission in case of lost arbitration or an error is disabled.
The CANIF2 Registers are used as a receive buffer. After the reception of a message, the contents
of the shift register are stored in the CANIF2 registers, without any acceptance filtering. Additionally,
the actual contents of the shift register can be monitored during the message transfer. Each time a
read message object is initiated by setting the BUSY bit of the CANIF2CRQ register, the contents
of the shift register are stored into the CANIF2 registers.
In Basic Mode, all message-object-related control and status bits and of the control bits of the
CANIFnCMSK registers are not evaluated. The message number of the CANIFnCRQ registers is
also not evaluated. In the CANIF2MCTL register, the NEWDAT and MSGLST bits retain their function,
the DLC[3:0] field shows the received DLC, the other control bits are cleared.
Basic Mode is enabled by setting the BASIC bit in the CANTST register.
16.3.13.5 Transmit Control
Software can directly override control of the CANnTX signal in four different ways.
CANnTX is controlled by the CAN Controller
The sample point is driven on the CANnTX signal to monitor the bit timing
CANnTX drives a low value
CANnTX drives a high value
April 10, 2013 1000
The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check
the physical layer of the CAN bus.
The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register.
The three test functions for the CANnTX signal interfere with all CAN protocol functions. TX[1:0]
must be cleared when CAN message transfer or Loopback Mode, Silent Mode, or Basic Mode are
selected.
16.3.14 Bit Timing Configuration Error Considerations
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly. In many cases, the CAN bit
synchronization amends a faulty configuration of the CAN bit timing to such a degree that only
occasionally an error frame is generated. In the case of arbitration, however, when two or more
CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the
transmitters to become error passive. The analysis of such sporadic errors requires a detailed
knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on
the CAN bus.
16.3.15 Bit Time and Bit Rate
The CANsystemsupports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member
of the CAN network has its own clock generator. The timing parameter of the bit time can be
configured individually for each CAN node, creating a common bit rate even though the CAN nodes'
oscillator periods may be different.
Because of small variations in frequency caused by changes in temperature or voltage and by
deteriorating components, these oscillators are not absolutely stable. As long as the variations
remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the
different bit rates by periodically resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure
16-4 on page 1002): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable
number of time quanta (see Table 16-3 on page 1002). The length of the time quantum(t
q
), which is
the basic time unit of the bit time, is defined by the CAN controller's input clock (fsys) and the Baud
Rate Prescaler (BRP):
t
q
= BRP / fsys
The fsys input clock is the system clock frequency as configured by the RCC or RCC2 registers
(see page 239 or page 246).
The Synchronization Segment Sync is that part of the bit time where edges of the CAN bus level
are expected to occur; the distance between an edge that occurs outside of Sync and the Sync is
called the phase error of that edge.
The Propagation Time Segment Prop is intended to compensate for the physical delay times within
the CAN network.
The Phase Buffer Segments Phase1 and Phase2 surround the Sample Point.
The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the
Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase
errors.
A given bit rate may be met by different bit-time configurations, but for the proper function of the
CAN network, the physical delay times and the oscillator's tolerance range have to be considered.
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Figure 16-4. CAN Bit Time
Sync Prop Phase2
Sample
Point
1 Time
Quantum
( t q )
q
Nominal CAN Bit Time
a. TSEG1 = Prop + Phase1
b. TSEG2 = Phase2
c. Phase1 = Phase2 or Phase1 + 1 = Phase2
TSEG1
a
TSEG2
b
Phase1
c
Table 16-3. CAN Protocol Ranges
a
Remark Range Parameter
Defines the length of the time quantum t
q
. The CANBRPE register can
be used to extend the range to 1024.
[1 .. 64] BRP
Fixed length, synchronization of bus input to system clock 1 t
q
Sync
Compensates for the physical delay times [1 .. 8] t
q
Prop
May be lengthened temporarily by synchronization [1 .. 8] t
q
Phase1
May be shortened temporarily by synchronization [1 .. 8] t
q
Phase2
May not be longer than either Phase Buffer Segment [1 .. 4] t
q
SJW
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. In the
CANBIT register, the four components TSEG2, TSEG1, SJW, and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1..n],
values in the range of [0..n-1] are programmed. That way, for example, SJW (functional range of
[1..4]) is represented by only two bits in the SJW bit field. Table 16-4 shows the relationship between
the CANBIT register values and the parameters.
Table 16-4. CANBIT Register Values
Setting CANBIT Register Field
Phase2 - 1 TSEG2
Prop + Phase1 - 1 TSEG1
SJW - 1 SJW
BRP BRP
Therefore, the length of the bit time is (programmed values):
[TSEG1 + TSEG2 + 3] t
q
or (functional values):
[Sync + Prop + Phase1 + Phase2] t
q
The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud
rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time
April 10, 2013 1002
unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the sample point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
The CAN controller translates messages to and from frames. In addition, the controller generates
and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks
the CRC code, performs the error management, and decides which type of synchronization is to be
used. The bit value is received or transmitted at the sample point. The information processing time
(IPT) is the time after the sample point needed to calculate the next bit to be transmitted on the CAN
bus. The IPT includes any of the following: retrieving the next data bit, handling a CRCbit, determining
if bit stuffing is required, generating an error flag or simply going idle.
The IPT is application-specific but may not be longer than 2 t
q
; the CAN's IPT is 0 t
q
. Its length is
the lower limit of the programmed length of Phase2. In case of synchronization, Phase2 may be
shortened to a value less than IPT, which does not affect bus timing.
16.3.16 Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the required bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is Prop. Its length depends on the delay times measured
in the system. A maximum bus length as well as a maximum node delay has to be defined for
expandable CAN bus systems. The resulting time for Prop is converted into time quanta (rounded
up to the nearest integer multiple of t
q
).
Sync is 1 t
q
long (fixed), which leaves (bit time - Prop - 1) t
q
for the two Phase Buffer Segments. If
the number of remaining t
q
is even, the Phase Buffer Segments have the same length, that is,
Phase2 = Phase1, else Phase2 = Phase1 + 1.
The minimum nominal length of Phase2 has to be regarded as well. Phase2 may not be shorter
than the CAN controller's Information Processing Time, which is, depending on the actual
implementation, in the range of [0..2] t
q
.
The length of the synchronization jump width is set to the least of 4, Phase1 or Phase2.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formula
given below:
( ) ( ) fnom df fosc fnom df + 1 1
( )
( ) 2 _ 13 2
mi n 2 _ , 1 _
Seg Phase tbit
seg Phase seg Phase
df

fnom df df = 2 max
where:
df = Maximum tolerance of oscillator frequency
fosc = Actual oscillator frequency
fnom = Nominal oscillator frequency
Maximum frequency tolerance must take into account the following formulas:
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( )
( ) 2 _ 13 2
mi n 2 _ , 1 _
Seg Phase tbit
seg Phase seg Phase
df

fnom df df = 2 max
( )
( ) 2 _ 13 2
mi n 2 _ , 1 _
Seg Phase tbit
seg Phase seg Phase
df

fnom df df = 2 max
where:
Phase1 and Phase2 are from Table 16-3 on page 1002
tbit = Bit Time
dfmax = Maximum difference between two oscillators
If more than one configuration is possible, that configuration allowing the highest oscillator tolerance
range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol-compliant configuration of the
CAN bit timing.
16.3.16.1 Example for Bit Timing at High Baud Rate
In this example, the frequency of CAN clock is 25 MHz, and the bit rate is 1 Mbps.
bit time = 1 s = n * t
q
= 5 * t
q
t
q
= 200 ns
t
q
= (Baud rate Prescaler)/CAN Clock
Baud rate Prescaler = t
q
* CAN Clock
Baud rate Prescaler = 200E-9 * 25E6 = 5
tSync = 1 * t
q
= 200 ns \\fixed at 1 time quanta
delay of bus driver 50 ns
delay of receiver circuit 30 ns
delay of bus line (40m) 220 ns
tProp 400 ns = 2 * t
q
\\400 is next integer multiple of t
q
bit time = tSync + tTSeg1 + tTSeg2 = 5 * t
q
bit time = tSync + tProp + tPhase 1 + tPhase2
tPhase 1 + tPhase2 = bit time - tSync - tProp
tPhase 1 + tPhase2 = (5 * t
q
) - (1 * t
q
) - (2 * t
q
)
tPhase 1 + tPhase2 = 2 * t
q
tPhase1 = 1 * t
q
tPhase2 = 1 * t
q
\\tPhase2 = tPhase1
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tTSeg1 = tProp + tPhase1
tTSeg1 = (2 * t
q
) + (1 * t
q
)
tTSeg1 = 3 * t
q
tTSeg2 = tPhase2
tTSeg2 = (Information Processing Time + 1) * t
q
tTSeg2 = 1 * t
q
\\Assumes IPT=0
tSJW = 1 * t
q
\\Least of 4, Phase1 and Phase2
In the above example, the bit field values for the CANBIT register are:
= TSeg2 -1
= 1-1
= 0
TSEG2
= TSeg1 -1
= 3-1
= 2
TSEG1
= SJW -1
= 1-1
= 0
SJW
= Baud rate prescaler - 1
= 5-1
=4
BRP
The final value programmed into the CANBIT register = 0x0204.
16.3.16.2 Example for Bit Timing at Low Baud Rate
In this example, the frequency of the CAN clock is 50 MHz, and the bit rate is 100 Kbps.
bit time = 10 s = n * t
q
= 10 * t
q
t
q
= 1 s
t
q
= (Baud rate Prescaler)/CAN Clock
Baud rate Prescaler = t
q
* CAN Clock
Baud rate Prescaler = 1E-6 * 50E6 = 50
tSync = 1 * t
q
= 1 s \\fixed at 1 time quanta
delay of bus driver 200 ns
delay of receiver circuit 80 ns
delay of bus line (40m) 220 ns
tProp 1 s = 1 * t
q
\\1 s is next integer multiple of t
q
bit time = tSync + tTSeg1 + tTSeg2 = 10 * t
q
bit time = tSync + tProp + tPhase 1 + tPhase2
tPhase 1 + tPhase2 = bit time - tSync - tProp
tPhase 1 + tPhase2 = (10 * t
q
) - (1 * t
q
) - (1 * t
q
)
tPhase 1 + tPhase2 = 8 * t
q
tPhase1 = 4 * t
q
tPhase2 = 4 * t
q
\\tPhase1 = tPhase2
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tTSeg1 = tProp + tPhase1
tTSeg1 = (1 * t
q
) + (4 * t
q
)
tTSeg1 = 5 * t
q
tTSeg2 = tPhase2
tTSeg2 = (Information Processing Time + 4) t
q
tTSeg2 = 4 * t
q
\\Assumes IPT=0
tSJW = 4 * t
q
\\Least of 4, Phase1, and Phase2
= TSeg2 -1
= 4-1
= 3
TSEG2
= TSeg1 -1
= 5-1
= 4
TSEG1
= SJW -1
= 4-1
= 3
SJW
= Baud rate prescaler - 1
= 50-1
=49
BRP
The final value programmed into the CANBIT register = 0x34F1.
16.4 Register Map
Table 16-5 on page 1006 lists the registers. All addresses given are relative to the CANbase address
of:
CAN0: 0x4004.0000
CAN1: 0x4004.1000
Note that the CAN controller clock must be enabled before the registers can be programmed (see
page 331). There must be a delay of 3 system clocks after the CAN module clock is enabled before
any CAN module registers are accessed.
Table 16-5. CAN Register Map
See
page
1009 CAN Control 0x0000.0001 R/W CANCTL 0x000
1011 CAN Status 0x0000.0000 R/W CANSTS 0x004
1014 CAN Error Counter 0x0000.0000 RO CANERR 0x008
1015 CAN Bit Timing 0x0000.2301 R/W CANBIT 0x00C
1016 CAN Interrupt 0x0000.0000 RO CANINT 0x010
1017 CAN Test 0x0000.0000 R/W CANTST 0x014
1019 CAN Baud Rate Prescaler Extension 0x0000.0000 R/W CANBRPE 0x018
1020 CAN IF1 Command Request 0x0000.0001 R/W CANIF1CRQ 0x020
April 10, 2013 1006
Table 16-5. CAN Register Map (continued)
See
page
1021 CAN IF1 Command Mask 0x0000.0000 R/W CANIF1CMSK 0x024
1024 CAN IF1 Mask 1 0x0000.FFFF R/W CANIF1MSK1 0x028
1025 CAN IF1 Mask 2 0x0000.FFFF R/W CANIF1MSK2 0x02C
1027 CAN IF1 Arbitration 1 0x0000.0000 R/W CANIF1ARB1 0x030
1030 CAN IF1 Message Control 0x0000.0000 R/W CANIF1MCTL 0x038
1033 CAN IF1 Data A1 0x0000.0000 R/W CANIF1DA1 0x03C
1033 CAN IF1 Data A2 0x0000.0000 R/W CANIF1DA2 0x040
1033 CAN IF1 Data B1 0x0000.0000 R/W CANIF1DB1 0x044
1033 CAN IF1 Data B2 0x0000.0000 R/W CANIF1DB2 0x048
1020 CAN IF2 Command Request 0x0000.0001 R/W CANIF2CRQ 0x080
1021 CAN IF2 Command Mask 0x0000.0000 R/W CANIF2CMSK 0x084
1024 CAN IF2 Mask 1 0x0000.FFFF R/W CANIF2MSK1 0x088
1025 CAN IF2 Mask 2 0x0000.FFFF R/W CANIF2MSK2 0x08C
1030 CAN IF2 Message Control 0x0000.0000 R/W CANIF2MCTL 0x098
1033 CAN IF2 Data A1 0x0000.0000 R/W CANIF2DA1 0x09C
1033 CAN IF2 Data A2 0x0000.0000 R/W CANIF2DA2 0x0A0
1033 CAN IF2 Data B1 0x0000.0000 R/W CANIF2DB1 0x0A4
1033 CAN IF2 Data B2 0x0000.0000 R/W CANIF2DB2 0x0A8
1034 CAN Transmission Request 1 0x0000.0000 RO CANTXRQ1 0x100
1034 CAN Transmission Request 2 0x0000.0000 RO CANTXRQ2 0x104
1035 CAN New Data 1 0x0000.0000 RO CANNWDA1 0x120
1035 CAN New Data 2 0x0000.0000 RO CANNWDA2 0x124
1036 CAN Message 1 Interrupt Pending 0x0000.0000 RO CANMSG1INT 0x140
1036 CAN Message 2 Interrupt Pending 0x0000.0000 RO CANMSG2INT 0x144
1037 CAN Message 1 Valid 0x0000.0000 RO CANMSG1VAL 0x160
1037 CAN Message 2 Valid 0x0000.0000 RO CANMSG2VAL 0x164
16.5 CAN Register Descriptions
The remainder of this section lists and describes the CAN registers, in numerical order by address
offset. There are two sets of Interface Registers that are used to access the Message Objects in
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the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used
to queue transactions.
April 10, 2013 1008
Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is cleared, each time a sequence of 11 High bits has been
monitored, a BITERROR0 code is written to the CANSTS register (the LEC field = 0x5), enabling
the CPUto readily check whether the CANbus is stuck Lowor continuously disturbed, and to monitor
the proceeding of the bus-off recovery sequence.
CAN Control (CANCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INIT IE SIE EIE reserved DAR CCE TEST reserved
R/W R/W R/W R/W RO R/W R/W R/W RO RO RO RO RO RO RO RO Type
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Test Mode Enable
Description Value
The CAN controller is operating normally. 0
The CAN controller is in test mode. 1
0 R/W TEST 7
Configuration Change Enable
Description Value
Write accesses to the CANBIT register are not allowed. 0
Write accesses to the CANBIT register are allowed if the
INIT bit is 1.
1
0 R/W CCE 6
Disable Automatic-Retransmission
Description Value
Auto-retransmission of disturbed messages is enabled. 0
Auto-retransmission is disabled. 1
0 R/W DAR 5
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0 RO reserved 4
Error Interrupt Enable
Description Value
No error status interrupt is generated. 0
A change in the BOFF or EWARN bits in the CANSTS
register generates an interrupt.
1
0 R/W EIE 3
Status Interrupt Enable
Description Value
No status interrupt is generated. 0
An interrupt is generated when a message has successfully
been transmitted or received, or a CAN bus error has been
detected. A change in the TXOK, RXOK or LEC bits in the
CANSTS register generates an interrupt.
1
0 R/W SIE 2
CAN Interrupt Enable
Description Value
Interrupts disabled. 0
Interrupts enabled. 1
0 R/W IE 1
Initialization
Description Value
Normal operation. 0
Initialization started. 1
1 R/W INIT 0
April 10, 2013 1010
Register 2: CAN Status (CANSTS), offset 0x004
The status register contains information for interrupt servicing such as Bus-Off, error count threshold,
and error types.
The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This
field is cleared when a message has been transferred (reception or transmission) without error. The
unused error code 0x7 may be written by the CPU to manually set this field to an invalid error so
that it can be checked for a change later.
An error interrupt is generated by the BOFF and EWARN bits, and a status interrupt is generated by
the RXOK, TXOK, and LEC bits, if the corresponding enable bits in the CAN Control (CANCTL)
register are set. A change of the EPASS bit or a write to the RXOK, TXOK, or LEC bits does not
generate an interrupt.
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is
pending.
CAN Status (CANSTS)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LEC TXOK RXOK EPASS EWARN BOFF reserved
R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Bus-Off Status
Description Value
The CAN controller is not in bus-off state. 0
The CAN controller is in bus-off state. 1
0 RO BOFF 7
Warning Status
Description Value
Both error counters are below the error warning limit of
96.
0
At least one of the error counters has reached the error
warning limit of 96.
1
0 RO EWARN 6
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Error Passive
Description Value
The CAN module is in the Error Active state, that is, the
receive or transmit error count is less than or equal to 127.
0
The CAN module is in the Error Passive state, that is, the
receive or transmit error count is greater than 127.
1
0 RO EPASS 5
Received a Message Successfully
Description Value
Since this bit was last cleared, no message has been
successfully received.
0
Since this bit was last cleared, a message has been
successfully received, independent of the result of the
acceptance filtering.
1
This bit must be cleared by writing a 0 to it.
0 R/W RXOK 4
Transmitted a Message Successfully
Description Value
Since this bit was last cleared, no message has been
successfully transmitted.
0
Since this bit was last cleared, a message has been
successfully transmitted error-free and acknowledged by
at least one other node.
1
This bit must be cleared by writing a 0 to it.
0 R/W TXOK 3
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Last Error Code
This is the type of the last error to occur on the CAN bus.
Description Value
No Error 0x0
Stuff Error
More than 5 equal bits in a sequence have occurred in a part
of a received message where this is not allowed.
0x1
Format Error
A fixed format part of the received frame has the wrong
format.
0x2
ACK Error
The message transmitted was not acknowledged by another
node.
0x3
Bit 1 Error
When a message is transmitted, the CANcontroller monitors
the data lines to detect any conflicts. When the arbitration
field is transmitted, data conflicts are a part of the arbitration
protocol. When other frame fields are transmitted, data
conflicts are considered errors.
A Bit 1 Error indicates that the device wanted to send a High
level (logical 1) but the monitored bus value was Low(logical
0).
0x4
Bit 0 Error
A Bit 0 Error indicates that the device wanted to send a Low
level (logical 0), but the monitored bus value was High (logical
1).
During bus-off recovery, this status is set each time a
sequence of 11 High bits has been monitored. By checking
for this status, software can monitor the proceeding of the
bus-off recovery sequence without any disturbances to the
bus.
0x5
CRC Error
The CRC checksum was incorrect in the received message,
indicating that the calculated value received did not match
the calculated CRC of the data.
0x6
No Event
When the LEC bit shows this value, no CAN bus event was
detected since this value was written to the LEC field.
0x7
0x0 R/W LEC 2:0
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Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TEC REC RP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Received Error Passive
Description Value
The Receive Error counter is below the Error Passive
level (127 or less).
0
The Receive Error counter has reached the Error Passive
level (128 or greater).
1
0 RO RP 15
Receive Error Counter
This field contains the state of the receiver error counter (0 to 127).
0x00 RO REC 14:8
Transmit Error Counter
This field contains the state of the transmit error counter (0 to 255).
0x00 RO TEC 7:0
April 10, 2013 1014
Register 4: CAN Bit Timing (CANBIT), offset 0x00C
This register is used to programthe bit width and bit quantum. Values are programmed to the system
clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL
register. See Bit Time and Bit Rate on page 1001 for more information.
CAN Bit Timing (CANBIT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x00C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BRP SJW TSEG1 TSEG2 reserved
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO Type
1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 Reset
Time Segment after Sample Point
0x00-0x07: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x2 means that 3 (2+1) bit time
quanta are defined for Phase2 (see Figure 16-4 on page 1002). The bit
time quanta is defined by the BRP field.
0x2 R/W TSEG2 14:12
Time Segment Before Sample Point
0x00-0x0F: The actual interpretation by the hardware of this value is
So, for example, the reset value of 0x3 means that 4 (3+1) bit time
quanta are defined for Phase1 (see Figure 16-4 on page 1002). The bit
time quanta is defined by the BRP field.
0x3 R/W TSEG1 11:8
(Re)Synchronization Jump Width
0x00-0x03: The actual interpretation by the hardware of this value is
During the start of frame (SOF), if the CAN controller detects a phase
error (misalignment), it can adjust the length of TSEG2 or TSEG1 by the
value in SJW. So the reset value of 0 adjusts the length by 1 bit time
quanta.
0x0 R/W SJW 7:6
Baud Rate Prescaler
The value by which the oscillator frequency is divided for generating the
bit time quanta. The bit time is built up from a multiple of this quantum.
0x00-0x03F: The actual interpretation by the hardware of this value is
BRP defines the number of CAN clock periods that make up 1 bit time
quanta, so the reset value is 2 bit time quanta (1+1).
The CANBRPE register can be used to further divide the bit time.
0x1 R/W BRP 5:0
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Register 5: CAN Interrupt (CANINT), offset 0x010
This register indicates the source of the interrupt.
If several interrupts are pending, the CANInterrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains
pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in
the CANCTL register is set, the interrupt is active. The interrupt line remains active until the INTID
field is cleared by reading the CANSTS register, or until the IE bit in the CANCTL register is cleared.
Note: Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register,
if it is pending.
CAN Interrupt (CANINT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTID
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Identifier
The number in this field indicates the source of the interrupt.
Description Value
No interrupt pending 0x0000
Number of the message object that
caused the interrupt
0x0001-0x0020
Reserved 0x0021-0x7FFF
Status Interrupt 0x8000
Reserved 0x8001-0xFFFF
0x0000 RO INTID 15:0
April 10, 2013 1016
Register 6: CAN Test (CANTST), offset 0x014
This register is used for self-test and external pin access. It is write-enabled by setting the TEST bit
in the CANCTL register. Different test functions may be combined, however, CAN transfers are
affected if the TX bits in this register are not zero.
CAN Test (CANTST)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x014
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved BASIC SILENT LBACK TX RX reserved
RO RO R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Receive Observation
Description Value
The CANnRx pin is low. 0
The CANnRx pin is high. 1
0 RO RX 7
Transmit Control
Overrides control of the CANnTx pin.
Description Value
CAN Module Control
CANnTx is controlled by the CAN module; default
operation
0x0
Sample Point
The sample point is driven on the CANnTx signal. This
mode is useful to monitor bit timing.
0x1
Driven Low
CANnTx drives a low value. This mode is useful for
checking the physical layer of the CAN bus.
0x2
Driven High
CANnTx drives a high value. This mode is useful for
checking the physical layer of the CAN bus.
0x3
0x0 R/W TX 6:5
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Loopback Mode
Description Value
Loopback mode is disabled. 0
Loopback mode is enabled. In loopback mode, the data
from the transmitter is routed into the receiver. Any data
on the receive input is ignored.
1
0 R/W LBACK 4
Silent Mode
Description Value
Silent mode is disabled. 0
Silent mode is enabled. In silent mode, the CAN controller
does not transmit data but instead monitors the bus. This
mode is also known as Bus Monitor mode.
1
0 R/W SILENT 3
Basic Mode
Description Value
Basic mode is disabled. 0
Basic mode is enabled. In basic mode, software should
use the CANIF1 registers as the transmit buffer and use
the CANIF2 registers as the receive buffer.
1
0 R/W BASIC 2
0x0 RO reserved 1:0
April 10, 2013 1018
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018
This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is
write-enabled by setting the CCE bit in the CANCTL register.
CAN Baud Rate Prescaler Extension (CANBRPE)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BRPE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Baud Rate Prescaler Extension
0x00-0x0F: Extend the BRP bit in the CANBIT register to values up to
1023. The actual interpretation by the hardware is one more than the
value programmed by BRPE (MSBs) and BRP (LSBs).
0x0 R/W BRPE 3:0
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Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080
A message transfer is started as soon as there is a write of the message object number to the MNUM
field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY
bit is automatically set to indicate that a transfer between the CAN Interface Registers and the
internal message RAM is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer
between the interface register and the message RAM completes, which then clears the BUSY bit.
CAN IFn Command Request (CANIFnCRQ)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MNUM reserved BUSY
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Busy Flag
Description Value
This bit is cleared when read/write action has finished. 0
This bit is set when a write occurs to the message
number in this register.
1
0 RO BUSY 15
Message Number
Selects one of the 32 message objects in the message RAM for data
transfer. The message objects are numbered from 1 to 32.
Description Value
Reserved
0 is not a valid message number; it is interpreted
as 0x20, or object 32.
0x00
Message Number
Indicates specified message object 1 to 32.
0x01-0x20
Reserved
Not a valid message number; values are shifted and
it is interpreted as 0x01-0x1F.
0x21-0x3F
0x01 R/W MNUM 5:0
April 10, 2013 1020
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
Reading the Command Mask registers provides status for various functions. Writing to the Command
Mask registers specifies the transfer direction and selects which buffer registers are the source or
target of the data transfer.
Note that when a read from the message object buffer occurs when the WRNRD bit is clear and the
CLRINTPND and/or NEWDAT bits are set, the interrupt pending and/or newdata flags in the message
object buffer are cleared.
CAN IFn Command Mask (CANIFnCMSK)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATAB DATAA
N
E
W
D
A
T
/
T
X
R
Q
S
T
CLRINTPND CONTROL ARB MASK WRNRD reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Write, Not Read
Description Value
Transfer the data in the CAN message object specified by
the the MNUM field in the CANIFnCRQ register into the
CANIFn registers.
0
Transfer the data in the CANIFn registers to the CAN
message object specified by the MNUM field in the CAN
Command Request (CANIFnCRQ).
1
Note: Interrupt pending and new data conditions in the message
buffer can be cleared by reading from the buffer (WRNRD = 0)
when the CLRINTPND and/or NEWDAT bits are set.
0 R/W WRNRD 7
Access Mask Bits
Description Value
Mask bits unchanged. 0
Transfer IDMASK + DIR + MXTD of the message object
into the Interface registers.
1
0 R/W MASK 6
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Access Arbitration Bits
Description Value
Arbitration bits unchanged. 0
Transfer ID + DIR + XTD + MSGVAL of the message
object into the Interface registers.
1
0 R/W ARB 5
Access Control Bits
Description Value
Control bits unchanged. 0
Transfer control bits from the CANIFnMCTL register
into the Interface registers.
1
0 R/W CONTROL 4
Clear Interrupt Pending Bit
The function of this bit depends on the configuration of the WRNRD bit.
Description Value
If WRNRD is clear, the interrupt pending status is transferred
from the message buffer into the CANIFnMCTL register.
If WRNRD is set, the INTPND bit in the message object remains
unchanged.
0
If WRNRD is clear, the interrupt pending status is cleared in the
message buffer. Note the value of this bit that is transferred
to the CANIFnMCTL register always reflects the status of the
bits before clearing.
If WRNRD is set, the INTPND bit is cleared in the message
object.
1
0 R/W CLRINTPND 3
NEWDAT / TXRQST Bit
Description Value
If WRNRD is clear, the value of the newdata status is transferred
from the message buffer into the CANIFnMCTL register.
If WRNRD is set, a transmission is not requested.
0
If WRNRD is clear, the newdata status is cleared in the message
buffer. Note the value of this bit that is transferred to the
CANIFnMCTL register always reflects the status of the bits
before clearing.
If WRNRD is set, a transmission is requested. Note that when
this bit is set, the TXRQST bit in the CANIFnMCTL register is
ignored.
1
0 R/W NEWDAT / TXRQST 2
April 10, 2013 1022
Access Data Byte 0 to 3
Description Value
Data bytes 0-3 are unchanged. 0
If WRNRD is clear, transfer data bytes 0-3 in CANIFnDA1
and CANIFnDA2 to the message object.
If WRNRD is set, transfer data bytes 0-3 in message object
to CANIFnDA1 and CANIFnDA2.
1
0 R/W DATAA 1
Access Data Byte 4 to 7
The function of this bit depends on the configuration of the WRNRD bit
as follows:
Description Value
Data bytes 4-7 are unchanged. 0
If WRNRD is clear, transfer data bytes 4-7 in CANIFnDA1
and CANIFnDA2 to the message object.
If WRNRD is set, transfer data bytes 4-7 in message object
to CANIFnDA1 and CANIFnDA2.
1
0 R/W DATAB 0
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Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088
The mask information provided in this register accompanies the data (CANIFnDAn), arbitration
information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the
message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance
filtering. Additional mask information is contained in the CANIFnMSK2 register.
CAN IFn Mask 1 (CANIFnMSK1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x028
Type R/W, reset 0x0000.FFFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSK
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [15:0] of the
ID. The MSK field in the CANIFnMSK2 register are used for bits [28:16]
of the ID. When using an 11-bit identifier, these bits are ignored.
Description Value
The corresponding identifier field (ID) in the message
object cannot inhibit the match in acceptance filtering.
0
The corresponding identifier field (ID) is used for
1
0xFFFF R/W MSK 15:0
April 10, 2013 1024
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C
This register holds extended mask information that accompanies the CANIFnMSK1 register.
CAN IFn Mask 2 (CANIFnMSK2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSK reserved MDIR MXTD
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W Type
1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 Reset
Mask Extended Identifier
Description Value
The extended identifier bit (XTD in the CANIFnARB2
register) has no effect on the acceptance filtering.
0
The extended identifier bit XTD is used for acceptance
filtering.
1
1 R/W MXTD 15
Mask Message Direction
Description Value
The message direction bit (DIR in the CANIFnARB2
register) has no effect for acceptance filtering.
0
The message direction bit DIR is used for acceptance
filtering.
1
1 R/W MDIR 14
1 RO reserved 13
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Identifier Mask
When using a 29-bit identifier, these bits are used for bits [28:16] of the
ID. The MSK field in the CANIFnMSK1 register are used for bits [15:0]
of the ID. When using an 11-bit identifier, MSK[12:2] are used for bits
[10:0] of the ID.
Description Value
The corresponding identifier field (ID) in the message
object cannot inhibit the match in acceptance filtering.
0
The corresponding identifier field (ID) is used for
1
0xFF R/W MSK 12:0
April 10, 2013 1026
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030
These registers hold the identifiers for acceptance filtering.
CAN IFn Arbitration 1 (CANIFnARB1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x030
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ID
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, bits 15:0 of the CANIFnARB1 register
are [15:0] of the ID, while bits 12:0 of the CANIFnARB2 register are
[28:16] of the ID.
When using an 11-bit identifier, these bits are not used.
0x0000 R/W ID 15:0
1027 April 10, 2013
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These registers hold information for acceptance filtering.
CAN IFn Arbitration 2 (CANIFnARB2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x034
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ID DIR XTD MSGVAL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Message Valid
Description Value
The message object is ignored by the message handler. 0
The message object is configured and ready to be
considered by the message handler within the CAN
controller.
1
All unused message objects should have this bit cleared during
initialization and before clearing the INIT bit in the CANCTL register.
The MSGVAL bit must also be cleared before any of the following bits
are modified or if the message object is no longer required: the ID fields
in the CANIFnARBn registers, the XTD and DIR bits in the CANIFnARB2
register, or the DLC field in the CANIFnMCTL register.
0 R/W MSGVAL 15
Extended Identifier
Description Value
An 11-bit Standard Identifier is used for this message
object.
0
A 29-bit Extended Identifier is used for this message
object.
1
0 R/W XTD 14
April 10, 2013 1028
Message Direction
Description Value
Receive. When the TXRQST bit in the CANIFnMCTL register
is set, a remote frame with the identifier of this message object
is received. On reception of a data frame with matching
identifier, that message is stored in this message object.
0
Transmit. When the TXRQST bit in the CANIFnMCTL register
is set, the respective message object is transmitted as a data
frame. On reception of a remote frame with matching identifier,
the TXRQST bit of this message object is set (if RMTEN=1).
1
0 R/W DIR 13
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, ID[15:0] of the CANIFnARB1 register
are [15:0] of the ID, while these bits, ID[12:0], are [28:16] of the ID.
When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of
the ID. The ID field in the CANIFnARB1 register is ignored.
0x000 R/W ID 12:0
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Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098
This register holds the control information associated with the message object to be sent to the
Message RAM.
CAN IFn Message Control (CANIFnMCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x038
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DLC reserved EOB TXRQST RMTEN RXIE TXIE UMASK INTPND MSGLST NEWDAT
R/W R/W R/W R/W RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
New Data
Description Value
No new data has been written into the data portion of this
message object by the message handler since the last time
this flag was cleared by the CPU.
0
The message handler or the CPU has written new data into
the data portion of this message object.
1
0 R/W NEWDAT 15
Message Lost
Description Value
No message was lost since the last time this bit was
cleared by the CPU.
0
The message handler stored a new message into this
object when NEWDAT was set; the CPUhas lost a message.
1
This bit is only valid for message objects when the DIR bit in the
CANIFnARB2 register is clear (receive).
0 R/W MSGLST 14
Interrupt Pending
Description Value
This message object is not the source of an interrupt. 0
This message object is the source of an interrupt. The
interrupt identifier in the CANINT register points to this
message object if there is not another interrupt source with
a higher priority.
1
0 R/W INTPND 13
April 10, 2013 1030
Use Acceptance Mask
Description Value
Mask is ignored. 0
Use mask (MSK, MXTD, and MDIR bits in the
CANIFnMSKn registers) for acceptance filtering.
1
0 R/W UMASK 12
Transmit Interrupt Enable
Description Value
The INTPND bit in the CANIFnMCTL register is unchanged
after a successful transmission of a frame.
0
The INTPND bit in the CANIFnMCTL register is set after
a successful transmission of a frame.
1
0 R/W TXIE 11
Receive Interrupt Enable
Description Value
The INTPND bit in the CANIFnMCTL register is unchanged
after a successful reception of a frame.
0
The INTPND bit in the CANIFnMCTL register is set after
a successful reception of a frame.
1
0 R/W RXIE 10
Remote Enable
Description Value
At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is left unchanged.
0
At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is set.
1
0 R/W RMTEN 9
Transmit Request
Description Value
This message object is not waiting for transmission. 0
The transmission of this message object is requested
and is not yet done.
1
Note: If the WRNRD and TXRQST bits in the CANIFnCMSK register
are set, this bit is ignored.
0 R/W TXRQST 8
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End of Buffer
Description Value
Message object belongs to a FIFO Buffer and is not the
last message object of that FIFO Buffer.
0
Single message object or last message object of a FIFO
Buffer.
1
This bit is used to concatenate two or more message objects (up to 32)
to build a FIFO buffer. For a single message object (thus not belonging
to a FIFO buffer), this bit must be set.
0 R/W EOB 7
0x0 RO reserved 6:4
Data Length Code
Description Value
Specifies the number of bytes in the data frame. 0x0-0x8
Defaults to a data frame with 8 bytes. 0x9-0xF
The DLC field in the CANIFnMCTL register of a message object must
be defined the same as in all the corresponding objects with the same
identifier at other nodes. When the message handler stores a data frame,
it writes DLC to the value given by the received message.
0x0 R/W DLC 3:0
April 10, 2013 1032
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8
These registers contain the data to be sent or that has been received. In a CAN data frame, data
byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted
or received. In CAN's serial bit stream, the MSB of each byte is transmitted first.
CAN IFn Data nn (CANIFnDnn)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x03C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Data
The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2
data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2
data bytes 7 and 6.
0x0000 R/W DATA 15:0
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Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By
reading out these bits, the CPUcan check which message object has a transmission request pending.
The TXRQST bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a remote
frame, or (3) the message handler state machine after a successful transmission.
The CANTXRQ1 register contains the TXRQST bits of the first 16 message objects in the message
RAM; the CANTXRQ2 register contains the TXRQST bits of the second 16 message objects.
CAN Transmission Request n (CANTXRQn)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x100
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXRQST
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Transmission Request Bits
Description Value
The corresponding message object is not waiting for
transmission.
0
The transmission of the corresponding message object
is requested and is not yet done.
1
0x0000 RO TXRQST 15:0
April 10, 2013 1034
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124
The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By
reading these bits, the CPU can check which message object has its data portion updated. The
NEWDAT bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a data frame,
or (3) the message handler state machine after a successful transmission.
The CANNWDA1 register contains the NEWDAT bits of the first 16 message objects in the message
RAM; the CANNWDA2 register contains the NEWDAT bits of the second 16 message objects.
CAN New Data n (CANNWDAn)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x120
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NEWDAT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
New Data Bits
Description Value
No new data has been written into the data portion of the
corresponding message object by the message handler since
the last time this flag was cleared by the CPU.
0
The message handler or the CPU has written new data into
the data portion of the corresponding message object.
1
0x0000 RO NEWDAT 15:0
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Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144
The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects.
By reading these bits, the CPU can check which message object has an interrupt pending. The
INTPND bit of a specific message object can be changed through two sources: (1) the CPU via the
CANIFnMCTL register, or (2) the message handler state machine after the reception or transmission
of a frame.
This field is also encoded in the CANINT register.
The CANMSG1INT register contains the INTPND bits of the first 16 message objects in the message
RAM; the CANMSG2INT register contains the INTPND bits of the second 16 message objects.
CAN Message n Interrupt Pending (CANMSGnINT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x140
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTPND
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Pending Bits
Description Value
The corresponding message object is not the source of
an interrupt.
0
The corresponding message object is the source of an
interrupt.
1
0x0000 RO INTPND 15:0
April 10, 2013 1036
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164
The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects.
By reading these bits, the CPU can check which message object is valid. The message valid bit of
a specific message object can be changed with the CANIFnARB2 register.
The CANMSG1VAL register contains the MSGVAL bits of the first 16 message objects in the message
RAM; the CANMSG2VAL register contains the MSGVAL bits of the second 16 message objects in
the message RAM.
CAN Message n Valid (CANMSGnVAL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x160
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSGVAL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Message Valid Bits
Description Value
The corresponding message object is not configured and
is ignored by the message handler.
0
The corresponding message object is configured and
should be considered by the message handler.
1
0x0000 RO MSGVAL 15:0
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17 Analog Comparators
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result.
Note: Not all comparators have the option to drive an output pin. See Signal
Description on page 1039 for more information.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board. In addition, the comparator can signal the application via interrupts or
trigger the start of a sample sequence in the ADC. The interrupt generation and ADCtriggering logic
is separate and independent. This flexibility means, for example, that an interrupt can be generated
on a rising edge and the ADC triggered on a falling edge.
The TM4C123AH6PM microcontroller provides two independent integrated analog comparators
with the following functions:
Compare external pin input to external pin input or to internal programmable voltage reference
Compare a test voltage against any one of the following voltages:
An individual external reference voltage
A shared single external reference voltage
A shared internal reference voltage
April 10, 2013 1038
Analog Comparators
17.1 Block Diagram
Figure 17-1. Analog Comparator Module Block Diagram
C2+
C2-
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 2
ACSTAT2
ACCTL2
C1-
C1+
output
+ve input
interrupt
-ve input
reference input
Comparator 1
ACSTAT1
ACCTL1
Voltage
Ref
ACREFCTL
output
+ve input
interrupt
-ve input
reference input
Comparator 0
ACSTAT0
ACCTL0
C0+
Internal
Bus
C0-
C0o
trigger trigger
trigger trigger
trigger trigger
Interrupt Control
ACRIS
ACMIS
ACINTEN
Interrupt
Module
Status
ACMPPP
C1o
C2o
Note: This block diagram depicts the maximum number of analog comparators and comparator outputs
for the family of microcontrollers; the number for this specific device may vary. See page 1052 for
what is included on this device.
The following table lists the external signals of the Analog Comparators and describes the function
of each. The Analog Comparator output signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment"
lists the possible GPIO pin placements for the Analog Comparator signals. The AFSEL bit in the
GPIO Alternate Function Select (GPIOAFSEL) register (page 612) should be set to choose the
Analog Comparator function. The number in parentheses is the encoding that must be programmed
into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 629) to assign the Analog
Comparator signal to the specified GPIO port pin. The positive and negative input signals are
configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more
Table 17-1. Analog Comparators Signals (64LQFP)
a
Assignment
Pin Number Pin Name
Analog comparator 0 positive input. Analog I PC6 14 C0+
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Table 17-1. Analog Comparators Signals (64LQFP) (continued)
a
Assignment
Pin Number Pin Name
Analog comparator 0 negative input. Analog I PC7 13 C0-
Analog comparator 0 output. TTL O PF0 (9) 28 C0o
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 17-2 on page 1040, the input source for VIN- is an external input, Cn-, where n
is the analog comparator number. In addition to an external input, Cn+, input sources for VIN+ can
be the C0+ or an internal reference, V
IREF
.
Figure 17-2. Structure of Comparator Unit
ACCTL
CINV
TrigGen
output
ACSTAT
IntGen
1
0
2
reference input
+ve input
-ve input
i
n
t
e
r
n
a
l
b
u
s
i
n
t
e
r
r
u
p
t
t
r
i
g
g
e
r
A comparator is configured through two status/control registers, Analog Comparator Control
(ACCTL) and Analog Comparator Status (ACSTAT). The internal reference is configured through
one control register, Analog Comparator Reference Voltage Control (ACREFCTL). Interrupt
status and control are configured through three registers, Analog Comparator Masked Interrupt
Status (ACMIS), Analog Comparator Raw Interrupt Status (ACRIS), and Analog Comparator
Interrupt Enable (ACINTEN).
Typically, the comparator output is used internally to generate an interrupt as controlled by the ISEN
bit in the ACCTL register. The output may also be used to drive one of the external pins (Cno), or
generate an analog-to-digital converter (ADC) trigger.
Important: The ASRCP bits in the ACCTL register must be set before using the analog comparators.
April 10, 2013 1040
Analog Comparators
17.3.1 Internal Reference Programming
The structure of the internal reference is shown in Figure 17-3 on page 1041. The internal reference
is controlled by a single configuration register (ACREFCTL).
Figure 17-3. Comparator Internal Reference Structure
N*R
N*R
0x0 0x1 0xE 0xF
Decoder
internal
reference
V
IREF
Note: In the figure above, N*R represents a multiple of the R value that produces the results specified
The internal reference can be programmed in one of two modes (lowrange or high range) depending
on the RNG bit in the ACREFCTL register. When RNG is clear, the internal reference is in high-range
mode, and when RNG is set the internal reference is in low-range mode.
In each range, the internal reference, V
IREF
, has 16 pre-programmed thresholds or step values. The
threshold to be used to compare the external input voltage against is selected using the VREF field
in the ACREFCTL register.
In the high-range mode, the V
IREF
threshold voltages start at the ideal high-range starting voltage
of V
DDA
/4.2 and increase in ideal constant voltage steps of V
DDA
/29.4.
In the low-range mode, the V
IREF
threshold voltages start at 0 V and increase in ideal constant
voltage steps of V
DDA
/22.12. The ideal V
IREF
step voltages for each mode and their dependence
on the RNG and VREF fields are summarized in Table 17-2.
Table 17-2. Internal Reference Voltage and ACREFCTL Field Values
Output Reference Voltage Based on VREF Field Value
ACREFCTL Register
RNG Bit Value EN Bit Value
0 V (GND) for any value of VREF. It is recommended that RNG=1 and VREF=0 to
minimize noise on the reference ground.
RNG=X EN=0
V
IREF
High Range: 16 voltage threshold values indexed by VREF = 0x0 .. 0xF
Ideal starting voltage (VREF=0): V
DDA
/ 4.2
Ideal step size: V
DDA
/ 29.4
Ideal V
IREF
threshold values: V
IREF
(VREF) = V
DDA
/ 4.2 + VREF * (V
DDA
/ 29.4), for
VREF = 0x0 .. 0xF
For minimum and maximum V
IREF
threshold values, see Table 17-3 on page 1042.
RNG=0
EN=1
V
IREF
Low Range: 16 voltage threshold values indexed by VREF = 0x0 .. 0xF
Ideal starting voltage (VREF=0): 0 V
Ideal step size: V
DDA
/ 22.12
Ideal V
IREF
threshold values: V
IREF
(VREF) = VREF * (V
DDA
/ 22.12), for VREF = 0x0 ..
0xF
For minimum and maximum V
IREF
threshold values, see Table 17-4 on page 1042.
RNG=1
1041 April 10, 2013
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Note that the values shown in Table 17-2 are the ideal values of the V
IREF
thresholds. These values
actually vary between minimumand maximumvalues for each threshold step, depending on process
and temperature. The minimum and maximum values for each step are given by:
V
IREF
(VREF) [Min] = Ideal V
IREF
(VREF) (Ideal Step size 2 mV) / 2
V
IREF
(VREF) [Max] = Ideal V
IREF
(VREF) + (Ideal Step size 2 mV) / 2
Examples of minimum and maximum V
IREF
values for V
DDA
= 3.3V for high and low ranges, are
shown inTable 17-3 and Table 17-4. Note that these examples are only valid for V
DDA
= 3.3V; values
scale up and down with V
DDA
.
DDA
= 3.3V, EN= 1, and
RNG = 0
Unit V
IREF
Max Ideal V
IREF
V
IREF
Min VREF Value
V 0.841 0.786 0.731 0x0
V 0.953 0.898 0.843 0x1
V 1.065 1.010 0.955 0x2
V 1.178 1.122 1.067 0x3
V 1.290 1.235 1.180 0x4
V 1.402 1.347 1.292 0x5
V 1.514 1.459 1.404 0x6
V 1.627 1.571 1.516 0x7
V 1.739 1.684 1.629 0x8
V 1.851 1.796 1.741 0x9
V 1.963 1.908 1.853 0xA
V 2.076 2.020 1.965 0xB
V 2.188 2.133 2.078 0xC
V 2.300 2.245 2.190 0xD
V 2.412 2.357 2.302 0xE
V 2.525 2.469 2.414 0xF
DDA
= 3.3V, EN= 1, and
RNG = 1
Unit V
IREF
Max Ideal V
IREF
V
IREF
Min VREF Value
V 0.074 0.000 0.000 0x0
V 0.223 0.149 0.076 0x1
V 0.372 0.298 0.225 0x2
V 0.521 0.448 0.374 0x3
V 0.670 0.597 0.523 0x4
V 0.820 0.746 0.672 0x5
V 0.969 0.895 0.822 0x6
V 1.118 1.044 0.971 0x7
V 1.267 1.193 1.120 0x8
V 1.416 1.343 1.269 0x9
V 1.565 1.492 1.418 0xA
April 10, 2013 1042
Analog Comparators
DDA
= 3.3V, EN= 1, and
RNG = 1 (continued)
Unit V
IREF
Max Ideal V
IREF
V
IREF
Min VREF Value
V 1.715 1.641 1.567 0xB
V 1.864 1.790 1.717 0xC
V 2.013 1.939 1.866 0xD
V 2.162 2.089 2.015 0xE
V 2.311 2.238 2.164 0xF
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator clock by writing a value of 0x0000.0001 to the RCGCACMP
register in the System Control module (see page 333).
2. Enable the clock to the appropriate GPIO modules via the RCGCGPIOregister (see page 322).
To find out which GPIO ports to enable, refer to Table 21-5 on page 1176.
3. In the GPIOmodule, enable the GPIOport/pin associated with the input signals as GPIOinputs.
To determine which GPIO to configure, see Table 21-4 on page 1170.
4. Configure the PMCn fields in the GPIOPCTL register to assign the analog comparator output
signals to the appropriate pins (see page 629 and Table 21-5 on page 1176).
5. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
6. Configure the comparator to use the internal voltage reference and to not invert the output by
writing the ACCTLn register with the value of 0x0000.040C.
7. Delay for 10 s.
8. Read the comparator output value by reading the ACSTATn registers OVAL value.
Change the level of the comparator negative input signal C- to see the OVAL value change.
17.5 Register Map
Table 17-5 on page 1043 lists the comparator registers. The offset listed is a hexadecimal increment
to the registers address, relative to the Analog Comparator base address of 0x4003.C000. Note
that the analog comparator clock must be enabled before the registers can be programmed (see
page 333). There must be a delay of 3 system clocks after the analog comparator module clock is
enabled before any analog comparator module registers are accessed.
Table 17-5. Analog Comparators Register Map
See
page
1045 Analog Comparator Masked Interrupt Status 0x0000.0000 R/W1C ACMIS 0x000
1046 Analog Comparator Raw Interrupt Status 0x0000.0000 RO ACRIS 0x004
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Table 17-5. Analog Comparators Register Map (continued)
See
page
1047 Analog Comparator Interrupt Enable 0x0000.0000 R/W ACINTEN 0x008
1048 Analog Comparator Reference Voltage Control 0x0000.0000 R/W ACREFCTL 0x010
1049 Analog Comparator Status 0 0x0000.0000 RO ACSTAT0 0x020
1050 Analog Comparator Control 0 0x0000.0000 R/W ACCTL0 0x024
1049 Analog Comparator Status 1 0x0000.0000 RO ACSTAT1 0x040
1050 Analog Comparator Control 1 0x0000.0000 R/W ACCTL1 0x044
1052 Analog Comparator Peripheral Properties 0x0003.0003 RO ACMPPP 0xFC0
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
April 10, 2013 1044
Analog Comparators
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
This register provides a summary of the interrupt status (masked) of the comparators.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IN0 IN1 reserved
R/W1C R/W1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Comparator 1 Masked Interrupt Status
Description Value
The IN1 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the IN1 bit
in the ACRIS register.
0 R/W1C IN1 1
Comparator 0 Masked Interrupt Status
Description Value
The IN0 bits in the ACRIS register and the ACINTEN registers
1
This bit is cleared by writing a 1. Clearing this bit also clears the IN0 bit
in the ACRIS register.
0 R/W1C IN0 0
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Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
This register provides a summary of the interrupt status (raw) of the comparators. The bits in this
register must be enabled to generate interrupts using the ACINTEN register.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IN0 IN1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Comparator 1 Interrupt Status
Description Value
Comparator 1 has generated an interruptfor an event as
configured by the ISEN bit in the ACCTL1 register.
1
This bit is cleared by writing a 1 to the IN1 bit in the ACMIS register.
0 RO IN1 1
Comparator 0 Interrupt Status
Description Value
Comparator 0 has generated an interrupt for an event as
configured by the ISEN bit in the ACCTL0 register.
1
This bit is cleared by writing a 1 to the IN0 bit in the ACMIS register.
0 RO IN0 0
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Analog Comparators
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008
This register provides the interrupt enable for the comparators.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IN0 IN1 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Comparator 1 Interrupt Enable
Description Value
A comparator 1 interrupt does not affect the interrupt status. 0
The raw interrupt signal comparator 1 is sent to the interrupt
controller.
1
0 R/W IN1 1
Comparator 0 Interrupt Enable
Description Value
A comparator 0 interrupt does not affect the interrupt status. 0
The raw interrupt signal comparator 0 is sent to the interrupt
controller.
1
0 R/W IN0 0
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Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x010
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VREF reserved RNG EN reserved
R/W R/W R/W R/W RO RO RO RO R/W R/W RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Resistor Ladder Enable
Description Value
The resistor ladder is unpowered. 0
Powers on the resistor ladder. The resistor ladder is connected
to V
DDA
.
1
This bit is cleared at reset so that the internal reference consumes the
least amount of power if it is not used.
0 R/W EN 9
Resistor Ladder Range
Description Value
The ideal step size for the internal reference is VDDA / 29.4. 0
The ideal step size for the internal reference is VDDA / 22.12. 1
0 R/W RNG 8
0x0 RO reserved 7:4
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
17-2 on page 1041 for some output reference voltage examples.
0x0 R/W VREF 3:0
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Analog Comparators
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040
These registers specify the current output value of the comparator.
Analog Comparator Status n (ACSTATn)
Base 0x4003.C000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved OVAL reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Comparator Output Value
Description Value
VIN- > VIN+ 0
VIN- < VIN+ 1
VIN - is the voltage on the Cn- pin. VIN+ is the voltage on the Cn+ pin,
the C0+ pin, or the internal voltage reference (V
IREF
) as defined by the
ASRCP bit in the ACCTL register.
0 RO OVAL 1
0 RO reserved 0
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Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044
These registers configure the comparators input and output.
Analog Comparator Control n (ACCTLn)
Base 0x4003.C000
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved CINV ISEN ISLVAL TSEN TSLVAL reserved ASRCP TOEN reserved
RO R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Trigger Output Enable
Description Value
ADC events are suppressed and not sent to the ADC. 0
ADC events are sent to the ADC. 1
0 R/W TOEN 11
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Description Value
Pin value of Cn+ 0x0
Pin value of C0+ 0x1
Internal voltage reference (V
IREF
) 0x2
Reserved 0x3
0x0 R/W ASRCP 10:9
0 RO reserved 8
Trigger Sense Level Value
Description Value
An ADC event is generated if the comparator output is Low. 0
An ADC event is generated if the comparator output is High. 1
0 R/W TSLVAL 7
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Analog Comparators
Trigger Sense
The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:
Description Value
Level sense, see TSLVAL 0x0
Falling edge 0x1
Rising edge 0x2
Either edge 0x3
0x0 R/W TSEN 6:5
Interrupt Sense Level Value
Description Value
An interrupt is generated if the comparator output is Low. 0
An interrupt is generated if the comparator output is High. 1
0 R/W ISLVAL 4
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Description Value
Level sense, see ISLVAL 0x0
Falling edge 0x1
Rising edge 0x2
Either edge 0x3
0x0 R/W ISEN 3:2
Comparator Output Invert
Description Value
The output of the comparator is unchanged. 0
The output of the comparator is inverted prior to being processed
by hardware.
1
0 R/W CINV 1
0 RO reserved 0
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Register 9: Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0
The ACMPPP register provides information regarding the properties of the analog comparator
module.
Analog Comparator Peripheral Properties (ACMPPP)
Base 0x4003.C000
Offset 0xFC0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
C0O C1O reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMP0 CMP1 reserved
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Comparator Output 1 Present
Description Value
Comparator output 1 is not present. 0
Comparator output 1 is present. 1
0x1 RO C1O 17
Comparator Output 0 Present
Description Value
Comparator output 0 is not present. 0
Comparator output 0 is present. 1
0x1 RO C0O 16
Comparator 1 Present
Description Value
Comparator 1 is not present. 0
Comparator 1 is present. 1
0x1 RO CMP1 1
Comparator 0 Present
Description Value
Comparator 0 is not present. 0
Comparator 0 is present. 1
0x1 RO CMP0 0
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Analog Comparators
18 Pulse Width Modulator (PWM)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
The TM4C123AH6PM microcontroller contains two PWM modules, each with four PWM generator
blocks and a control block, for a total of 16 PWM outputs. The control block determines the polarity
of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that share the same timer and frequency
and can either be programmed with independent actions or as a single pair of complementary signals
with dead-band delays inserted. The output signals, pwmA' and pwmB', of the PWM generation
blocks are managed by the output control block before being passed to the device pins as MnPWM0
and MnPWM1 or MnPWM2 and MnPWM3, and so on.
Each TM4C123AH6PM PWM module provides a great deal of flexibility and can generate simple
PWM signals, such as those required by a simple charge pump as well as paired PWM signals with
dead-band delays, such as those required by a half-H bridge driver. Three generator blocks can
also generate the full six channels of gate controls required by a 3-phase inverter bridge.
Each PWM generator block has the following features:
Three fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage
to the motor being controlled, for a total of six inputs
One 16-bit counter
Runs in Down or Up/Down mode
Output frequency controlled by a 16-bit load value
Load value updates can be synchronized
Produces output signals at zero and load value
Two PWM comparators
Comparator value updates can be synchronized
Produces output signals on match
PWM signal generator
Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
Produces two independent PWM signals
Dead-band generator
Produces two PWMsignals with programmable dead-band delays suitable for driving a half-H
bridge
Can be bypassed, leaving input PWM signals unmodified
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Can initiate an ADC sample sequence
The control block determines the polarity of the PWM signals and which signals are passed through
to the pins. The output of the PWM generation blocks are managed by the output control block
before being passed to the device pins. The PWM control block has the following options:
PWM output enable of each PWM signal
Optional output inversion of each PWM signal (polarity control)
Optional fault handling for each PWM signal
Synchronization of timers in the PWM generator blocks
Synchronization of timer/comparator updates across the PWM generator blocks
Extended PWM synchronization of timer/comparator updates across the PWM generator blocks
Interrupt status summary of the PWM generator blocks
Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering
PWM generators can be operated independently or synchronized with other generators
18.1 Block Diagram
Figure 18-1 on page 1055 provides the TM4C123AH6PM PWM module diagram and Figure
18-2 on page 1055 provides a more detailed diagram of a TM4C123AH6PM PWM generator. The
TM4C123AH6PM controller contains two PWM modules, each with four generator blocks that
generate eight independent PWMsignals or four paired PWMsignals with dead-band delays inserted.
April 10, 2013 1054
Figure 18-1. PWM Module Diagram
PWM
Generator 0
PWM
Generator 1
PWM
Generator 2
PWM
Generator 3
PWM 0
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
PWM 6
PWM 7
PWM
Output
Control
Logic
PWM Clock
System Clock
Interrupts
Triggers
pwm0A
pwm0B
pwm1A
pwm1B
pwm2A
pwm2B
pwm3A
pwm3B
pwm0fault
pwm1fault
pwm2fault
pwm3fault
Triggers / Faults
PWMENABLE
Output
PWMINVERT
PWMFAULT
PWMFAULTVAL
PWMENUPD
PWMINTEN
Interrupt
PWMRIS
PWMISC
PWMCTL
Control and
Status
PWMSYNC
PWMSTATUS
PWMPP
PWMPC
Figure 18-2. PWM Generator Block Diagram
PWMnCMPA
Comparators
PWMnCMPB
PWMnLOAD
Timer
PWMnCOUNT
PWMnDBCTL
Dead-Band
Generator
PWMnDBRISE
PWMnDBFALL
PWMnCTL
Control
PWMnFLTSRC0
Fault
Condition
PWMnFLTSRC1
PWMnMINFLTPER
PWMnFLTSEN
PWMnFLTSTAT0
PWMnFLTSTAT1
PWM Clock
PWM Generator Block
Signal
Generator
PWMnGENA
PWMnGENB
PWMnINTEN
Interrupt and
Trigger
Generator
PWMnRIS
PWMnISC
Digital Trigger(s)
Fault(s)
pwmA
pwmB
Interrupts /
Triggers
pwmfault
cmpA
cmpB
zero
load
dir
pwmA
pwmB
The following table lists the external signals of the PWM modules and describes the function of
each. The PWM controller signals are alternate functions for some GPIO signals and default to be
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GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the
possible GPIOpin placements for these PWMsignals. The AFSEL bit in the GPIOAlternate Function
Select (GPIOAFSEL) register (page 612) should be set to choose the PWM function. The number
in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port
Control (GPIOPCTL) register (page 629) to assign the PWM signal to the specified GPIO port pin.
For more information on configuring GPIOs, see General-Purpose Input/Outputs
Table 18-1. PWM Signals (64LQFP)
a
Assignment
Pin Number Pin Name
Motion Control Module 0 PWM Fault 0. TTL I PF2 (4)
PD6 (4)
PD2 (4)
30
53
63
M0FAULT0
Motion Control Module 0 PWM Fault 1. TTL I PD7 (4)
PF3 (4)
PG2 (4)
10
31
35
M0FAULT1
PG3 (4)
5
34
M0FAULT2
Motion Control Module 0 PWM 0. This signal is
controlled by Module 0 PWM Generator 0.
TTL O PB6 (4) 1 M0PWM0
TTL O PG4 (4)
PE4 (4)
33
59
M0PWM4
TTL O PG5 (4)
PE5 (4)
32
60
M0PWM5
TTL O PC4 (4)
PD0 (4)
16
61
M0PWM6
TTL O PC5 (4)
PD1 (4)
15
62
M0PWM7
Motion Control Module 1 PWM Fault 0. TTL I PF4 (5) 5 M1FAULT0
Motion Control Module 1 PWM Fault 1. TTL I PG0 (5) 37 M1FAULT1
TTL O PG2 (5)
PD0 (5)
35
61
M1PWM0
TTL O PG3 (5)
PD1 (5)
34
62
M1PWM1
TTL O PA6 (5)
PG4 (5)
PE4 (5)
23
33
59
M1PWM2
TTL O PA7 (5)
PG5 (5)
PE5 (5)
24
32
60
M1PWM3
TTL O PF0 (5) 28 M1PWM4
April 10, 2013 1056
Table 18-1. PWM Signals (64LQFP) (continued)
a
Assignment
Pin Number Pin Name
18.3.1 PWM Timer
The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down
mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load
value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the
load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode
is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used
for generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse. In the figures in this chapter, these signals are
labelled "dir," "zero," and "load."
18.3.2 PWM Comparators
Each PWM generator has two comparators that monitor the value of the counter; when either
comparator matches the counter, they output a single-clock-cycle-width High pulse, labelled "cmpA"
and "cmpB" in the figures in this chapter. When in Count-Up/Down mode, these comparators match
both when counting up and when counting down, and thus are qualified by the counter direction
signal. These qualified pulses are used in the PWM generation process. If either comparator match
value is greater than the counter load value, then that comparator never outputs a High pulse.
Figure 18-3 on page 1058 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 18-4 on page 1058 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode. In these figures,
the following definitions apply:
LOAD is the value in the PWMnLOAD register
COMPA is the value in the PWMnCMPA register
COMPB is the value in the PWMnCMPB register
0 is the value zero
load is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to the load value
zero is the internal signal that has a single-clock-cycle-width High pulse when the counter is zero
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cmpA is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPA
cmpB is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPB
dir is the internal signal that indicates the count direction
Figure 18-3. PWM Count-Down Mode
LOAD
0
COMPB
COMPA
load
zero
cmpB
cmpA
dir
ADown
BDown
Figure 18-4. PWM Count-Up/Down Mode
LOAD
0
COMPA
load
zero
cmpB
cmpA
dir
BUp
AUp ADown
BDown
COMPB
18.3.3 PWM Signal Generator
Each PWM generator takes the load, zero, cmpA, and cmpB pulses (qualified by the dir signal) and
generates two internal PWMsignals, pwmA and pwmB. In Count-Down mode, there are four events
that can affect these signals: zero, load, match A down, and match B down. In Count-Up/Down
mode, there are six events that can affect these signals: zero, load, match A down, match A up,
match B down, and match B up. The match A or match B events are ignored when they coincide
with the zero or load events. If the match A and match B events coincide, the first signal, pwmA, is
April 10, 2013 1058
generated based only on the match A event, and the second signal, pwmB, is generated based only
on the match B event.
For each event, the effect on each output PWMsignal is programmable: it can be left alone (ignoring
the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be
used to generate a pair of PWM signals of various positions and duty cycles, which do or do not
overlap. Figure 18-5 on page 1059 shows the use of Count-Up/Down mode to generate a pair of
center-aligned, overlapped PWMsignals that have different duty cycles. This figure shows the pwmA
and pwmB signals before they have passed through the dead-band generator.
Figure 18-5. PWM Generation Example In Count-Up/Down Mode
LOAD
0
COMPB
COMPA
pwmB
pwmA
In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
changes the duty cycle of the pwmA signal, and changing the value of comparator B changes the
duty cycle of the pwmB signal.
18.3.4 Dead-Band Generator
The pwmA and pwmB signals produced by each PWM generator are passed to the dead-band
generator. If the dead-band generator is disabled, the PWM signals simply pass through to the
pwmA' and pwmB' signals unmodified. If the dead-band generator is enabled, the pwmB signal is
lost and two PWM signals are generated based on the pwmA signal. The first output PWM signal,
pwmA' is the pwmA signal with the rising edge delayed by a programmable amount. The second
output PWM signal, pwmB', is the inversion of the pwmA signal with a programmable delay added
between the falling edge of the pwmA signal and the rising edge of the pwmB' signal.
The resulting signals are a pair of active High signals where one is always High, except for a
programmable amount of time at transitions where both are Low. These signals are therefore suitable
for driving a half-Hbridge, with the dead-band delays preventing shoot-through current fromdamaging
the power electronics. Figure 18-6 on page 1059 shows the effect of the dead-band generator on the
pwmA signal and the resulting pwmA' and pwmB' signals that are transmitted to the output control
block.
Figure 18-6. PWM Dead-Band Generator
pwmA
pwmA
pwmB
Rising Edge
Delay
Falling Edge
Delay
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18.3.5 Interrupt/ADC-Trigger Selector
Each PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a
source for an interrupt; when any of the selected events occur, an interrupt is generated. Additionally,
the same event, a different event, the same set of events, or a different set of events can be selected
as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is
generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position
within the pwmA or pwmB signal. Note that interrupts and ADCtriggers are based on the rawevents;
delays in the PWM signal edges caused by the dead-band generator are not taken into account.
18.3.6 Synchronization Methods
Each PWM module provides four PWM generators, each providing two PWM outputs that may be
used in a wide variety of applications. Generally speaking, the PWMis used in one of two categories
of operation:
Unsynchronized. The PWM generator and its two output signals are used alone, independent
of other PWM generators.
Synchronized. The PWM generator and its two outputs signals are used in conjunction with
other PWM generators using a common, unified time base. If multiple PWM generators are
configured with the same counter load value, synchronization can be used to guarantee that
they also have the same count value (the PWM generators must be configured before they are
synchronized). With this feature, more than two MnPWMn signals can be produced with a known
relationship between the edges of those signals because the counters always have the same
values. Other states in the module provide mechanisms to maintain the common time base and
mutual synchronization.
The counter in a PWM generator can be reset to zero by writing the PWM Time Base Sync
(PWMSYNC) register and setting the SYNCn bit associated with the generator. Multiple PWM
generators can be synchronized together by setting all necessary SYNCn bits in one access. For
example, setting the SYNC0 and SYNC1 bits in the PWMSYNCregister causes the counters in PWM
generators 0 and 1 to reset together.
Additional synchronization can occur between multiple PWMgenerators by updating register contents
in one of the following three ways:
Immediately. The write value has immediate effect, and the hardware reacts immediately.
Locally Synchronized. The write value does not affect the logic until the counter reaches the
value zero at the end of the PWM cycle. In this case, the effect of the write is deferred, providing
a guaranteed defined behavior and preventing overly short or overly long output PWM pulses.
Globally Synchronized. The write value does not affect the logic until two sequential events
have occurred: (1) the Update mode for the generator function is programmed for global
synchronization in the PWMnCTL register, and (2) the counter reaches zero at the end of the
PWMcycle. In this case, the effect of the write is deferred until the end of the PWMcycle following
the end of all updates. This mode allows multiple items in multiple PWMgenerators to be updated
simultaneously without odd effects during the update; everything runs from the old values until
a point at which they all run from the new values. The Update mode of the load and comparator
match values can be individually configured in each PWM generator block. It typically makes
sense to use the synchronous update mechanismacross PWMgenerator blocks when the timers
in those blocks are synchronized, although this is not required in order for this mechanism to
function properly.
April 10, 2013 1060
The following registers provide either local or global synchronization based on the state of various
Update mode bits and fields in the PWMnCTL register (LOADUPD; CMPAUPD; CMPBUPD):
Generator Registers: PWMnLOAD, PWMnCMPA, and PWMnCMPB
The following registers default to immediate update, but are provided with the optional functionality
of synchronously updating rather than having all updates take immediate effect:
Module-Level Register: PWMENABLE(based on the state of the ENUPDn bits in the PWMENUPD
register).
Generator Register: PWMnGENA, PWMnGENB, PWMnDBCTL, PWMnDBRISE, and
PWMnDBFALL (based on the state of various Update mode bits and fields in the PWMnCTL
register (GENAUPD; GENBUPD; DBCTLUPD; DBRISEUPD; DBFALLUPD)).
All other registers are considered statically provisioned for the execution of an application or are
used dynamically for purposes unrelated to maintaining synchronization and therefore do not need
synchronous update functionality.
18.3.7 Fault Conditions
A fault condition is one in which the controller must be signaled to stop normal PWM function and
then set the MnPWMn signals to a safe state. Two basic situations cause fault conditions:
The microcontroller is stalled and cannot performthe necessary computation in the time required
for motion control
An external error or event is detected
Each PWM generator can use the following inputs to generate a fault condition, including:
MnFAULTn pin assertion
A stall of the controller generated by the debugger
The trigger of an ADC digital comparator
Fault conditions are calculated on a per-PWM generator basis. Each PWM generator configures
the necessary conditions to indicate a fault condition exists. This method allows the development
of applications with dependent and independent control.
Six fault input pins (MnFAULTn) are available. These inputs may be used with circuits that generate
an active High or active Low signal to indicate an error condition. A MnFAULTn pins may be
individually programmed for the appropriate logic sense using the PWMnFLTSEN register.
The PWMgenerator's mode control, including fault condition handling, is provided in the PWMnCTL
register. The PWMnCTL register also selects whether the fault condition is maintained as long as
the external condition lasts or if it is latched until the fault condition until cleared by software. Finally,
this register also enables a counter that may be used to extend the period of a fault condition for
external events to assure that the duration is a minimum length. The minimum fault period count is
specified in the PWMnMINFLTPER register.
Status regarding the specific fault cause is provided in the PWMnFLTSTAT0 and PWMnFLTSTAT1
registers.
PWM generator fault conditions may be promoted to a controller interrupt using the PWMINTEN
register.
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18.3.8 Output Control Block
The output control block takes care of the final conditioning of the pwmA' and pwmB' signals before
they go to the pins as the MnPWMn signals. Via a single register, the PWM Output Enable
(PWNENABLE) register, the set of PWMsignals that are actually enabled to the pins can be modified.
This function can be used, for example, to perform commutation of a brushless DC motor with a
single register write (and without modifying the individual PWM generators, which are modified by
the feedback control loop). In addition, the updating of the bits in the PWMENABLE register can
be configured to be immediate or locally or globally synchronized to the next synchronous update
using the PWM Enable Update (PWMENUPD) register.
During fault conditions, the PWM output signals, MnPWMn, usually must be driven to safe values so
that external equipment may be safely controlled. The PWMFAULT register specifies whether during
a fault condition, the generated signal continues to be passed driven or to an encoding specified in
the PWMFAULTVAL register.
A final inversion can be applied to any of the MnPWMn signals, making them active Low instead of
the default active High using the PWM Output Inversion (PWMINVERT). The inversion is applied
even if a value has been enabled in the PWMFAULT register and specified in the PWMFAULTVAL
register. In other words, if a bit is set in the PWMFAULT, PWMFAULTVAL, and PWMINVERT
registers, the output on the MnPWMn signal is 0, not 1 as specified in the PWMFAULTVAL register.
The following example shows how to initialize PWM Generator 0 with a 25-kHz frequency, a 25%
duty cycle on the MnPWM0 pin, and a 75% duty cycle on the MnPWM1 pin. This example assumes
the system clock is 20 MHz.
1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System
Control module (see page 430).
2. Enable the clock to the appropriate GPIOmodule via the RCGC2 register in the SystemControl
module (see page 438).
GPIOAFSEL register. To determine which GPIOs to configure, see Table 21-4 on page 1170.
4. Configure the PMCn fields in the GPIOPCTL register to assign the PWMsignals to the appropriate
5. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
6. Configure the PWM generator for countdown mode with immediate updates to the parameters.
Write the PWM0CTL register with a value of 0x0000.0000.
Write the PWM0GENA register with a value of 0x0000.008C.
Write the PWM0GENB register with a value of 0x0000.080C.
7. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the systemclock divided by 2. Thus there are 400 clock ticks per period.
Use this value to set the PWM0LOAD register. In Count-Down mode, set the LOAD field in the
PWM0LOAD register to the requested period minus one.
April 10, 2013 1062
Write the PWM0LOAD register with a value of 0x0000.018F.
8. Set the pulse width of the MnPWM0 pin for a 25% duty cycle.
Write the PWM0CMPA register with a value of 0x0000.012B.
9. Set the pulse width of the MnPWM1 pin for a 75% duty cycle.
Write the PWM0CMPB register with a value of 0x0000.0063.
10. Start the timers in PWM generator 0.
Write the PWM0CTL register with a value of 0x0000.0001.
11. Enable PWM outputs.
Write the PWMENABLE register with a value of 0x0000.0003.
18.5 Register Map
Table 18-2 on page 1063 lists the PWMregisters. The offset listed is a hexadecimal increment to the
register's address, relative to the PWM module's base address:
PWM0: 0x4002.8000
PWM1: 0x4002.9000
Note that the PWM module clock must be enabled before the registers can be programmed (see
page 430). There must be a delay of 3 system clocks after the PWMmodule clock is enabled before
any PWM module registers are accessed.
Table 18-2. PWM Register Map
See
page
1067 PWM Master Control 0x0000.0000 R/W PWMCTL 0x000
1069 PWM Time Base Sync 0x0000.0000 R/W PWMSYNC 0x004
1070 PWM Output Enable 0x0000.0000 R/W PWMENABLE 0x008
1072 PWM Output Inversion 0x0000.0000 R/W PWMINVERT 0x00C
1074 PWM Output Fault 0x0000.0000 R/W PWMFAULT 0x010
1076 PWM Interrupt Enable 0x0000.0000 R/W PWMINTEN 0x014
1078 PWM Raw Interrupt Status 0x0000.0000 RO PWMRIS 0x018
1081 PWM Interrupt Status and Clear 0x0000.0000 R/W1C PWMISC 0x01C
1084 PWM Status 0x0000.0000 RO PWMSTATUS 0x020
1086 PWM Fault Condition Value 0x0000.0000 R/W PWMFAULTVAL 0x024
1088 PWM Enable Update 0x0000.0000 R/W PWMENUPD 0x028
1092 PWM0 Control 0x0000.0000 R/W PWM0CTL 0x040
1097 PWM0 Interrupt and Trigger Enable 0x0000.0000 R/W PWM0INTEN 0x044
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Table 18-2. PWM Register Map (continued)
See
page
1100 PWM0 Raw Interrupt Status 0x0000.0000 RO PWM0RIS 0x048
1102 PWM0 Interrupt Status and Clear 0x0000.0000 R/W1C PWM0ISC 0x04C
1104 PWM0 Load 0x0000.0000 R/W PWM0LOAD 0x050
1105 PWM0 Counter 0x0000.0000 RO PWM0COUNT 0x054
1106 PWM0 Compare A 0x0000.0000 R/W PWM0CMPA 0x058
1107 PWM0 Compare B 0x0000.0000 R/W PWM0CMPB 0x05C
1108 PWM0 Generator A Control 0x0000.0000 R/W PWM0GENA 0x060
1111 PWM0 Generator B Control 0x0000.0000 R/W PWM0GENB 0x064
1114 PWM0 Dead-Band Control 0x0000.0000 R/W PWM0DBCTL 0x068
1115 PWM0 Dead-Band Rising-Edge Delay 0x0000.0000 R/W PWM0DBRISE 0x06C
1116 PWM0 Dead-Band Falling-Edge-Delay 0x0000.0000 R/W PWM0DBFALL 0x070
1117 PWM0 Fault Source 0 0x0000.0000 R/W PWM0FLTSRC0 0x074
1122 PWM0 Minimum Fault Period 0x0000.0000 R/W PWM0MINFLTPER 0x07C
1108 PWM1 Generator A Control 0x0000.0000 R/W PWM1GENA 0x0A0
1111 PWM1 Generator B Control 0x0000.0000 R/W PWM1GENB 0x0A4
1114 PWM1 Dead-Band Control 0x0000.0000 R/W PWM1DBCTL 0x0A8
1115 PWM1 Dead-Band Rising-Edge Delay 0x0000.0000 R/W PWM1DBRISE 0x0AC
1116 PWM1 Dead-Band Falling-Edge-Delay 0x0000.0000 R/W PWM1DBFALL 0x0B0
1117 PWM1 Fault Source 0 0x0000.0000 R/W PWM1FLTSRC0 0x0B4
1119 PWM1 Fault Source 1 0x0000.0000 R/W PWM1FLTSRC1 0x0B8
1122 PWM1 Minimum Fault Period 0x0000.0000 R/W PWM1MINFLTPER 0x0BC
1092 PWM2 Control 0x0000.0000 R/W PWM2CTL 0x0C0
1097 PWM2 Interrupt and Trigger Enable 0x0000.0000 R/W PWM2INTEN 0x0C4
April 10, 2013 1064
See
page
1100 PWM2 Raw Interrupt Status 0x0000.0000 RO PWM2RIS 0x0C8
1102 PWM2 Interrupt Status and Clear 0x0000.0000 R/W1C PWM2ISC 0x0CC
1104 PWM2 Load 0x0000.0000 R/W PWM2LOAD 0x0D0
1105 PWM2 Counter 0x0000.0000 RO PWM2COUNT 0x0D4
1106 PWM2 Compare A 0x0000.0000 R/W PWM2CMPA 0x0D8
1107 PWM2 Compare B 0x0000.0000 R/W PWM2CMPB 0x0DC
1108 PWM2 Generator A Control 0x0000.0000 R/W PWM2GENA 0x0E0
1111 PWM2 Generator B Control 0x0000.0000 R/W PWM2GENB 0x0E4
1114 PWM2 Dead-Band Control 0x0000.0000 R/W PWM2DBCTL 0x0E8
1115 PWM2 Dead-Band Rising-Edge Delay 0x0000.0000 R/W PWM2DBRISE 0x0EC
1116 PWM2 Dead-Band Falling-Edge-Delay 0x0000.0000 R/W PWM2DBFALL 0x0F0
1117 PWM2 Fault Source 0 0x0000.0000 R/W PWM2FLTSRC0 0x0F4
1119 PWM2 Fault Source 1 0x0000.0000 R/W PWM2FLTSRC1 0x0F8
1122 PWM2 Minimum Fault Period 0x0000.0000 R/W PWM2MINFLTPER 0x0FC
1108 PWM3 Generator A Control 0x0000.0000 R/W PWM3GENA 0x120
1111 PWM3 Generator B Control 0x0000.0000 R/W PWM3GENB 0x124
1114 PWM3 Dead-Band Control 0x0000.0000 R/W PWM3DBCTL 0x128
1115 PWM3 Dead-Band Rising-Edge Delay 0x0000.0000 R/W PWM3DBRISE 0x12C
1116 PWM3 Dead-Band Falling-Edge-Delay 0x0000.0000 R/W PWM3DBFALL 0x130
1122 PWM3 Minimum Fault Period 0x0000.0000 R/W PWM3MINFLTPER 0x13C
1123 PWM0 Fault Pin Logic Sense 0x0000.0000 R/W PWM0FLTSEN 0x800
1124 PWM0 Fault Status 0 0x0000.0000 - PWM0FLTSTAT0 0x804
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See
page
1129 PWM Peripheral Properties 0x0000.0334 RO PWMPP 0xFC0
The remainder of this section lists and describes the PWM registers, in numerical order by address
offset.
April 10, 2013 1066
Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation blocks.
PWM Master Control (PWMCTL)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
G
L
O
B
A
L
S
Y
N
C
0
G
L
O
B
A
L
S
Y
N
C
1
G
L
O
B
A
L
S
Y
N
C
2
G
L
O
B
A
L
S
Y
N
C
3
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Update PWM Generator 3
Description Value
No effect. 0
Any queued update to a load or comparator register in PWM
generator 3 is applied the next time the corresponding counter
becomes zero.
1
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
0 R/W GLOBALSYNC3 3
Description Value
No effect. 0
becomes zero.
1
0 R/W GLOBALSYNC2 2
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Description Value
No effect. 0
becomes zero.
1
0 R/W GLOBALSYNC1 1
Description Value
No effect. 0
becomes zero.
1
0 R/W GLOBALSYNC0 0
April 10, 2013 1068
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Setting a bit in this register causes the specified counter to reset back to 0; setting multiple
bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading
them back as zero indicates that the synchronization has completed.
PWM Time Base Sync (PWMSYNC)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SYNC0 SYNC1 SYNC2 SYNC3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Reset Generator 3 Counter
Description Value
No effect. 0
Resets the PWM generator 3 counter. 1
0 R/W SYNC3 3
Description Value
No effect. 0
0 R/W SYNC2 2
Description Value
No effect. 0
0 R/W SYNC1 1
Description Value
No effect. 0
0 R/W SYNC0 0
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Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated pwmA' and pwmB' signals are output to
the MnPWMn pins. By disabling a PWM output, the generation process can continue (for example,
when the time bases are synchronized) without driving PWM signals to the pins. When bits in this
register are set, the corresponding pwmA' or pwmB' signal is passed through to the output stage.
When bits are clear, the pwmA' or pwmB' signal is replaced by a zero value which is also passed
to the output stage. The PWMINVERT register controls the output stage, so if the corresponding
bit is set in that register, the value seen on the MnPWMn signal is inverted from what is configured
by the bits in this register. Updates to the bits in this register can be immediate or locally or globally
synchronized to the next synchronous update as controlled by the ENUPDn fields in the PWMENUPD
register.
PWM Output Enable (PWMENABLE)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PWM0EN PWM1EN PWM2EN PWM3EN PWM4EN PWM5EN PWM6EN PWM7EN reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
MnPWM7 Output Enable
Description Value
The MnPWM7 signal has a zero value. 0
The generated pwm3B' signal is passed to the MnPWM7 pin. 1
0 R/W PWM7EN 7
Description Value
The generated pwm3A' signal is passed to the MnPWM6 pin. 1
0 R/W PWM6EN 6
Description Value
0 R/W PWM5EN 5
April 10, 2013 1070
Description Value
0 R/W PWM4EN 4
Description Value
0 R/W PWM3EN 3
Description Value
0 R/W PWM2EN 2
Description Value
0 R/W PWM1EN 1
Description Value
0 R/W PWM0EN 0
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Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
This register provides a master control of the polarity of the MnPWMn signals on the device pins. The
pwmA' and pwmB' signals generated by the PWMgenerator are active High; but can be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive signals can be High. In addition, if the PWMFAULT register enables a
specific value to be placed on the MnPWMn signals during a fault condition, that value is inverted if
the corresponding bit in this register is set.
PWM Output Inversion (PWMINVERT)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x00C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PWM0INV PWM1INV PWM2INV PWM3INV PWM4INV PWM5INV PWM6INV PWM7INV reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Invert MnPWM7 Signal
Description Value
The MnPWM7 signal is not inverted. 0
The MnPWM7 signal is inverted. 1
0 R/W PWM7INV 7
Description Value
0 R/W PWM6INV 6
Description Value
0 R/W PWM5INV 5
Description Value
0 R/W PWM4INV 4
April 10, 2013 1072
Description Value
0 R/W PWM3INV 3
Description Value
0 R/W PWM2INV 2
Description Value
0 R/W PWM1INV 1
Description Value
0 R/W PWM0INV 0
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Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the MnPWMn outputs in the presence of fault conditions. Both
the fault inputs (MnFAULTn pins and digital comparator outputs) and debug events are considered
fault conditions. On a fault condition, each pwmA' or pwmB' signal can be passed through unmodified
or driven to the value specified by the corresponding bit in the PWMFAULTVAL register. For outputs
that are configured for pass-through, the debug event handling on the corresponding PWMgenerator
also determines if the pwmA' or pwmB' signal continues to be generated.
Fault condition control occurs before the output inverter, so PWM signals driven to a specified value
on fault are inverted if the channel is configured for inversion (therefore, the pin is driven to the
logical complement of the specified value on a fault condition).
PWM Output Fault (PWMFAULT)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FAULT0 FAULT1 FAULT2 FAULT3 FAULT4 FAULT5 FAULT6 FAULT7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
MnPWM7 Fault
Description Value
The MnPWM7 output signal is driven to the value specified by
the PWM7 bit in the PWMFAULTVAL register.
1
0 R/W FAULT7 7
MnPWM6 Fault
Description Value
1
0 R/W FAULT6 6
MnPWM5 Fault
Description Value
1
0 R/W FAULT5 5
April 10, 2013 1074
MnPWM4 Fault
Description Value
1
0 R/W FAULT4 4
MnPWM3 Fault
Description Value
1
0 R/W FAULT3 3
MnPWM2 Fault
Description Value
1
0 R/W FAULT2 2
MnPWM1 Fault
Description Value
1
0 R/W FAULT1 1
MnPWM0 Fault
Description Value
1
0 R/W FAULT0 0
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Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts fromthe PWMgenerators.
Note: The "n" in the INTFAULTn and INTPWMn bits in this register correspond to the PWM
generators, not to the FAULTn signals.
PWM Interrupt Enable (PWMINTEN)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x014
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INTFAULT0 INTFAULT1 INTFAULT2 INTFAULT3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTPWM0 INTPWM1 INTPWM2 INTPWM3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Fault 3
Description Value
The fault condition for PWM generator 3 is suppressed and not
sent to the interrupt controller.
0
An interrupt is sent to the interrupt controller when the fault
condition for PWM generator 3 is asserted.
1
0 R/W INTFAULT3 19
Interrupt Fault 2
Description Value
0
1
0 R/W INTFAULT2 18
Interrupt Fault 1
Description Value
0
1
0 R/W INTFAULT1 17
April 10, 2013 1076
Interrupt Fault 0
Description Value
0
1
0 R/W INTFAULT0 16
PWM3 Interrupt Enable
Description Value
The PWM generator 3 interrupt is suppressed and not sent to
0
An interrupt is sent to the interrupt controller when the PWM
generator 3 block asserts an interrupt.
1
0 R/W INTPWM3 3
Description Value
0
1
0 R/W INTPWM2 2
Description Value
0
1
0 R/W INTPWM1 1
Description Value
0
1
0 R/W INTPWM0 0
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Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they are enabled to cause an interrupt to be asserted to the interrupt controller. The fault interrupt
is asserted based on the fault condition source that is specified by the PWMnCTL, PWMnFLTSRC0
and PWMnFLTSRC1 registers. The fault interrupt is latched on detection and must be cleared
through the PWMInterrupt Status and Clear (PWMISC) register. The actual value of the MnFAULTn
signals can be observed using the PWMSTATUS register.
The PWM generator interrupts simply reflect the status of the PWM generators and are cleared via
the interrupt status register in the PWM generator blocks. If a bit is set, the event is active; if a bit
is clear the event is not active.
PWM Raw Interrupt Status (PWMRIS)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Interrupt Fault PWM 3
Description Value
The fault condition for PWMgenerator 3 has not been asserted. 0
The fault condition for PWM generator 3 is asserted. 1
Note: If the LATCH bit is set in the PWM3CTL register, the
INTFAULT3 bit in this register can be cleared by writing a 1
to the INTFAULT3 bit in the PWMISC register. If the LATCH
bit is 0 in the PWM3CTL register, writing a 1 to the
INTFAULT3 bit in the PWMISC register has no effect.
0 RO INTFAULT3 19
Description Value
0 RO INTFAULT2 18
April 10, 2013 1078
Description Value
0 RO INTFAULT1 17
Description Value
0 RO INTFAULT0 16
PWM3 Interrupt Asserted
Description Value
The PWM generator 3 block interrupt has not been asserted. 0
The PWM generator 3 block interrupt is asserted. 1
The PWM3RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM3ISC register.
0 RO INTPWM3 3
Description Value
0 RO INTPWM2 2
Description Value
0 RO INTPWM1 1
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Description Value
0 RO INTPWM0 0
April 10, 2013 1080
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the individual PWM generator blocks. If
a fault interrupt is set, the corresponding MnFAULTn input has caused an interrupt. For the fault
interrupt, a write of 1 to that bit position clears the latched interrupt status. If an block interrupt bit
is set, the corresponding generator block is asserting an interrupt. The individual interrupt status
registers, PWMnISC, in each block must be consulted to determine the reason for the interrupt and
used to clear the interrupt.
PWM Interrupt Status and Clear (PWMISC)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x01C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
FAULT3 Interrupt Asserted
Description Value
The fault condition for PWM generator 3 has not been asserted
or is not enabled.
0
An enabled interrupt for the fault condition for PWM generator
3 is asserted or is latched.
1
Writing a 1 to this bit clears it and the INTFAULT3 bit in the PWMRIS
register.
0 R/W1C INTFAULT3 19
Description Value
or is not enabled.
0
1
register.
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Description Value
or is not enabled.
0
1
register.
Description Value
or is not enabled.
0
1
register.
PWM3 Interrupt Status
Description Value
The PWM generator 3 block interrupt is not asserted or is not
enabled.
0
An enabled interrupt for the PWMgenerator 3 block is asserted. 1
0 RO INTPWM3 3
Description Value
enabled.
0
0 RO INTPWM2 2
Description Value
enabled.
0
0 RO INTPWM1 1
April 10, 2013 1082
Description Value
enabled.
0
0 RO INTPWM0 0
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Register 9: PWM Status (PWMSTATUS), offset 0x020
This register provides the unlatched status of the PWM generator fault condition.
PWM Status (PWMSTATUS)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FAULT0 FAULT1 FAULT2 FAULT3 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Generator 3 Fault Status
Description Value
The fault condition for PWM generator 3 is not asserted. 0
The fault condition for PWM generator 3 is asserted.
If the FLTSRC bit in the PWM3CTL register is clear, the input
is the source of the fault condition, and is therefore asserted.
1
0 RO FAULT3 3
Description Value
1
0 RO FAULT2 2
Description Value
1
0 RO FAULT1 1
April 10, 2013 1084
Description Value
1
0 RO FAULT0 0
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Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024
This register specifies the output value driven on the MnPWMn signals during a fault condition if
enabled by the corresponding bit in the PWMFAULT register. Note that if the corresponding bit in
the PWMINVERT register is set, the output value is driven to the logical NOT of the bit value in this
register.
PWM Fault Condition Value (PWMFAULTVAL)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
MnPWM7 Fault Value
Description Value
The MnPWM7 output signal is driven Low during fault conditions
if the FAULT7 bit in the PWMFAULT register is set.
0
The MnPWM7 output signal is driven High during fault conditions
1
0 R/W PWM7 7
MnPWM6 Fault Value
Description Value
0
1
0 R/W PWM6 6
MnPWM5 Fault Value
Description Value
0
1
0 R/W PWM5 5
April 10, 2013 1086
MnPWM4 Fault Value
Description Value
0
1
0 R/W PWM4 4
MnPWM3 Fault Value
Description Value
0
1
0 R/W PWM3 3
MnPWM2 Fault Value
Description Value
0
1
0 R/W PWM2 2
MnPWM1 Fault Value
Description Value
0
1
0 R/W PWM1 1
MnPWM0 Fault Value
Description Value
0
1
0 R/W PWM0 0
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Register 11: PWM Enable Update (PWMENUPD), offset 0x028
This register specifies when updates to the PWMnEN bit in the PWMENABLE register are performed.
The PWMnEN bit enables the pwmA' or pwmB' output to be passed to the microcontroller's pin.
Updates can be immediate or locally or globally synchronized to the next synchronous update.
PWM Enable Update (PWMENUPD)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x028
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ENUPD0 ENUPD1 ENUPD2 ENUPD3 ENUPD4 ENUPD5 ENUPD6 ENUPD7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
MnPWM7 Enable Update Mode
Description Value
Immediate
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x0
Reserved 0x1
Locally Synchronized
by the PWM generator the next time the counter is 0.
0x2
Globally Synchronized
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
0x3
0 R/W ENUPD7 15:14
April 10, 2013 1088
Description Value
Immediate
0x0
Reserved 0x1
0x2
0x3
0 R/W ENUPD6 13:12
Description Value
Immediate
0x0
Reserved 0x1
0x2
0x3
0 R/W ENUPD5 11:10
Description Value
Immediate
0x0
Reserved 0x1
0x2
0x3
0 R/W ENUPD4 9:8
1089 April 10, 2013
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Description Value
Immediate
0x0
Reserved 0x1
0x2
0x3
0 R/W ENUPD3 7:6
Description Value
Immediate
0x0
Reserved 0x1
0x2
0x3
0 R/W ENUPD2 5:4
Description Value
Immediate
0x0
Reserved 0x1
0x2
0x3
0 R/W ENUPD1 3:2
April 10, 2013 1090
Description Value
Immediate
0x0
Reserved 0x1
0x2
0x3
0 R/W ENUPD0 1:0
1091 April 10, 2013
Tiva
Register 12: PWM0 Control (PWM0CTL), offset 0x040
Register 14: PWM2 Control (PWM2CTL), offset 0x0C0
These registers configure the PWMsignal generation blocks (PWM0CTL controls the PWMgenerator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the MnPWM0 and MnPWM1 outputs, the PWM1 block produces the MnPWM2
and MnPWM3 outputs, the PWM2 block produces the MnPWM4 and MnPWM5 outputs, and the PWM3
block produces the MnPWM6 and MnPWM7 outputs.
PWMn Control (PWMnCTL)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x040
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FLTSRC MINFLTPER LATCH reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ENABLE MODE DEBUG LOADUPD CMPAUPD CMPBUPD GENAUPD GENBUPD DBCTLUPD DBRISEUPD DBFALLUPD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Latch Fault Input
Description Value
Fault Condition Not Latched
A fault condition is in effect for as long as the generating source
is asserting.
0
Fault Condition Latched
A fault condition is set as the result of the assertion of the
faulting source and is held (latched) while the PWMISC
INTFAULTn bit is set. Clearing the INTFAULTn bit clears the
fault condition.
1
0 R/W LATCH 18
April 10, 2013 1092
Minimum Fault Period
This bit specifies that the PWM generator enables a one-shot counter
to provide a minimum fault condition period.
The timer begins counting on the rising edge of the fault condition to
extend the condition for a minimum duration of the count value. The
timer ignores the state of the fault condition while counting.
The minimum fault delay is in effect only when the MINFLTPER bit is
set. If a detected fault is in the process of being extended when the
MINFLTPER bit is cleared, the fault condition extension is aborted.
The delay time is specified by the PWMnMINFLTPER register MFP field
value. The effect of this is to pulse stretch the fault condition input.
The delay value is defined by the PWM clock period. Because the fault
input is not synchronized to the PWM clock, the period of the time is
PWMClock * (MFP value + 1) or PWMClock * (MFP value + 2).
The delay function makes sense only if the fault source is unlatched. A
latched fault source makes the fault condition appear asserted until
cleared by software and negates the utility of the extend feature. It
applies to all fault condition sources as specified in the FLTSRC field.
Description Value
The FAULT input deassertion is unaffected. 0
The PWMnMINFLTPERone-shot counter is active and extends
the period of the fault condition to a minimum period.
1
0 R/W MINFLTPER 17
Fault Condition Source
Description Value
The Fault condition is determined by the Fault0 input. 0
The Fault condition is determined by the configuration of the
PWMnFLTSRC0 and PWMnFLTSRC1 registers.
1
0 R/W FLTSRC 16
PWMnDBFALL Update Mode
Description Value
Immediate
The PWMnDBFALL register value is immediately updated on
a write.
0x0
Reserved 0x1
Updates to the register are reflected to the generator the next
time the counter is 0.
0x2
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
0x3
0x0 R/W DBFALLUPD 15:14
1093 April 10, 2013
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PWMnDBRISE Update Mode
Description Value
Immediate
The PWMnDBRISE register value is immediately updated on
a write.
0x0
Reserved 0x1
0x2
0x3
0x0 R/W DBRISEUPD 13:12
PWMnDBCTL Update Mode
Description Value
Immediate
The PWMnDBCTL register value is immediately updated on a
write.
0x0
Reserved 0x1
0x2
0x3
0x0 R/W DBCTLUPD 11:10
PWMnGENB Update Mode
Description Value
Immediate
The PWMnGENB register value is immediately updated on a
write.
0x0
Reserved 0x1
0x2
0x3
0x0 R/W GENBUPD 9:8
April 10, 2013 1094
PWMnGENA Update Mode
Description Value
Immediate
The PWMnGENA register value is immediately updated
on a write.
0x0
Reserved 0x1
Updates to the register are reflected to the generator the
next time the counter is 0.
0x2
Updates to the register are delayed until the next time
the counter is 0 after a synchronous update has been
requested through the PWMCTL register.
0x3
0x0 R/W GENAUPD 7:6
Comparator B Update Mode
Description Value
Updates to the PWMnCMPB register are reflected to the
generator the next time the counter is 0.
0
1
0 R/W CMPBUPD 5
Comparator A Update Mode
Description Value
Updates to the PWMnCMPA register are reflected to the
0
1
0 R/W CMPAUPD 4
Load Register Update Mode
Description Value
Updates to the PWMnLOAD register are reflected to the
0
1
0 R/W LOADUPD 3
1095 April 10, 2013
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Debug Mode
Description Value
The counter stops running when it next reaches 0 and continues
running again when no longer in Debug mode.
0
The counter always runs when in Debug mode. 1
0 R/W DEBUG 2
Counter Mode
Description Value
The counter counts down from the load value to 0 and then
wraps back to the load value (Count-Down mode).
0
The counter counts up from 0 to the load value, back down to
0, and then repeats (Count-Up/Down mode).
1
0 R/W MODE 1
PWM Block Enable
Description Value
The entire PWM generation block is disabled and not clocked. 0
The PWM generation block is enabled and produces PWM
signals.
1
0 R/W ENABLE 0
April 10, 2013 1096
Register 16: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 18: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
These registers control the interrupt and ADCtrigger generation capabilities of the PWMgenerators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt,or an ADC trigger are:
The counter being equal to the load register
The counter being equal to zero
The counter being equal to the PWMnCMPA register while counting up
The counter being equal to the PWMnCMPA register while counting down
The counter being equal to the PWMnCMPB register while counting up
The counter being equal to the PWMnCMPB register while counting down
Any combination of these events can generate either an interrupt or an ADC trigger, though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified. The PWMnRIS register provides information about which events have caused raw
interrupts.
PWMn Interrupt and Trigger Enable (PWMnINTEN)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x044
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTCNTZERO INTCNTLOAD INTCMPAU INTCMPAD INTCMPBU INTCMPBD reserved TRCNTZERO TRCNTLOAD TRCMPAU TRCMPAD TRCMPBU TRCMPBD reserved
R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:14
Trigger for Counter=PWMnCMPB Down
Description Value
No ADC trigger is output. 0
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting down.
1
0 R/W TRCMPBD 13
1097 April 10, 2013
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Trigger for Counter=PWMnCMPB Up
Description Value
value in the PWMnCMPB register value while counting up.
1
0 R/W TRCMPBU 12
Trigger for Counter=PWMnCMPA Down
Description Value
value in the PWMnCMPA register value while counting down.
1
0 R/W TRCMPAD 11
Trigger for Counter=PWMnCMPA Up
Description Value
value in the PWMnCMPA register value while counting up.
1
0 R/W TRCMPAU 10
Trigger for Counter=PWMnLOAD
Description Value
PWMnLOAD register.
1
0 R/W TRCNTLOAD 9
Trigger for Counter=0
Description Value
An ADC trigger pulse is output when the counter is 0. 1
0 R/W TRCNTZERO 8
0x0 RO reserved 7:6
Interrupt for Counter=PWMnCMPB Down
Description Value
No interrupt. 0
A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting down.
1
0 R/W INTCMPBD 5
April 10, 2013 1098
Interrupt for Counter=PWMnCMPB Up
Description Value
No interrupt. 0
the PWMnCMPB register value while counting up.
1
0 R/W INTCMPBU 4
Interrupt for Counter=PWMnCMPA Down
Description Value
No interrupt. 0
the PWMnCMPA register value while counting down.
1
0 R/W INTCMPAD 3
Interrupt for Counter=PWMnCMPA Up
Description Value
No interrupt. 0
the PWMnCMPA register value while counting up.
1
0 R/W INTCMPAU 2
Interrupt for Counter=PWMnLOAD
Description Value
No interrupt. 0
the PWMnLOAD register value.
1
0 R/W INTCNTLOAD 1
Interrupt for Counter=0
Description Value
No interrupt. 0
A raw interrupt occurs when the counter is zero. 1
0 R/W INTCNTZERO 0
1099 April 10, 2013
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Register 20: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
Register 22: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). If a bit is set, the event has occurred; if a bit is clear, the event has not occurred.
Bits in this register are cleared by writing a 1 to the corresponding bit in the PWMnISC register.
PWMn Raw Interrupt Status (PWMnRIS)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x048
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTCNTZERO INTCNTLOAD INTCMPAU INTCMPAD INTCMPBU INTCMPBD reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
Comparator B Down Interrupt Status
Description Value
The counter has matched the value in the PWMnCMPBregister
while counting down.
1
This bit is cleared by writing a 1 to the INTCMPBD bit in the PWMnISC
register.
0 RO INTCMPBD 5
Comparator B Up Interrupt Status
Description Value
The counter has matched the value in the PWMnCMPBregister
while counting up.
1
This bit is cleared by writing a 1 to the INTCMPBU bit in the PWMnISC
register.
0 RO INTCMPBU 4
April 10, 2013 1100
Comparator A Down Interrupt Status
Description Value
The counter has matched the value in the PWMnCMPAregister
while counting down.
1
This bit is cleared by writing a 1 to the INTCMPAD bit in the PWMnISC
register.
0 RO INTCMPAD 3
Comparator A Up Interrupt Status
Description Value
The counter has matched the value in the PWMnCMPAregister
while counting up.
1
This bit is cleared by writing a 1 to the INTCMPAU bit in the PWMnISC
register.
0 RO INTCMPAU 2
Counter=Load Interrupt Status
Description Value
The counter has matched the value in the PWMnLOADregister. 1
This bit is cleared by writing a 1 to the INTCNTLOAD bit in the PWMnISC
register.
0 RO INTCNTLOAD 1
Counter=0 Interrupt Status
Description Value
The counter has matched zero. 1
This bit is cleared by writing a 1 to the INTCNTZERO bit in the PWMnISC
register.
0 RO INTCNTZERO 0
1101 April 10, 2013
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Register 24: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 26: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
These registers provide the current set of interrupt sources that are asserted to the interrupt controller
(PWM0ISC controls the PWM generator 0 block, and so on). A bit is set if the event has occurred
and is enabled in the PWMnINTEN register; if a bit is clear, the event has not occurred or is not
enabled. These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt
reason.
PWMn Interrupt Status and Clear (PWMnISC)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x04C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTCNTZERO INTCNTLOAD INTCMPAU INTCMPAD INTCMPBU INTCMPBD reserved
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:6
Comparator B Down Interrupt
Description Value
The INTCMPBD bits in the PWMnRISand PWMnINTENregisters
1
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPBD bit in the PWMnRIS register.
0 R/W1C INTCMPBD 5
Comparator B Up Interrupt
Description Value
The INTCMPBU bits in the PWMnRISand PWMnINTENregisters
1
INTCMPBU bit in the PWMnRIS register.
0 R/W1C INTCMPBU 4
April 10, 2013 1102
Comparator A Down Interrupt
Description Value
The INTCMPAD bits in the PWMnRISand PWMnINTENregisters
1
INTCMPAD bit in the PWMnRIS register.
0 R/W1C INTCMPAD 3
Comparator A Up Interrupt
Description Value
The INTCMPAU bits in the PWMnRISand PWMnINTENregisters
1
INTCMPAU bit in the PWMnRIS register.
0 R/W1C INTCMPAU 2
Counter=Load Interrupt
Description Value
The INTCNTLOAD bits in the PWMnRIS and PWMnINTEN
registers are set, providing an interrupt to the interrupt controller.
1
INTCNTLOAD bit in the PWMnRIS register.
0 R/W1C INTCNTLOAD 1
Counter=0 Interrupt
Description Value
The INTCNTZERO bits in the PWMnRIS and PWMnINTEN
1
INTCNTZERO bit in the PWMnRIS register.
0 R/W1C INTCNTZERO 0
1103 April 10, 2013
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Register 28: PWM0 Load (PWM0LOAD), offset 0x050
Register 30: PWM2 Load (PWM2LOAD), offset 0x0D0
These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM
generator 0 block, and so on). Based on the counter mode configured by the MODE bit in the
PWMnCTL register, this value is either loaded into the counter after it reaches zero or is the limit
of up-counting after which the counter decrements back to zero. When this value matches the
counter, a pulse is output which can be configured to drive the generation of the pwmA and/or pwmB
signal (via the PWMnGENA/PWMnGENB register) or drive an interruptor ADC trigger (via the
PWMnINTEN register).
If the Load Value Update mode is locally synchronized (based on the LOADUPD field encoding in
the PWMnCTL register), the 16-bit LOAD value is used the next time the counter reaches zero. If
the update mode is globally synchronized, it is used the next time the counter reaches zero after a
synchronous update has been requested through the PWM Master Control (PWMCTL) register
(see page 1067). If this register is re-written before the actual update occurs, the previous value is
never used and is lost.
PWMn Load (PWMnLOAD)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x050
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LOAD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Counter Load Value
The counter load value.
0x0000 R/W LOAD 15:0
April 10, 2013 1104
Register 32: PWM0 Counter (PWM0COUNT), offset 0x054
Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4
These registers contain the current value of the PWM counter (PWM0COUNT is the value of the
PWMgenerator 0 block, and so on). When this value matches zero or the value in the PWMnLOAD,
PWMnCMPA, or PWMnCMPB registers, a pulse is output which can be configured to drive the
generation of a PWM signal or drive an interrupt or ADC trigger.
PWMn Counter (PWMnCOUNT)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x054
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
COUNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Counter Value
The current value of the counter.
0x0000 RO COUNT 15:0
1105 April 10, 2013
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Register 36: PWM0 Compare A (PWM0CMPA), offset 0x058
Register 38: PWM2 Compare A (PWM2CMPA), offset 0x0D8
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which
can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA
and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If
the value of this register is greater than the PWMnLOAD register (see page 1104), then no pulse is
ever output.
If the comparator A update mode is locally synchronized (based on the CMPAUPD bit in the PWMnCTL
register), the 16-bit COMPA value is used the next time the counter reaches zero. If the update mode
is globally synchronized, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWMMaster Control (PWMCTL) register (see page 1067).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWMn Compare A (PWMnCMPA)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x058
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
COMPA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Comparator A Value
The value to be compared against the counter.
0x00 R/W COMPA 15:0
April 10, 2013 1106
Register 40: PWM0 Compare B (PWM0CMPB), offset 0x05C
Register 42: PWM2 Compare B (PWM2CMPB), offset 0x0DC
These registers contain a value to be compared against the counter (PWM0CMPB controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which
can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA
and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If
the value of this register is greater than the PWMnLOAD register, no pulse is ever output.
If the comparator B update mode is locally synchronized (based on the CMPBUPD bit in the PWMnCTL
register), the 16-bit COMPB value is used the next time the counter reaches zero. If the update mode
is globally synchronized, it is used the next time the counter reaches zero after a synchronous
lost.
PWMn Compare B (PWMnCMPB)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x05C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
COMPB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Comparator B Value
The value to be compared against the counter.
0x0000 R/W COMPB 15:0
1107 April 10, 2013
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Register 44: PWM0 Generator A Control (PWM0GENA), offset 0x060
Register 45: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
Register 46: PWM2 Generator A Control (PWM2GENA), offset 0x0E0
Register 47: PWM3 Generator A Control (PWM3GENA), offset 0x120
These registers control the generation of the pwmA signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM
signal.
The PWM0GENA register controls generation of the pwm0A signal; PWM1GENA, the pwm1A
signal; PWM2GENA, the pwm2A signal; and PWM3GENA, the pwm3A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
If the Generator Aupdate mode is immediate (based on the GENAUPD field encoding in the PWMnCTL
register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are
used immediately. If the update mode is locally synchronized, these values are used the next time
the counter reaches zero. If the update mode is globally synchronized, these values are used the
next time the counter reaches zero after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register (see page 1067). If this register is rewritten before the
actual update occurs, the previous value is never used and is lost.
PWMn Generator A Control (PWMnGENA)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x060
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ACTZERO ACTLOAD ACTCMPAU ACTCMPAD ACTCMPBU ACTCMPBD reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
April 10, 2013 1108
Action for Comparator B Down
This field specifies the action to be taken when the counter matches
comparator B while counting down.
Description Value
Do nothing. 0x0
Invert pwmA. 0x1
Drive pwmA Low. 0x2
Drive pwmA High. 0x3
0x0 R/W ACTCMPBD 11:10
Action for Comparator B Up
comparator B while counting up. This action can only occur when the
MODE bit in the PWMnCTL register is set.
Description Value
Do nothing. 0x0
Invert pwmA. 0x1
Drive pwmA Low. 0x2
0x0 R/W ACTCMPBU 9:8
Action for Comparator A Down
comparator A while counting down.
Description Value
Do nothing. 0x0
Invert pwmA. 0x1
Drive pwmA Low. 0x2
0x0 R/W ACTCMPAD 7:6
Action for Comparator A Up
comparator A while counting up. This action can only occur when the
Description Value
Do nothing. 0x0
Invert pwmA. 0x1
Drive pwmA Low. 0x2
0x0 R/W ACTCMPAU 5:4
1109 April 10, 2013
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Action for Counter=LOAD
This field specifies the action to be taken when the counter matches the
value in the PWMnLOAD register.
Description Value
Do nothing. 0x0
Invert pwmA. 0x1
Drive pwmA Low. 0x2
0x0 R/W ACTLOAD 3:2
Action for Counter=0
This field specifies the action to be taken when the counter is zero.
Description Value
Do nothing. 0x0
Invert pwmA. 0x1
Drive pwmA Low. 0x2
0x0 R/W ACTZERO 1:0
April 10, 2013 1110
Register 48: PWM0 Generator B Control (PWM0GENB), offset 0x064
Register 49: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
Register 50: PWM2 Generator B Control (PWM2GENB), offset 0x0E4
Register 51: PWM3 Generator B Control (PWM3GENB), offset 0x124
These registers control the generation of the pwmB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM
signal.
The PWM0GENB register controls generation of the pwm0B signal; PWM1GENB, the pwm1B
signal; PWM2GENB, the pwm2B signal; and PWM3GENB, the pwm3B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
If the Generator Bupdate mode is immediate (based on the GENBUPD field encoding in the PWMnCTL
register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are
used immediately. If the update mode is locally synchronized, these values are used the next time
the counter reaches zero. If the update mode is globally synchronized, these values are used the
next time the counter reaches zero after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register (see page 1067). If this register is rewritten before the
actual update occurs, the previous value is never used and is lost.
PWMn Generator B Control (PWMnGENB), offset 0x064
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x064
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ACTZERO ACTLOAD ACTCMPAU ACTCMPAD ACTCMPBU ACTCMPBD reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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Action for Comparator B Down
comparator B while counting down.
Description Value
Do nothing. 0x0
Invert pwmB. 0x1
Drive pwmB Low. 0x2
Drive pwmB High. 0x3
0x0 R/W ACTCMPBD 11:10
Action for Comparator B Up
comparator B while counting up. This action can only occur when the
Description Value
Do nothing. 0x0
Invert pwmB. 0x1
Drive pwmB Low. 0x2
0x0 R/W ACTCMPBU 9:8
Action for Comparator A Down
comparator A while counting down.
Description Value
Do nothing. 0x0
Invert pwmB. 0x1
Drive pwmB Low. 0x2
0x0 R/W ACTCMPAD 7:6
Action for Comparator A Up
comparator A while counting up. This action can only occur when the
Description Value
Do nothing. 0x0
Invert pwmB. 0x1
Drive pwmB Low. 0x2
0x0 R/W ACTCMPAU 5:4
April 10, 2013 1112
Action for Counter=LOAD
This field specifies the action to be taken when the counter matches the
load value.
Description Value
Do nothing. 0x0
Invert pwmB. 0x1
Drive pwmB Low. 0x2
0x0 R/W ACTLOAD 3:2
Action for Counter=0
This field specifies the action to be taken when the counter is 0.
Description Value
Do nothing. 0x0
Invert pwmB. 0x1
Drive pwmB Low. 0x2
0x0 R/W ACTZERO 1:0
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Register 52: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068
Register 53: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8
Register 54: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8
Register 55: PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128
The PWMnDBCTL register controls the dead-band generator, which produces the MnPWMn signals
based on the pwmA and pwmB signals. When disabled, the pwmA signal passes through to the
pwmA' signal and the pwmB signal passes through to the pwmB' signal. When dead-band control
is enabled, the pwmB signal is ignored, the pwmA' signal is generated by delaying the rising edge(s)
of the pwmAsignal by the value in the PWMnDBRISEregister (see page 1115), and the pwmB' signal
is generated by inverting the pwmA signal and delaying the falling edge(s) of the pwmA signal by
the value in the PWMnDBFALLregister (see page 1116). The Output Control block outputs the pwm0A'
signal on the MnPWM0 signal and the pwm0B' signal on the MnPWM1 signal. In a similar manner,
MnPWM2 and MnPWM3 are produced from the pwm1A' and pwm1B' signals, MnPWM4 and MnPWM5
are produced from the pwm2A' and pwm2B' signals, and MnPWM6 and MnPWM7 are produced from
the pwm3A' and pwm3B' signals.
If the Dead-Band Control mode is immediate (based on the DBCTLUPD field encoding in the
PWMnCTL register), the ENABLE bit value is used immediately. If the update mode is locally
synchronized, this value is used the next time the counter reaches zero. If the update mode is
globally synchronized, this value is used the next time the counter reaches zero after a synchronous
lost.
PWMn Dead-Band Control (PWMnDBCTL)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x068
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ENABLE reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Dead-Band Generator Enable
Description Value
The pwmA and pwmB signals pass through to the pwmA' and
pwmB' signals unmodified.
0
The dead-band generator modifies the pwmA signal by inserting
dead bands into the pwmA' and pwmB' signals.
1
0 R/W ENABLE 0
April 10, 2013 1114
Register 56: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
0x0AC
0x0EC
0x12C
The PWMnDBRISE register contains the number of clock cycles to delay the rising edge of the
pwmA signal when generating the pwmA' signal. If the dead-band generator is disabled through the
PWMnDBCTL register, this register is ignored. If the value of this register is larger than the width
of a High pulse on the pwmA signal, the rising-edge delay consumes the entire High time of the
signal, resulting in no High time on the output. Care must be taken to ensure that the pwmA High
time always exceeds the rising-edge delay.
If the Dead-Band Rising-Edge Delay mode is immediate (based on the DBRISEUPD field encoding
in the PWMnCTL register), the 12-bit RISEDELAY value is used immediately. If the update mode
is locally synchronized, this value is used the next time the counter reaches zero. If the update mode
is globally synchronized, this value is used the next time the counter reaches zero after a synchronous
lost.
PWMn Dead-Band Rising-Edge Delay (PWMnDBRISE)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x06C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RISEDELAY reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Dead-Band Rise Delay
The number of clock cycles to delay the rising edge of pwmA' after the
rising edge of pwmA.
0x000 R/W RISEDELAY 11:0
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Register 60: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
0x0B0
0x0F0
0x130
The PWMnDBFALL register contains the number of clock cycles to delay the rising edge of the
pwmB' signal from the falling edge of the pwmA signal. If the dead-band generator is disabled
through the PWMnDBCTL register, this register is ignored. If the value of this register is larger than
the width of a Low pulse on the pwmA signal, the falling-edge delay consumes the entire Low time
of the signal, resulting in no Low time on the output. Care must be taken to ensure that the pwmA
Low time always exceeds the falling-edge delay.
If the Dead-Band Falling-Edge-Delay mode is immediate (based on the DBFALLUP field encoding
in the PWMnCTL register), the 12-bit FALLDELAY value is used immediately. If the update mode
is locally synchronized, this value is used the next time the counter reaches zero. If the update mode
is globally synchronized, this value is used the next time the counter reaches zero after a synchronous
lost.
PWMn Dead-Band Falling-Edge-Delay (PWMnDBFALL)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x070
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FALLDELAY reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Dead-Band Fall Delay
The number of clock cycles to delay the falling edge of pwmB' from the
rising edge of pwmA.
0x000 R/W FALLDELAY 11:0
April 10, 2013 1116
Register 64: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074
Register 65: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4
Register 66: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4
This register specifies which fault pin inputs are used to generate a fault condition. Each bit in the
following register indicates whether the corresponding fault pin is included in the fault condition. All
enabled fault pins are ORed together to form the PWMnFLTSRC0 portion of the fault condition.
The PWMnFLTSRC0 fault condition is then ORed with the PWMnFLTSRC1 fault condition to
generate the final fault condition for the PWM generator.
If the FLTSRC bit in the PWMnCTL register (see page 1092) is clear, only the Fault0 signal affects
the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1
affect the fault condition generated.
PWMn Fault Source 0 (PWMnFLTSRC0)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x074
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
Fault3 Input
Description Value
The Fault3 signal is suppressed and cannot generate a fault
condition.
0
The Fault3 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
1
Note: The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
0 R/W FAULT3 3
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Fault2 Input
Description Value
condition.
0
1
0 R/W FAULT2 2
Fault1 Input
Description Value
condition.
0
1
0 R/W FAULT1 1
Fault0 Input
Description Value
condition.
0
1
0 R/W FAULT0 0
April 10, 2013 1118
Register 69: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8
Register 70: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8
This register specifies which digital comparator triggers from the ADC are used to generate a fault
condition. Each bit in the following register indicates whether the corresponding digital comparator
trigger is included in the fault condition. All enabled digital comparator triggers are ORed together
to form the PWMnFLTSRC1 portion of the fault condition. The PWMnFLTSRC1 fault condition is
then ORed with the PWMnFLTSRC0 fault condition to generate the final fault condition for the PWM
generator.
If the FLTSRC bit in the PWMnCTL register (see page 1092) is clear, only the PWMFault0 pin affects
the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1
affect the fault condition generated.
PWMn Fault Source 1 (PWMnFLTSRC1)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x078
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DCMP0 DCMP1 DCMP2 DCMP3 DCMP4 DCMP5 DCMP6 DCMP7 reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Digital Comparator 7
Description Value
The trigger from digital comparator 7 is suppressed and cannot
generate a fault condition.
0
The trigger fromdigital comparator 7 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
1
0 R/W DCMP7 7
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Description Value
0
comparators).
1
0 R/W DCMP6 6
Description Value
0
comparators).
1
0 R/W DCMP5 5
Description Value
0
comparators).
1
0 R/W DCMP4 4
Description Value
0
comparators).
1
0 R/W DCMP3 3
April 10, 2013 1120
Description Value
0
comparators).
1
0 R/W DCMP2 2
Description Value
0
comparators).
1
0 R/W DCMP1 1
Description Value
0
comparators).
1
0 R/W DCMP0 0
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Register 72: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C
Register 73: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC
Register 74: PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC
Register 75: PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C
If the MINFLTPER bit in the PWMnCTL register is set, this register specifies the 16-bit time-extension
value to be used in extending the fault condition. The value is loaded into a 16-bit down counter,
and the counter value is used to extend the fault condition. The fault condition is released in the
clock immediately after the counter value reaches 0. The fault condition is asynchronous to the
PWM clock; and the delay value is the product of the PWM clock period and the (MFP field value
+ 1) or (MFP field value + 2) depending on when the fault condition asserts with respect to the PWM
clock. The counter decrements at the PWM clock rate, without pause or condition.
PWMn Minimum Fault Period (PWMnMINFLTPER)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x07C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MFP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Minimum Fault Period
The number of PWMclocks by which a fault condition is extended when
the delay is enabled by PWMnCTL MINFLTPER.
0x0000 R/W MFP 15:0
April 10, 2013 1122
Register 76: PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800
This register defines the PWM fault pin logic sense.
PWMn Fault Pin Logic Sense (PWMnFLTSEN)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x800
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Fault3 Sense
Description Value
An error is indicated if the Fault3 signal is High. 0
An error is indicated if the Fault3 signal is Low. 1
0 R/W FAULT3 3
Fault2 Sense
Description Value
0 R/W FAULT2 2
Fault1 Sense
Description Value
0 R/W FAULT1 1
Fault0 Sense
Description Value
0 R/W FAULT0 0
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Register 80: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804
Along with the PWMnFLTSTAT1 register, this register provides status regarding the fault condition
inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT0 register
are read-only (RO) and provide the current state of the MnFAULTn inputs.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT0 register are
read / write 1 to clear (R/W1C) and provide a latched version of the MnFAULTn inputs. In this mode,
the register bits are cleared by writing a 1 to a set bit. The MnFAULTn inputs are recorded after their
sense is adjusted in the generator.
The contents of this register can only be written if the fault source extensions are enabled (the
FLTSRC bit in the PWMnCTL register is set).
PWMn Fault Status 0 (PWMnFLTSTAT0)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x804
Type -, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- - - - RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 RO reserved 31:4
Fault Input 3
If the PWMnCTL register LATCH bit is clear, this bit is ROand represents
the current state of the MnFAULT3 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is R/W1C and
represents a sticky version of the MnFAULT3 input signal after the logic
sense adjustment.
If FAULT3 is set, the input transitioned to the active state previously.
If FAULT3 is clear, the input has not transitioned to the active state
since the last time it was cleared.
The FAULT3 bit is cleared by writing it with the value 1.
0 - FAULT3 3
April 10, 2013 1124
Fault Input 2
adjustment.
sense adjustment.
0 - FAULT2 2
Fault Input 1
adjustment.
sense adjustment.
0 - FAULT1 1
Fault Input 0
the current state of the input signal after the logic sense adjustment.
represents a sticky version of the input signal after the logic sense
adjustment.
0 - FAULT0 0
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Along with the PWMnFLTSTAT0 register, this register provides status regarding the fault condition
inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT1 register
are read-only (RO) and provide the current state of the digital comparator triggers.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT1 register are
read / write 1 to clear (R/W1C) and provide a latched version of the digital comparator triggers. In
this mode, the register bits are cleared by writing a 1 to a set bit. The contents of this register can
only be written if the fault source extensions are enabled (the FLTSRC bit in the PWMnCTL register
is set).
PWMn Fault Status 1 (PWMnFLTSTAT1)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x808
Type -, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DCMP0 DCMP1 DCMP2 DCMP3 DCMP4 DCMP5 DCMP6 DCMP7 reserved
- - - - - - - - RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Digital Comparator 7 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 7 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
If DCMP7 is set, the trigger transitioned to the active state previously.
If DCMP7 is clear, the trigger has not transitioned to the active state
The DCMP7 bit is cleared by writing it with the value 1.
0 - DCMP7 7
April 10, 2013 1126
0 - DCMP6 6
0 - DCMP5 5
0 - DCMP4 4
0 - DCMP3 3
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0 - DCMP2 2
0 - DCMP1 1
0 - DCMP0 0
April 10, 2013 1128
Register 88: PWM Peripheral Properties (PWMPP), offset 0xFC0
The PWMPP register provides information regarding the properties of the PWM module.
PWM Peripheral Properties (PWMPP)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0xFC0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GCNT FCNT ESYNC EFAULT ONE reserved
0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 Reset
One-Shot Mode
Description Value
One-shot modes are not available. 0
One-shot modes are available. 1
0x0 RO ONE 10
Extended Fault
Description Value
Extended fault capabilities are not available. 0
Extended fault capabilities are available. 1
0x1 RO EFAULT 9
Extended Synchronization
Description Value
Extended synchronization is not available. 0
Extended synchronization is available. 1
0x1 RO ESYNC 8
Fault Inputs
Description Value
No fault inputs. 0x0
1 fault input. 0x1
2 fault input. 0x2
3 fault input. 0x3
4 fault input. 0x4
reserved 0x5 - 0xF
0x3 RO FCNT 7:4
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Generators
Description Value
No generators. 0x0
1 generator 0x1
2 generators 0x2
3 generators 0x3
4 generators 0x4
reserved 0x5 - 0xF
The number of PWMoutputs is 2 times the number of PWMgenerators.
0x4 RO GCNT 3:0
April 10, 2013 1130
19 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The TM4C123AH6PM microcontroller includes two quadrature encoder interface (QEI) modules.
Each QEI module interprets the code produced by a quadrature encoder wheel to integrate position
over time and determine direction of rotation. In addition, it can capture a running estimate of the
velocity of the encoder wheel.
The TM4C123AH6PM microcontroller includes two QEI modules providing control of two motors at
the same time with the following features:
Position integrator that tracks the encoder position
Programmable noise filter on the inputs
Velocity capture using built-in timer
The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
Interrupt generation on:
Index pulse
Velocity-timer expiration
Direction change
Quadrature error detection
19.1 Block Diagram
Figure 19-1 on page 1132 provides an internal block diagramof a TM4C123AH6PMQEI module. The
PhA and PhB inputs shown in this diagramare the internal signals that enter the Quadrature Encoder
after the external signals, PhAn and PhBn, have passed through inversion and swapping logic shown
in Figure 19-2 on page 1133. The QEI module has the option of inverting and/or swapping the incoming
signals.
Note: Any references in this chapter to PhA and PhB refer to the internal PhA and PhB inputs that
enter the Quadrature Encoder after the external signals, PhAn and PhBn, have passed
through inversion and swapping logic that is enabled through the QEI Control (QEICTL)
register.
1131 April 10, 2013
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Figure 19-1. QEI Block Diagram
Quadrature
Encoder
Velocity
Predivider
Interrupt Control
QEIINTEN
QEIRIS
QEIISC
Position Integrator
QEIMAXPOS
QEIPOS
Velocity Accumulator
QEICOUNT
QEISPEED
Velocity Timer
QEILOAD
QEITIME
PhA
PhB
IDX
clk
dir
Interrupt
Control & Status
QEICTL
QEISTAT
Figure 19-2 on page 1133 shows the logic that is provided to allow the PhAn and PhBn signals to be
inverted and/or swapped.
April 10, 2013 1132
Quadrature Encoder Interface (QEI)
Figure 19-2. QEI Input Signal Logic
Quadrature
Encoder
PhAn
PhBn
QEICTL.SWAP
0
1
0
1
PhA
PhB
QEICTL.INVA
QEICTL.INVB
QEICTL.SWAP
clk
dir
The following table lists the external signals of the QEI module and describes the function of each.
The QEI signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 612) should be set to choose the QEI function. The number in
(GPIOPCTL) register (page 629) to assign the QEI signal to the specified GPIO port pin. For more
Table 19-1. QEI Signals (64LQFP)
a
Assignment
Pin Number Pin Name
QEI module 0 index. TTL I PF4 (6)
PD3 (6)
5
64
IDX0
QEI module 1 index. TTL I PC4 (6)
PG5 (6)
16
32
IDX1
QEI module 0 phase A. TTL I PF0 (6)
PD6 (6)
28
53
PhA0
QEI module 1 phase A. TTL I PC5 (6)
PG3 (6)
PG0 (6)
15
34
37
PhA1
QEI module 0 phase B. TTL I PD7 (6)
PF1 (6)
10
29
PhB0
QEI module 1 phase B. TTL I PC6 (6)
PG4 (6)
PG1 (6)
14
33
36
PhB1
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The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate
position over time and determine direction of rotation. In addition, it can capture a running estimate
of the velocity of the encoder wheel.
The position integrator and velocity capture can be independently enabled, though the position
integrator must be enabled before the velocity capture can be enabled. The two phase signals,
PhAn and PhBn, can be swapped before being interpreted by the QEI module to change the meaning
of forward and backward and to correct for miswiring of the system. Alternatively, the phase signals
can be interpreted as a clock and direction signal as output by some encoders.
The QEI module input signals have a digital noise filter on them that can be enabled to prevent
spurious operation. The noise filter requires that the inputs be stable for a specified number of
consecutive clock cycles before updating the edge detector. The filter is enabled by the FILTEN bit
in the QEI Control (QEICTL) register. The frequency of the input update is programmable using
the FILTCNT bit field in the QEICTL register.
The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction
mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of
phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode,
the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction
of rotation. This mode is determined by the SIGMODE bit of the QEICTL register (see page 1138).
When the QEI module is set to use the quadrature phase mode (SIGMODE bit is clear), the capture
mode for the position integrator can be set to update the position counter on every edge of the PhA
signal or to update on every edge of both PhA and PhB. Updating the position counter on every PhA
and PhB edge provides more positional resolution at the cost of less range in the positional counter.
When edges on PhA lead edges on PhB, the position counter is incremented. When edges on PhB
lead edges on PhA, the position counter is decremented. When a rising and falling edge pair is seen
on one of the phases without any edges on the other, the direction of rotation has changed.
The positional counter is automatically reset on one of two conditions: sensing the index pulse or
reaching the maximum position value. The reset mode is determined by the RESMODE bit of the
QEICTL register.
When RESMODE is set, the positional counter is reset when the index pulse is sensed. This mode
limits the positional counter to the values [0:N-1], where N is the number of phase edges in a full
revolution of the encoder wheel. The QEI Maximum Position (QEIMAXPOS) register must be
programmed with N-1 so that the reverse direction from position 0 can move the position counter
to N-1. In this mode, the position register contains the absolute position of the encoder relative to
the index (or home) position once an index pulse has been seen.
When RESMODE is clear, the positional counter is constrained to the range [0:M], where M is the
programmable maximum value. The index pulse is ignored by the positional counter in this mode.
Velocity capture uses a configurable timer and a count register. The timer counts the number of
phase edges (using the same configuration as for the position integrator) in a given time period.
The edge count from the previous time period is available to the controller via the QEI Velocity
(QEISPEED) register, while the edge count for the current time period is being accumulated in the
QEI Velocity Counter (QEICOUNT) register. As soon as the current time period is complete, the
total number of edges counted in that time period is made available in the QEISPEED register
(overwriting the previous value), the QEICOUNT register is cleared, and counting commences on
a new time period. The number of edges counted in a given time period is directly proportional to
the velocity of the encoder.
April 10, 2013 1134
Figure 19-3 on page 1135 shows howthe TM4C123AH6PMquadrature encoder converts the phase
input signals into clock pulses, the direction signal, and how the velocity predivider operates (in
Divide by 4 mode).
Figure 19-3. Quadrature Encoder and Velocity Predivider Operation
PhB
clk
clkdiv
dir
-1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 pos
PhA
+1 +1 +1 +1 +1 +1 +1 +1 rel
The period of the timer is configurable by specifying the load value for the timer in the QEI Timer
Load (QEILOAD) register. When the timer reaches zero, an interrupt can be triggered, and the
hardware reloads the timer with the QEILOADvalue and continues to count down. At lower encoder
speeds, a longer timer period is required to be able to capture enough edges to have a meaningful
result. At higher encoder speeds, both a shorter timer period and/or the velocity predivider can be
used.
The following equation converts the velocity counter value into an rpm value:
rpm = (clock * (2 ^ VELDIV) * SPEED * 60) (LOAD * ppr * edges)
where:
clock is the controller clock rate
ppr is the number of pulses per revolution of the physical encoder
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CAPMODE clear and
4 for CAPMODE set)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder
is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of
1 (VELDIV is clear) and clocking on both PhA and PhB edges, this results in 81,920 pulses per
second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (of a second), it would count 20,480 pulses per update. Using the above equation:
rpm = (10000 * 1 * 20480 * 60) (2500 * 2048 * 4) = 600 rpm
Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second,
or 102,400 every of a second. Again, the above equation gives:
rpm = (10000 * 1 * 102400 * 60) (2500 * 2048 * 4) = 3000 rpm
Care must be taken when evaluating this equation because intermediate values may exceed the
capacity of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500;
both could be predivided by 100 (at compile time if they are constants) and therefore be 100 and
25. In fact, if they were compile-time constants, they could also be reduced to a simple multiply by
4, cancelled by the 4 for the edge-count factor.
Important: Reducing constant factors at compile time is the best way to control the intermediate
values of this equation and reduce the processing requirement of computing this
equation.
1135 April 10, 2013
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The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a
simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses
per revolution, the load value can be a power of 2. For other encoders, a load value must be selected
such that the product is very close to a power of 2. For example, a 100 pulse-per-revolution encoder
could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 2
14
. In this
case a shift by 15 would be an adequate approximation of the divide in most cases. If absolute
accuracy were required, the microcontrollers divide instruction could be used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.
The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:
1. Enable the QEI clock using the RCGCQEI register in the SystemControl module (see page 335).
Control module (see page 322).
GPIOAFSEL register. To determine which GPIOs to configure, see Table 21-4 on page 1170.
4. Configure the PMCn fields in the GPIOPCTL register to assign the QEI signals to the appropriate
5. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. A 1000-line encoder with four edges per line, results in
4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) as the count
is zero-based.
Write the QEICTL register with the value of 0x0000.0018.
Write the QEIMAXPOS register with the value of 0x0000.0F9F.
6. Enable the quadrature encoder by setting bit 0 of the QEICTL register.
Note: Once the QEI module has been enabled by setting the ENABLE bit in the QEICTL
register, it cannot be disabled. The only way to clear the ENABLE bit is to reset the
module using the Quadrature Encoder Interface Software Reset (SRQEI) register.
7. Delay until the encoder position is required.
8. Read the encoder position by reading the QEI Position (QEIPOS) register value.
19.5 Register Map
Table 19-2 on page 1137 lists the QEI registers. The offset listed is a hexadecimal increment to the
registers address, relative to the modules base address:
QEI0: 0x4002.C000
QEI1: 0x4002.D000
April 10, 2013 1136
Note that the QEI module clock must be enabled before the registers can be programmed (see
page 335). There must be a delay of 3 system clocks after the QEI module clock is enabled before
any QEI module registers are accessed.
Table 19-2. QEI Register Map
See
page
1138 QEI Control 0x0000.0000 R/W QEICTL 0x000
1141 QEI Status 0x0000.0000 RO QEISTAT 0x004
1142 QEI Position 0x0000.0000 R/W QEIPOS 0x008
1143 QEI Maximum Position 0x0000.0000 R/W QEIMAXPOS 0x00C
1144 QEI Timer Load 0x0000.0000 R/W QEILOAD 0x010
1145 QEI Timer 0x0000.0000 RO QEITIME 0x014
1146 QEI Velocity Counter 0x0000.0000 RO QEICOUNT 0x018
1147 QEI Velocity 0x0000.0000 RO QEISPEED 0x01C
1148 QEI Interrupt Enable 0x0000.0000 R/W QEIINTEN 0x020
1150 QEI Raw Interrupt Status 0x0000.0000 RO QEIRIS 0x024
1152 QEI Interrupt Status and Clear 0x0000.0000 R/W1C QEIISC 0x028
The remainder of this section lists and describes the QEI registers, in numerical order by address
offset.
1137 April 10, 2013
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Register 1: QEI Control (QEICTL), offset 0x000
This register contains the configuration of the QEI module. Separate enables are provided for the
quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in
order to capture the velocity, but the velocity does not need to be captured in applications that do
not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset
mode, and velocity predivider are all set via this register.
QEI Control (QEICTL)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FILTCNT reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ENABLE SWAP SIGMODE CAPMODE RESMODE VELEN VELDIV INVA INVB INVI STALLEN FILTEN reserved
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Input Filter Prescale Count
This field controls the frequency of the input update.
When this field is clear, the input is sampled after 2 systemclocks. When
this field ix 0x1, the input is sampled after 3 system clocks. Similarly,
when this field is 0xF, the input is sampled after 17 clocks.
0x0 R/W FILTCNT 19:16
Enable Input Filter
Description Value
The QEI inputs are not filtered. 0
Enables the digital noise filter on the QEI input signals. Inputs
must be stable for 3 consecutive clock edges before the edge
detector is updated.
1
0 R/W FILTEN 13
Stall QEI
Description Value
The QEI module does not stall when the microcontroller is
stopped by a debugger.
0
The QEI module stalls when the microcontroller is stopped by
a debugger.
1
0 R/W STALLEN 12
April 10, 2013 1138
Invert Index Pulse
Description Value
No effect. 0
Inverts the IDX input. 1
0 R/W INVI 11
Invert PhB
Description Value
No effect. 0
Inverts the PhBn input. 1
0 R/W INVB 10
Invert PhA
Description Value
No effect. 0
Inverts the PhAn input. 1
0 R/W INVA 9
Predivide Velocity
This field defines the predivider of the input quadrature pulses before
being applied to the QEICOUNT accumulator.
Predivider Value
1 0x0
2 0x1
4 0x2
8 0x3
16 0x4
32 0x5
64 0x6
128 0x7
0x0 R/W VELDIV 8:6
Capture Velocity
Description Value
No effect. 0
Enables capture of the velocity of the quadrature encoder. 1
0 R/W VELEN 5
Reset Mode
Description Value
The position counter is reset when it reaches the maximum as
defined by the MAXPOS field in the QEIMAXPOS register.
0
The position counter is reset when the index pulse is captured. 1
0 R/W RESMODE 4
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Capture Mode
Note: When SIGMODE=1, the CAPMODE setting is not applicable and
is reserved.
Description Value
Only the PhA edges are counted. 0
The PhA and PhB edges are counted, providing twice the
positional resolution but half the range.
1
0 R/W CAPMODE 3
Signal Mode
Description Value
The internal PhA and PhB signals operate as quadrature phase
signals.
0
The internal PhA input operates as the clock (CLK) signal and
the internal PhB input operates as the direction (DIR) signal.
1
0 R/W SIGMODE 2
Swap Signals
Note if the INVA or INVB bit are set, the inversion of the signals occur
prior to the swap.
Description Value
No effect. 0
Swaps the PhAn and PhBn signals. 1
0 R/W SWAP 1
Enable QEI
Description Value
No effect. 0
Enables the quadrature encoder module. 1
Note: Once the QEI module has been enabled by setting the
ENABLE bit, it cannot be disabled. The only way to clear the
ENABLE bit is to reset the module using the Quadrature
Encoder Interface Software Reset (SRQEI) register.
0 R/W ENABLE 0
April 10, 2013 1140
Register 2: QEI Status (QEISTAT), offset 0x004
This register provides status about the operation of the QEI module.
QEI Status (QEISTAT)
Offset 0x004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ERROR DIRECTION reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Direction of Rotation
Indicates the direction the encoder is rotating.
Description Value
The encoder is rotating forward. 0
The encoder is rotating in reverse. 1
0 RO DIRECTION 1
Error Detected
Description Value
No error. 0
An error was detected in the gray code sequence (that is, both
signals changing at the same time).
1
0 RO ERROR 0
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Register 3: QEI Position (QEIPOS), offset 0x008
This register contains the current value of the position integrator. The value is updated by the status
of the QEI phase inputs and can be set to a specific value by writing to it.
QEI Position (QEIPOS)
Offset 0x008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
POSITION
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
POSITION
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Current Position Integrator Value
The current value of the position integrator.
0x0000.0000 R/W POSITION 31:0
April 10, 2013 1142
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C
This register contains the maximum value of the position integrator. When moving forward, the
position register resets to zero when it increments past this value. When moving in reverse, the
position register resets to this value when it decrements from zero.
QEI Maximum Position (QEIMAXPOS)
Offset 0x00C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MAXPOS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MAXPOS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Maximum Position Integrator Value
The maximum value of the position integrator.
0x0000.0000 R/W MAXPOS 31:0
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Register 5: QEI Timer Load (QEILOAD), offset 0x010
This register contains the load value for the velocity timer. Because this value is loaded into the
timer on the clock cycle after the timer is zero, this value should be one less than the number of
clocks in the desired period. So, for example, to have 2000 decimal clocks per timer period, this
register should contain 1999 decimal.
QEI Timer Load (QEILOAD)
Offset 0x010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LOAD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LOAD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Velocity Timer Load Value
The load value for the velocity timer.
0x0000.0000 R/W LOAD 31:0
April 10, 2013 1144
Register 6: QEI Timer (QEITIME), offset 0x014
This register contains the current value of the velocity timer. This counter does not increment when
the VELEN bit in the QEICTL register is clear.
QEI Timer (QEITIME)
Offset 0x014
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TIME
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TIME
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Velocity Timer Current Value
The current value of the velocity timer.
0x0000.0000 RO TIME 31:0
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Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018
This register contains the running count of velocity pulses for the current time period. Because this
count is a running total, the time period to which it applies cannot be known with precision (that is,
a read of this register does not necessarily correspond to the time returned by the QEITIME register
because there is a small window of time between the two reads, during which either value may have
changed). The QEISPEED register should be used to determine the actual encoder velocity; this
register is provided for information purposes only. This counter does not increment when the VELEN
bit in the QEICTL register is clear.
QEI Velocity Counter (QEICOUNT)
Offset 0x018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
COUNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
COUNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Velocity Pulse Count
The running total of encoder pulses during this velocity timer period.
0x0000.0000 RO COUNT 31:0
April 10, 2013 1146
Register 8: QEI Velocity (QEISPEED), offset 0x01C
This register contains the most recently measured velocity of the quadrature encoder. This value
corresponds to the number of velocity pulses counted in the previous velocity timer period. This
register does not update when the VELEN bit in the QEICTL register is clear.
QEI Velocity (QEISPEED)
Offset 0x01C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPEED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SPEED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Velocity
The measured speed of the quadrature encoder in pulses per period.
0x0000.0000 RO SPEED 31:0
1147 April 10, 2013
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Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module interrupts. An interrupt is asserted to the
interrupt controller if the corresponding bit in this register is set.
QEI Interrupt Enable (QEIINTEN)
Offset 0x020
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTINDEX INTTIMER INTDIR INTERROR reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Phase Error Interrupt Enable
Description Value
INTERROR bit in the QEIRIS register is set.
1
The INTERROR interrupt is suppressed and not sent to the
0
0 R/W INTERROR 3
Direction Change Interrupt Enable
Description Value
An interrupt is sent to the interrupt controller when the INTDIR
bit in the QEIRIS register is set.
1
The INTDIR interrupt is suppressed and not sent to the interrupt
controller.
0
0 R/W INTDIR 2
Timer Expires Interrupt Enable
Description Value
INTTIMER bit in the QEIRIS register is set.
1
The INTTIMER interrupt is suppressed and not sent to the
0
0 R/W INTTIMER 1
April 10, 2013 1148
Index Pulse Detected Interrupt Enable
Description Value
INTINDEX bit in the QEIRIS register is set.
1
The INTINDEX interrupt is suppressed and not sent to the
0
0 R/W INTINDEX 0
1149 April 10, 2013
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Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (configured through the QEIINTEN register).
If a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
Offset 0x024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Phase Error Detected
Description Value
A phase error has been detected. 1
This bit is cleared by writing a 1 to the INTERROR bit in the QEIISC
register.
0 RO INTERROR 3
Direction Change Detected
Description Value
The rotation direction has changed 1
This bit is cleared by writing a 1 to the INTDIR bit in the QEIISCregister.
0 RO INTDIR 2
Velocity Timer Expired
Description Value
The velocity timer has expired. 1
This bit is cleared by writing a 1 to the INTTIMER bit in the QEIISC
register.
0 RO INTTIMER 1
April 10, 2013 1150
Index Pulse Asserted
Description Value
The index pulse has occurred. 1
This bit is cleared by writing a 1 to the INTINDEX bit in the QEIISC
register.
0 RO INTINDEX 0
1151 April 10, 2013
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Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. If a bit
is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the
event in question has not occurred or is not enabled to generate an interrupt. This register is R/W1C;
writing a 1 to a bit position clears the bit and the corresponding interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
Offset 0x028
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Phase Error Interrupt
Description Value
The INTERROR bits in the QEIRIS register and the QEIINTEN
1
INTERROR bit in the QEIRIS register.
0 R/W1C INTERROR 3
Direction Change Interrupt
Description Value
The INTDIR bits in the QEIRIS register and the QEIINTEN
1
This bit is cleared by writing a 1. Clearing this bit also clears the INTDIR
bit in the QEIRIS register.
0 R/W1C INTDIR 2
Velocity Timer Expired Interrupt
Description Value
The INTTIMER bits in the QEIRIS register and the QEIINTEN
1
INTTIMER bit in the QEIRIS register.
0 R/W1C INTTIMER 1
April 10, 2013 1152
Index Pulse Interrupt
Description Value
The INTINDEX bits in the QEIRIS register and the QEIINTEN
1
INTINDEX bit in the QEIRIS register.
0 R/W1C INTINDEX 0
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20 Pin Diagram
The TM4C123AH6PM microcontroller pin diagram is shown below.
Each GPIO signal is identified by its GPIO port unless it defaults to an alternate function on reset.
In this case, the GPIO port name is followed by the default alternate function. To see a complete
list of possible functions for each pin, see Table 21-5 on page 1176.
Figure 20-1. 64-Pin LQFP Package Pin Diagram
April 10, 2013 1154
Pin Diagram
21 Signal Tables
The following tables list the signals available for each pin. Signals are configured as GPIOs on reset,
except for those noted below. Use the GPIOAMSEL register (see page 628) to select analog mode.
For a GPIO pin to be used for an alternate digital function, the corresponding bit in the GPIOAFSEL
register (see page 612) must be set. Further pin muxing options are provided through the PMCx bit
field in the GPIOPCTL register (see page 629), which selects one of several available peripheral
functions for that GPIO.
Important: All GPIO pins are configured as GPIOs by default with the exception of the pins shown
in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their
default state.
Table 21-1. GPIO Pins With Default Alternate Functions
GPIOPCTL PMCx Bit Field GPIOAFSEL Bit Default State GPIO Pin
0x1 0 UART0 PA[1:0]
0x1 0 SSI0 PA[5:2]
0x1 0 I
2
C0 PB[3:2]
0x3 1 JTAG/SWD PC[3:0]
Table 21-2 on page 1156 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Each possible alternate analog and digital function is listed for each pin.
Table 21-3 on page 1163 lists the signals in alphabetical order by signal name. If it is possible for a
signal to be on multiple pins, each possible pin assignment is listed. The "Pin Mux" column indicates
the GPIO and the encoding needed in the PMCx bit field in the GPIOPCTL register.
Table 21-4 on page 1170 groups the signals by functionality, except for GPIOs. If it is possible for a
signal to be on multiple pins, each possible pin assignment is listed.
Table 21-5 on page 1176 lists the GPIOpins and their analog and digital alternate functions. The AINx
analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry.
These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable
(GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select
(GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to their
circuitry (C0-, C0+, C1-, C1+). These signals are configured by clearing the DEN bit in the GPIO
Digital Enable (GPIODEN) register. The digital signals are enabled by setting the appropriate bit
in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring
the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric enoding shown in
the table below. Table entries that are shaded gray are the default values for the corresponding
GPIO pin.
Table 21-6 on page 1178 lists the signals based on number of possible pin assignments. This table
can be used to plan howto configure the pins for a particular functionality. Application Note AN01274
Configuring Tiva C Series Microcontrollers with Pin Multiplexing provides an overview of the pin
muxing implementation, an explanation of how a system designer defines a pin configuration, and
examples of the pin configuration process.
Note: All digital inputs are Schmitt triggered.
1155 April 10, 2013
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21.1 Signals by Pin Number
Table 21-2. Signals by Pin Number
a
Pin Type Pin Name Pin Number
GPIO port B bit 6. TTL I/O PB6
1
I
2
C module 5 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
OD I/O I2C5SCL
Motion Control Module 0 PWM 0. This signal is controlled by
Module 0 PWM Generator 0.
TTL O M0PWM0
SSI module 2 receive. TTL I SSI2Rx
16/32-Bit Timer 0 Capture/Compare/PWM 0. TTL I/O T0CCP0
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 22-5 on page 1185, regardless of system
implementation.
Power - VDDA
2
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
Power - GNDA
3
4
I
2
C module 5 data. OD I/O I2C5SDA
TTL O M0PWM1
SSI module 2 transmit. TTL O SSI2Tx
GPIO port F bit 4. TTL I/O PF4
5
QEI module 0 index. TTL I IDX0
Motion Control Module 0 PWM Fault 2. TTL I M0FAULT2
GPIO port E bit 3. TTL I/O PE3
6
Analog-to-digital converter input 0. Analog I AIN0
7
8 Analog-to-digital converter input 2. Analog I AIN2
UART module 7 transmit. TTL O U7Tx
9 Analog-to-digital converter input 3. Analog I AIN3
UART module 7 receive. TTL I U7Rx
April 10, 2013 1156
Signal Tables
Table 21-2. Signals by Pin Number (continued)
a
GPIO port D bit 7. TTL I/O PD7
10
Non-maskable interrupt. TTL I NMI
QEI module 0 phase B. TTL I PhB0
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1. TTL I/O WT5CCP1
Positive supply for I/O and some logic. Power - VDD 11
Ground reference for logic and I/O pins. Power - GND 12
GPIO port C bit 7. TTL I/O PC7
13
Analog comparator 0 negative input. Analog I C0-
14
Analog comparator 0 positive input. Analog I C0+
15
Analog comparator 1 positive input. Analog I C1+
TTL O M0PWM7
QEI module 1 phase A. TTL I PhA1
UART module 1 Clear To Send modem flow control input signal. TTL I U1CTS
16
Analog comparator 1 negative input. Analog I C1-
TTL O M0PWM6
UART module 1 Request to Send modem flow control output line. TTL O U1RTS
GPIO port A bit 0. TTL I/O PA0
17 CAN module 1 receive. TTL I CAN1Rx
18 CAN module 1 transmit. TTL O CAN1Tx
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a
19
SSI module 0 clock TTL I/O SSI0Clk
20
SSI module 0 frame signal TTL I/O SSI0Fss
21
SSI module 0 receive TTL I SSI0Rx
22
SSI module 0 transmit TTL O SSI0Tx
23
I
2
OD I/O I2C1SCL
TTL O M1PWM2
24
I
2
TTL O M1PWM3
Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.2 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to each other and an external capacitor as
specified in Table 22-12 on page 1197 .
Power - VDDC
25
28
Analog comparator 0 output. TTL O C0o
CAN module 0 receive. TTL I CAN0Rx
TTL O M1PWM4
Non-maskable interrupt. TTL I NMI
UART module 1 Request to Send modem flow control output line. TTL O U1RTS
29
Analog comparator 1 output. TTL O C1o
TTL O M1PWM5
Trace data 1. TTL O TRD1
UART module 1 Clear To Send modem flow control input signal. TTL I U1CTS
April 10, 2013 1158
Signal Tables
a
30
TTL O M1PWM6
SSI module 1 clock. TTL I/O SSI1Clk
Trace data 0. TTL O TRD0
31
CAN module 0 transmit. TTL O CAN0Tx
TTL O M1PWM7
SSI module 1 frame signal. TTL I/O SSI1Fss
Trace clock. TTL O TRCLK
GPIO port G bit 5. TTL I/O PG5
32
I
2
TTL O M0PWM5
TTL O M1PWM3
33
I
2
OD I/O I2C1SCL
TTL O M0PWM4
TTL O M1PWM2
34
I
2
TTL O M1PWM1
1159 April 10, 2013
Tiva
a
35
I
2
OD I/O I2C4SCL
TTL O M1PWM0
36
I
2
37
I
2
OD I/O I2C3SCL
System reset input. TTL I RST 38
Main oscillator crystal input or an external clock reference input. Analog I OSC0 40
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
Analog O OSC1
41
GPIO port D bit 4. This pin is not 5-V tolerant. TTL I/O PD4
43 UART module 6 receive. TTL I U6Rx
GPIO port D bit 5. This pin is not 5-V tolerant. TTL I/O PD5
44 UART module 6 transmit. TTL O U6Tx
GPIO port B bit 0. This pin is not 5-V tolerant. TTL I/O PB0
45 16/32-Bit Timer 2 Capture/Compare/PWM 0. TTL I/O T2CCP0
GPIO port B bit 1. This pin is not 5-V tolerant. TTL I/O PB1
47
I
2
OD I/O I2C0SCL
48 I
2
April 10, 2013 1160
Signal Tables
a
49
JTAG TDO and SWO. TTL O SWO
JTAG TDO and SWO. TTL O TDO
JTAG TDI. TTL I TDI
51
JTAG TMS and SWDIO. TTL I/O SWDIO
JTAG TMS and SWDIO. TTL I TMS
52
JTAG/SWD CLK. TTL I SWCLK
JTAG/SWD CLK. TTL I TCK
53
Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.2 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to each other and an external capacitor as
specified in Table 22-12 on page 1197 .
Power - VDDC
56
57
TTL O M0PWM3
58
TTL O M0PWM2
1161 April 10, 2013
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a
59
I
2
OD I/O I2C2SCL
TTL O M0PWM4
TTL O M1PWM2
60
I
2
TTL O M0PWM5
TTL O M1PWM3
61
I
2
OD I/O I2C3SCL
TTL O M0PWM6
TTL O M1PWM0
62
I
2
TTL O M0PWM7
TTL O M1PWM1
April 10, 2013 1162
Signal Tables
a
63
64
21.2 Signals by Signal Name
Table 21-3. Signals by Signal Name
a
Assignment
Pin Number Pin Name
CAN module 0 receive. TTL I PF0 (3)
PB4 (8)
PE4 (8)
28
58
59
CAN0Rx
CAN module 0 transmit. TTL O PF3 (3)
PB5 (8)
PE5 (8)
31
57
60
CAN0Tx
1163 April 10, 2013
Tiva
Table 21-3. Signals by Signal Name (continued)
a
Assignment
Pin Number Pin Name
CAN module 1 receive. TTL I PA0 (8) 17 CAN1Rx
CAN module 1 transmit. TTL O PA1 (8) 18 CAN1Tx
Ground reference for logic and I/O pins. Power - fixed 12
27
39
55
GND
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
fromGNDto minimize the electrical noise contained
on VDD from affecting the analog functions.
Power - fixed 3 GNDA
I
2
I
2
I
2
OD I/O PA6 (3)
PG4 (3)
23
33
I2C1SCL
I
2
C module 1 data. OD I/O PA7 (3)
PG5 (3)
24
32
I2C1SDA
I
2
OD I/O PE4 (3) 59 I2C2SCL
I
2
C module 2 data. OD I/O PE5 (3) 60 I2C2SDA
I
2
OD I/O PG0 (3)
PD0 (3)
37
61
I2C3SCL
I
2
C module 3 data. OD I/O PG1 (3)
PD1 (3)
36
62
I2C3SDA
I
2
OD I/O PG2 (3) 35 I2C4SCL
I
2
C module 4 data. OD I/O PG3 (3) 34 I2C4SDA
I
2
I
2
QEI module 0 index. TTL I PF4 (6)
PD3 (6)
5
64
IDX0
QEI module 1 index. TTL I PC4 (6)
PG5 (6)
16
32
IDX1
PD6 (4)
PD2 (4)
30
53
63
M0FAULT0
Motion Control Module 0 PWM Fault 1. TTL I PD7 (4)
PF3 (4)
PG2 (4)
10
31
35
M0FAULT1
PG3 (4)
5
34
M0FAULT2
April 10, 2013 1164
Signal Tables
a
Assignment
Pin Number Pin Name
TTL O PG4 (4)
PE4 (4)
33
59
M0PWM4
TTL O PG5 (4)
PE5 (4)
32
60
M0PWM5
TTL O PC4 (4)
PD0 (4)
16
61
M0PWM6
TTL O PC5 (4)
PD1 (4)
15
62
M0PWM7
Motion Control Module 1 PWM Fault 0. TTL I PF4 (5) 5 M1FAULT0
TTL O PG2 (5)
PD0 (5)
35
61
M1PWM0
TTL O PG3 (5)
PD1 (5)
34
62
M1PWM1
TTL O PA6 (5)
PG4 (5)
PE4 (5)
23
33
59
M1PWM2
TTL O PA7 (5)
PG5 (5)
PE5 (5)
24
32
60
M1PWM3
Non-maskable interrupt. TTL I PD7 (8)
PF0 (8)
10
28
NMI
reference input.
Analog I fixed 40 OSC0
Analog O fixed 41 OSC1
GPIO port A bit 0. TTL I/O - 17 PA0
1165 April 10, 2013
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a
Assignment
Pin Number Pin Name
GPIO port B bit 0. This pin is not 5-V tolerant. TTL I/O - 45 PB0
GPIO port B bit 1. This pin is not 5-V tolerant. TTL I/O - 46 PB1
GPIO port B bit 2. TTL I/O - 47 PB2
GPIO port C bit 0. TTL I/O - 52 PC0
GPIO port D bit 0. TTL I/O - 61 PD0
GPIO port D bit 4. This pin is not 5-V tolerant. TTL I/O - 43 PD4
GPIO port D bit 5. This pin is not 5-V tolerant. TTL I/O - 44 PD5
GPIO port E bit 0. TTL I/O - 9 PE0
GPIO port F bit 0. TTL I/O - 28 PF0
GPIO port G bit 0. TTL I/O - 37 PG0
April 10, 2013 1166
Signal Tables
a
Assignment
Pin Number Pin Name
QEI module 0 phase A. TTL I PF0 (6)
PD6 (6)
28
53
PhA0
QEI module 1 phase A. TTL I PC5 (6)
PG3 (6)
PG0 (6)
15
34
37
PhA1
QEI module 0 phase B. TTL I PD7 (6)
PF1 (6)
10
29
PhB0
QEI module 1 phase B. TTL I PC6 (6)
PG4 (6)
PG1 (6)
14
33
36
PhB1
System reset input. TTL I fixed 38 RST
SSI module 0 clock TTL I/O PA2 (2) 19 SSI0Clk
SSI module 0 frame signal TTL I/O PA3 (2) 20 SSI0Fss
SSI module 0 receive TTL I PA4 (2) 21 SSI0Rx
SSI module 0 transmit TTL O PA5 (2) 22 SSI0Tx
SSI module 1 clock. TTL I/O PF2 (2)
PD0 (2)
30
61
SSI1Clk
SSI module 1 frame signal. TTL I/O PF3 (2)
PD1 (2)
31
62
SSI1Fss
SSI module 1 receive. TTL I PF0 (2)
PD2 (2)
28
63
SSI1Rx
SSI module 1 transmit. TTL O PF1 (2)
PD3 (2)
29
64
SSI1Tx
SSI module 2 clock. TTL I/O PB4 (2) 58 SSI2Clk
SSI module 2 frame signal. TTL I/O PB5 (2) 57 SSI2Fss
SSI module 2 receive. TTL I PB6 (2) 1 SSI2Rx
SSI module 2 transmit. TTL O PB7 (2) 4 SSI2Tx
SSI module 3 clock. TTL I/O PD0 (1) 61 SSI3Clk
SSI module 3 frame signal. TTL I/O PD1 (1) 62 SSI3Fss
SSI module 3 receive. TTL I PD2 (1) 63 SSI3Rx
SSI module 3 transmit. TTL O PD3 (1) 64 SSI3Tx
JTAG/SWD CLK. TTL I PC0 (1) 52 SWCLK
JTAG TMS and SWDIO. TTL I/O PC1 (1) 51 SWDIO
JTAG TDO and SWO. TTL O PC3 (1) 49 SWO
PF0 (7)
1
28
T0CCP0
PF1 (7)
4
29
T0CCP1
PB4 (7)
30
58
T1CCP0
1167 April 10, 2013
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a
Assignment
Pin Number Pin Name
PB5 (7)
31
57
T1CCP1
PB0 (7)
5
45
T2CCP0
PC0 (7)
37
52
T4CCP0
PC1 (7)
36
51
T4CCP1
PC2 (7)
35
50
T5CCP0
PC3 (7)
34
49
T5CCP1
JTAG/SWD CLK. TTL I PC0 (1) 52 TCK
JTAG TDI. TTL I PC2 (1) 50 TDI
JTAG TDO and SWO. TTL O PC3 (1) 49 TDO
JTAG TMS and SWDIO. TTL I PC1 (1) 51 TMS
Trace clock. TTL O PF3 (14) 31 TRCLK
Trace data 0. TTL O PF2 (14) 30 TRD0
Trace data 1. TTL O PF1 (14) 29 TRD1
UART module 0 receive. TTL I PA0 (1) 17 U0Rx
UART module 0 transmit. TTL O PA1 (1) 18 U0Tx
input signal.
TTL I PC5 (8)
PF1 (1)
15
29
U1CTS
TTL O PC4 (8)
PF0 (1)
16
28
U1RTS
UART module 1 receive. TTL I PC4 (2)
PB0 (1)
16
45
U1Rx
UART module 1 transmit. TTL O PC5 (2)
PB1 (1)
15
46
U1Tx
UART module 2 receive. TTL I PG4 (1)
PD6 (1)
33
53
U2Rx
UART module 2 transmit. TTL O PD7 (1)
PG5 (1)
10
32
U2Tx
UART module 6 receive. TTL I PD4 (1) 43 U6Rx
UART module 6 transmit. TTL O PD5 (1) 44 U6Tx
April 10, 2013 1168
Signal Tables
a
Assignment
Pin Number Pin Name
Positive supply for I/O and some logic. Power - fixed 11
26
42
54
VDD
The positive supply for the analog circuits (ADC,
fromVDDto minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 22-5 on page 1185, regardless
of system implementation.
Power - fixed 2 VDDA
Positive supply for most of the logic function,
including the processor core and most peripherals.
The voltage on this pin is 1.2 V and is supplied by
the on-chip LDO. The VDDC pins should only be
connected to each other and an external capacitor
as specified in Table 22-12 on page 1197 .
Power - fixed 25
56
VDDC
PG4 (7)
16
33
WT0CCP0
PG5 (7)
15
32
WT0CCP1
1169 April 10, 2013
Tiva
21.3 Signals by Function, Except for GPIO
Table 21-4. Signals by Function, Except for GPIO
a
Pin Type Pin Number Pin Name Function
Analog-to-digital converter input 0. Analog I 6 AIN0
ADC
Analog comparator 0 positive input. Analog I 14 C0+
Analog Comparators
Analog comparator 0 negative input. Analog I 13 C0-
Analog comparator 0 output. TTL O 28 C0o
Analog comparator 1 positive input. Analog I 15 C1+
Analog comparator 1 negative input. Analog I 16 C1-
Analog comparator 1 output. TTL O 29 C1o
CAN module 0 receive. TTL I 28
58
59
CAN0Rx
Controller Area
Network
CAN module 0 transmit. TTL O 31
57
60
CAN0Tx
CAN module 1 receive. TTL I 17 CAN1Rx
CAN module 1 transmit. TTL O 18 CAN1Tx
Trace clock. TTL O 31 TRCLK
Core Trace data 0. TTL O 30 TRD0
Trace data 1. TTL O 29 TRD1
April 10, 2013 1170
Signal Tables
Table 21-4. Signals by Function, Except for GPIO (continued)
a
16/32-Bit Timer 0 Capture/Compare/PWM 0. TTL I/O 1
28
T0CCP0
General-Purpose
Timers
29
T0CCP1
58
T1CCP0
57
T1CCP1
45
T2CCP0
16/32-Bit Timer 2 Capture/Compare/PWM 1. TTL I/O 46 T2CCP1
52
T4CCP0
51
T4CCP1
50
T5CCP0
49
T5CCP1
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0. TTL I/O 16
33
WT0CCP0
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1. TTL I/O 15
32
WT0CCP1
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0. TTL I/O 14 WT1CCP0
1171 April 10, 2013
Tiva
a
I
2
OD I/O 47 I2C0SCL
I2C
I
2
C module 0 data. OD I/O 48 I2C0SDA
I
2
OD I/O 23
33
I2C1SCL
I
2
C module 1 data. OD I/O 24
32
I2C1SDA
I
2
OD I/O 59 I2C2SCL
I
2
I
2
OD I/O 37
61
I2C3SCL
I
2
C module 3 data. OD I/O 36
62
I2C3SDA
I
2
OD I/O 35 I2C4SCL
I
2
I
2
OD I/O 1 I2C5SCL
I
2
JTAG/SWD CLK. TTL I 52 SWCLK
JTAG/SWD/SWO
JTAG TMS and SWDIO. TTL I/O 51 SWDIO
JTAG TDO and SWO. TTL O 49 SWO
JTAG/SWD CLK. TTL I 52 TCK
JTAG TDI. TTL I 50 TDI
JTAG TDO and SWO. TTL O 49 TDO
JTAG TMS and SWDIO. TTL I 51 TMS
April 10, 2013 1172
Signal Tables
a
Motion Control Module 0 PWM Fault 0. TTL I 30
53
63
M0FAULT0
PWM
31
35
M0FAULT1
34
M0FAULT2
TTL O 1 M0PWM0
TTL O 4 M0PWM1
TTL O 58 M0PWM2
TTL O 57 M0PWM3
TTL O 33
59
M0PWM4
TTL O 32
60
M0PWM5
TTL O 16
61
M0PWM6
TTL O 15
62
M0PWM7
Motion Control Module 1 PWM Fault 0. TTL I 5 M1FAULT0
TTL O 35
61
M1PWM0
TTL O 34
62
M1PWM1
TTL O 23
33
59
M1PWM2
TTL O 24
32
60
M1PWM3
TTL O 28 M1PWM4
TTL O 29 M1PWM5
TTL O 30 M1PWM6
TTL O 31 M1PWM7
1173 April 10, 2013
Tiva
a
Ground reference for logic and I/O pins. Power - 12
27
39
55
GND
Power
The ground reference for the analog circuits (ADC,
fromGNDto minimize the electrical noise contained
on VDD from affecting the analog functions.
Power - 3 GNDA
Positive supply for I/O and some logic. Power - 11
26
42
54
VDD
The positive supply for the analog circuits (ADC,
fromVDDto minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 22-5 on page 1185, regardless
of system implementation.
Power - 2 VDDA
Positive supply for most of the logic function,
including the processor core and most peripherals.
The voltage on this pin is 1.2 V and is supplied by
the on-chip LDO. The VDDC pins should only be
connected to each other and an external capacitor
as specified in Table 22-12 on page 1197 .
Power - 25
56
VDDC
QEI module 0 index. TTL I 5
64
IDX0
QEI
QEI module 1 index. TTL I 16
32
IDX1
QEI module 0 phase A. TTL I 28
53
PhA0
QEI module 1 phase A. TTL I 15
34
37
PhA1
QEI module 0 phase B. TTL I 10
29
PhB0
QEI module 1 phase B. TTL I 14
33
36
PhB1
April 10, 2013 1174
Signal Tables
a
SSI module 0 clock TTL I/O 19 SSI0Clk
SSI
SSI module 0 frame signal TTL I/O 20 SSI0Fss
SSI module 0 receive TTL I 21 SSI0Rx
SSI module 0 transmit TTL O 22 SSI0Tx
SSI module 1 clock. TTL I/O 30
61
SSI1Clk
SSI module 1 frame signal. TTL I/O 31
62
SSI1Fss
SSI module 1 receive. TTL I 28
63
SSI1Rx
SSI module 1 transmit. TTL O 29
64
SSI1Tx
SSI module 2 clock. TTL I/O 58 SSI2Clk
SSI module 2 frame signal. TTL I/O 57 SSI2Fss
SSI module 2 receive. TTL I 1 SSI2Rx
SSI module 2 transmit. TTL O 4 SSI2Tx
SSI module 3 clock. TTL I/O 61 SSI3Clk
SSI module 3 frame signal. TTL I/O 62 SSI3Fss
SSI module 3 receive. TTL I 63 SSI3Rx
SSI module 3 transmit. TTL O 64 SSI3Tx
Non-maskable interrupt. TTL I 10
28
NMI
System Control &
Clocks
reference input.
Analog I 40 OSC0
Analog O 41 OSC1
System reset input. TTL I 38 RST
1175 April 10, 2013
Tiva
a
UART module 0 receive. TTL I 17 U0Rx
UART
UART module 0 transmit. TTL O 18 U0Tx
input signal.
TTL I 15
29
U1CTS
TTL O 16
28
U1RTS
UART module 1 receive. TTL I 16
45
U1Rx
UART module 1 transmit. TTL O 15
46
U1Tx
UART module 2 receive. TTL I 33
53
U2Rx
UART module 2 transmit. TTL O 10
32
U2Tx
21.4 GPIO Pins and Alternate Functions
Table 21-5. GPIO Pins and Alternate Functions
a
Analog
Function
Pin IO
15 14 9 8 7 6 5 4 3 2 1
- - - CAN1Rx - - - - - - U0Rx - 17 PA0
- - - CAN1Tx - - - - - - U0Tx - 18 PA1
- - - - - - - - - SSI0Clk - - 19 PA2
- - - - - - - - - SSI0Fss - - 20 PA3
- - - - - - - - - SSI0Rx - - 21 PA4
- - - - - - - - - SSI0Tx - - 22 PA5
- - - - - - M1PWM2 - I2C1SCL - - - 23 PA6
- - - - - - M1PWM3 - I2C1SDA - - - 24 PA7
- - - - T2CCP0 - - - - - U1Rx - 45 PB0
- - - - T2CCP1 - - - - - U1Tx - 46 PB1
- - - - T3CCP0 - - - I2C0SCL - - - 47 PB2
- - - - T3CCP1 - - - I2C0SDA - - - 48 PB3
April 10, 2013 1176
Signal Tables
Table 21-5. GPIO Pins and Alternate Functions (continued)
a
Analog
Function
Pin IO
15 14 9 8 7 6 5 4 3 2 1
- - - CAN0Rx T1CCP0 - - M0PWM2 - SSI2Clk - AIN10 58 PB4
- - - CAN0Tx T1CCP1 - - M0PWM3 - SSI2Fss - AIN11 57 PB5
- - - - T0CCP0 - - M0PWM0 I2C5SCL SSI2Rx - - 1 PB6
- - - - T0CCP1 - - M0PWM1 I2C5SDA SSI2Tx - - 4 PB7
- - - - T4CCP0 - - - - -
TCK
SWCLK
- 52 PC0
- - - - T4CCP1 - - - - -
TMS
SWDIO
- 51 PC1
- - - - T5CCP0 - - - - - TDI - 50 PC2
- - - - T5CCP1 - - - - -
TDO
SWO
- 49 PC3
- - - U1RTS WT0CCP0 IDX1 - M0PWM6 - U1Rx U4Rx C1- 16 PC4
- - - U1CTS WT0CCP1 PhA1 - M0PWM7 - U1Tx U4Tx C1+ 15 PC5
- - - - WT1CCP0 PhB1 - - - - U3Rx C0+ 14 PC6
- - - - WT1CCP1 - - - - - U3Tx C0- 13 PC7
- - - - WT2CCP0 - M1PWM0 M0PWM6 I2C3SCL SSI1Clk SSI3Clk AIN7 61 PD0
- - - - WT2CCP1 - M1PWM1 M0PWM7 I2C3SDA SSI1Fss SSI3Fss AIN6 62 PD1
- - - - WT3CCP0 - - M0FAULT0 - SSI1Rx SSI3Rx AIN5 63 PD2
- - - - WT3CCP1 IDX0 - - - SSI1Tx SSI3Tx AIN4 64 PD3
- - - - WT4CCP0 - - - - - U6Rx - 43 PD4
- - - - WT4CCP1 - - - - - U6Tx - 44 PD5
- - - - WT5CCP0 PhA0 - M0FAULT0 - - U2Rx - 53 PD6
- - - NMI WT5CCP1 PhB0 - M0FAULT1 - - U2Tx - 10 PD7
- - - - - - - - - - U7Rx AIN3 9 PE0
- - - - - - - - - - U7Tx AIN2 8 PE1
- - - - - - - - - - - AIN1 7 PE2
- - - - - - - - - - - AIN0 6 PE3
- - - CAN0Rx - - M1PWM2 M0PWM4 I2C2SCL - U5Rx AIN9 59 PE4
- - - CAN0Tx - - M1PWM3 M0PWM5 I2C2SDA - U5Tx AIN8 60 PE5
- - C0o NMI T0CCP0 PhA0 M1PWM4 - CAN0Rx SSI1Rx U1RTS - 28 PF0
- TRD1 C1o - T0CCP1 PhB0 M1PWM5 - - SSI1Tx U1CTS - 29 PF1
- TRD0 - - T1CCP0 - M1PWM6 M0FAULT0 - SSI1Clk - - 30 PF2
- TRCLK - - T1CCP1 - M1PWM7 M0FAULT1 CAN0Tx SSI1Fss - - 31 PF3
- - - - T2CCP0 IDX0 M1FAULT0 M0FAULT2 - - - - 5 PF4
- - - - T4CCP0 PhA1 M1FAULT1 - I2C3SCL - - - 37 PG0
- - - - T4CCP1 PhB1 M1FAULT2 - I2C3SDA - - - 36 PG1
- - - - T5CCP0 - M1PWM0 M0FAULT1 I2C4SCL - - - 35 PG2
- - - - T5CCP1 PhA1 M1PWM1 M0FAULT2 I2C4SDA - - - 34 PG3
- - - - WT0CCP0 PhB1 M1PWM2 M0PWM4 I2C1SCL - U2Rx - 33 PG4
- - - - WT0CCP1 IDX1 M1PWM3 M0PWM5 I2C1SDA - U2Tx - 32 PG5
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. Encodings 10-13 are not used
on this device.
1177 April 10, 2013
Tiva
21.5 Possible Pin Assignments for Alternate Functions
Table 21-6. Possible Pin Assignments for Alternate Functions
GPIO Function Alternate Function # of Possible Assignments
PE3 AIN0
one
PE2 AIN1
PB4 AIN10
PB5 AIN11
PE1 AIN2
PE0 AIN3
PD3 AIN4
PD2 AIN5
PD1 AIN6
PD0 AIN7
PE5 AIN8
PE4 AIN9
PC6 C0+
PC7 C0-
PF0 C0o
PC5 C1+
PC4 C1-
PF1 C1o
PA0 CAN1Rx
PA1 CAN1Tx
PB2 I2C0SCL
PB3 I2C0SDA
PE4 I2C2SCL
PE5 I2C2SDA
PG2 I2C4SCL
PG3 I2C4SDA
PB6 I2C5SCL
PB7 I2C5SDA
PB6 M0PWM0
PB7 M0PWM1
PB4 M0PWM2
PB5 M0PWM3
PF4 M1FAULT0
PG0 M1FAULT1
PG1 M1FAULT2
PF0 M1PWM4
PF1 M1PWM5
PF2 M1PWM6
PF3 M1PWM7
April 10, 2013 1178
Signal Tables
Table 21-6. Possible Pin Assignments for Alternate Functions (continued)
SSI0Clk PA2
PA3 SSI0Fss
PA4 SSI0Rx
PA5 SSI0Tx
PB4 SSI2Clk
PB5 SSI2Fss
PB6 SSI2Rx
PB7 SSI2Tx
PD0 SSI3Clk
PD1 SSI3Fss
PD2 SSI3Rx
PD3 SSI3Tx
PC0 SWCLK
PC1 SWDIO
PC3 SWO
PB1 T2CCP1
PB2 T3CCP0
PB3 T3CCP1
PC0 TCK
PC2 TDI
PC3 TDO
PC1 TMS
PF3 TRCLK
PF2 TRD0
PF1 TRD1
PA0 U0Rx
PA1 U0Tx
PC6 U3Rx
PC7 U3Tx
PC4 U4Rx
PC5 U4Tx
PE4 U5Rx
PE5 U5Tx
PD4 U6Rx
PD5 U6Tx
PE0 U7Rx
PE1 U7Tx
PC6 WT1CCP0
PC7 WT1CCP1
PD0 WT2CCP0
PD1 WT2CCP1
1179 April 10, 2013
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WT3CCP0 PD2
PD3 WT3CCP1
PD4 WT4CCP0
PD5 WT4CCP1
PD6 WT5CCP0
PD7 WT5CCP1
April 10, 2013 1180
Signal Tables
PA6 PG4 I2C1SCL
two
PA7 PG5 I2C1SDA
PD0 PG0 I2C3SCL
PD1 PG1 I2C3SDA
PD3 PF4 IDX0
PC4 PG5 IDX1
PF4 PG3 M0FAULT2
PE4 PG4 M0PWM4
PE5 PG5 M0PWM5
PC4 PD0 M0PWM6
PC5 PD1 M0PWM7
PD0 PG2 M1PWM0
PD1 PG3 M1PWM1
PD7 PF0 NMI
PD6 PF0 PhA0
PD7 PF1 PhB0
PD0 PF2 SSI1Clk
PD1 PF3 SSI1Fss
PD2 PF0 SSI1Rx
PD3 PF1 SSI1Tx
PB6 PF0 T0CCP0
PB7 PF1 T0CCP1
PB4 PF2 T1CCP0
PB5 PF3 T1CCP1
PB0 PF4 T2CCP0
PC0 PG0 T4CCP0
PC1 PG1 T4CCP1
PC2 PG2 T5CCP0
PC3 PG3 T5CCP1
PC5 PF1 U1CTS
PC4 PF0 U1RTS
PB0 PC4 U1Rx
PB1 PC5 U1Tx
PD6 PG4 U2Rx
PD7 PG5 U2Tx
PC4 PG4 WT0CCP0
PC5 PG5 WT0CCP1
1181 April 10, 2013
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PB4 PE4 PF0 CAN0Rx
three
PB5 PE5 PF3 CAN0Tx
PD2 PD6 PF2 M0FAULT0
PD7 PF3 PG2 M0FAULT1
PA6 PE4 PG4 M1PWM2
PA7 PE5 PG5 M1PWM3
PC5 PG0 PG3 PhA1
PC6 PG1 PG4 PhB1
21.6 Connections for Unused Signals
Table 21-7 on page 1182 shows how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 64-pin LQFP package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics.
Table 21-7. Connections for Unused Signals (64-Pin LQFP)
Preferred Practice Acceptable Practice Pin Number Signal Name Function
GND NC - All unused GPIOs GPIO
NC NC - NC No Connects
GND NC 40 OSC0
System Control
NC NC 41 OSC1
Connect through a capacitor to
GND as close to pin as possible
Pull up as shown in Figure
5-1 on page 204
38 RST
April 10, 2013 1182
Signal Tables
22 Electrical Characteristics
22.1 Operating Characteristics
Table 22-1. Temperature Characteristics
Unit Value Symbol Characteristic
C -40 to +90 T
C
Case operating temperature range
C -65 to +150 T
S
Unpowered storage temperature range
Table 22-2. Thermal Characteristics
a
Unit Value Symbol Characteristic
C/W 27.5
JB
Thermal resistance (junction to board)
b
C/W 15.8
JC
Thermal resistance (junction to case)
b
C/W 0.7
JT
Junction to top of package
C/W 27.1
JB
Junction to board
C T
B
+ (P
JB
)
c
T
C
+ (P
JC
)
d
T
J
Junction temperature
a. For more details about thermal metrics and definitions, see the Semiconductor and ICPackage Thermal Metrics Application
Report (literature number SPRA953).
b. Junction to board thermal resistance (
JB
) and junction to case thermal resistance (
JC
) numbers are determined by a
package simulator.
c. T
B
is temperature of the board.
d. This equation may give a junction temperature estimate that is higher than the actual junction temperature. Please see
the Semiconductor and IC Package Thermal Metrics Application Report (literature number SPRA953)
Table 22-3. ESD Absolute Maximum Ratings
Unit Max Nom Min Parameter
kV 2.0 - - V
ESDHBM
b
Component-Level ESD
Stress Voltage
a
V 500 - - V
ESDCDM
c
a. Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges in
device.
b. Level listed is passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process.
c. Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows
safe manufacturing with a standard ESD control process.
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22.2 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Device reliability may be adversely affected by exposure to absolute-maximum
ratings for extended periods.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 22-4. Maximum Ratings
Unit
Value
Parameter Name
a
Parameter
Max Min
V 4 0 V
DD
supply voltage V
DD
V 4 0 V
DDA
supply voltage
b
V
DDA
V 5.5 -0.3 Input voltage on GPIOs, regardless of whether the
microcontroller is powered
cd
V
IN_GPIO
V V
DD
+ 0.3 -0.3 Input voltage for PD4, PD5, PB0 and PB1 when configured
as GPIO
mA 25 - Maximum current per output pin I
GPIOMAX
a. Voltages are measured with respect to GND.
b. To ensure proper operation, VDDA must be powered before VDD if sourced from different supplies, or connected to the
same supply as VDD. Note that the minimum operating voltage for VDD differs from the minimum operating voltage for
VDDA. This change should be accounted for in the system design if both are sourced from the same supply. There is
not a restriction on order for powering off.
c. Applies to static and dynamic signals including overshoot.
d. Refer to Figure 22-15 on page 1207 for a representation of the ESD protection on GPIOs.
Important: This device contains circuitry to protect the I/Os against damage due to high-static
voltages; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are connected to an appropriate
logic voltage level (see Connections for Unused Signals on page 1182).
April 10, 2013 1184
Electrical Characteristics
22.3 Recommended Operating Conditions
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIOpins configured as 8-mA output drivers, a total of four GPIOoutputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the V
OL
value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package with the total number of high-current GPIO
outputs not exceeding four for the entire package.
Table 22-5. Recommended DC Operating Conditions
Unit Max Nom Min Parameter Name Parameter
V 3.63 3.3 3.15 V
DD
supply voltage V
DD
V 3.63 3.3 2.97 V
DDA
supply voltage V
DDA
V 1.32 1.2 1.08 V
DDC
supply voltage V
DDC
V 1.32 - 1.08 V
DDC
supply voltage, Deep-sleep mode V
DDCDS
ab
a. These values are valid when LDO is in operation.
b. There are peripheral timing restrictions for SSI and LPCin Deep-sleep mode. Please refer to those peripheral characteristic
sections for more information.
Table 22-6. Recommended GPIO Pad Operating Conditions
V 5.5 - 0.65 * V
DD
GPIO high-level input voltage V
IH
V 0.35 * V
DD
- 0 GPIO low-level input voltage V
IL
V - - 0.2 GPIO input hysteresis V
HYS
V - - 2.4 GPIO high-level output voltage V
OH
V 0.4 - - GPIO low-level output voltage V
OL
High-level source current, V
OH
=2.4 V
a
I
OH
mA - - 2.0 2-mA Drive
Low-level sink current, V
OL
=0.4 V
a
I
OL
mA - - 18.0 8-mA Drive, V
OL
=1.2 V
a. I
O
specifications reflect the maximum current where the corresponding output voltage meets the V
OH
/V
OL
thresholds. I
O
current can exceed these limits (subject to absolute maximum ratings).
Table 22-7. GPIO Current Restrictions
a
mA 30 - - Cumulative maximum GPIO current per side, left
b
I
MAXL
mA 35 - - Cumulative maximumGPIOcurrent per side, bottom
b
I
MAXB
mA 40 - - Cumulative maximum GPIO current per side, right
b
I
MAXR
mA 40 - - Cumulative maximum GPIO current per side, top
b
I
MAXT
a. Based on design simulations, not tested in production.
b. Sum of sink and source current for GPIOs as shown in Table 22-8 on page 1186.
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Table 22-8. GPIO Package Side Assignments
GPIOs Side
PB[6-7], PC[4-7], PD7, PE[0-3], PF4 Left
PA[0-7], PF[0-3], PG5 Bottom
PB[0-3], PD[4-5], PG[0-4] Right
PB[4-5], PC[0-3], PD[0-3,6], PE[4-5] Top
April 10, 2013 1186
22.4 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements.
Figure 22-1. Load Conditions
C
L
= 50 pF
GND
pin
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22.5 JTAG and Boundary Scan
Table 22-9. JTAG Characteristics
Unit Max Nom Min Parameter Name Parameter Parameter
No.
MHz 10 - 0 TCK operational clock frequency
a
F
TCK
J1
ns - - 100 TCK operational clock period T
TCK
J2
ns - t
TCK
/2 - TCK clock Low time T
TCK_LOW
J3
ns - t
TCK
/2 - TCK clock High time T
TCK_HIGH
J4
ns 10 - 0 TCK rise time T
TCK_R
J5
ns 10 - 0 TCK fall time T
TCK_F
J6
ns - - 8 TMS setup time to TCK rise T
TMS_SU
J7
ns - - 4 TMS hold time from TCK rise T
TMS_HLD
J8
ns - - 18 TDI setup time to TCK rise T
TDI_SU
J9
ns - - 4 TDI hold time from TCK rise T
TDI_HLD
J10
ns 35 13
-
TCK fall to Data Valid from High-Z, 2-mA drive
T
TDO_ZDV
J11
ns 26 9 TCK fall to Data Valid from High-Z, 4-mA drive
ns 26 8 TCK fall to Data Valid from High-Z, 8-mA drive
ns 29 10 TCK fall to Data Valid fromHigh-Z, 8-mA drive with
slew rate control
ns 20 14
-
TCK fall to Data Valid from Data Valid, 2-mA drive
T
TDO_DV
J12
ns 26 10 TCK fall to Data Valid from Data Valid, 4-mA drive
with slew rate control
ns 16 7
-
TCK fall to High-Z from Data Valid, 2-mA drive
T
TDO_DVZ
J13
ns 16 7 TCK fall to High-Z from Data Valid, 4-mA drive
ns 16 7 TCK fall to High-Z from Data Valid, 8-mA drive
ns 19 8 TCK fall to High-Z fromData Valid, 8-mA drive with
slew rate control
a. A ratio of at least 8:1 must be kept between the system clock and TCK.
Figure 22-2. JTAG Test Clock Input Timing
TCK
J6 J5
J3 J4
J2
April 10, 2013 1188
Figure 22-3. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8 J8 J7
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22.6 Power and Brown-Out
Table 22-10. Power-On and Brown-Out Levels
No.
s - - Analog Supply Voltage (VDDA) Rise Time T
VDDA_RISE
P1
s - - I/O Supply Voltage (VDD) Rise Time T
VDD_RISE
P2
s 50.00 - 12.50 Core Supply Voltage (VDDC) Rise Time T
VDDC_RISE
a
P3
V 2.60 2.30 2.00 Power-On Reset Threshold V
POR
P4
V 3.00 2.85 2.70 VDDAPower-OKThreshold (Rising Edge)
V
VDDA_POK
P5
V 2.89 2.80 2.71 VDDAPower-OKThreshold (Falling Edge)
V 3.15 3.00 2.85 VDD Power-OK Threshold (Rising Edge)
V
VDD_POK
P6
V 2.87 2.78 2.70 VDD Power-OK Threshold (Falling Edge)
V 3.11 3.02 2.93 Brown-Out 0 Reset Threshold V
VDD_BOR0
P7
V 3.01 2.92 2.83 Brown-Out 1 Reset Threshold V
VDD_BOR1
P8
V 1.10 0.95 0.80 VDDCPower-OKThreshold (Rising Edge)
V
VDDC_POK
P9
V 0.89 0.80 0.71 VDDCPower-OKThreshold (Falling Edge)
a. The MIN and MAX value is based on an external filter capacitor load within the range of CLDO. Please refer to On-Chip
Low Drop-Out (LDO) Regulator on page 1197 for the CLDO value.
22.6.1 VDDA Levels
The V
DDA
supply has two monitors:
Power-On Reset (POR)
Power-OK (POK)
The POR monitor is used to keep the analog circuitry in reset until the V
DDA
supply has reached
the correct range for the analog circuitry to begin operating. The POK monitor is used to keep the
digital circuitry in reset until the V
DDA
power supply is at an acceptable operational level. The digital
Power-On Reset (Digital POR) is only released when the Power-On Reset has de-asserted and
all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges.
Once the V
DDA
POK monitor has released the digital Power-On Reset on the initial power-up, voltage
drops on the V
DDA
supply will only be reflected in the following bits. The digital Power-On Reset will
not be re-asserted.
VDDARIS bit in the Raw Interrupt Status (RIS) register (see page 230).
VDDAMIS bit in the Masked Interrupt Status and Clear (MISC) register (see page 234). This bit
is set only if the VDDAIM bit in the Interrupt Mask Control (IMC) register has been set.
Figure 22-4 on page 1191 shows the relationship between V
DDA
, POR, POK, and an interrupt event.
April 10, 2013 1190
Figure 22-4. Power Assertions versus VDDA Levels
P1
V
D
D
A
P5
RISE
P4
P5
FALL
P
O
K
I
N
T
P4
1
VDDAMIN
1
1
0
0
0
P
O
R
22.6.2 VDD Levels
The V
DD
supply has three monitors:
Power-OK (POK)
Brown-Out Reset0 (BOR0)
Brown-Out Reset1 (BOR1)
The POK monitor is used to keep the digital circuitry in reset until the V
DD
power supply is at an
acceptable operational level. The digital Power-On Reset (Digital POR) is only released when
the Power-On Reset has de-asserted and all of the Power-OK monitors for each of the supplies
indicate that power levels are in operational ranges. The BOR0 and the BOR1 monitors are used
to generate a reset to the device or assert an interrupt if the V
DD
supply drops below its operational
range. The BOR1 monitor's threshold is in between the BOR0 and POK thresholds.
If either a BOR0 event or a BOR1 event occurs, the following bits are affected:
BOR0RIS or BOR1RIS bits in the Raw Interrupt Status (RIS) register (see page 230).
BOR0MIS or BOR1MIS bits in the Masked Interrupt Status and Clear (MISC) register (see
page 234). These bits are set only if the respective BOR0IM or BOR1IM bits in the Interrupt Mask
Control (IMC) register have been set.
BOR bit in the Reset Cause (RESC) register (see page 237). This bit is set only if either of the
BOR0 or BOR1 events have been configured to initiate a reset.
In addition, the following bits control both the BOR0 and BOR1 events:
BOR0IM or BOR1IM bits in the Interrupt Mask Control (IMC) register (see page 232).
1191 April 10, 2013
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BOR0 or BOR1 bits in the Power-On and Brown-Out Reset Control (PBORCTL) register (see
page 229).
Figure 22-5 on page 1192 shows the relationship between:
V
DD
, POK, and a BOR0 event
V
DD
, POK, and a BOR1 event
Figure 22-5. Power and Brown-Out Assertions versus VDD Levels
P2
V
D
D
P6
RISE
P7
P
O
K
B
O
R
1
VDDMIN
1
1
0
0
P8
P6
FALL
B
O
R
0
1
0
22.6.3 VDDC Levels
The V
DDC
supply has one monitor: the Power-OK (POK). The POK monitor is used to keep the
digital circuitry in reset until the V
DDC
power supply is at an acceptable operational level. The digital
Power-On Reset (Digital POR) is only released when the Power-On Reset has de-asserted and
all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges. Figure 22-6 on page 1193 shows the relationship between POK and V
DDC
.
April 10, 2013 1192
Figure 22-6. POK assertion vs VDDC
P3
V
D
D
C
P9
RISE
P
O
K
VDDCMIN
1
0
P9
FALL
22.6.4 VDD Glitches
Figure 22-7 on page 1193 shows the response of the BOR0, BOR1, and the POR circuit to glitches
on the V
DD
supply.
Figure 22-7. POR-BOR0-BOR1 VDD Glitch Response
22.6.5 VDD Droop Response
Figure 22-8 on page 1194 shows the response of the BOR0, BOR1, and the PORmonitors to a drop
on the V
DD
supply.
1193 April 10, 2013
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Figure 22-8. POR-BOR0-BOR1 VDD Droop Response
April 10, 2013 1194
22.7 Reset
Table 22-11. Reset Characteristics
No.
s 5.35 - 0.80 Digital POR to Internal Reset assertion
delay
a
T
DPORDLY
R1
s 500 - - Internal Reset timeout T
IRTOUT
R2
s 1.95 - 0.25 BOR0 to Internal Reset assertion delay
a
T
BOR0DLY
R3
s 5.95 - 0.75 BOR1 to Internal Reset assertion delay
a
T
BOR1DLY
R3
ns - 250 - Minimum RST pulse width T
RSTMIN
R4
ns - 250 - RST to Internal Reset assertion delay T
IRHWDLY
R5
s - 2.07 - Internal reset timeout after software-initiated
system reset
T
IRSWR
R6
s - 2.10 - Internal reset timeout after Watchdog reset T
IRWDR
R7
s - 1.92 - Internal reset timeout after MOSC failure
reset
T
IRMFR
R8
a. Timing values are dependent on the V
DD
power-down ramp rate.
Figure 22-9. Digital Power-On Reset Timing
Reset
(Internal)
R2
Digital POR
R
1
The digital Power-On Reset is only released when the analog Power-On Reset has de-asserted
and all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges.
Figure 22-10. Brown-Out Reset Timing
Reset
(Internal)
R2
BOR
R
3
1195 April 10, 2013
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Figure 22-11. External Reset Timing (RST)
RST
(Package Pin)
Reset
(Internal)
R
4
R
5
R
2
Figure 22-12. Software Reset Timing
Software
Reset
Reset
(Internal)
R
6
Figure 22-13. Watchdog Reset Timing
Watchdog
Reset
Reset
(Internal)
R
7
Figure 22-14. MOSC Failure Reset Timing
MOSC Fail
Reset
Reset
(Internal)
R
8
April 10, 2013 1196
22.8 On-Chip Low Drop-Out (LDO) Regulator
Table 22-12. LDO Regulator Characteristics
F 4.0 - 2.5 External filter capacitor size for internal power
supply
a
C
LDO
m 100 - 10 Filter capacitor equivalent series resistance ESR
nH 0.5 - - Filter capacitor equivalent series inductance ESL
V 1.32 1.2 1.08 LDO output voltage V
LDO
mA 250 - 50 Inrush current I
INRUSH
a. The capacitor should be connected as close as possible to pin 56.
1197 April 10, 2013
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22.9 Clocks
The following sections provide specifications on the various clock sources and mode.
22.9.1 PLL Specifications
The following tables provide specifications for using the PLL.
Table 22-13. Phase Locked Loop (PLL) Characteristics
MHz 25 - 5
a
Crystal reference F
REF_XTAL
MHz 25 - 5
a
External clock reference
a
F
REF_EXT
MHz - 400 - PLL frequency
b
F
PLL
reference clocks
d
512 * (N+1)
c
- - PLL lock time, enabling the PLL
T
READY
reference clocks
d
128 * (N+1)
c
- - PLL lock time, changing the XTAL field in the
RCC/RCC2 register or changing the OSCSRC
between MOSC and PIOSC
a. If the PLL is not used, the minimum input frequency can be 4 MHz.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCCregister. The PLL frequency
that is set by the hardware can be calculated using the values in the PLLFREQ0 and PLLFREQ1 registers.
c. N is the value in the N field in the PLLFREQ1 register.
d. A reference clock is the clock period of the crystal being used, which can be MOSC or PIOSC. For example, a 16-MHz
crystal connected to MOSC yields a reference clock of 62.5 ns.
Table 22-14 on page 1198 shows the actual frequency of the PLL based on the crystal frequency used
(defined by the XTAL field in the RCC register).
Table 22-14. Actual PLL Frequency
Error PLL
Frequency
(MHz)
PLL Multiplier N Q MFRAC MINT Crystal
Frequency
(MHz)
XTAL
- 400 80 0x0 0x0 0x0 0x50 5.0 0x09
- 400 156.25 0x1 0x0 0x100 0x9C 5.12 0x0A
- 400 200 0x2 0x0 0x0 0xC8 6.0 0x0B
- 400 195.3125 0x2 0x0 0x140 0xC3 6.144 0x0C
0.0004% 399.9984 162.7598 0x2 0x0 0x30A 0xA2 7.3728 0x0D
- 400 50 0x0 0x0 0x0 0x32 8.0 0x0E
- 400 195.3125 0x3 0x0 0x140 0xC3 8.192 0x0F
- 400 80 0x1 0x0 0x0 0x50 10.0 0x10
- 400 200 0x5 0x0 0x0 0xC8 12.0 0x11
- 400 195.3125 0x5 0x0 0x140 0xC3 12.288 0x12
0.0005% 399.9979 176.9902 0x5 0x0 0x3F6 0xB0 13.56 0x13
0.0005% 399.9982 195.5547 0x6 0x0 0x238 0xC3 14.318 0x14
- 400 50 0x1 0x0 0x0 0x32 16.0 0x15
- 400 195.3125 0x7 0x0 0x140 0xC3 16.384 0x16
- 400 200 0x8 0x0 0x0 0xC8 18 0x17
- 400 80 0x3 0x0 0x0 0x50 20 0x18
- 400 50 0x2 0x0 0x0 0x32 24 0x19
April 10, 2013 1198
Table 22-14. Actual PLL Frequency (continued)
Error PLL
Frequency
(MHz)
PLL Multiplier N Q MFRAC MINT Crystal
Frequency
(MHz)
XTAL
- 400 80 0x4 0x0 0x0 0x50 25 0x1A
22.9.2 PIOSC Specifications
Table 22-15. PIOSC Clock Characteristics
- 3% - - Internal 16-MHz precision oscillator frequency variance
(factory calibrated at 25 C C and 3.3 V) across the
specified voltage and temperature range
F
PIOS
a
a. This parameter value remains valid if recalibration occurs.
22.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications
Table 22-16. Low-Frequency internal Oscillator Characteristics
KHz 90 33 10 Low-frequency internal oscillator (LFIOSC)
frequency
F
LFIOSC
22.9.4 Main Oscillator Specifications
Table 22-17. Main Oscillator Input Characteristics
MHz 25 - 4
a
Parallel resonance frequency F
MOSC
pF 24 - 12 External load capacitance on OSC0, OSC1 pins
b
C
1
, C
2
pF - 0.5 - Device package stray shunt capacitance
b
C
PKG
pF - 0.5 - PCB stray shunt capacitance
b
C
PCB
pF - 4 - Crystal shunt capacitance
bc
C
0
pF 4 - - Total shunt capacitance
b
C
SHUNT
300 - - Crystal effective series resistance, 4 MHz
dc
ESR
dc
dc
dc
dc
dc
mW - OSC
PWR
- Oscillator output drive level
e
DL
ms 18 - - Oscillator startup time, when using a crystal
f
T
START
V V
DD
- 0.65 * V
DD
CMOS input high level, when using an external
oscillator
V
IH
V 0.35 * V
DD
- GND CMOSinput lowlevel, when using an external oscillator V
IL
mV - - 150 CMOS input buffer hysteresis, when using an external
oscillator
V
HYS
1199 April 10, 2013
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Table 22-17. Main Oscillator Input Characteristics (continued)
% 55 - 45 External clock reference duty cycle DC
OSC_EXT
a. 5 MHz is the minimum when using the PLL.
b. See information below table.
c. Crystal vendors can be contacted to confirm these specifications are met for a specific crystal part number if the vendors
generic crystal datasheet show limits outside of these specifications.
d. Crystal ESR specified by crystal manufacturer.
e. OSC
PWR
= (2 * pi * F
P
* C
L
* 2.5)
2
* ESR / 2. An estimation of the typical power delivered to the crystal is based on the
C
L
, F
P
and ESR parameters of the crystal in the circuit as calculated by the OSC
PWR
equation. Ensure that the value
calculated for OSC
PWR
does not exceed the crystal's drive-level maximum.
f. Oscillator startup time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation
such that the internal clock is valid.
The load capacitors added on the board, C
1
and C
2
, should be chosen such that the following
equation is satisfied (see Table 22-17 on page 1199 for typical values and Table 22-18 on page 1201
for detailed crystal parameter information).
C
L
= load capacitance specified by crystal manufacturer
C
L
= (C
1
*C
2
)/(C
1
+C
2
) + C
SHUNT
C
SHUNT
= C
0
+ C
PKG
+ C
PCB
(total shunt capacitance seen across OSC0, OSC1 crystal inputs)
C
PKG
, C
PCB
= the mutual caps as measured across the OSC0,OSC1 pins excluding the crystal.
C
0
= Shunt capacitance of crystal specified by the crystal manufacturer
Table 22-18 on page 1201 lists part numbers of crystals that have been simulated and confirmed to
operate within the specifications in Table 22-17 on page 1199. Other crystals that have nearly identical
crystal parameters can be expected to work as well.
In the table below, the crystal parameters labeled C0, C1 and L1 are values that are obtained from
the crystal manufacturer. These numbers are usually a result of testing a relevant batch of crystals
on a network analyzer. The parameters labeled ESR, DL and C
L
are maximum numbers usually
available in the data sheet for a crystal.
The table also includes three columns of Recommended Component Values. These values apply
to system board components. C
1
and C
2
are the values in pico Farads of the load capacitors that
should be put on each leg of the crystal pins to ensure oscillation at the correct frequency. Rs is the
value in kof a resistor that is placed in series with the crystal between the OSC1 pin and the crystal
pin. Rs dissipates some of the power so the Max Dl crystal parameter is not exceeded. Only use
the recommended C
1
, C
2
, and Rs values with the associated crystal part. The values in the table
were used in the simulation to ensure crystal startup and to determine the worst case drive level
(WC Dl). The value in the WC Dl column should not be greater than the Max Dl Crystal parameter.
The WC Dl value can be used to determine if a crystal with similar parameter values but a lower
Max Dl value is acceptable.
April 10, 2013 1200
Table 22-18. Crystal Parameters
W
C
D
l
(
W
)
Recommended
Component
Values
Crystal Parameters
C
r
y
s
t
a
l
S
p
e
c
F
r
e
q
(
M
H
z
)
P
K
G
S
i
z
e
(
m
m
x
m
m
)
H
o
l
d
e
r
M
F
G
P
a
r
t
#
M
F
G
Max Values Typical Values
R
s
(
k
)
C
2
(
p
F
)
C
1
(
p
F
)
C
L
(
p
f
)
M
a
x
D
l
(
W
)
E
S
R
(
)
L
1
(
m
H
)
C
1
(
f
F
)
C
0
(
p
F
)
132 0 12 12 8 500 300 598.10 2.70 1.00 STD-CJL-5 4 8 x 4.5 NX8045GB NX8045GB-
4.000M-STD-
CJL-5
NDK
103 0 14 14 10 500 150 396.00 4.05 1.18 FQ1045A 4 10 x 4.5 2-SMD FQ1045A-4 FOX
5.000M-STD-
CSF-4
NDK
6.000M-STD-
CSF-4
NDK
209 0 14 14 10 500 150 112.30 6.26 1.37 FQ1045A 6 10 x 4.5 2-SMD FQ1045A-6 FOX
277 0 12 12 8 500 200 139.30 2.80 1.00 STD-CSF-6 8 8 x 4.5 NX8045GB NX8045GB-
8.000M-STD-
CSF-6
NDK
217 0 14 14 10 500 80 59.10 6.69 1.95 FQ7050 8 7 x 5 4-SMD FQ7050B-8 FOX
298 0 24 24 16 500 80 85.70 4.90 1.82 CSM-4A 8 12.5 x
4.85
HC49/US ECS-80-16-28A-TR ECS
147 2.5 12 12 8 200 100 81.00 2.20 0.70 STD-CRG-2 12 3.2 x 2.5 NX3225GA NX3225GA-
12.000MHZ-
STD-CRG-2
NDK
362 0 12 12 8 500 120 56.40 3.12 0.93 LN-CD-1 12 5 x 3.2 NX5032GA NX5032GA-
12.000MHZ-
LN-CD-1
NDK
370 0 14 14 10 500 80 42.30 4.16 1.16 FQ5032 12 5 x 3.2 4-SMD FQ5032B-12 FOX
188 2 12 12 8 200 80 33.90 2.90 1.00 STD-CRG-2 16 3.2 x 2.5 NX3225GA NX3225GA-
16.000MHZ-
STD-CRG-2
NDK
437 0 10 10 8 500 120 25.90 3.82 1.02 LN-CD-1 16 5 x 3.2 NX5032GA NX5032GA-
16.000MHZ-
LN-CD-1
NDK
289 0.5 12 12 9 300 60 25.84 3.90 1.47 ECX-42 16 4 x 2.5 ECX-42 ECS-160-9-42-CKM-TR ECS
181 2 12 12 8 200 50 8.70 4.70 1.10 STD-CRG-2 25 3.2 x 2.5 NX3225GA NX3225GA-
25.000MHZ-
STD-CRG-2
NDK
331 1 16 16 12 500 50 8.34 5.01 1.58 HC3225 25 3.2 x 2.5 HC3225/4 Q-25.000M-
HC3225/4-
F-30-30-E-12-TR
AURIS
433 0.5 14 14 10 500 50 5.13 7.92 1.69 FQ5032 25 5 x 3.2 4-SMD FQ5032B-25 FOX
1201 April 10, 2013
Tiva
Table 22-19. Supported MOSC Crystal Frequencies
Crystal Frequency (MHz) Using the PLL Crystal Frequency (MHz) Not Using the PLL Value
reserved 0x00-0x5
reserved 4 MHz 0x06
5 MHz 0x09
5.12 MHz 0x0A
6 MHz 0x0B
6.144 MHz 0x0C
7.3728 MHz 0x0D
8 MHz 0x0E
8.192 MHz 0x0F
10.0 MHz 0x10
12.0 MHz 0x11
12.288 MHz 0x12
13.56 MHz 0x13
14.31818 MHz 0x14
16.0 MHz (reset value) 0x15
16.384 MHz 0x16
18.0 MHz 0x17
20.0 MHz 0x18
24.0 MHz 0x19
25.0 MHz 0x1A
22.9.5 System Clock Specification with ADC Operation
Table 22-20. System Clock Characteristics with ADC Operation
MHz 16.0048 16 15.9952 System clock frequency when the ADC
module is operating (when PLL is bypassed).
a
F
sysadc
a. Clock frequency (plus jitter) must be stable inside specified range. ADC can be clocked from the PLL, directly from an
external clock source, or from the PIOSC, as long as frequency absolute precision is inside specified range.
April 10, 2013 1202
22.10 Sleep Modes
Table 22-21. Sleep Modes AC Characteristics
a
No
system
clocks
2 - - Time to wake from interrupt in sleep mode
b
T
WAKE_S
D1
s - 1.25 - Time to wake from interrupt in deep-sleep mode,
using PIOSC for both Run mode and Deep-sleep
mode
b c
T
WAKE_DS
s - 350 - Time to wake from interrupt in deep-sleep mode,
using PIOSC for Run mode and LFIOSC for
Deep-sleep mode
b c
ms T
READY
- - Time to wake from interrupt in deep-sleep mode
when using the PLL
b
T
WAKE_PLL_DS
D2
a. Values in this table assume the LFIOSC is the clock source during sleep or deep-sleep mode.
b. Specified from registering the interrupt to first instruction.
c. If the main oscillator is used for run mode, add the main oscillator startup time, T
START
.
Table 22-22. Time to Wake with Respect to Low-Power Modes
ab
Unit
Time to Wake
SRAMPM FLASHPM
Sleep/Deep-Sleep
Mode
Clock/Frequency
Run Mode
Clock/Frequency
Mode
Max Min
s 0.30 0.28 0x0
0x0
MOSC, PLL on -
80MHz
MOSC, PLL on -
80MHz
Sleep
s 35.00 33.57 0x1
s 35.05 33.75 0x3
s 109.23 105.02 0x0
0x2 s 143.93 137.85 0x1
s 143.86 138.06 0x3
1203 April 10, 2013
Tiva
Table 22-22. Time to Wake with Respect to Low-Power Modes (continued)
Unit
Time to Wake
SRAMPM FLASHPM
Sleep/Deep-Sleep
Mode
Clock/Frequency
Run Mode
Clock/Frequency
Mode
Max Min
s 2.60 2.47 0x0
0x0
PIOSC - 16MHz
MOSC, PLL on -
80MHz
Deep-Sleep
s 36.35 35.31 0x1
s 36.76 35.40 0x3
s 111.54 107.05 0x0
0x2 s 145.64 139.34 0x1
s 145.53 140.41 0x3
s 2.61 2.47 0x0
0x0
PIOSC - 16MHz PIOSC - 16MHz
s 36.65 35.25 0x1
s 36.79 35.38 0x3
s 111.52 107.43 0x0
0x2 s 145.85 139.83 0x1
s 145.54 139.35 0x3
s 728.38 415.06 0x0
0x0
LFIOSC, PIOSC
off
c
- 30kHz
PIOSC - 16MHz
s 740.88 436.60 0x1
s 755.32 433.80 0x3
s 812.82 503.73 0x0
0x2 s 846.23 537.72 0x1
s 839.25 536.10 0x3
ms 19.55 18.95 0x0
0x0
LFIOSC, PIOSC
off
c
- 30kHz
MOSC, PLL on -
80MHz
ms 19.54 18.94 0x1
ms 19.53 18.95 0x3
ms 19.54 18.95 0x0
0x2 ms 19.53 18.94 0x1
ms 19.54 18.95 0x3
a. Time from wake event to first instruction of code execution.
b. If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or Deep-sleep mode.
c. PIOSC is turned off by setting the PIOSCPD bit in the DSLPCLKCFG register.
April 10, 2013 1204
22.11 Flash Memory and EEPROM
Table 22-23. Flash Memory Characteristics
cycles - - 100,000 Number of program/erase cycles before failure
a
PE
CYC
years - - 20 Data retention, -40C to +85C T
RET
s 300 50 30 Program time for double-word-aligned 64 bits of
data
b
T
PROG64
ms - 25 2 Page erase time, <1k cycles
T
ERASE
ms 900 - - Page erase time, 100k cycles
ms - 200 70 Mass erase time, <1k cycles
T
ME
ms 900 - - Mass erase time, 100k cycles
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
b. If programming fewer than 64 bits of data, the programming time is the same. For example, if only 32 bits of data need
to be programmed, the other 32 bits are masked off.
Table 22-24. EEPROM Characteristics
a
cycles - - 500,000 Number of mass program/erase cycles of a single word before
failure
c
EPE
CYC
b
years - - 20 Data retention, -40C to +85C ET
RET
s 600 110 - Program time for 32 bits of data - space available
ET
PROG
ms - 30 - Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer has space and less than 10% of EEPROM
endurance used
ms 900 - - Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer has space and greater than 90% of
EEPROM endurance used
ms - 60 - Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer requires an erase and less than 10% of
ms 1800 - - Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer requires an erase and greater than 90% of
system clocks - 4 - Read access time ET
READ
ms - 200 70 Mass erase time, <1k cycles
ET
ME
ms 900 - - Mass erase time, 100k cycles
a. Because the EEPROM operates as a background task and does not prevent the CPU from executing from Flash memory,
the operation will complete within the maximum time specified provided the EEPROM operation is not stalled by a Flash
memory program or erase operation.
b. One word can be written more than 500K times, but these writes impact the endurance of the words in the meta-block
that the word is within. Different words can be written such that any or all words can be written more than 500K times
when write counts per word stay about the same. See the section called Endurance on page 481 for more information.
c. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
1205 April 10, 2013
Tiva
22.12 Input/Output Pin Characteristics
22.12.1 GPIO Module Characteristics
Note: All GPIO signals are 5-V tolerant when configured as inputs except for PD4, PD5, PB0 and
PB1, which are limited to 3.6 V. See Signal Description on page 591 for more information
on GPIO configuration.
Note: GPIO pads are tolerant to 5-V digital inputs without creating reliability issues, as long as
the supply voltage, VDD, is present. There are limitations to how long a 5-V input can be
present on any given I/O pad if VDD is not present. Not meeting these conditions will affect
reliability of the device and affect the GPIO characteristics specifications.
If the voltage applied to a GPIO pad is in the high voltage range (5V +/- 10%) while VDD
is not present, such condition should be allowed for a maximum of 10,000 hours at 27C
or 5,000 hours at 85C, over the lifetime of the device.
If the voltage applied to a GPIO pad is in the normal voltage range (3.3V +/- 10%) while
VDD is not present or if the voltage applied is in the high voltage range (5V +/- 10%)
while VDD is present, there are no constraints on the lifetime of the device.
Table 22-25. GPIO Module Characteristics
a
k 30 20 13 GPIO internal pull-up resistor R
GPIOPU
k 35 20 13 GPIO internal pull-down resistor R
GPIOPD
A 1.0 - - GPIO input leakage current, 0 V V
IN
V
DD
GPIO
pins
b
I
LKG+
A 2.0 - - GPIO input leakage current, 0 V < V
IN
V
DD
, GPIO
pins configured as ADC or analog comparator inputs
ns 16.1 14.2
-
GPIO rise time, 2-mA drive
c
T
GPIOR
ns 15.5 11.9 GPIO rise time, 4-mA drive
c
ns 11.2 8.1 GPIO rise time, 8-mA drive
c
ns 11.8 9.5 GPIO rise time, 8-mA drive with slew rate control
c
ns 29.4 25.2
-
GPIO fall time, 2-mA drive
d
T
GPIOF
ns 16.8 13.3 GPIO fall time, 4-mA drive
d
ns 11.2 8.6 GPIO fall time, 8-mA drive
d
ns 12.9 11.3 GPIO fall time, 8-mA drive with slew rate control
d
a. V
DD
must be within the range specified in Table 22-5 on page 1185.
b. The leakage current is measured with V
IN
applied to the corresponding pin(s). The leakage of digital port pins is measured
individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled.
c. Time measured from 20% to 80% of V
DD
.
d. Time measured from 80% to 20% of V
DD
.
22.12.2 Types of I/O Pins and ESD Protection
With respect to ESD and leakage current, three types of I/O pins exist on the device: Power I/O
pins, I/O pins with fail-safe ESD protection (GPIOs other than PD4 and PD5 ) and I/O pins with
non-fail-safe ESD protection (any non-power, non-GPIO (other than PD4 and PD5) and pins). This
section covers I/O pins with fail-safe ESD protection and I/O pins with non-fail-safe ESD protection.
April 10, 2013 1206
Power I/O pin voltage and current limitations are specified in Recommended Operating
Conditions on page 1185.
22.12.2.1 Fail-Safe Pins
GPIOs other than PD4 and PD5 use ESD protection as shown in Figure 22-15 on page 1207.
An unpowered device cannot be parasitically powered through any of these pins. This ESDprotection
prevents a direct path between these I/O pads and any power supply rails in the device. GPIO pad
input voltages should be kept inside the maximum ratings specified in Table 22-4 on page 1184 to
ensure current leakage and current injections are within acceptable range. Current leakages and
current injection for these pins are specified in Table 22-25 on page 1206.
Figure 22-15 on page 1207 shows a diagram of the ESD protection on fail-safe pins.
Some GPIOs when configured as inputs require a strong pull-up resistor to maintain a threshold
above VIH during power-on. See Table 22-27 on page 1208.
Figure 22-15. ESD Protection on Fail-Safe Pins
GND
V
DD
I/O Pad
ESD
Clamp
Table 22-26. Pad Voltage/Current Characteristics for Fail-Safe Pins
a
A 700 - - GPIO input leakage current, V
DD
< V
IN
4.5 V
bb
I
LKG+
A 100 - - GPIO input leakage current, 4.5 V < V
IN
5.5 V
bc
A -
e
- - GPIO input leakage current, V
IN
< -0.3 V
bd
I
LKG-
A 10 - - GPIO input leakage current, -0.3 V V
IN
< 0 V
b
A I
LKG+
- - DC injection current, V
DD
< V
IN
5.5 V
fg
I
INJ+
mA 0.5 - - DC injection current, V
IN
0 V
g
I
INJ-
a. VIN must be within the range specified in Table 22-4 on page 1184.
b. To protect internal circuitry from over-voltage, the GPIOs have an internal voltage clamp that limits internal swings to V
DD
without affecting swing at the I/Opad. This internal clamp starts turning on while V
DD
< V
IN
< 4.5 V and causes a somewhat
larger (but bounded) current draw. To save power, static input voltages between V
DD
and 4.5 V should be avoided.
c. Leakage current above maximum voltage (V
IN
= 5.5V) is not guaranteed, this condition is not allowed and can result in
permanent damage to the device.
d. Leakage outside the minimum range (-0.3V) is unbounded and must be limited to IINJ- using an external resistor.
e. In this case, I
LKG-
is unbounded and must be limited to I
INJ-
using an external resistor.
f. Current injection is internally bounded for GPIOs, and maximum current into the pin is given by ILKG+ for V
DD
< V
IN
< 5.5
V.
1207 April 10, 2013
Tiva
g. If the I/O pad is not voltage limited, it should be current limited (to IINJ+ and IINJ-) if there is any possibility of the pad
voltage exceeding the VIO limits (including transient behavior during supply ramp up, or at any time when the part is
unpowered).
Table 22-27. Fail-Safe GPIOs that Require an External Pull-up
Unit Pull-Up Resistor Value Pin GPIO
1k R 10k 45 PB0
1k R 10k 46 PB1
1k R 10k 6 PE3
22.12.2.2 Non-Fail-Safe Pins
The Main Oscillator (MOSC) crystal connection pins and GPIOpins PD4 and PD5 have ESDprotection
as shown in Figure 22-16 on page 1208. These pins have a potential path between the I/O pad and
an internal power rail if either one of the ESD diodes is accidentally forward biased. The voltage
and current of these pins should follow the specifications in Table 22-28 on page 1208 to prevent
potential damage to the device. In addition to the specifications outlined in Table 22-28 on page 1208,
it is recommended that the ADC external reference specifications in Table 22-29 on page 1210 be
adhered to in order to prevent any gain error.
Figure 22-16 on page 1208 shows a diagram of the ESD protection on non-fail-safe pins.
Figure 22-16. ESD Protection on Non-Fail-Safe Pins
GND
V
DD
I/O Pad
Table 22-28. Non-Fail-Safe I/O Pad Voltage/Current Characteristics
abcd
V V
DD
+0.3 V
DD
-0.3 IO pad voltage limits V
IO
A 10 - - Positive IO leakage for V
IO
Max
ef
I
LKG+
A 10 - - Negative IO leakage for V
IO
Min
ef
I
LKG-
mA 2 - - Max positive injection
g
I
INJ+
mA -0.5 - - Max negative injection if not voltage protected
g
I
INJ-
a. V
IN
must be within the range specified in Table 22-4 on page 1184. Leakage current outside of this maximumvoltage is not
guaranteed and can result in permanent damage of the device.
b. VDD must be within the range specified in Table 22-5 on page 1185.
c. To avoid potential damage to the part, either the voltage or current on the ESD-protected, non-Power, non-Hibernate/XOSC
input/outputs should be limited externally as shown in this table.
April 10, 2013 1208
d. I/O pads should be protected if at any point the IO voltage has a possibility of going outside the limits shown in the table.
If the part is unpowered, the IO pad Voltage or Current must be limited (as shown in this table) to avoid powering the
part through the IO pad, causing potential irreversible damage.
e. This value applies to an I/O pin that is voltage-protected within the Min and Max V
IO
ratings. Leakage outside the specified
voltage range is unbounded and must be limited to I
INJ-
using an external resistor.
f. MIN and MAX leakage current for the case when the I/O is voltage-protected to VIO Min or VIO Max.
g. If an I/O pin is not voltage-limited, it should be current-limited (to I
INJ+
and I
INJ-
) if there is any possibility of the pad voltage
exceeding the V
IO
limits (including transient behavior during supply ramp up, or at any time when the part is unpowered).
1209 April 10, 2013
Tiva
22.13 Analog-to-Digital Converter (ADC)
Table 22-29. ADC Electrical Characteristics
ab
POWER SUPPLY REQUIREMENTS
V 3.63 3.3 2.97 ADC supply voltage V
DDA
V - 0 - ADC ground voltage GNDA
VDDA / GNDA VOLTAGE REFERENCE
F - 1.0 // 0.01
c
- Voltage reference decoupling capacitance C
REF
ANALOG INPUT
V V
DDA
- 0 Single-ended, full- scale analog input voltage,
internal reference
de
V
ADCIN
V V
DDA
- -V
DDA
Differential, full-scale analog input voltage,
internal reference
df
mV (VREFP +
VREFN) / 2
25
- - Input common mode voltage, differential mode
g
VIN
CM
A 2.0 - - ADC input leakage current
h
I
L
k 2.5 - - ADC equivalent input resistance
h
R
ADC
pF 10 - - ADC equivalent input capacitance
h
C
ADC
500 - - Analog source resistance
h
R
S
SAMPLING DYNAMICS
MHz - 16 - ADC conversion clock frequency
i
F
ADC
MSPS 1 ADC conversion rate F
CONV
ns - 250 - ADC sample time T
S
s 1 ADC conversion time
j
T
C
ADC clocks - 2 - Latency from trigger to start of conversion T
LT
SYSTEM PERFORMANCE when using internal reference
bits 12 Resolution N
LSB 3.0 1.5 - Integral nonlinearity error, over full input range INL
LSB 1.0 0.8 - Differential nonlinearity error, over full input
range
DNL
LSB 15.0 5.0 - Offset error E
O
LSB 30.0 10.0 - Gain error
k
E
G
LSB 30.0 10.0 - Total unadjusted error, over full input range
l
E
T
DYNAMIC CHARACTERISTICS
mn
dB - 72 70 Signal-to-noise-ratio, Differential input, V
ADCIN
:
-20dB FS, 1KHz
o
SNR
D
dB - 75 72 Signal-to-distortion ratio, Differential input,
V
ADCIN
: -3dB FS, 1KHz
opq
SDR
D
dB - 70 68 Signal-to-Noise+Distortion ratio, Differential
input, V
ADCIN
: -3dB FS, 1KHz
ors
SNDR
D
dB - 65 60 Signal-to-noise-ratio, Single-ended input,
V
ADCIN
: -20dB FS, 1KHz
t
SNR
S
April 10, 2013 1210
Table 22-29. ADC Electrical Characteristics (continued)
dB - 72 70 Signal-to-distortion ratio, Single-ended input,
V
ADCIN
: -3dB FS, 1KHz
pq
SDR
S
dB - 63 60 Signal-to-Noise+Distortion ratio, Single-ended
input, V
ADCIN
: -3dB FS, 1KHz
rst
SNDR
S
TEMPERATURE SENSOR
V - 1.633 - Temperature sensor voltage, junction
temperature 25 C
V
TSENS
mV/C - -13.3 - Temperature sensor slope S
TSENS
C 5 - - Temperature sensor accuracy,
u
E
TSENS
a. V
REF+
= 3.3V, F
ADC
=16 MHz unless otherwise noted.
b. Best design practices suggest that static or quiet digital I/O signals be configured adjacent to sensitive analog inputs to
reduce capacitive coupling and cross talk. Analog signals configured adjacent to ADC input channels should meet the
same source resistance and bandwidth limitations that apply to the ADC input signals.
c. Two capacitors in parallel.
d. Internal reference is connected directly between V
DDA
and GNDA (VREFi = V
DDA
- GNDA). In this mode, E
O
, E
G
, E
T
, and
dynamic specifications are adversely affected due to internal voltage drop and noise on V
DDA
and GNDA.
e. V
ADCIN
= V
INP
- V
INN
f. With signal common mode as V
DDA
/2.
g. This parameter is defined as the average of the differential inputs.
h. As shown in Figure 22-17 on page 1212, R
ADC
is the total equivalent resistance in the input line all the way up to the sampling
node at the input of the ADC.
i. See System Clock Specification with ADC Operation on page 1202 for full ADC clock frequency specification.
j. ADC conversion time (Tc) includes the ADC sample time (Ts).
k. Gain error is measured at max code after compensating for offset. Gain error is equivalent to "Full Scale Error." It can be
given in % of slope error, or in LSB, as done here.
l. Total Unadjusted Error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors (offset
error, gain error and INL) at any given ADC code.
m. A low-noise environment is assumed in order to obtain values close to spec. The board must have good ground isolation
between analog and digital grounds and a clean reference voltage. The input signal must be band-limited to Nyquist
bandwidth. No anti-aliasing filter is provided internally.
n. ADC dynamic characteristics are measured using low-noise board design, with low-noise reference voltage ( < -74dB
noise level in signal BW) and low-noise analog supply voltage. Board noise and ground bouncing couple into the ADC
and affect dynamic characteristics. Clean external reference must be used to achieve shown specs.
o. Differential signal with correct common mode, applied between two ADC inputs.
p. SDR = -THD in dB.
q. For higher frequency inputs, degradation in SDR should be expected.
r. SNDR = S/(N+D) = SINAD (in dB)
s. Effective number of bits (ENOB) can be calculated from SNDR: ENOB = (SNDR - 1.76) / 6.02.
t. Single-ended inputs are more sensitive to board and trace noise than differential inputs; SNR and SNDR measurements
on single-ended inputs are highly dependent on how clean the test set-up is. If the input signal is not well-isolated on
the board, higher noise than specified could potentially be seen at the ADC output.
u. Note that this parameter does not include ADC error.
1211 April 10, 2013
Tiva
Figure 22-17. ADC Input Equivalency Diagram
Rs
Cs
C
ADC
Pin
V
S
I
L
Zs
5VESD
Clamp
R
ADC
InputPAD
Equivalent
Circuit Z
ADC
InputPAD
Equivalent
Circuit
R
ADC
InputPAD
Equivalent
Circuit
R
ADC
12bit
SARADC
Converter
Pin
Pin
Tiva Microcontroller
12bit
Word
V
ADCIN
ESDclamps
toGNDonly
April 10, 2013 1212
22.14 Synchronous Serial Interface (SSI)
Table 22-30. SSI Characteristics
No.
ns - - 40 SSIClk cycle time, as master
a
T
CLK_PER
S1
ns - - 150 SSIClk cycle time, as slave
b
ns - - 20 SSIClk high time, as master
T
CLK_HIGH
S2
ns - - 75 SSIClk high time, as slave
ns - - 20 SSIClk low time, as master
T
CLK_LOW
S3
ns - - 75 SSIClk low time, as slave
ns - - 1.25 SSIClk rise time
c
T
CLKR
S4
ns - - 1.25 SSIClk fall time
c
T
CLKF
S5
ns T
SYSCLK
- 0 Data from master valid delay time T
DMD
S6
ns - - 9.1 Data from master setup time, as master in
Tx mode
T
DMS
S7
ns - - 0.3 Data from master hold time, as master in
Tx mode
T
DMH
S8
ns 0.5*T
CLK_PER
- 17.1
- 2.8 Data to master setup time, as master in Rx
mode
T
DMS
S9
ns 0.5*T
CLK_PER
- 4.0
- 15.97 Data to master hold time, as master in Rx
mode
T
DMH
S10
ns - - 0.1666*T
CLK_PER
-
27.7
Data from slave setup time, as slave in Tx
mode
T
DSS
S11
ns - - 0.333*
TCLK_PER
+
5.5
Data from slave hold time, as slave in Tx
mode
T
DSH
S12
ns - - 0.1666*
TCLK_PER
-
2.96
Data to slave setup time, as slave in Rx
mode
T
DSS
S13
ns - - 0.333*
TCLK_PER
-
0.73
Data to slave hold time, as slave in Rx
mode
T
DSH
S14
a. In master mode, the system clock must be at least twice as fast as the SSIClk.
b. In slave mode, the system clock must be at least 6 times faster than the SSIClk.
c. Note that the delays shown are using 8-mA drive strength.
Figure 22-18. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
S2
S3
S1
S5
4 to 16 bits
S4
1213 April 10, 2013
Tiva
Figure 22-19. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
0
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
MSB LSB
S2
S3
S1
8-bit control
4 to 16 bits output data
S5 S4
Figure 22-20. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=0)
SSITx
(master)
SSIRx
(slave)
LSB
SSIClk
(SPO=1)
S2
S1
S5
SSIFss
LSB
S3
MSB
S6
S7 S8
S10 S9
MSB
S4
April 10, 2013 1214
22.15 Inter-Integrated Circuit (I
2
C) Interface
Table 22-31. I
2
C Characteristics
No.
system clocks - - 36 Start condition hold time T
SCH
I1
a
system clocks - - 36 Clock Low period T
LP
I2
a
ns (see note
b)
- - I2CSCL/I2CSDA rise time (V
IL
=0.5 V
to V
IH
=2.4 V)
T
SRT
I3
b
system clocks - - 2 Data hold time T
DH
I4
a
ns 10 9 - I2CSCL/I2CSDA fall time (V
IH
=2.4 V
to V
IL
=0.5 V)
T
SFT
I5
c
system clocks - - 24 Clock High time T
HT
I6
a
system clocks - - 18 Data setup time T
DS
I7
a
system clocks - - 36 Start condition setup time (for
repeated start condition only)
T
SCSR
I8
a
system clocks - - 24 Stop condition setup time T
SCS
I9
a
a. Values depend on the value programmed into the TPR bit in the I
2
C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I
2
C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA operate as open-drain-type signals, which the controller can only actively drive Low, the
time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 22-21. I
2
C Timing
I2CSCL
I2CSDA
I1
I2
I4
I6
I7 I8
I5
I3 I9
1215 April 10, 2013
Tiva
22.16 Analog Comparator
Table 22-32. Analog Comparator Characteristics
ab
V V
DDA
- GNDA Input voltage range V
INP
,V
INN
c
V V
DDA
- GNDA Input common mode voltage range V
CM
mV 50
d
10 - Input offset voltage V
OS
A 2.0 - - Input leakage current over full voltage range I
INP
,I
INN
dB - 50 - Common mode rejection ratio C
MRR
s 1.0
e
- - Response time T
RT
s 10 - - Comparator mode change to Output Valid T
MC
a. Best design practices suggest that static or quiet digital I/O signals be configured adjacent to sensitive analog inputs to
reduce capacitive coupling and cross talk.
b. To achieve best analog results, the source resistance driving the analog inputs, V
INP
and V
INN
, should be kept low.
c. The external voltage inputs to the Analog Comparator are designed to be highly sensitive and can be affected by external
noise on the board. For this reason, V
INP
and V
INN
must be set to different voltage levels during idle states to ensure the
analog comparator triggers are not enabled. If an internal voltage reference is used, it should be set to a mid-supply
level. When operating in Sleep/Deep-Sleep modes, the Analog Comparator module external voltage inputs set to different
levels (greater than the input offset voltage) to achieve minimum current draw.
d. Measured at VREF=100 mV.
e. Measured at external VREF=100 mV, input signal switching from 75 mV to 125 mV.
Table 22-33. Analog Comparator Voltage Reference Characteristics
V - V
DDA
/29.4 - Resolution in high range R
HR
V - V
DDA
/22.12 - Resolution in low range R
LR
V R
HR
/2 - - Absolute accuracy high range A
HR
V R
LR
/2 - - Absolute accuracy low range A
LR
DDA
= 3.3V, EN= 1, and
RNG = 0
Unit V
IREF
Max Ideal V
IREF
V
IREF
Min VREF Value
V 0.841 0.786 0.731 0x0
V 0.953 0.898 0.843 0x1
V 1.065 1.010 0.955 0x2
V 1.178 1.122 1.067 0x3
V 1.290 1.235 1.180 0x4
V 1.402 1.347 1.292 0x5
V 1.514 1.459 1.404 0x6
V 1.627 1.571 1.516 0x7
V 1.739 1.684 1.629 0x8
V 1.851 1.796 1.741 0x9
V 1.963 1.908 1.853 0xA
V 2.076 2.020 1.965 0xB
V 2.188 2.133 2.078 0xC
April 10, 2013 1216
DDA
= 3.3V, EN= 1, and
RNG = 0 (continued)
Unit V
IREF
Max Ideal V
IREF
V
IREF
Min VREF Value
V 2.300 2.245 2.190 0xD
V 2.412 2.357 2.302 0xE
V 2.525 2.469 2.414 0xF
DDA
= 3.3V, EN= 1, and
RNG = 1
Unit V
IREF
Max Ideal V
IREF
V
IREF
Min VREF Value
V 0.074 0.000 0.000 0x0
V 0.223 0.149 0.076 0x1
V 0.372 0.298 0.225 0x2
V 0.521 0.448 0.374 0x3
V 0.670 0.597 0.523 0x4
V 0.820 0.746 0.672 0x5
V 0.969 0.895 0.822 0x6
V 1.118 1.044 0.971 0x7
V 1.267 1.193 1.120 0x8
V 1.416 1.343 1.269 0x9
V 1.565 1.492 1.418 0xA
V 1.715 1.641 1.567 0xB
V 1.864 1.790 1.717 0xC
V 2.013 1.939 1.866 0xD
V 2.162 2.089 2.015 0xE
V 2.311 2.238 2.164 0xF
1217 April 10, 2013
Tiva
22.17 Current Consumption
22.17.1 Current Consumption
Table 22-36. Current Consumption
Unit
Max Nom System Clock
Conditions Parameter Name Parameter
85C 25C Clock Source Frequency
mA pending pending MOSC with PLL 80 MHz
V
DD
= 3.3 V
V
DDA
= 3.3 V
Peripherals = All ON
Run mode (Flash loop)
I
DD_RUN
mA pending pending PIOSC 16 MHz
V
DD
= 3.3 V
V
DDA
= 3.3 V
Peripherals = All OFF
V
DD
= 3.3 V
V
DDA
= 3.3 V
Run mode (SRAM loop)
V
DD
= 3.3 V
V
DDA
= 3.3 V
V
DD
= 3.6 V
V
DDA
= 3.6 V
Run mode I
DDA_RUN
a
April 10, 2013 1218
Table 22-36. Current Consumption (continued)
Unit
Max Nom System Clock
Conditions Parameter Name Parameter
85C 25C Clock Source Frequency
V
DD
= 3.3 V
V
DDA
= 3.3 V
LDO = 1.2 V
Sleep mode (FLASHPM =
0x0)
I
DD_SLEEP
mA pending pending PIOSC
b
16 MHz
b
1 MHz
V
DD
= 3.3 V
V
DDA
= 3.3 V
LDO = 1.2 V
b
16 MHz
b
1 MHz
V
DD
= 3.3 V
V
DDA
= 3.3 V
LDO = 1.2 V
Sleep mode (FLASHPM =
0x2)
b
16 MHz
b
1 MHz
V
DD
= 3.3 V
V
DDA
= 3.3 V
LDO = 1.2 V
b
16 MHz
b
1 MHz
mA pending pending PISOC 16 MHz V
DD
= 3.3 V
V
DDA
= 3.3 V
LDO = 1.2 V
Deep-sleep mode
(FLASHPM = 0x0)
I
DD_DEEPSLEEP
mA pending pending LFIOSC 30 kHz
DD
= 3.3 V
V
DDA
= 3.3 V
LDO = 1.2 V
DD
= 3.3 V
V
DDA
= 3.3 V
LDO = 1.2 V
Deep-sleep mode
(FLASHPM = 0x2)
DD
= 3.3 V
V
DDA
= 3.3 V
LDO = 1.2 V
a. The value for I
DDA_RUN
is included in the above values for I
DD_RUN
.
b. Note that if the MOSC is the source of the Run-mode system clock and is powered down in Sleep mode, wake time is increased by
T
MOSC_SETTLE
.
1219 April 10, 2013
Tiva
A Package Information
A.1 Orderable Devices
Figure A-1. Key to Part Numbers
T M4 C 1 SSS M Y PPP T Z R
Prefix
T = Qualified Device
X = Experimental Device
Core
M4 = ARM Cortex-M4
Tiva Series
C = Connected MCUs
Family
Part Number
SSS = Series part number
Program Memory
C = 32 KB
D = 64 KB
E = 128 KB
H = 256 KB
Data Memory
3 = 12 KB
5 = 24 KB
6 = 32 KB
Package

PZ = 100-pin LQFP
PGE = 144-pin LQFP
ZRB = 157-ball BGA

PM = 64-pin LQFP
Temperature
I =
=
40C to +85C
T 40C to +105C
Special Codes
Optional
Revision
For Experimental Device Only
Shipping Medium
R = Tape-and-reel
Omitted = Default shipping (tray or tube)
XX
The Package Option Addendum that follows lists the devices available to order. The addendum
reflects the most current data available for the designated devices. This data is subject to change
without notice and without revision of this document.
A.2 Part Markings
Tiva C Series microcontrollers are marked with an identifying number. This code contains the
following information:
The first and fifth lines contain internal tracking numbers.
The second and third lines indicate the part number, for example, TM4C123G on the second
line followed by H6PGEIRon the third line. Note that the second letter in the part number indicates
the product status. An M indicates the part is fully qualified and released to production; an X
indicates the part is experimental (pre-production) and requires a waiver. Experimental parts
also include a revision number in the part number, for example, XM4C123G followed by
H6PGEI5R.
The first two characters on the fourth line indicate the date code, followed by internal tracking
numbers. The two-digit date code indicates the last digit of the year, then the month. For example,
a 34 for the first two digits of the fourth line indicate a date code of April 2013.
A.3 Packaging Diagram
The Mechanical Data addendum that follows reflects the most current data available for the
designated devices. This data is subject to change without notice and without revision of this
document.
April 10, 2013 1220
Package Information
PACKAGE OPTION ADDENDUM
www.ti.com 12-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (C) Top-Side Markings
(4)
Samples
TM4C123AH6PMI ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 85 TM4C123A
H6PMI
TM4C123AH6PMIR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 85 TM4C123A
H6PMI

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MECHANICAL DATA

MTQF008A JANUARY 1995 REVISED DECEMBER 1996
1 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PM (S-PQFP-G64) PLASTIC QUAD FLATPACK
4040152/ C 11/96
32
17
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50 M 0,08
07
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
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Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
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Products Applications
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Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
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TM4C123x Block Diagram .......................................................................... 37

TM4C123x Block Diagram

processor family for better performance and power efficiency

Peripheral Driver Library

32-channel configurable DMA controller

-M4F architecture optimized for small-footprint embedded applications

processor family for better performance and power efficiency

TM4C123x microcontrollers 0x05

Boot Loader and vector table

32-channel configurable DMA controller

Driver Library uses a base address of 0x800 for the I

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