bq29330 PDF

LDO +
Reset
I
2
C
SMBus
HDQ
UART
Pack +
Pack
Discharge / Charge /
Precharge FETs
2-Tier Overcurrent
Protection
2K Bytes of
Data Flash
Fuse
Watchdog &
Protection Timing
C
e
ll
B
a
la
n
c
i
n
g
D
r
iv
e
System Interface System Interface
32.768 kHz
16 Dig GPIO & Peripherals
8 Dig GPIO or Analog GPI
2.5 V Nch FET Drive
(Charge Pumps)
RAM Configuration, Status
and Control Registers
24K x 22 Program
Flash
2K Bytes
of RAM
6K x 22
Mask ROM
C
e
ll,
B
a
t
a
n
d
P
a
c
k
V
o
lt
a
g
e
T
r
a
n
s
la
t
io
n
Precharge
Control
H
o
s
t
I
n
t
e
r
f
a
c
e
U
A
R
T
&
D
a
t
a
M
a
n
a
g
e
m
e
n
t
TOUT and LEDOUT
Power Support
Reset
Analog Output Drive
Oscillator and PLL
T1
Internal
Only
Standard Delta-Sigma A-to-D Converter
Integrating Delta-Sigma A-to-D Converter
b q 2 9 3 3 0
www.ti.com SLUS673E SEPTEMBER 2005REVISED MARCH 2012
2 - S E R I E S , 3 - S E R I E S , A N D 4 - S E R I E S C E L L L I T H I U M - I O N O R
L I T H I U M - P O L Y M E R B A T T E R Y P R O T E C T I O N A F E
C heck for S amples: b q 2 9 3 3 0
1F E A T U R E S
2 - S eries, 3 - S eries, or 4 - S eries C ell P rotection N M O S F E T D rive for C harge and D ischarge
C ontrol F E T s
C an D irectly I nterface with the b q 80 3 x- B ased H ost C ontrol can I nitiate S leep and S hip P ower
Gas Gauge F amily M odes
Watchdog and P O R for the H ost I ntegrated 2 .5- V, 16- mA L D O
P rovides I ndividual C ell Voltages and B attery I ntegrated 3 .3 - V, 2 5- mA L D O
Voltage to B attery M anagement H ost
S upply Voltage R ange from 4 .5 V to 2 8 V
C apab le of O peration With 5- m S ense
L ow S upply C urrent of 10 0 A T ypical
R esistor I ntegrated C ell B alancing D rive
I
2
C C ompatib le U ser I nterface A llows A ccess A P P L I C A T I O N S
to B attery I nformation
N oteb ook C omputers
P rogrammab le T hreshold and D elay for
M edical and T est E q uipment
O verload S hort C ircuit in D ischarge and S hort
I nstrumentation and M easurement S ystems
C ircuit in C harge
D E S C R I P T I O N
The bq29330 is a 2-series, 3-series, and 4-series cell lithium-ion battery pack full-protection analog front end
(AFE) IC that incorporates a 2.5-V, 16-mA and 3.3-V, 25-mA low dropout regulator (LDO). The bq29330 also
integrates an I
2
C-compatible interface to extract battery parameters such as battery voltage, individual cell
voltages, and control output status. Other parameters such as current protection thresholds and delays can also
be programmed into the bq29330 to increase the flexibility of the battery management system.
S Y S T E M D I A GR A M
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20052012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
b q 2 9 3 3 0
SLUS673E SEPTEMBER 2005REVISED MARCH 2012 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
D E S C R I P T I O N (C O N T I N U E D )
The bq29330 provides safety protection for overload, short circuit in charge, and short circuit in discharge
conditions and can also provide cell overvoltage, battery overvoltage and battery undervoltage protection with the
battery management host. In overload, short circuit in charge and short circuit in discharge conditions, the
bq29330 turns off the FET drive autonomously, depending on the internal configuration setting. The
communications interface allows the host to observe and control the status of the bq29330, enable cell
balancing, enter different power modes, set current protection levels, and set the blanking delay times.
Cell balancing of each cell can be performed via a cell bypass path integrated into the bq29330, which can be
enabled via the internal control register accessible via the I
2
C-compatible interface. The maximum bypass current
is set via an external series resistor and internal FET on resistance (typ. 400 ).
O R D E R I N G I N F O R M A T I O N
(1)
P A C KA GE
T
A
T S S O P (D B T )
(2 )
QF N (R S M )
(2 )
40C to 110C bq29330DBT bq29330RSM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The bq29330 can be ordered in tape and reel by adding the suffix R to the orderable part number, i.e., bq29330DBTR.
SPACER
T H E R M A L I N F O R M A T I O N
b q 2 9 3 3 0
T H E R M A L M E T R I C
(1)
T S S O P (D B T ) QF N (R S M ) U N I T S
3 0 P I N S 3 2 P I N S
JA, High K
Junction-to-ambient thermal resistance 81.4 37.4
JC(top)
Junction-to-case(top) thermal resistance 16.2 30.6
JB
Junction-to-board thermal resistance 34.1 7.7
C/W
JT
Junction-to-top characterization parameter 0.4 0.4
JB
Junction-to-board characterization parameter 33.6 7.5
JC(bottom)
Junction-to-case(bottom) thermal resistance N/A 2.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2 Submit Documentation Feedback Copyright 20052012, Texas Instruments Incorporated
Product Folder Link(s): bq29330
1
SRN
2
NC
3
SRP
4
VC5
5
VC4
6
VC3
7
VC2
8
VC1
9 1
0
1
1
1
2
1
3
1
4
1
5
1
6
24
WDI
23
TOUT
22
LEDOUT
21
VSS
20
NC
19
PMS
18
GPOD
17
ZVCHG
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
S
C
L
K
R
E
G
V
S
S
X
R
S
T
C
E
L
L
-
N
C
X
A
L
E
R
T
C
E
L
L
+
D
S
G
P
A
C
K
V
C
C
C
H
G
S
D
A
T
A
B
A
T
N
C
N
C
RSM PACKAGE
(TOP VIEW)
2
7
6
5
4
3
28
27
26
25
24
23
22
8
9
10
11
12
21
20
19
18
17
13
14
16
1
WDI
SCLK
REG
VSS
XRST
SRN
CELL-
NC
XALERT
TOUT
CELL+
PMS
GPOD
SRP
VC5
ZVCHG
VC3
VC2
DSG
PACK
VCC
CHG
SDATA
VC1
LEDOUT
VC4
VSS
15
BAT
NC
30
29
NC
TSSOP PACKAGE
(TOP VIEW)
b q 2 9 3 3 0
P A C KA GE O P T I O N P I N D I A GR A M S
P I N F U N C T I O N S
P I N
N A M E D B T N O . R S M N O .
CELL 1 28 Output of scaled value of the measured cell voltage.
CELL+ 2 29 Output of scaled value of the measured cell voltage.
REG 3 30 Integrated 2.5-V regulator output
VSS 4, 23 31,21 Power supply ground
XRST 5 32 Active-low output
SRN 6 1 Current sense terminal
Current sense positive terminal when charging relative to SRN; current sense negative terminal when
SRP 7 3
discharging relative to SRN
VC5 8 4 Sense voltage input terminal for most negative cell; balance current input for least positive cell.
Sense voltage input terminal for least positive cell, balance current input for least positive cell, and return
VC4 9 5
balance current for third most positive cell.
Sense voltage input terminal for third most positive cell, balance current input for third most positive cell,
VC3 10 6
and return balance current for second most positive cell.
Sense voltage input terminal for second most positive cell, balance current input for second most
VC2 11 7
positive cell, and return balance current for most positive cell.
Sense voltage input terminal for most positive cell, balance current input for most positive cell, and
VC1 12 8
battery stack measurement input
BAT 13 9 Device power supply input
CHG 14 11 Charge pump, charge N-CH FET gate drive
DSG 16 13 Charge pump output, discharge N-CH FET gate drive
PACK 17 15 PACK positive terminal and alternative power source
VCC 19 16 Power supply voltage
ZVCHG 20 17 Connect the precharge P-CH FET drive here
GPOD 21 18 NCH FET open-drain output
PMS 22 19 Determines CHG output state on POR
LEDOUT 24 22 3.3-V output for LED display power supply
TOUT 25 23 Provides thermistor bias current
Copyright 20052012, Texas Instruments Incorporated Submit Documentation Feedback 3
GND
OVERCURRENT
CELL1..4
SRP
SRN
OVERLOAD -
COMPARATOR
SHORT CIRCUIT
COMPARATOR
SHORT_CIRCUIT
DELAY
OPEN
DRAIN
OUTPUT
WATCHDOG
TIMER
GPOD
CELL VOLTAGE
TRANSLATION
POWER
MODE
CIRCUIT
DRIVE
CONTROL
CELL+
R
SNS
C
CELL
TOUT
R
THERM
C
THERM
THERMISTOR
CELL
SELECTION
SWITCHES
2.5-V LDO
POR
SHIP_ON
SLEEP_ON
VCC PACK
REG
C
REG
FET
LOGIC
NCH GATE
DRIVER
CHG_ON
DSG_ON
ZVCHG_ON
DSG CHG ZVCHG
PACK
GG VDD
VC1
VC2
VC5
CELL 3
CELL 4
VC3
VC4
CELL 1
CELL 2
GG TS
INPUT
GG ANALOG
INPUT
WDI
32 kHz INPUT
FROM GG
GG INTERFACE
SDATA
ALERT TO GG
OPEN DRAIN
OUTPUT
GG INTERFACE
SCLK
SDATA
SCLK
XALERT
S
E
R
I
A
L
I
N
T
E
R
F
A
C
E
STATUS
OUTPUT CTL
STATE CTL
FUNCTION CTL
CELL SEL
OLV
OLD
SCC
SCD
REGISTERS
R
ZVCHG
GATE DRIVER
0.975V
BAT/25
PACK/25
RST
GG RST
PACK+
2nd
Protection
3.3-V LDO
LEDOUT
C
LED
GG LED
INPUT
BAT
CELL
PMS
b q 2 9 3 3 0
P I N F U N C T I O N S (continued)
P I N
N A M E D B T N O . R S M N O .
Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog
WDI 26 24
clock.
SCLK 28 25 Open-drain serial interface clock with internal 10-k pullup to V
REG
SDATA 29 26 Open-drain bidirectional serial interface data with internal 10-k pullup to V
REG
Open-drain output used to indicate status register changes. With internal 100-k
XALERT 30 27
pullup to V
REG
2, 10, 12,
NC 15,18,27 Not electrically connected to the IC
14, 20
F U N C T I O N A L B L O C K D I A GR A M
No Power Supply
UVLO Mode
CHG: OFF
DSG: OFF
ZVCHG: OFF
VREG: OFF
RST: HIGH
I
2
C: Disabled
Current Protection: Disabled
VCELL: Disabled
Watchdog: Disabled
Therm, Output: Disabled
Power Supply to PACK
Normal Mode
CHG: ON
DSG: ON
ZVCHG: OFF
VREG/VLED: 2.5V/3.3V
RST: Driven low after t
RST
I
2
C: Enabled
Current Protection: Enabled
VCELL: Enabled
Watchdog: Enabled
Therm, Output: Enabled
LEGEND:
UVLO = Undervoltage Lock Out
KEY:
Disabled = OFF and cannot be changed via firmware
Enabled= Can be changed by firmware
Internal
V
LED < 2.3 V
Firmware
Command
32 kHz Input Halted
and t
WTO
expired
32 kHz Resumes
Internal V
LED
> 2.4 V
Power Supply to PACK
Current Protection Mode
CHG: OFF
DSG: OFF
ZVCHG: OFF
VREG/VLED: 2.5 V/3.3 V
I
2
C: Enabled
VCELL: Enabled
Watchdog: Enabled
WTO Mode
CHG: OFF
DSG: OFF
ZVCHG: OFF
RST: Pulsed
I
2
C: Enabled
VCELL: Enabled
Watchdog: Enabled
Ship Mode
CHG: OFF
DSG: OFF
ZVCHG: OFF
I2C: Disabled
Current Protection: Disabled
VCELL: Disabled
Watchdog: Disabled
Sleep Mode
CHG: OFF
DSG: OFF
ZVCHG: OFF
I
2
C: Enabled
VCELL: Enabled
Watchdog: Enabled
Firmware
Command
Firmware Command
& No Supply to PACK
Firmware
Command
Firmware
Command
32 kHz Input Halted
and t
WTO
expired
FirmwareCommand
VREG/VLED: 2.5 V/3.3 V
VREG/VLED: ON/ON
VREG/VLED: OFF/OFF
DSG: OFF
No supply PACK
voltage Mode
DSG: OFF
Firmware
Command
V > V or V for a period of t or t
Respectively, or V > V
SR OL SCD OL SCD
SR SCC
for a period
of t
SCC
b q 2 9 3 3 0
S A F E T Y S T A T E D I A GR A M
b q 2 9 3 3 0
A B S O L U T E M A XI M U M R A T I N GS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
b q 2 9 3 3 0 U N I T
Supply voltage range (VCC, BAT) 0.3 to 34
(VC1, VC2, VC3, VC4, PACK, PMS) 0.3 to 34
(VC5) 0.3 to 1.0
(SRP, SRN) 1.0 to 1.0
Input voltage range
(VC1 to VC2, VC2 to VC3, VC3 to VC4, VC4 0.3 to 8.5
to VC5)
(WDI, SCLK, SDATA) 0.3 to 8.5 V
(DSG,CHG) 0.3 to BAT
(ZVCHG) 0.3 to 34
(GPOD) 0.3 to 34
Output voltage range
(TOUT, SDATA, CELL, XALERT, XRST, 0.3 to 7
LEDOUT)
(CELL+) 0.3 to 7
Current for cell balancing 10 mA
Storage temperature range, T
stg
65 to 150 C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground of this device except VCnVC(n+1), where n=1, 2, 3, 4 cell voltage.
R E C O M M E N D E D O P E R A T I N G C O N D I T I O N S
M I N N O M M A X U N I T
Supply voltage ( VCC, BAT) 4.5 25 V
V
I(STARTUP)
Start up voltage (VCC, BAT) 5.5 V
VC1, VC2, VC3, VC4 0 VDD
VC5 0 0.5
V
I
Input voltage range SRP, SRN 0.5 0.5 V
VCn VC(n+1), (n=1, 2, 3, 4 ) 0 5.0
PACK, PMS 25
V
IH
0.8REG REG
Logic level input voltage SCLK, SDATA, WDI V
V
IL
0 0.2REG
V
O
Output voltage GPOD 25 V
XALERT, SDATA, XRST REG
V
O
Output voltage range V
CELL+, CELL 0.975
External 2.5-V REG capacitor C
REG
1.0 F
External LEDOUT capacitor C
LED
2.2 F
Extend CELL output capacitor C
CELL
0.1 F
IOL GPOD 1 mA
RPACK 1 k
Input frequency WDI 32.768 kHz
WDI high time 2 s
Operating temperature 25 85 C
T
A
Functional temperature 40 110 C
b q 2 9 3 3 0
E L E C T R I C A L C H A R A C T E R I S T I C S
S U P P L Y C U R R E N T , T
A
= 2 5C , C R E G = 1 F , C
L
= 2 .2 F , VC C or B A T = 14 V (unless otherwise noted)
P A R A M E T E R T E S T C O N D I T I O N S M I N T Y P M A X U N I T
No load at REG, LEDOUT, TOUT, XALERT, SCLK, SDATA, T
A
= 25C 140 190 A
ZVCHG= off, WDI = 32 kHz
I
CC1
Supply Current 1
T
A
= 40C
VMEN = on, VC5 = VC4 = VC3 = VC2 = VC1 = 0 V
220 A
to 110C
select VC5 = VC4 = 0 V
No load at REG, LEDOUT TOUT,
T
A
= 40C
I
CC2
Supply Current 2 XALERT, SCLK, SDATA. ZVCHG = off, WDI = 32 kHz, 105 185 A
to 110C
VMEN = off
CHG, DSG and ZVCHG = off, T
A
= 40C
I
(SLEEP)
Sleep current 30 50 A
REG = on, VMEN = off, WDI no clock, SLEEP = 1 to 110C
CHG, DSG and ZVCHG = off,
T
A
= 40C
I
(SHUTDOWN)
Shutdown mode REG = off, VMEN = off, WDI no clock, 0.1 1 A
to 110C
VPACK = 0 V, VC1 = VC2 = VC3 = VC4 = 3.5 V
2 .5 V L D O , T
A
= 2 5C , C R E G = 1 F , C
L
= 2 .2 F , VC C or B A T = 14 V, I
O U T 3 3
= 0 mA (unless otherwise noted)
Regulator output 4.5 V < VCC or BAT 25 V, I
OUT25
16 mA T
A
= 40C V
V
(REG)
2.41 2.5 2.59
voltage to 110C
Regulator output VCC or BAT = 14 V, I
OUT25
= 2 mA
T
A
= 40C
V
(EGTEMP)
change with 0.2%
to 110C
temperature
V
(REGLINE)
Line regulation 5.4 V VCC or BAT 25 V, I
OUT25
= 2 mA T
A
= 25C 3 10 mV
VCC or BAT = 14 V, 0.2 mA I
OUT25
2 mA T
A
= 25C 7 15 mV
V
(REGLOAD)
Load regulation
OUT25
16 mA T
A
= 25C 15 50 mV
VCC or BAT = 14 V, REG = 2 V T
A
= 25C 16 75
I
(REGMAX)
Current limit mA
VCC or BAT = 14 V, REG = 0 V T
A
= 25C 5 45
3 .3 V L E D , T
A
= 2 5C , C R E G = 1.0 F , C
L
= 2 .2 F , VC C or B A T = 14 V, I
O U T 2 5
= 0 mA (unless otherwise noted)
4.5 V < VCC or BAT 25 V, I
OUT33
10 mA 3 3.3 3.6
Regulator output T
A
= 40C
V
O(LED)
V
voltage to 110C
6.5 V < VCC or BAT 25 V, I
OUT33
25 mA 3 3.3 3.6
Regulator output VCC or BAT = 14 V, I
OUT33
= 2 mA
T
A
= 40C
V
(LEDEMP)
change with 0.2%
to 110C
temperature
V
(LEDLINE)
Line regulation 5.4 V VCC or BAT 25 V, I
OUT33
= 2 mA T
A
= 25C 3 10 mV
OUT33
2 mA 7 15
V
(LEDLOAD)
Load regulation T
A
= 25C mV
OUT33
25 mA 40 100
VCC or BAT = 14 V, REG = 3 V 25 125
I
(LEDMAX)
Current limit T
A
= 25C mA
VCC or BAT = 14 V, REG = 0 V 12 50
T H E R M I S T O R D R I VE , T
A
= 2 5C , C R E G = 1 F , C
L
VTOUT I
TOUT
= 0 mA 2.4 2.6 V
TOUT Pass-element I
TOUT
= 1 mA at TOUT pin, T
A
= 40C
R
DS(ON)
50 100
series resistance R
DS(ON)
= [V
REG
V
OUT
(TOUT)] / 1 mA to 110C
S H U T D O WN WA KE , T
A
= 2 5C , C R E G = 1 F , C
L
PACK Exit shutdown VCC or BAT = 14 V, PACK = 1.4 V
V
STARTUP
1 A
threshold
P O R , T
A
= 2 5C , C R E G = 1 F , C
L
V
POR
VREGTH 3% 1.8 3% V
Hysteresis
50 150 250 mV
(V
regth+
V
regth
)
b q 2 9 3 3 0
E L E C T R I C A L C H A R A C T E R I S T I C S (C ontinued)
C E L L VO L T A GE M O N I T O R , T
A
= 2 5C , C R E G = 1 F , C
L
V
Cn
V
Cn+1
= 0 V, 8 V VDD 25 V 0.950 0.975 1
V
(CELLOUT)
V
V
Cn
V
Cn+1
= 4.5 V, 8 V VDD 25 V 0.275 0.3 0.325
REF Mode
(1)
, 8 V VDD 25 V 1% 0.975 1% V
CELL output
Mode
PACK 2% PACK/18 2% V
[Register Address = 0x03, b1(PACK) = 1, b0( VMEN) = 1]
Mode
BAT 2% BAT/18 2% V
[Register Address = 0X03, b6(BAT) = 1, b0 ( VMEN) = 1]
CMRR Common mode rejection CELL max to CELL min 40 dB
V
(CELLSLEW)
CELL output rise Min to Max 10% to 90% 9 ms
K = {CELL output (VC5 = 0 V, VC4 = 4.5 V)
0.147 0.150 0.153
CELL output (VC5 = VC4 = 0 V)} / 4.5
K CELL scale factor
K = {CELL output (VC2 = 13.5 V, VC1 = 18 V)
0.147 0.150 0.153
CELL output (VC2 = VC1 = 13.5 V)} / 4.5
I
(VCELLOUT)
Drive current V
Cn
V
Cn+1
= 0 V , Vcell = 0 V, T
A
= 40to 110 12 18 A
CELL output offset error CELL output (VC2 = 18 V, VC1 = 18 V)
V
ICR
1 mV
CELL output (VC2 = VC1 = 0 V)
R
(BAL)
Cell balance internal resistance R
DS(ON)
for internal FET switch at V
DS
= 2 V 50% 400 50%
(1) Register Address = 0x04, b2(CAL0) = b3(CAL1) = 1, Register Address = 0x03, b0(VMEN) = 1
C U R R E N T P R O T E C T I O N D E T E C T I O N , T
A
= 2 5C , C R E G = 1 F , C
L
RSNS = 0 50 205
V
(OLT)
OL detection threshold voltage range, typical
(1)
mV
RSNS = 1 25 102.5
RSNS = 0 5
V
(OLT)
OL detection threshold voltage program step mV
RSNS = 1 2.5
RSNS = 0 100 475
SCC detection threshold voltage range, typical
V
(SCCT)
mV
(2)
RSNS = 1 50 237.5
RSNS is set in
FUNCTION_CTL register
RSNS = 0 25
V
(SCCT)
SCC detection threshold voltage program step mV
RSNS = 1 12.5
RSNS = 0 100 475
SCD detection threshold voltage range,
V
(SCDT)
mV
typical
(3)
RSNS = 1 50 237.5
RSNS = 0 25
V
(SCDT)
SCD detection threshold voltage program step mV
RSNS = 1 12.5
V
OL
= 25 mV (typ) 15 25 35
V
OL(acr)
V
OL
= 100 mV (typ) (RSNS = 0,1) 90 100 110 mV OL detection threshold voltage accuracy
(1)
V
OL
= 205 mV (typ) 185 205 225
V
SCC
= 50 mV (typ) 30 50 70
V
(SCC_acr)
V
SCC
= 200 mV (typ) (RSNS = 0,1) 180 200 220 mV SCC detection threshold voltage accuracy
(2)
V
SCC
= 475 mV (typ) 428 475 523
V
SCD
= 50 mV (typ) 30 50 70
V
(SCD_acr)
V
SCD
= 200 mV (typ) (RSNS = 0,1) 180 200 220 mV SCD detection threshold voltage accuracy
(3)
V
SCD
= 475 mV (typ) 426 475 523
(1) See OLV register for setting detection threshold
(2) See SCC register for setting detection threshold
(3) See SCD register for setting detection threshold
b q 2 9 3 3 0
E L E C T R I C A L C H A R A C T E R I S T I C S (C ontinued)
F E T D R I VE C I R C U I T , T
A
= 2 5C , C R E G = 1 F , C
L
V
O(FETOND)
= V
(DSG)
Vpack T
A
= 25C 7.5 12 15.5
V
VGS connect 10 M
T
A
= 40C to 110C 8 12 16
Output voltage, charge,
V
O(FETON)
and discharge FETs on
V
O(FETONC)
= V
(CHG)
V
BAT
T
A
= 25C 7.5 12 15.5
V
VGS connect 10 M
T
A
= 40C to 110C 8 12 16
V
(ZCHG)
ZVCHG clamp voltage BAT = 4.5 V 3.3 3.5 3.7 V
VFETOND = VDSG 0.2
V
O(FETOF
Output voltage, charge,
Vpack
V
F)
and discharge FETs off
VFETONC = VCHG VBAT 0.2
V
(CHG)
: Vpack Vpack + 4 V 400 1000
t
r
Rise time C
L
= 4700 pF s
V
(DSG)
: VBAT VBAT + 4 V 400 1000
V
(CHG)
: Vpack + VCHG (FETON) pack + 1 V 40 200
t
f
Fall time C
L
= 4700 pF s
V
(DSG)
: VC1 + VDSG (FETON) VC1 + 1 V 40 200
L O GI C , T
A
= 2 5C , C R E G = 1 F , C
L
XALERT 60 100 200
R
(PUP)
Internal pullup resistance SDATA, SCLK T
A
= 40C to 110C 6 10 20 k
XRST 1 3 6
XALERT 0.2
SDATA, I
OUT
= 200 A 0.4
Low Logic level output
GPOD, I
OUT
= 50 A 0.6
V
OL
T
A
= 40C to 110C V
voltage
VCC or BAT = 7 V, 0.4
VREG = 1.5 V,
XRST, I
OUT
= 200 A
V
IH
SCLK (hysteresis input) Hysteresis 450 mV
A C E L E C T R I C A L C H A R A C T E R I S T I C S
T
A
= 25C, CREG = 1 F, C
L
= 2.2 F, VCC or BAT = 14 V (unless otherwise noted)
t
WDTINT
WDT start up detect time 250 500 1000 ms
t
WDWT
WDT detect time 50 100 150 s
t
RST
XRST Active high time 100 250 560 s
t
su(STA)
SCLK
SDATA
SCLK
SDATA
SCLK
SDATA
t
w(H)
t
w(L)
t
f
t
r
t
r
t
f
Start
Condition
SDA
Input
SDA
Change
Stop
Condition
t
h(STA)
t
h(DAT)
t
su(DAT)
t
h(ch)
Start Condition
t
v
1 2 3 7 8 9
MSB ACK
Stop Condition
t
su(STOP)
1 2 3 7 8 9
MSB ACK
t
su(BUF)
b q 2 9 3 3 0
A C T I M I N G R E QU I R E M E N T S (I
2
C compatib le serial interface)
T
A
= 25C, CREG = 1 F, VCC or BAT = 14 V (unless otherwise noted)
P A R A M E T E R M I N M A X U N I T
t
r
SCLK, SDATA rise time 1000 ns
t
f
SCLK, SDATA fall time 300 ns
t
w(H)
SCLK pulse width high 4 s
t
w(L)
SCLK pulse width low 4.7 s
t
su(STA)
Setup time for start condition 4.7 s
t
h(STA)
Start condition hold time after which first clock pulse is generated 4 s
t
su(DAT)
Data setup time 250 ns
t
h(DAT)
Data hold time 0 s
t
su(STOP)
Setup time for Stop condition 4 s
t
su(BUF)
Time the bus must be free before new transmission can start 4.7 s
t
v
Clock low to data out valid 900 ns
t
h(CH)
Data out hold time after clock low 10 ns
f
SCL
Clock frequency 0 100 kHz
b q 2 9 3 3 0
F U N C T I O N A L D E S C R I P T I O N
L O W D R O P O U T P U T R E GU L A T O R (L E D O U T )
The inputs for this regulator can be derived from the VCC or BAT terminals. The output is a fixed voltage of
typically 3.3 V with the minimum output capacitance for stable operation of 2.2 F and is also internally current
limited. This output is used for LED drive, power supply source for REG (2.5 V) and bq29330 internal circuit.
During normal operation, the regulator limits output current to typically 50 mA. Until the internal regulator circuit is
correctly powered, the DSG and CHG FET drives are low (FETs = OFF).
L O W D R O P O U T P U T R E GU L A T O R (R E G)
The inputs for this regulator can be derived from the LED (3.3 V). The output is typically 2.5 V with the minimum
output capacitance for stable operation of 1 F and is also internally current limited. During normal operation, the
regulator limits output current to typically 50 mA.
I N I T I A L I ZA T I O N
From a shutdown situation, the bq29330 requires a voltage greater that start-up voltage (V
STARTUP
) applied to the
PACK pin to enable its integrated regulator and provide the regulators power source. Once the REG output is
stable, the power source of the regulator is switched to VCC.
After the regulator has started, it then continues to operate through the VCC input. If the VCC input is below the
minimum operating range, then the bq29330 will not operate if the supply to the PACK input is removed.
If the voltage at VLED falls below about 2.3 V, the internal circuit turns off the FETs and disables all controllable
functions including the REG, LEDOUT, and TOUT outputs.
The initial state of the CHG and DSG FET drive is low (OFF) and the ZVCHG FET drive is low (ON).
O VE R L O A D D E T E C T I O N
The overload detection is used to detect abnormal currents in the discharge direction. This feature is used to
protect the pass FETs, cells, and any other inline components from excessive discharge current conditions. The
detection circuit also incorporates a blanking delay before driving the control for the pass FETs to the OFF state.
The overload sense voltage is set in the OLV register, and delay time is set in the OLD register. The thresholds
can be individually programmed from 50 mV to 205 mV in 5-mV steps with the default being 50 mV.
If the RSNS bit in the FUNCTION_CTL register is set to 1, then the voltage threshold, programmable step size,
and hysteresis is divided by 2.
S H O R T C I R C U I T I N C H A R GE A N D S H O R T C I R C U I T I N D I S C H A R GE D E T E C T I O N
The short current circuit in charge and short circuit in discharge detections are used to detect severe abnormal
current in the charge and discharge directions, respectively. This safety feature is used to protect the pass FETs,
cells, and any other inline components from excessive current conditions. The detection circuit also incorporates
a blanking delay before driving the control for the pass FETs to the OFF state. The short circuit in charge
threshold and delay time are set in the SCC register. The short circuit in discharge threshold and delay time are
set in the SCD register. The short-circuit thresholds can be programmed from 100 mV to 475 mV in 25-mV steps.
If the RSNS bit in the FUNCTION_CTL register is set to 1, then the voltage threshold, programmable step size,
and hysteresis is divided by 2.
O VE R L O A D , S H O R T C I R C U I T I N C H A R GE A N D S H O R T C I R C U I T I N D I S C H A R GE D E L A Y
The overload delay (default = 1 ms) allows the system to momentarily accept a high current condition without
disconnecting the supply to the load. The delay time can be increased via the OLD register which can be
programmed for a range of 1 ms to 31 ms with 2-ms steps.
The short circuit in charge and short circuit in discharge delays (default = 0 s) are programmable in the SCC
and SCD registers, respectively. These registers can be programmed from 0 s to 915 s with 61-s steps.
b q 2 9 3 3 0
O VE R L O A D , S H O R T C I R C U I T I N C H A R GE A N D S H O R T C I R C U I T I N D I S C H A R GE R E S P O N S E
When an overload, short circuit in charge, or short circuit in discharge fault is detected, the FETs are turned off.
The STATUS (b0b3) register reports the details of overload, short circuit in charge or short-circuit discharge.
The respective STATUS (b0b3) bits are set to 1 and the XALERT output is triggered. This condition is latched
until the STATE_CONTROL (b7) is set and then reset. If a FET is turned on after resetting STATE_CONTROL
(b0) and the error condition is still present on the system, then the device again enters the protection response
state.
2 - , 3 - , or 4 - C E L L C O N F I GU R A T I O N
In a 2-cell configuration, VC1 and VC2 are shorted to VC3. In a 3-cell configuration, VC1 is shorted to VC2.
C E L L VO L T A GE
The cell voltage is translated to allow a system host to measure individual series elements of the battery. The
series element voltage is translated to a GND-based voltage equal to 0.15 0.003 of the series element voltage.
This provides a range from 0 to 4.5 V. The translation output is presented between CELL+ and CELL pins of
the bq29330 and is inversely proportional to the input using the following equation.
Where, V
(CELLOUT)
= K V
(CELLIN)
+ 0.975 (V)
Programming CELL_SEL (b1, b0) selects the individual series element. The CELL_SEL (b3, b2) selects the
voltage monitor mode, cell monitor, offset, etc.
C A L I B R A T I O N O F C E L L VO L T A GE M O N I T O R A M P L I F I E R GA I N
The cell voltage monitor amplifier has an offset, and to increase accuracy, this can be calibrated.
The following procedure shows how to measure and calculate the offset as an example.
S tep 1
Set CAL1=1, CAL0=1, VMEN=1.
VREF is trimmed to 0.975 V within 1%; measuring VREF eliminates its error.
Measure internal reference voltage VREF from VCELL directly.
VREF = measured reference voltage
S tep 2
Set CAL1=0, CAL0=1, CELL1=0, CELL0=0, VMEN=1.
The output voltage includes the offset and represented by:
V
OUT(4-5)
= VREF + (1 + K) V
OS
(V)
Where K = CELL Scaling Factor
V
OS
= Offset voltage at input of the internal operational amplifier
S tep 3
Measure scaled REF voltage through VCELL amplifier.
The output voltage includes the scale factor error and offset and is represented by:
V
(OUTR)
= VREF + (1 + K) VOS K VREF (V)
S tep 4
Calculate (V
OUT(4-5)
V
(OUTR)
) / VREF.
The result is the actual scaling factor, K
ACT
and is represented by:
K
ACT
= (V
OUT(4-5)
V
(OUTR)
) / VREF = (VREF + (1 + K) V
OS
) (VREF + (1 + K) V
OS
K
VREF)/VREF = K VREF/VREF = K
b q 2 9 3 3 0
S tep 5
Calculate the actual offset value where:
V
OS(ACT)
= (V
(OUTR)
VREF) / (1 + K
ACT
)
S tep 6
Calibrated cell voltage is calculated by:
VCn VC(n+1) = { VREF + (1 + K
ACT
) V
OS(ACT)
V
(CELLOUT)
}/K
ACT
= {V
OUT(4-5)
V
(CELLOUT)
}/K
ACT
To seek greater accuracy, it is better to measure V
OS(ACT)
for each cell voltage.
Measure V
OUT(3-4)
, V
OUT(2-3)
, V
OUT(1-2)
,
VC4 VC5 = {V
OUT(4-5)
V
(CELLOUT)
}/K
ACT
VC3 VC4 = {V
OUT(3-4)
V
(CELLOUT)
}/K
ACT
VC2 VC3 = {V
OUT(2-3)
V
(CELLOUT)
}/K
ACT
VC1 VC2 = {V
OUT(1-2)
V
(CELLOUT)
}/K
ACT
B A T T E R Y P A C K A N D B A T T E R Y S T A C K M E A S U R E M E N T S
The PACK (battery pack) and VC1 (battery stack) inputs can be translated to the CELL+, CELL outputs of the
bq29330 through control bits in the FUNCTION_CONTROL register. If PACK is set, then the input at the PACK
is divided by 18 and presented at the CELL+, CELL outputs. If the BAT bit is set, then the input to VC1 is
divided by 18 and presented at the CELL+, CELL outputs. If setting both bits at the same time, VC1 is
presented at the CELL+, CELL outputs.
C E L L B A L A N C E C O N T R O L
The cell balance control allows a small bypass path to be controlled for any one series element. The purpose of
this bypass path is to reduce the current into any one cell during charging to bring the series elements to the
same voltage. Series resistors placed between the input pins and the positive series element nodes control the
bypass current value. Individual series element selection is made using bits 4 through 7 of CELL_SEL register.
Series input resistors between 500 and 1 k are recommended for effective cell balancing.
XA L E R T (XA L E R T )
XALERT is driven Low, when WDF, OL, SCC, or SCD OC are detected. To clear XALERT, toggle (from 0, set to
1, then reset to 0) STATE_CONTROL, LTCLR (bit 7), then read the STATUS register.
T H E R M I S T O R D R I VE C I R C U I T (T O U T )
The TOUT pin can be enabled to drive a thermistor from REG. The typical thermistor resistance is 10 k at
25C. The default state for this is OFF to conserve power. The maximum output impedance is 100 . TOUT is
enabled in FUNCTION_CONTROL register (bit 3).
GE N E R A L P U R P O S E O P E N D R A I N D R I VE C I R C U I T (GP O D )
The General Purpose Open Drain output has 1-mA current source drive with a maximum output voltage of 25 V.
The OD output is enabled or disabled by OUTPUT_CONTROL register (bit 4) and has a default state of OFF.
FET Control Access
by Host
LTCLR Bit
Fault Flag Set
XALERT Output
Fault Timeout
Expired
STATUS Register
Read
REG Output
RST Output
t
RST
V
REGTH+
V
REGTH-
b q 2 9 3 3 0
L A T C H C L E A R (L T C L R )
When a protection fault occurs, the state is latched. To clear the fault flag, toggle (from 0, set 1, then reset to 0)
the LTCLR bit in the STATE_CONTROL register (bit 7). The OL, SCC, SCD, and WDF bits are unlatched by this
function. The FETs can now be controlled by programming the OUTPUT_CONTROL register, and the XALERT
output can be cleared by reading the STATUS register.
F igure 1. L T C L R and XL A E R T C lear T iming
P O R and WA T C H D O G R E S E T (XR S T )
The XRST pin is activated by activation of the REG output. This holds the host in reset for the duration of the
t
RST
period, allowing the VREG to stabilize before the host is released from reset. When the regulator power is
down, XRST is active below the regulators voltage of 1.8 V. Also, when a watchdog fault is detected, the XRST
is also activated to ensure a valid reset of the battery management host.
F igure 2 . XR S T T iming C hart P ower U p and P ower D own
WA T C H D O G I N P U T (WD I )
The WDI input is required as a time base for delay timing when determining fault detection and is used as part of
the system watchdog.
Initially, the watchdog monitors the host oscillator start-up; if there is no response from the host within t
WDINT
of
t
RST
expiring, then the bq29330 turns CHG, DSG, and ZVCHG FETs off. It then activates the XRST output in an
attempt to reset the host.
Once the watchdog has been started during this wake-up period, it monitors the host for an oscillation stop
condition which is defined as a period of t
WDWT
where no clock input is received. If an oscillator stop condition is
identified, then the watchdog turns the CHG, DSG, and ZVCHG FETs off. The bq29330 then activates the XRST
output in an attempt to reset the host.
REG Output
REG Output
WDI Input
XALERT
FET Control
Access by Host
t
RST
t (500 ms)
DWTINIT
t (500 ms)
DWTINIT
CHG, DSG, and
ZVCHG = OFF
WDRST = L
REG Output
REG Output
WDI Input
XALERT
FET Control
Access by Host
CHG, DSG, and
ZVCHG = OFF
t (500 ms)
DWTINIT
t (500 ms)
DWTINIT
t
RST
t
RST
t
RST
WDRST = H
b q 2 9 3 3 0
If the host clock oscillation is started after the reset, the bq29330 still has the WDF flag set until it is cleared. See
the LTCLR section for further details on clearing the fault flags.
During Sleep mode, the watchdog function is not disabled.
F igure 3 . Watchdog T iming C hart WD I F ault at S tartup
REG Output
REG Output
WDI Input
XALERT
FET Control
Access by Host
CHG, DSG, and
ZVCHG = OFF
t (500 ms)
DWTINIT
t (500 ms)
DWTINIT
t
RST
WDRST = L
t
WDWT Normal Operation
REG Output
REG Output
WDI Input
XALERT
FET Control
Access by Host
t (500 ms)
DWTINIT
t (500 ms)
DWTINIT
t
WDWT Normal Operation
t
RST
t
RST
t
RST
CHG, DSG, and
ZVCHG = OFF
WDRST = H
b q 2 9 3 3 0
F igure 4 . Watchdog T iming C hart WD I F ault A fter S tartup
D S G and C H G N C H F E T D R I VE R C O N T R O L
The bq29330 drives either the DSG or CHG FET off if an OL, SCC, or SCD safety threshold is breached
depending on the current direction. The host can force any FET on or off only if the bq29330 integrated
protection control allows.
The default-state of the FET drive is off. A host can control the FET drive by programming OUTPUT_CONTROL
(b2...b0), where b0 is used to control the discharge FET, b1 is used to control the charge FET, and b2 is used to
control the ZVCHG FET. These controls are only valid when not in the initialized state. The CHG drive FET can
be powered by PACK and the DSG FET can be powered by BAT.
When the bq29330 powers down, the NCH FET drivers power down to GND causing the FETs to turn off.
b q 2 9 3 3 0
P R E C H A R GE A N D 0 V C H A R GI N G
The bq29330 supports both a charger that has a precharge mode and one that does not. The bq29330 also
supports charging even when the battery falls to 0 V. In order to charge, the charge FET (CHG) must be turned
on to create a current path. When the V
BAT
is ~0 V, the V
(PACK)
is as low as the battery voltage. In this case, the
supply voltage for the device is too low to operate.
P O WE R M O D E S
The bq29330 has three power modes, normal, sleep, and ship. The following table outlines the operational
functions during these power modes.
T ab le 1. O utlines the O perational F unctions
P O WE R T O E N T E R P O WE R M O D E T O E XI T P O WE R M O D E M O D E D E S C R I P T I O N
M O D E
Normal STATE_CONTROL, SLEEP( b0) = 0 and The battery is in normal operation with protection,
STATE_CONTROL, SHIP ( b1) = 0 power management and battery monitoring
functions available and operating.
The supply current of this mode varies as the host
can enable and disable various power
management features.
Sleep STATE_CONTROL, SLEEP( b0) = 1 and STATE_CONTROL, CHG, DSG, and ZVCHG OFF, OL, SCC, and SCD
STATE_CONTROL, SHIP ( b1) = 0 SLEEP( b0) = 0 function is disabled.
Cell AMP, GPOD , CELL BAL, and WDF is not
disabled
Ship STATE_CONTROL, SHIP ( b1) = 1 Supply voltage to PACK The bq29330 is completely shut down as in the
and supply at the PACK < V
WAKE
Supply sleep mode. In addition, the REG output is
disabled, I
2
C interface is powered down, and
memory is not valid.
VO L T A GE B A S E D E XI T F R O M S H U T D O WN
If a voltage greater than V
STARTUP
is applied to the PACK pin, then the bq29330 exits shutdown and enters
normal mode.
C O M M U N I C A T I O N S
The I
2
C-compatible serial communications provides read and write access to the bq29330 data area. The data is
clocked via separate data (SDATA) and clock (SCLK) pins. The bq29330 acts as a slave device and does not
generate clock pulses. Communication to the bq29330 can be provided from GPIO pins or an I
2
C supporting port
of a host system controller. The slave address for the bq29330 is 7 bits, and the value is 0100 000 (0x20).
(M S B ) I 2 C A ddress +R /W b it (L S B )
(M S B ) I 2 C A ddress (0 x2 0 ) (L S B )
Write 0 1 0 0 0 0 0 0
Read 1
The bq29330 does NOT have the following functions compatible with the I
2
C specification.
The bq29330 is always regarded as a slave.
The bq29330 does not support the General Code of the I
2
C specification, and therefore will not return an ACK
but may return a NACK.
The bq29330 does not support the Address Auto Increment, which allows continuous reading and writing.
The bq29330 will allow data to be written or read from the same location without re-sending the location
address.
SCLK
SDATA
Stop Start
A6 R7 A5 R6 A4 R5 D7 D6 D5 D0 R0 R/W ACK
ACK
ACK A0
0 0 0 0

Register Address Slave Address Data
Note: Slave = bq29330
Stop

SCLK
A6 A5 A0 R/W R/W ACK ACK
ACK
R7 A6 D7 D6 D0 NACK A0 R6 R0 SDATA
Start
0 0 0 1 0
Start
Slave Address Register Address Slave Address
Slave Drives
The Data
Master
Drives
NACK and
Stop

SCLK
SDATA
0
Stop Stop
A6 A6 A5 A5 A0 R/W R/W ACK ACK ACK R7 D7 D0 NACK A0 R6 R0
Start
Start Register Address Slave Slave Address
Slave Drives
The Data
Master
Drives
NACK and
Stop
b q 2 9 3 3 0
F igure 5. I
2
C - B us Write to b q 2 9 3 3 0
F igure 6. I
2
C - B us R ead from b q 2 9 3 3 0 : P rotocol A
F igure 7. I
2
C - B us R ead from b q 2 9 3 3 0 : P rotocol B
R E GI S T E R M A P
The bq29330 has nine addressable registers. These registers provide status, control, and configuration
information for the battery protection system.
N A M E A D D R T Y P E D E S C R I P T I O N
STATUS 0x00 R Status register
OUTPUT_CONTROL 0x01 R/W Output pin control from system host and external pin status
STATE_CONTROL 0x02 R/W State control
FUNCTION_CONTROL 0x03 R/W Function control
CELL _SEL 0x04 R/W Battery cell select for cell translation and balance bypass and select mode for calibration
OLV 0x05 R/W Overload voltage threshold
OLD 0x06 R/W Overload delay time
SCC 0x07 R/W Short circuit in charge current threshold voltage and delay
SCD 0x08 R/W Short circuit in discharge current threshold voltage and delay
b q 2 9 3 3 0
B I T M A P
N A M E A D D R T Y P E
B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0
STATUS 0x00 R 0 0 0 ZV WDF OL SCC SCD
OUTPUT_ CONTROL 0x01 R/W 0 0 PMS_CHG GPOD XZV CHG DSG LTCLR
STATE_ CONTROL 0x02 R/W 0 0 0 RSNS WDRST WDDIS SHIP SLEEP
FUNCTION_ CONTROL 0x03 R/W 0 0 0 0 TOUT BAT PACK VMEN
CELL _SEL 0x04 R/W CB3 CB2 CB1 CB0 CAL1 CAL0 CELL1 CELL0
OLV 0x05 R/W 0 0 0 OLV4 OLV3 OLV2 OLV1 OLV0
OLD 0x06 R/W 0 0 0 0 OLD3 OLD2 OLD1 OLD0
SCC 0x07 R/W SCCD3 SCCD2 SCCD1 SCCD0 SCCV3 SCCV2 SCCV1 SCCV0
SCD 0x08 R/W SCDD3 SCDD2 SCDD1 SCDD0 SCDV3 SCDV2 SCDV1 SCDV0
S T A T U S : S tatus register
S T A T U S R E GI S T E R (0 x0 0 )
7 6 5 4 3 2 1 0
0 0 0 ZV WDF OL SCC SCD
The STATUS register provides information about the current state of the bq29330.
STATUS b0 (SCD): This bit indicates a short circuit in discharge condition.
0 = Voltage below the short circuit in discharge threshold (default).
1 = Voltage greater than or equal to the short circuit in discharge threshold.
STATUS b1 (SCC): This bit indicates a short circuit in charge condition in the charge direction.
0 = Voltage below the short circuit in charge threshold (default).
1 = Voltage greater than or equal to the short circuit in charge threshold.
STATUS b2 (OL): This bit indicates an overload condition.
0 = Voltage less than or equal to the overload threshold (default).
1 = Voltage greater than overload threshold.
STATUS b3 (WDF): This bit indicates a watchdog fault condition has occurred.
0 = 32-kHz oscillation is normal (default).
1 = 32-kHz oscillation stopped or not started, and the watchdog has timed out.
STATUS b4 (ZV): This bit indicates ZVCHG output is clamped.
0 = ZVCHG pin is not clamped (default).
1 = ZVCHG pin is clamped.
STATUS b5, b6, b7: Reserved
O U T P U T _C O N T R O L : O utput control register
O U T P U T _C O N T R O L R E GI S T E R (0 x0 1)
7 6 5 4 3 2 1 0
0 0 PMS_CHG GPOD XZV CHG DSG LTCLR
The OUTPUT_CONTROL register controls the outputs of the bq29330 and can show the state of the external pin
corresponding to the control.
OUTPUT_ CONTROL b0 (LTCLR): When a fault is latched, this bit releases the fault latch when toggled from 0
to 1 and back to 0 (default =0).
0 = (default)
0->1 ->0 clears the fault latches, allowing STATUS to be cleared on its next read.
b q 2 9 3 3 0
OUTPUT_ CONTROL b1 (DSG): This bit controls the external discharge FET.
0 = Discharge FET is off and is controlled by the system host (default).
1 = Discharge FET is on, and the bq29330 is in normal operating mode.
OUTPUT_ CONTROL b2 (CHG): This bit controls the external charge FET.
0 = Charge FET is off, and is controlled by the system host (default).
1 = Charge FET is on, and the bq29330 is in normal operating mode.
OUTPUT_CONTROL b3(ZV): This bit enables or disables the precharge function.
0 = ZVCHG FET is on, and is controlled by the system host (default).
1 = ZVCHG FET is off, and the bq29330 is in normal operating mode.
OUTPUT_CONTROL b4 (GPOD): This bit enables or disables the GPOD output.
0 = GPOD is high impedance (default).
1 = GPOD output is active (GND).
OUTPUT_CONTROL b5 (PMS_CHG): This bit enables the CHG output for 0-V charge, when PMS terminal is
connected to Pack.
0 = CHG FET is off (When PMS = GND, default).
1 = CHG FET is on by connecting CHG and PACK terminal. (When PMS = PACK, default).
S T A T E _C O N T R O L : S tate control register
S T A T E _C O N T R O L R E GI S T E R (0 x0 2 )
7 6 5 4 3 2 1 0
0 0 0 RSNS WDRST WDDIS SHIP SLEEP
The STATE_CTL register controls the outputs of the bq29330 and can be used to clear certain states.
STATE_CONTROL b0 (SLEEP): This bit is used to enter the sleep power mode.
0 = bq29330 exits sleep mode (default).
1 = bq29330 enters the sleep mode.
STATE_CONTROL b1 (SHIP): This bit is used to enter the ship power mode when Pack supply voltage is not
applied.
0 = bq29330 is in normal mode (default).
1 = bq29330 enters ship mode when pack voltage is removed.
STATE_CONTROL b2 (WDDIS): This bit is used to enable the watchdog timer.
0 = Watchdog timer is enabled (default).
1 = Watchdog timer is disabled.
STATE_CONTROL b3 (WDRST): This bit is used to enable the reset for GC, when watchdog timer is active.
0 = Reset output is disabled, when watchdog timer is active (default).
1 = 2 Times reset output is enabled, when watchdog timer is active.
STATE_CONTROL b4 (RSNS): This bit sets the OL, SCC, and SCD thresholds into a range suitable for a low
sense resistor value by dividing the OLV, SCCV, and SCDV selected voltage thresholds by 2.
0 = Current protection voltage threshold as programmed (default)
1 = Current protection voltage thresholds divided by 2 as programmed
STATE_CONTROL b6..7 (0): These bits are not used and should be set to 0.
b q 2 9 3 3 0
F U N C T I O N _C O N T R O L : F unction control register
F U N C T I O N _C T L R E GI S T E R (0 x0 3 )
7 6 5 4 3 2 1 0
0 0 0 0 TOUT BAT PACK VMEN
The FUNCTION_CONTROL register enables and disables features of the bq29330.
FUNCTION_CONTROL b0 (VMEN): This bit enables or disables the cell and battery voltage monitoring
function.
0 = Disable voltage monitoring (default). CELL output is pulled down to GND level.
1 = Enable voltage monitoring
FUNCTION_CONTROL b1 (PACK): This bit is used to translate the PACK input to the CELL+, CELL pins
when VMEN = 1. The PACK input voltage is divided by 18 and is presented on CELL+, CELL pins regardless
of the CELL_SEL register settings.
0 = CELL_SEL (b0, b1) settings determine CELL+, CELL output when VMEN = 1(default).
1 = PACK input translated to CELL output regardless of CELL_SEL (b0, b1) selection when VMEN=1
FUNCTION_CTL b2 (BAT): This bit is used to translate the BAT input to the CELL+, CELL pins when
VMEN=1. The VC5 input voltage is divided by 18 and is presented on CELL+, CELL regardless of the
CELL_SEL register settings.
0 = CELL_SEL (b0, b1) settings determine CELL+, CELL output when VMEN = 1(default).
1 = BAT input translated to CELL+, CELL output regardless of CELL_SEL (b0, b1) selection when
VMEN = 1
This bit priority is higher than PACK(b1).
FUNCTION_CONTROL b3 (TOUT): This bit controls the power to the thermistor.
0 = Thermistor power is off (default).
1 = Thermistor power is on.
C E L L _S E L : C ell select register
C E L L _S E L R E GI S T E R (0 x0 4 )
7 6 5 4 3 2 1 0
CB3 CB2 CB1 CB0 CAL1 CAL0 CELL1 CELL0
This register determines cell selection for voltage measurement and translation, cell balancing, and the
operational mode of the cell voltage monitoring.
CELL_SEL b0b1 (CELL0CELL1): These two bits select the series cell for voltage measurement translation.
C E L L 1 C E L L 0 S E L E C T E D C E L L
0 0 VC4VC5, Bottom series element (default)
0 1 VC4VC3, Second lowest series element
1 0 VC3VC2, Second highest series element
1 1 VC1VC2, Top series element
b q 2 9 3 3 0
CELL_SEL b2b3 (CAL1, CAL0): These bits determine the mode of the voltage monitor block
C A L 1 C A L 0 S E L E C T E D M O D E
0 0 Cell translation for selected cell (default)
0 1 Offset measurement for selected cell
1 0 Monitor the VREF value for gain calibration
Monitor the V
REF
directly value for gain calibration,
1 1
bypassing the translation circuit
CELL_SEL b4b7 (CB0 CB3): These 4 bits select the series cell for cell balance bypass path.
CELL_SEL b4 (CB0): This bit enables or disables the bottom series cell balance charge bypass path.
0 = Disable bottom series cell balance charge bypass path (default)
1 = Enable bottom series cell balance charge bypass path
CELL_SEL b5 (CB1): This bit enables or disables the second lowest series cell balance charge bypass path.
0 = Disable series cell balance charge bypass path (default)
1 = Enable series cell balance charge bypass path
CELL_SEL b6 (CB2): This bit enables or disables the second highest cell balance charge bypass path.
CELL_SEL b7 (CB3): This bit enables or disables the highest series cell balance charge bypass path.
O L V: O verload Voltage threshold register
O L V R E GI S T E R (0 x0 5)
7 6 5 4 3 2 1 0
0 0 0 OLV4 OLV3 OLV2 OLV1 OLV0
OLV (b4b0): These four bits select the value of the overload threshold with a default of 0000.
OLV (b5b7): These bits are not used and should be set to 0.
OLV (b4b0) configuration bits with corresponding voltage threshold
(1)
0x00 0.050 V 0x08 0.090 V 0x10 0.130 V 0x18 0.170 V
0x01 0.055 V 0x09 0.095 V 0x11 0.135 V 0x19 0.175 V
0x02 0.060 V 0x0a 0.100 V 0x12 0.140 V 0x1a 0.180 V
0x03 0.065 V 0x0b 0.105 V 0x13 0.145 V 0x1b 0.185 V
0x04 0.070 V 0x0c 0.110 V 0x14 0.150 V 0x1c 0.190 V
0x05 0.075 V 0x0d 0.115 V 0x15 0.155 V 0x1d 0.195 V
0x06 0.080 V 0x0e 0.120 V 0x16 0.160 V 0x1e 0.200 V
0x07 0.085 V 0x0f 0.125 V 0x17 0.165 V 0x1f 0.205 V
(1) If RSNS bit is FUNCTION_CONTROL = 1, then the corresponding voltage threshold is divided by 2.
b q 2 9 3 3 0
O L D : O verload D elay time configuration register
O L D R E GI S T E R (0 x0 7)
7 6 5 4 3 2 1 0
0 0 0 0 OLD3 OLD2 OLD1 OLD0
OLD(b3b0): These four bits select the value of the delay time for overload with a default of 0000.
0x00 1 ms 0x04 9 ms 0x08 17 ms 0x0c 25 ms
0x01 3 ms 0x05 11 ms 0x09 19 ms 0x0d 27 ms
0x02 5 ms 0x06 13 ms 0x0a 21 ms 0x0e 29 ms
0x03 7 ms 0x07 15 ms 0x0b 23 ms 0x0f 31 ms
S C C : S hort C ircuit I n C harge configuration register
S C C R E GI S T E R (0 x0 8)
7 6 5 4 3 2 1 0
SCCD3 SCCD2 SCCD1 SCCD0 SCCV3 SCCV2 SCCV1 SCCV0
This register selects the short circuit in charge voltage threshold and delay.
SCCV (b3b0) : These lower nibble bits select the value of the short circuit in charge voltage threshold with 0000 as the default.
(1)
0x00 0.100 V 0x04 0.200 V 0x08 0.300 V 0x0c 0.400 V
0x01 0.125 V 0x05 0.225 V 0x09 0.325 V 0x0d 0.425 V
0x02 0.150 V 0x06 0.250 V 0x0a 0.350 V 0x0e 0.450 V
0x03 0.175 V 0x07 0.275 V 0x0b 0.375 V 0x0f 0.475 V
(1) If RSNS bit is FUNCTION_CTL = 1, then the corresponding voltage threshold is divided by 2.
SCCD (b7b4): These upper nibble bits select the value of the short circuit in charge delay time. Exceeding the short circuit in charge
voltage threshold for longer than this period turns off the CHG and DSG outputs. 0000 is the default.
0x00 0 s 0x04 244 s 0x08 488 s 0x0c 732 s
0x01 61 s 0x05 305 s 0x09 549 s 0x0d 793 s
0x02 122 s 0x06 366 s 0x0a 610 s 0x0e 854 s
0x03 183 s 0x07 427 s 0x0b 671 s 0x0f 915 s
S C D : S hort C ircuit I n D ischarge configuration register
S C D R E GI S T E R (0 x0 8)
7 6 5 4 3 2 1 0
SCDD3 SCDD2 SCDD1 SCDD0 SCDV3 SCDV2 SCDV1 SCDV0
This register selects the short circuit in discharge voltage threshold and delay.
SCDV(b3b0) : These lower nibble bits select the value of the short circuit in discharge voltage threshold with 0000 as the default.
(1)
0x00 0.100 V 0x04 0.200 V 0x08 0.300 V 0x0c 0.400 V
0x01 0.125 V 0x05 0.225 V 0x09 0.325 V 0x0d 0.425 V
0x02 0.150 V 0x06 0.250 V 0x0a 0.350 V 0x0e 0.450 V
0x03 0.175 V 0x07 0.275 V 0x0b 0.375 V 0x0f 0.475 V
(1) If RSNS bit is FUNCTION_CTL = 1, then the corresponding voltage threshold is divided by 2.
SCCD (b7b4): These upper nibble bits select the value of the short circuit in charge delay time. Exceeding the Short Circuit in charge
voltage threshold for longer than this period will turn off the CHG and DSG outputs. 0000 is the default.
0x00 0 s 0x04 244 s 0x08 488 s 0x0c 732 s
0x01 61 s 0x05 305 s 0x09 549 s 0x0d 793 s
0x02 122 s 0x06 366 s 0x0a 610 s 0x0e 854 s
0x03 183 s 0x07 427 s 0x0b 671 s 0x0f 915 s
b q 2 9 3 3 0
R E VI S I O N H I S T O R Y
C hanges from O riginal (S eptemb er 2 0 0 5) to R evision A P age
Changed package name From: SSOP(DBT) To: TSSOP(DBT) in the Ordering Information Table .................................... 2
Changed the SCLK pin description From: Open-drain bi-directional serial interface clock with internal 10-k pullup
to V
REG
To: Open-drain serial interface clock with internal 10-k pullup to V
REG
................................................................. 4
Changed Supply Current 2 From: XALERT, SCLK, SDATA. ZVCHG = off, Input WDI, To: XALERT, SCLK, SDATA.
ZVCHG = off, WDI = 32 kHz, ................................................................................................................................................ 7
Changed Calibration of Cell Voltage Monitor Amplifier Gain, Step 3 - From: Set CAL1=1, CAL0=1, CELL1=0,
CELL0=0, VMEN=1. To: Set CAL1=1, CAL0=0, CELL1=0, CELL0=0, VMEN=1. ............................................................. 12
C hanges from R evision A (D ecemb er 2 0 0 5) to R evision B P age
Deleted the QFN(RHB) package from the Ordering Information Table, the Package Option Pin Diagrams, and the
Pin Functions table. .............................................................................................................................................................. 2
C hanges from R evision B (A ugust 2 0 0 6) to R evision C P age
Changed BAT Pin description From: Charge pump, charge N-CH FET gate drive To: Device power supply input ............ 3
Changed ELECTRICAL CHARACTERISTICS - CURRENT PROTECTION DETECTION section - positive and
negative values were not properly displayed. ....................................................................................................................... 8
Changed Figure 3 - Watchdog Timing Chart WDI Fault at Start-up ................................................................................ 15
Added Figure 4 - Watchdog Timing Chart WDI Fault After Startup ................................................................................ 16
C hanges from R evision C (M arch 2 0 0 9 ) to R evision D P age
Added the RSM package to the Ordering Information Table ............................................................................................... 2
Added the RSM pin out package illustration. ........................................................................................................................ 3
C hanges from R evision D (July 2 0 0 9 ) to R evision E P age
Changed the device numbers in the Ordering Information Table From: bq29330ADBT and bq29330ARSM To:
bq29330DBT and bq29330RSM ........................................................................................................................................... 2
Added Thermal Information .................................................................................................................................................. 2
Changed the AC Timing Requiremenst Table, f
SCL
- Clock frequency MAX value From: 400 kHz To: 100 kHz ............... 10
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
BQ29330DBT ACTIVE TSSOP DBT 30 60 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ29330DBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS &
no Sb/Br)
BQ29330DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS &
no Sb/Br)
BQ29330DBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
BQ29330DBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ29330DBTR TSSOP DBT 30 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
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