JUNE 2012: Amiete - Et (New Scheme)
JUNE 2012: Amiete - Et (New Scheme)
JUNE 2012: Amiete - Et (New Scheme)
___________________
Code: AE74
JUNE 2012
PLEASE WRITE YOUR ROLL NO. AT THE SPACE PROVIDED ON EACH PAGE
IMMEDIATELY AFTER RECEIVING THE QUESTION PAPER.
NOTE: There are 9 Questions in all.
Question 1 is compulsory and carries 20 marks. Answer to Q.1 must be written in
the space provided for it in the answer book supplied and nowhere else.
The answer sheet for the Q.1 will be collected by the invigilator after 45 minutes of
the commencement of the examination.
Out of the remaining EIGHT Questions answer any FIVE Questions. Each question
carries 16 marks.
Any required data not explicitly given, may be suitably assumed and stated.
Q.1
(2 10)
(B) Compactness
(D) High Noise margin.
(B) Vds
(C) L
(D) E ds
ins 0 WL
D
W
(C) ins 0
L
(A)
(B)
Code: AE74
(B) 8:1
(D) 4:1
(B) 2
(D) 4
(B) 40K
(D) 90K
(B) 2.5 Ne
(D) 7 Ne
Q.3
(8)
a. Derive an expression for Pull-up to Pull-down ratio for an n-MOS inverter driven
by another n-MOS inverter.
(8)
b. Draw CMOS inverter circuit. Also compare CMOS & Bipolar transistor
parameter.
(8)
Q.4
(8)
(8)
Code: AE74
Q.5
(4)
Q.7
Q.8
Q.9
(8)
(10)
(ii) Frequency
(iv) Current diversity
(6)
(8)
(8)
a. Draw the structure of Six- transistor static CMOS memory-cell and explain its
Read and Write operations.
(10)
b. Discuss about Ground rules for successful design of VLSI chip.
(6)
(6)
(4)
c. Write Sequential logic circuit containing scan path for testing and explain its
operation briefly.
(6)