Chapter 3 Mano Questions
Chapter 3 Mano Questions
Chapter 3 Mano Questions
Chapter 3
Gate-Level Minimization
A
B
UDP_02467
C
F
FIGURE 3.37
Schematic for Circuit with_UDP_02467
Note that the variables listed on top of the table are part of a comment and are shown
only for clarity. The system recognizes the variables by the order in which they are listed
in the input declaration. A user-defined primitive can be instantiated in the construction
of other modules (digital circuits), just as the system primitives are used. For example,
the declaration
Circuit _with _UDP_ 02467 (E, F, A, B, C, D);
will produce a circuit that implements the hardware shown in Figure 3.37.
Although Verilog HDL uses this kind of description for UDPs only, other HDLs and
computer-aided design (CAD) systems use other procedures to specify digital circuits
in tabular form. The tables can be processed by CAD software to derive an efficient gate
structure of the design. None of Verilogs predefined primitives describes sequential
logic. The model of a sequential UDP requires that its output be declared as a reg data
type, and that a column be added to the truth table to describe the next state. So the
columns are organized as inputs : state : next state.
In this section, we introduced the Verilog HDL and presented simple examples to
illustrate alternatives for modeling combinational logic. A more detailed presentation
of Verilog HDL can be found in the next chapter. The reader familiar with combinational circuits can go directly to Section 4.12 to continue with this subject.
PROBLEMS
(Answers to problems marked with * appear at the end of the text.)
3.1*
3.2
3.3*
Problems
3.4
3.5
119
(f)
3.7
3.8
Find the minterms of the following Boolean expressions by first plotting each function in
a map:
(a)* xy + yz + xy z
(b)* CD + ABC + ABD + ABD
(c) wyz + wx + wxz
(d) AB + ACD + BCD + BCD
3.9
Find all the prime implicants for the following Boolean functions, and determine which
are essential:
(a)* F (w, x, y, z) = (0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
(b)* F (A, B, C, D) = (0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
(c)
3.11 Convert the following Boolean function from a sum-of-products form to a simplified
product-of-sums form.
F 1x, y, z2 = 10, 1, 2, 5, 8, 10, 132
120
Chapter 3
Gate-Level Minimization
x z + y z + yz + xy
ACD + CD + AB + ABCD
1A + B + D2 1A + B + C2 1A + B + C2 1B + C + D2
BCD + ABC + ACD
3.14 Give three possible ways to express the following Boolean function with eight or fewer literals:
F = ABCD + ABCD + ABC + ACD
3.15 Simplify the following Boolean function F, together with the dont-care conditions d, and
then express the simplified function in sum-of-minterms form:
(a) F 1x, y, z2 = 10, 1, 4, 5, 62
d1x, y, z2 = 12, 3, 72
(c) F 1A, B, C, D2 = 15, 6, 7, 12, 14, 15,2 (d) F 1A, B, C, D2 = 14, 12, 7, 2, 10,2
d1A, B, C, D2 = 13, 9, 11, 152
d1A, B, C, D2 = 10, 6, 82
3.16 Simplify the following functions, and implement them with two-level NAND gate circuits:
(a)
(b)
(c)
(d)
F 1A, B, C, D2
F 1A, B, C, D2
F 1A, B, C2 =
F 1A, B, C, D2
3.17* Draw a NAND logic diagram that implements the complement of the following function:
F 1A, B, C, D2 = 10, 1, 2, 3, 6, 10, 11, 142
3.18 Draw a logic diagram using only two-input NOR gates to implement the following function:
F 1A, B, C, D2 = (A { B)'(C { D)
3.19 Simplify the following functions, and implement them with two-level NOR gate circuits:
(a)* F = wx + y z + w yz
(b) F 1w, x, y, z2 = 10, 3, 12, 152
(c)
3.20 Draw the multiple-level NOR circuit for the following expression:
CD1B + C2A + 1BC + DE2
3.21 Draw the multiple-level NAND circuit for the following expression:
w 1x + y + z2 + xyz
3.22 Convert the logic diagram of the circuit shown in Fig. 4.4 into a multiple-level NAND circuit.
3.23 Implement the following Boolean function F, together with the dont-care conditions d,
using no more than two NOR gates:
F 1A, B, C, D2 = 12, 4, 10, 12, 14,2
d1A, B, C, D2 = 10, 1, 5, 82
Assume that both the normal and complement inputs are available.
Problems
121
3.24 Implement the following Boolean function F, using the two-level forms of logic (a) NANDAND, (b) AND-NOR, (c) OR-NAND, and (d) NOR-OR:
F 1A, B, C, D2 = 10, 4, 8, 9, 10, 11, 12, 142
3.25 List the eight degenerate two-level forms and show that they reduce to a single operation.
Explain how the degenerate two-level forms can be used to extend the number of inputs
to a gate.
3.26 With the use of maps, find the simplest sum-of-products form of the function F = fg, where
f = abc + cd + acd + bcz
and
g = 1a + b + c + d2 1b + c + d2 1a + c + d2
3.27 Show that the dual of the exclusive-OR is also its complement.
3.28 Derive the circuits for a three-bit parity generator and four-bit parity checker using an odd
parity bit.
3.29 Implement the following four Boolean expressions with three half adders:
D
E
F
G
=
=
=
=
A{B{C
A BC + AB C
ABC + (A + B) C
ABC
3.30* Implement the following Boolean expression with exclusive-OR and AND gates:
F = AB CD + A BC D + AB C D + A BC D
3.31 Write a Verilog gate-level description of the circuit shown in
(a) Fig. 3.20(a)
(b) Fig. 3.20(b)
(c) Fig. 3.21(a)
(d) Fig. 3.21(b)
(e) Fig. 3.24
(f) Fig. 3.25
3.32 Using continuous assignment statements, write a Verilog description of the circuit
shownin
(a) Fig. 3.20(a)
(b) Fig. 3.20(b)
(c) Fig. 3.21(a)
(d) Fig. 3.21(b)
(e) Fig. 3.24
(f) Fig. 3.25
3.33 The exclusive-OR circuit of Fig. 3.30(a) has gates with a delay of 3 ns for an inverter, a 6ns
delay for an AND gate, and a 8 ns delay for an OR gate. The input of the circuit goes from
xy = 00 to xy = 01.
(a) Determine the signals at the output of each gate from t = 0 to t = 50 ns.
(b) Write a Verilog gate-level description of the circuit, including the delays.
(c) Write a stimulus module (i.e., a test bench similar to HDL Example 3.3), and simulate
the circuit to verify the answer in part (a).
3.34 Using continuous assignments, write a Verilog description of the circuit specified by the
following Boolean functions:
Out_1 = 1A + B2C 1C + D2
Out_2 = 1CD + BCD + CD2 1A + B2
Out_3 = 1AB + C2D + BC
Write a test bench and simulate the circuits behavior.
122
Chapter 3
Gate-Level Minimization
3.35* Find the syntax errors in the following declarations (note that names for primitive gates
are optional):
module Exmpl-3(A, B, C, D, F)
inputs
A, B, C, Output D, F,
output
B
and
g1(A, B, D);
not
(D, A, C),
OR
(F, B; C);
endmodule;
// Line 1
// Line 2
// Line 3
// Line 4
// Line 5
// Line 6
// Line 7
3.36 Draw the logic diagram of the digital circuit specified by the following Verilog description:
(a) module Circuit_A (A, B, C, D, F);
input
A, B, C, D;
output
F;
wire
w, x, y, z, a, d;
or
(x, B, C, d);
and
(y, a ,C);
and
(w, z ,B);
and
(z, y, A);
or
(F, x, w);
not
(a, A);
not
(d, D);
endmodule
(b) module Circuit_B (F1, F2, F3, A0, A1, B0, B1);
output
F1, F2, F3;
input
A0, A1, B0, B1;
nor
(F1, F2, F3);
or
(F2, w1, w2, w3);
and
(F3, w4, w5);
and
(w1, w6, B1);
or
(w2, w6, w7, B0);
and
(w3, w7, B0, B1);
not
(w6, A1);
not
(w7, A0);
xor
(w4, A1, B1);
xnor
(w5, A0, B0);
endmodule
(c) module Circuit_C (y1, y2, y3, a, b);
output y1, y2, y3;
input a, b;
assign y1 = a || b;
and (y2, a, b);
assign y3 = a && b;
endmodule
References
123
3.37 A majority logic function is a Boolean function that is equal to 1 if the majority of the
variables are equal to 1, equal to 0 otherwise.
(a) Write a truth table for a four-bit majority function.
(b) Write a Verilog user-defined primitive for a four-bit majority function.
3.38 Simulate the behavior of Circuit_with_UDP_02467, using the stimulus waveforms shown
in Fig. P3.38.
A
t, ns
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
B
t, ns
C
t, ns
D
t, ns
FIGURE P3.38
Stimulus waveforms for Problem 3.38
3.39 Using primitive gates, write a Verilog model of a circuit that will produce two outputs,
sand c, equal to the sum and carry produced by adding two binary input bits a and b (e.g.,
s = 1 and c = 0 if a = 0 and b = 1). (Hint: Begin by developing a truth table for s and c.)
REFERENCES
1.
2.
3.
4.
5.
6.
Bhasker, J. 1997. A Verilog HDL Primer. Allentown, PA: Star Galaxy Press.
Ciletti, M. D. 1999. Modeling, Synthesis and Rapid Prototyping with the Verilog HDL.
Upper Saddle River, NJ: Prentice Hall.
Hill, F. J., and G. R. Peterson. 1981. Introduction to Switching Theory and Logical Design,
3rd ed. New York: John Wiley.
IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language (IEEE Std. 1364-1995). 1995. New York: The Institute of Electrical and
Electronics Engineers.
Karnaugh, M. A Map Method for Synthesis of Combinational Logic Circuits. Transactions
of AIEE, Communication and Electronics. 72, part I (Nov. 1953): 59399.
Kohavi, Z. 1978. Switching and Automata Theory, 2nd ed. New York: McGraw-Hill.
124
Chapter 3
7.
8.
9.
Gate-Level Minimization
Mano, M. M. and C. R. Kime. 2004. Logic and Computer Design Fundamentals, 3rd ed.
Upper Saddle River, NJ: Prentice Hall.
McCluskey, E. J. 1986. Logic Design Principles. Englewood Cliffs, NJ: Prentice-Hall.
Palnitkar, S. 1996. Verilog HDL: A Guide to Digital Design and Synthesis. Mountain View,
CA: SunSoft Press (a Prentice Hall title).