Keyboard Controller Data Sheet: Revision 1.1 Dec. 2008

KB926D
Keyboard Controller
Data Sheet
Revision 1.1
Dec. 2008
ENE RESERVES THE RIGHT TO AMEND THIS DOCUMENT WITHOUT NOTICE AT ANY TIME. ENE
ASSUMES NO RESPONSIBILITY FOR ANY ERRORS APPEAR IN THE DOCUMENT, AND ENE DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF ENE PRODUCTS
INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, OR
INFRINGEMENT OF ANY PATENTS, COPYRIGHTS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
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Copyright2008, ENE Technology Inc. All rights reserved.
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KB926D Keyboard Controller Datasheet
ENE Technology Inc.

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This document is the property of ENE Technology Corp. It should be returned once unused.
Please do not make any copy of this document and deliver to others.
only. Please do not transfer it to other companies.
THIS DOCUMENT CONTAINS CONFIDEMTIAL

INFORMATION OF ENE PRODUCTS. ANY
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IMPACT ENES COMPETITIVE ADVANTAGE.
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Copyright2008, ENE Technology Inc.
ii
Revision
Revision
Description
Date
0.1
0.2
1. First Release
1. Fix some ESB description, decoding rangeetc
2. ECCFG[1] reserved
1. Change part number to D1
1. Update power-on state of GPIO0B(Pin 17)
1. The register PLLCFG reset value is 0x70 and the output
frequency is 38MHz
1. Adding programming model/sample code
2008/4
2008/4
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1. Adding interrupt enable/pending flag table In 4.18.1.3

2. Adding PCICLK and CLKRUN# description in 4.1.3
3. Part number update
1. Adding more description for CLKRUN# and PCICLK
1. Update I/O cell characteristics
1. Update I/O cell information
2. Update EnE to ENE
3. Restore ECCFG[1]
1. Add a suggestion on I/O Cell OCT04H application
2. Update the reset default states of SPICS#(Pin 128), SPICLK(Pin
126), MOSI(Pin 120), MISO(Pin 119) and PCIRST#(Pin 13)
3. Add new part number KB926QFD3
4. Remove section 4.12.4 and 4.12.5
5. Add 5.7.1 SPI Flash Timing spec.
2008/4
2008/5
2008/6
2008/7
2008/8
2008/8
2008/9
2008/10
2008/12
ii
CONTENT
CONTENT ............................................................................................................... III
1. GENERAL DESCRIPTION .................................................................................. 0
1.1 OVERVIEW ........................................................................................................ 0
1.2 FEATURES ........................................................................................................ 1
1.3 COMPARISON (KB926C VS. KB926D ) .............................................................. 6
1.4 BLOCK DIAGRAM .............................................................................................. 7
2. PIN ASSIGNMENT AND DESCRIPTION ............................................................ 8
2.1 KB926D 128-PIN LQFP DIAGRAM TOP VIEW ..................................................... 8
2.2 KB926D 128 LFBGA BALL MAP ...................................................................... 9
2.3 KB926D PIN ASSIGNMENT SIDE A ................................................................... 10
2.4 KB926D PIN ASSIGNMENT SIDE B................................................................... 11
2.5 KB926D PIN ASSIGNMENT SIDE C................................................................... 12
2.6 KB926D PIN ASSIGNMENT SIDE D................................................................... 13
2.7 I/O CELL DESCRIPTIONS .................................................................................. 14
2.7.1 I/O Buffer Table ..................................................................................... 14
3. PIN DESCRIPTIONS ......................................................................................... 15
3.1 HARDWARE TRAP ........................................................................................... 15
3.2 PIN DESCRIPTIONS BY FUNCTIONS ................................................................... 16
3.2.1 Low Pin Count I/F Descriptions. ......................................................... 16
3.2.2 SPI Flash I/F Descriptions ................................................................... 16
3.2.3 PS/2 I/F Descriptions............................................................................ 16
3.2.4 Internal Keyboard Encoder (IKB) Descriptions ................................. 17
3.2.5 SMBus Descriptions ............................................................................ 17
3.2.6 FAN Descriptions ................................................................................. 17
3.2.7 Pulse Width Modulation (PWM) Descriptions .................................... 17
3.2.8 Analog-to-Digital Converter Descriptions .......................................... 17
3.2.9 Digital-to-Analog Converter Descriptions .......................................... 17
3.2.10 8051 External I/F Descriptions .......................................................... 18
3.2.11 External Clock Descriptions .............................................................. 18
3.2.12 Miscellaneous Signals Descriptions ................................................ 18
3.2.13 Power Pins Descriptions ................................................................... 18
iii
4. MODULE DESCRIPTIONS ................................................................................ 19

4.1 CHIP ARCHITECTURE ....................................................................................... 19
4.1.1 Power Planes ........................................................................................ 19
4.1.2 Clock Domains ..................................................................................... 20
4.1.3 PCICLK and CLKRUN# ........................................................................ 21
4.1.4 Internal Memory Map ........................................................................... 22
4.2 GPIO ............................................................................................................. 23
4.2.1 GPIO Function Description ................................................................. 23
4.2.2 GPIO Structures ................................................................................... 26
4.2.3 GPIO Attribution Table ......................................................................... 27
4.2.3 GPIO Registers Descriptions .............................................................. 30
4.2.4 GPIO Programming Sample ................................................................ 41
4.3 KEYBOARD AND MOUSE CONTROL INTERFACE (KBC) ....................................... 42
4.3.1 KBC I/F Function Description ............................................................. 42
4.4 ENE SERIAL BUS CONTROLLER (ESB) ............................................................ 48
4.4.1 ESB Function Description ................................................................... 48
4.4.2 ESB Registers Description .................................................................. 49
4.5 INTERNAL KEYBOARD (IKB) ENCODER ............................................................ 55
4.5.1 IKB Function Description .................................................................... 55
4.5.2 IKB Registers Description ................................................................... 56
4.5.3 IKB Matrix Value Mapping Table ......................................................... 62
4.6 PULSE WIDTH MODULATION (PWM) ................................................................. 65
4.6.1 PWM Function Description .................................................................. 65
4.6.2 PWM Registers Description ................................................................ 66
4.6.3 PWM Programming Sample ................................................................ 68
4.7 FAN CONTROLLER........................................................................................... 69
4.7.1 Fan Function Description .................................................................... 69
4.7.2 Fan Registers Description ................................................................... 71
4.7.3 Fan Programming Sample ................................................................... 76
4.8 GENERAL PURPOSE TIMER (GPT).................................................................... 77
4.8.1 GPT Function Description ................................................................... 77
4.8.2 GPT Registers Description .................................................................. 77
4.8.3 GPT Programming Sample .................................................................. 79
4.9 SERIAL DEVICE INTERFACE CONTROLLER (SDI) ................................................ 80
4.9.1 SDI Function Description .................................................................... 80
4.9.2 SDI Registers Description ................................................................... 81
iv
4.9.3 SDI Programming Sample ................................................................... 82

4.10 WATCHDOG TIMER (WDT) ............................................................................. 83
4.10.1 WDT Function Description ................................................................ 83
4.10.2 WDT Registers Description ............................................................... 83
4.10.3 WDT Programming Sample ............................................................... 86
4.11 LOW PIN COUNT INTERFACE (LPC) ................................................................ 87
4.11.1 LPC Function Description ................................................................. 87
4.11.2 LPC I/O Decode Range....................................................................... 87
4.11.3 LPC Memory Decode Range .............................................................. 87
4.11.4 FWH Memory Decode Range ............................................................. 88
4.11.5 Index-I/O Port ...................................................................................... 88
4.11.6 Extended I/O Port (Debug Port, Port80)............................................ 89
4.11.7 LPC Registers Description ................................................................ 90
4.12 X-BUS INTERFACE (XBI) ............................................................................... 95
4.12.1 XBI Function Description .................................................................. 95
4.12.2 XBI SPI Enhancement ........................................................................ 95
4.12.2.1 Original Read Protocol ......................................................................................... 96
4.12.2.2 Short Read Protocol .............................................................................................. 97
4.12.2.3 Offset Read Protocol ............................................................................................. 98
4.12.2.4 Dual Input Protocol ............................................................................................... 99
4.12.3 XBI Registers Description ............................................................... 100
4.13 CONSUMER IR CONTROLLER (CIR) .............................................................. 105
4.13.1 CIR Function Description ................................................................ 105
4.13.2 CIR Block Diagram ........................................................................... 107
4.13.3 CIR Remote Protocol ....................................................................... 108
4.13.3.1 Philips RC5 Protocol ........................................................................................... 108
4.13.3.2 Philips RC6 Protocol ........................................................................................... 109
4.13.3.3 NEC Protocol ....................................................................................................... 109
4.13.4 CIR Automatic Carrier Frequency Detection and Modulation ...... 110
4.13.5 CIR Registers Description ............................................................... 112
4.13.3 CIR Programming Sample ............................................................... 117
4.14 PS/2 INTERFACE (PS/2) .............................................................................. 118
4.14.1 PS/2 Interface Function Description ............................................... 118
4.14.2 PS/2 Interface Registers Description.............................................. 118
4.15 EMBEDDED CONTROLLER (EC) .................................................................... 123
4.15.1 EC Function Description ................................................................. 123
4.15.2 EC Command Program Sequence .................................................. 124
4.15.3 EC SCI Generation ........................................................................... 125

4.15.4 EC/KBC Clock Configuration .......................................................... 126
4.15.5 A/D Converter Control...................................................................... 126
4.15.6 D/A Converter Control...................................................................... 128
4.15.7 Power Management Control ............................................................ 129
4.15.8 EC Registers Description ................................................................ 130
4.16 GENERAL PURPOSE WAKE-UP CONTROLLER (GPWU) .................................. 140
4.16.1 GPWU Function Description ........................................................... 140
4.16.2 GPWU Registers Description .......................................................... 141
4.16.3 GPWU Programming Sample .......................................................... 151
4.17 SYSTEM MANAGEMENT BUS CONTROLLER (SMBUS) .................................... 152
4.17.1 SMBus Function Description .......................................................... 152
4.17.2 SMBus Register Description ........................................................... 154
4.17.3 SMBus Programming Sample ......................................................... 159
4.18 8051 MICROPROCESSOR ............................................................................. 160
4.18.1 8051 Microprocessor Function Description ................................... 160
4.18.1.1 8051 Instruction ................................................................................................... 161
4.18.1.2 Interrupt Controller.............................................................................................. 165
4.18.1.3 Interrupt Enable/Flag Table ................................................................................ 166
4.18.1.4 8051 Special Function Register (SFR)............................................................... 168
4.18.2 8051 Microprocessor Register Description ................................... 169
5. ELECTRICAL CHARACTERISTICS ............................................................... 177
5.1 ABSOLUTE MAXIMUM RATING ........................................................................ 177
5.2 DC ELECTRICAL CHARACTERISTICS ............................................................... 177
5.3 A/D CHARACTERISTICS ................................................................................. 178
5.4 RECOMMEND OPERATION CONDITION ............................................................. 179
5.5 OPERATING CURRENT ................................................................................... 179
5.6 PACKAGE THERMAL INFORMATION ................................................................. 179
5.7 AC ELECTRICAL CHARACTERISTICS ............................................................... 180
5.7.1 SPI Flash Timing ................................................................................ 180
6. PACKAGE INFORMATION ............................................................................. 181
6.1 LQFP 128-PIN OUTLINE DIAGRAM ................................................................ 181
6.1.1 Top View .............................................................................................. 181
6.1.2 Side View ............................................................................................ 182
6.1.3 Lead View ............................................................................................ 183
vi
6.1.4 LQFP Outline Dimensions ................................................................. 184

6.2 LFBGA 128-PIN OUTLINE DIAGRAM .............................................................. 185
6.2.1 Top View .............................................................................................. 185
6.2.2 Side View ............................................................................................ 186
6.2.3 Bottom View........................................................................................ 187
6.2.4 LFBGA Outline Dimensions .............................................................. 188
6.3 PART NUMBER DESCRIPTION ......................................................................... 189
vii
1. General Description
1.1 Overview
The KB926D is an embedded controller with LPC interface to connect with host. The
embedded controller contains industrial standard 8051 microprocessor and provides function of
i8042 keyboard controller basically. The KB926D is designed with Shared-ROM architecture with
SPI flash. The EC firmware and system BIOS will exist in one SPI flash. The embedded controller
also features rich interfaces for applications, such as PS/2 interface, Keyboard Matrix, PWM, A/D
converter, D/A converter, Fan controller, SMBus controller, GPIO controllers and extension interface
for future applications. The chapter 1.2 highlights of all features in the KB926D.
1.2 Features
LPC Low Pin Count Interface
SIRQ supporting IRQ1, IRQ12, SCI or SMI# interrupt and one programmable
IRQ provided.
I/O Address Decoding:
Legacy KBC I/O port 60h/64h
Programmable EC I/O port, 62h/66h(recommend)
I/O port 68h/6Ch (sideband)
2 Programmable 4-byte Index-I/O ports to access internal EC registers.
1 Programmable extended (debug) port I/O.
Memory Decoding:
Firmware Hub decode
LPC memory decode
Compatible with LPC specification v1.1
X-bus Bus Interface (XBI) : Flash Interface

SPI flash is supported, size up to 4MB.
SPI frequency supports 33/45/66MHz.
New SPI command (dual read) to enhance the performance.
The 64KB code memory can be mapped into system memory by one 16KB and
one 48KB programmable pages independently.
Support SPI flash in-system-programming via IKB pins.
Enhanced pre-fetch mechanism.
8051 Microprocessor
Compatible with industrial 8051 instructions with 3 cycles.
8051 runs at 8/16/22 MHz, programmable.
128 bytes internal RAM.
24 extended interrupt sources.
Two 16-bit timers.
Full duplex UART integrated.
Supports idle and stop mode.
Enhanced embedded debug interface.
8042 Keyboard Controller

8 standard 8042 commands processed by hardware.
Each hardware command can be optionally processed by firmware.
Pointing device multiplex mode support.
Fast GA20 and KB reset support.
PS/2 Controller
Support at most 3 external PS/2 devices.
External PS/2 device operation in firmware mode.
Internal Keyboard Matrix (IKB)

18x8 keyboard scan matrix.
Support W2K Internet and multimedia keys.
Support hotkey events defined.
Ghost key cancellation mechanism provided.
Embedded Controller (EC)

ACPI Spec 2.0 compliant.
5 standard EC command supported directly by hardware.
Each hardware command can be processed by firmware optionally.
Programmable EC I/O ports, 62h/66h by default.
SMBus Host Controller

SMBus Spec 2.0 compliant.
SMBus with 2 interfaces.
Byte mode support.
Slave function support.
Digital-to-Analog Converter (DAC)

4 DAC channels with 8-bit resolution.
All DAC pins can be alternatively configured as GPO (general purpose output)
function.
Analog-to-Digital Converter (ADC)

6 ADC channels with 10-bit resolution.
All ADC pins can be alternatively configured as GPI (general purpose input)
function.
Pulse Width Modulator (PWM)

6 PWM channels are provided. (8-bit *2, 14-bit *2 and FANPWM(12-bit) *2)
Clock source selectable:.
1MHz/64KHz/4KHz/256Hz (for 8-bit PWM)
Peripheral clock or 1MHz (for 14-bit PWM)
Peripheral clock (for FANPWM)
Duty cycle programmable and cycle time up to 1 sec(for 8-bit PWM)
WatchDog Timer (WDT)

32.768KHz input clock.
8-bit counter with 128ms unit for watchdog reset.
Two watchdog reset mechanism.
Reset 8051
Reset whole chip, except GPIO.
Real Time Clock

32.768KHz input clock.
24-bit timer support.
General Purpose Timer (GPT)

Two 16-bit and two 8-bit general purpose timer with 32.768KHz clock source.
General Purpose Wakeup (GPWU)

Those I/O with GPI (general purpose input) configuration can generate
interrupts or wakeup events, except those pins named in GPXIOAxx and
GPXIODxx.
General Purpose Input/Output (GPIO)

All general purpose I/O can be programmed as input or output.
All output pins can be configured to be tri-state optionally.
All input pins are equipped with pull-up, high/low active and edge/level trigger
selection.
For the pins of DAC can be configured as GPO function only.
For the pins of ADC can be configured as GPI function only.
A specific pair of GPIO pins with signal pass-through feature.
FAN Controller
Two fan controllers with tachometer inputs.
Automatic fan control support.
12-bit FANPWM support.
Consumer IR (CIR)
Several protocols decoded/encoded by hardware.
Interrupt for CIR application.
Support wide/narrow band receiver.
Transmit/Receive simultaneously.
Remote power-on support.
ENE Serial Bus Interface (ESB)

A proprietary and flexible interface for extension with ENE KBC.
Firmware accesses ESB devices via internal memory address directly.
Interrupt capability.
ENE Debug Interface (EDI)

Flexible debug interface with SPI pins.
Keil-C development tool compatible
SPI Device Interface (SDI)

A simple SPI master controller is embedded in the KBC.
Flexible design for SPI applications.
Power Management
Sleep mode: 8051 program counter (PC) stops and enters idle mode.
Deep sleep mode: All clocks stop except external 32.768KHz OSC. 8051
enters stop mode.
Package
128-pin LQFP package, Lead Free (RoHS).
128-ball LFBGA package, Lead Free (RoHS).
1.3 Comparison (KB926C vs. KB926D )

Microprocessor
Built-in SRAM
LPC
X-Bus
Real Time Clock
ADC
DAC
WDT
PWM
External PS/2 I/F

GPIO
IKB Matrix
FAN controller
GPT
SMBus
CIR
EDI
ESB
SDI
Package
Dimension
KB926C
8051
2KB
2 index-I/O sets
SPI ROM: 4MB
KB926D
8051
2KB
2 index-I/O sets
SPI ROM: 4MB
Enhanced pre-fetch mechanism.
Support
Six 10-bit ADC channels
Four 8-bit DAC channels
20 bit
6 sets
PWM0/1
8 bit
PWM2/3
14 bit
FANPWM0/1 12 bit
3
Programmable Bi-direction I/O
GPIO pass through : 1 pair
Max GPIO: 100(926D)
18x8
2
4
2
Byte mode support
Hardware encode/decode
IRQ and I/O port support
Carrier frequency calculation
TX with carrier modulation
Learning mode support
TX/RX simultaneously
Support
Support and Enhanced
Support
128 LQFP
14mmx14mm
support
Six 10-bit ADC channels
Four 8-bit DAC channels
20 bit
6 sets
PWM0/1
8 bit
PWM2/3
14 bit
FANPWM0/1 12 bit
3
Programmable Bi-direction I/O
GPIO pass through : 1 pair
Max GPIO: 100(926C)
18x8
2
4
2
Byte mode support
Hardware encode/decode
IRQ and I/O port support
Carrier frequency calculation
TX with carrier modulation
Learning mode support
None
Support
Support
128 LQFP
14mmx14mm
1.4 Block Diagram

3
4
5
6
7
8
9
10
11
12
13
SERIRQ
LFRAME#
LAD3
GPIO04
LAD2
LAD1
VCC
LAD0
GND
PCICLK
PCIRST#
18
19
20
21
22
23
GPIO0D
SCI#
PWM0
VCC
PWM1
28
29
30
31
32
FANFB0
FANFB1
GPIO16
GPIO17
GPIO18
27
26
FANPWM0
FANPWM1
25
24
GPIO11
GND
17
GPIO0C
16
GPIO08
GPIO0A
GPIO0B
15
14
KBRST#
GPIO07
GA20
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
VCC
AD2
AD3
AVCC
DA0
AGND
DA1
DA2
DA3
GPIO40
GPIO41
GPI 4 2
GPI 43
SCL0
SDA0
SCL1
SDA1
KSO16
KSO17
PSCLK0
PSDAT0
PSCLK1
PSDAT1
PSCLK2
PSDAT2
GPIO50
GPIO52
GPIO53
GPIO55
GPIO54
GND
GPIO56
2. Pin Assignment and Description

2.1 KB926D 128-pin LQFP Diagram Top View
2.2 KB926D 128 LFBGA Ball Map
2.3 KB926D Pin Assignment Side A

KB926D
KB926D
Pin No.
BGA
Name
GPIO
Alt
Alt.
Output
Input
Default
ECRST#
IO CELL
M2
GA20
GA20
GPIO00
HiZ / HiZ
BQC04HIV
L2
KBRST#
KBRST#
GPIO01
HiZ / HiZ
BQC04HIV
M3
SERIRQ
HiZ / HiZ
BCC16HI
K4
LFRAME#
HiZ / HiZ
BCC16HI
N3
LAD3
HiZ / HiZ
BCC16HI
J5
GPIO04
HiZ / HiZ
BQC04HIV
M4
LAD2
HiZ / HiZ
BCC16HI
K5
LAD1
HiZ / HiZ
BCC16HI
J7/K12/M12
VCC
10
N4
LAD0
11
J8/J9/N13
GND
12
N5
PCICLK
13
M5
PCIRST#
14
N9
GPIO07
GPIO07
15
L13
GPIO08
GPIO08
16
K6
GPIO0A
GPIO0A
17
N7
GPIO0B
GPIO0B
ESB_CLK
18
M7
GPIO0C
GPIO0C
ESB_DAT_O
19
N8
GPIO0D
GPIO0D
20
N6
SCI#
21
M9
22
L/H
GPIO04
VCC
HiZ / HiZ
BCC16HI
GND
IE/IE
BCC16HI
GPIO05
HiZ / IE
BCC16HI
i_clk_8051
GPIO07
HiZ / HiZ
BQC04HIV
i_clk_peri
GPIO08
HiZ / HiZ
BQC04HIV
GPIO0A
HiZ / HiZ
BQC04HIV
GPIO0B
PU / PU
BQCW16HIV
GPIO0C
HiZ / HiZ
BQCW16HIV
RLC_TX2
GPIO0D
HiZ / HiZ
BQC04HIV
GPIO0E
SCI#
GPIO0E
HiZ / HiZ
BQC04HIV
PWM0
GPIO0F
PWM0
GPIO0F
HiZ / HiZ
BQC04HI
K7
VCC
VCC
23
M8
PWM1
GPIO10
24
J10
GND
GND
25
K8
GPIO11
GPIO11
PWM2
GPIO11
HiZ / HiZ
BQC04HIV
26
M10
FANPWM0
GPIO12
FANPWM0
GPIO12
HiZ / HiZ
BQC04HI
27
N10
FANPWM1
GPIO13
FANPWM1
GPIO13
HiZ / HiZ
BQC04HI
28
M11
FANFB0
GPIO14
FANFB0
GPIO14
HiZ / HiZ
BQC04HI
29
N11
FANFB1
GPIO15
FANFB1
GPIO15
HiZ / HiZ
BQC04HI
30
K10
GPIO16
GPIO16
E51TXD
GPIO16
HiZ / HiZ
BQC04HI
31
K9
GPIO17
GPIO17
E51CLK
GPIO17
HiZ / HiZ
BQC04HI
32
N12
GPIO18
GPIO18
GPIO18
HiZ / HiZ
BQC04HIV
PCIRST#
RLC_RX2
ESB_DAT_I
VCC
PWM1
GPIO10
HiZ / HiZ
BQC04HI
GND
E51RXD
10
2.4 KB926D Pin Assignment Side B

KB926D
KB926D
Name
GPIO
Alt
Alt.
Pin No.
BGA
Output
Input
33
J7/K12/M12
VCC
34
M13
GPIO19
35
J8/J9/N13
GND
36
L12
GPIO1A
37
K13
ECRST#
38
M6
CLKRUN#
GPIO1D
CLKRUN#
CLKRUN#
39
J13
KSO0
GPIO20
KSO0
40
J12
KSO1
GPIO21
41
H12
KSO2
42
H13
43
Default
ECRST#
IO CELL
L/H
VCC
GPIO19
PWM3
GPIO19
HiZ / HiZ
BCC16HI
GND
GPIO1A
HiZ / HiZ
BCC16HI
IE / IE
BQC04HIV
GPIO1D
HiZ / HiZ
BCC16HI
TP_TEST
GPIO20
IE(PU)/IE(PU)
BQC04HIV
KSO1
TP_PLL
GPIO21
IE(PU)/IE(PU)
BQC04HIV
GPIO22
KSO2
TP_ANA_TEST
GPIO22
IE(PU)/IE(PU)
BQC04HIV
KSO3
GPIO23
KSO3
TP_ISP
GPIO23
IE(PU)/IE(PU)
BQC04HIV
H10
KSO4
GPIO24
KSO4
GPIO24
HiZ / HiZ
BQC04HIV
44
H9
KSO5
GPIO25
KSO5
GPIO25
HiZ / HiZ
BQC04HIV
45
G9
KSO6
GPIO26
KSO6
GPIO26
HiZ / HiZ
BQC04HIV
46
G10
KSO7
GPIO27
KSO7
GPIO27
HiZ / HiZ
BQC04HIV
47
G13
KSO8
GPIO28
KSO8
GPIO28
HiZ / HiZ
BQC04HIV
48
G12
KSO9
GPIO29
KSO9
GPIO29
HiZ / HiZ
BQC04HIV
49
F13
KSO10
GPIO2A
KSO10
GPIO2A
HiZ / HiZ
BQC04HIV
50
F12
KSO11
GPIO2B
KSO11
GPIO2B
HiZ / HiZ
BQC04HIV
51
F10
KSO12
GPIO2C
KSO12
GPIO2C
HiZ / HiZ
BQC04HIV
52
F9
KSO13
GPIO2D
KSO13
GPIO2D
HiZ / HiZ
BQC04HIV
53
E10
KSO14
GPIO2E
KSO14
GPIO2E
HiZ / HiZ
BQC04HIV
54
E9
KSO15
GPIO2F
KSO15
E51_RXD(ISP)
GPIO2F
HiZ / HiZ
BQC04HIV
55
D9
KSI0
GPIO30
E51_TXD(ISP)
KSI0
GPIO30
IE(PU)/IE(PU)
BQC04HIV
56
E12
KSI1
GPIO31
KSI1
GPIO31
IE(PU)/IE(PU)
BQC04HIV
57
E13
KSI2
GPIO32
KSI2
GPIO32
IE(PU)/IE(PU)
BQC04HIV
58
D12
KSI3
GPIO33
KSI3
GPIO33
IE(PU)/IE(PU)
BQC04HIV
59
D13
KSI4
GPIO34
KSI4/EDI_CS
GPIO34
IE(PU)/IE(PU)
BQC04HIV
60
C12
KSI5
GPIO35
KSI5/EDI_CLK
GPIO35
IE(PU)/IE(PU)
BQC04HIV
61
C13
KSI6
GPIO36
KSI6/EDI_DIN
GPIO36
IE(PU)/IE(PU)
BQC04HIV
62
D10
KSI7
GPIO37
KSI7
GPIO37
IE(PU)/IE(PU)
BQC04HIV
63
B13
AD0
GPI38
AD0
GPI38
HiZ / HiZ
IQTHI
64
A13
AD1
GPI39
AD1
GPI39
HiZ / HiZ
IQTHI
NUMLED#
GPIO1A
EDI_DO
11
2.5 KB926D Pin Assignment Side C

KB926D
KB926D
Name
GPIO
Alt
Alt.
Output
Input
Default
ECRST#
IO CELL
Pin No.
BGA
65
B12
AD2
GPI3A
AD2
GPI3A
HiZ / HiZ
IQTHI
66
A12
AD3
GPI3B
AD3
GPI3B
HiZ / HiZ
IQTHI
67
B11
AVCC
68
B10
DA0
69
A11
AGND
70
A9
DA1
GPO3D
DA1
GPO3D
HiZ / HiZ
OCT04H
71
A10
DA2
GPO3E
DA2
GPO3E
HiZ / HiZ
OCT04H
72
B9
DA3
GPO3F
DA3
GPO3F
HiZ / HiZ
OCT04H
73
B6
GPIO40
GPIO40
GPIO40
HiZ / HiZ
BQC04HI
74
B7
GPIO41
GPIO41
GPIO41
HiZ / HiZ
BQC04HIV
75
E7
AD4
GPI42
AD4
GPI42
HiZ / HiZ
IQTHI
76
D7
AD5
GPI43
AD5
GPI43
HiZ / HiZ
IQTHI
77
A8
SCL0
GPIO44
SCL0
GPIO44
HiZ / HiZ
BQC04HI
78
A7
SDA0
GPIO45
SDA0
GPIO45
HiZ / HiZ
BQC04HI
79
B8
SCL1
GPIO46
SCL1
GPIO46
HiZ / HiZ
BQC04HI
80
A6
SDA1
GPIO47
SDA1
GPIO47
HiZ / HiZ
BQC04HI
81
E8
KSO16
GPIO48
KSO16
GPIO48
HiZ / HiZ
BQC04HIV
82
D8
KSO17
GPIO49
KSO17
GPIO49
HiZ / HiZ
BQC04HIV
83
D6
PSCLK0
GPIO4A
PSCLK0/P80CLK
GPIO4A
HiZ / HiZ
BQC04HI
84
E6
PSDAT0
GPIO4B
PSDAT0/P80DAT
GPIO4B
HiZ / HiZ
BQC04HI
85
E5
PSCLK1
GPIO4C
PSCLK1
GPIO4C
HiZ / HiZ
BCC16HI
86
D5
PSDAT1
GPIO4D
PSDAT1
GPIO4D
HiZ / HiZ
BCC16HI
87
A5
PSCLK2
GPIO4E
PSCLK2
GPIO4E
HiZ / HiZ
BQC04HI
88
B5
PSDAT2
GPIO4F
PSDAT2
GPIO4F
HiZ / HiZ
BQC04HI
89
B4
GPIO50
GPIO50
GPIO50
HiZ / HiZ
BQC04HI
90
A4
GPIO52
GPIO52
E51CS#
GPIO52
HiZ / HiZ
BCC16HI
91
B3
GPIO53
GPIO53
CAPSLED#
E51TMR1
GPIO53
HiZ / HiZ
BCC16HI
92
A3
GPIO54
GPIO54
WDT_LED#
E51TMR0
GPIO54
HiZ / HiZ
BCC16HI
93
A2
GPIO55
GPIO55
SCROLED#
E51INT0
GPIO55
HiZ / HiZ
BCC16HI
94
J8/J9/N13
GND
95
B2
GPIO56
96
J7/K12/M12
VCC
L/H
AVCC
GPO3C
DA0
GPO3C
HiZ / HiZ
OCT04H
AGND
CIR_RX
CIR_RLC_TX
GND
GPIO56
E51INT1
GPIO56
HiZ / HiZ
BQC04HIV
VCC
12
2.6 KB926D Pin Assignment Side D

KB926D
KB926D
Pin No.
BGA
97
B1
GPXIOA00
GPXIOA00
SDICS#
HiZ / HiZ
BQC04HIV
98
A1
GPXIOA01
GPXIOA01
SDICLK
HiZ / HiZ
BQC04HIV
99
C1
GPXIOA02
GPXIOA02
SDIMOSI
HiZ / HiZ
BQC04HIV
100
D4
GPXIOA03
GPXIOA03
HiZ / HiZ
BQC04HIV
101
D1
GPXIOA04
GPXIOA04
HiZ / HiZ
BQC04HIV
102
D2
GPXIOA05
GPXIOA05
HiZ / HiZ
BQC04HIV
103
E2
GPXIOA06
GPXIOA06
HiZ / HiZ
BQC04HIV
104
E4
GPXIOA07
GPXIOA07
HiZ / HiZ
BQC04HIV
105
E1
GPXIOA08
GPXIOA08
HiZ / HiZ
BQCZ16HIV
106
F4
GPXIOA09
GPXIOA09
HiZ / HiZ
BQCZ16HIV
107
F2
GPXIOA10
GPXIOA10
HiZ / HiZ
BQCZ16HIV
108
F1
GPXIOA11
GPXIOA11
HiZ / HiZ
BQCZ16HIV
109
C2
GPXIOD0
GPXIOD0
HiZ / HiZ
BQC04HIV
110
F5
GPXIOD1
GPXIOD1
HiZ / HiZ
BQC04HIV
111
J6
VCC
HiZ / HiZ
VCC
112
G1
GPXIOD2
HiZ / HiZ
BQC04HIV
113
G2
GND
HiZ / HiZ
GND
114
G5
GPXIOD3
GPXIOD3
HiZ / HiZ
BQC04HIV
115
H1
GPXIOD4
GPXIOD4
HiZ / HiZ
BQC04HIV
116
G4
GPXIOD5
GPXIOD5
HiZ / HiZ
BQC04HIV
117
H4
GPXIOD6
GPXIOD6
HiZ / HiZ
BQC04HIV
118
H2
GPXIOD7
GPXIOD7
HiZ / HiZ
BQC04HIV
119
K2
MISO
MISO
HiZ / IE
BQC04HI
120
J2
MOSI
MOSI
MOSI
HiZ / Ox
BQCZ16HIV
121
H5
GPIO57
XCLK32K
GPIO57
HiZ / HiZ
BQC04HIV
122
J1
XCLKI
123
K1
XCLKO
124
L1
V18R
125
J4
VCC
126
M1
SPICLK
GPIO58
GPIO59
GPIO59
127
Name
GPIO
Alt
Alt.
Output
Input
GPXIOD2
MISO
GPIO57
N2
ECRST#
IO CELL
L/H
SDIMISO
VCC
SPICLK
TEST_CLK
N1
128
Default
SPICLK
HiZ / Ox
BQCW16HIV
GPIO59
IE / IE
BQC04HIV
SPICS#
HiZ / Ox
BQCZ16HIV
SPICLKI
SPICS#
SPICS#
13
2.7 I/O Cell Descriptions

2.7.1 I/O Buffer Table
Cell
BQCZ16HIV
BQC04HIV
Description
Application
Schmitt trigger, 16mA Output / Sink Current, Input / Output / Pull Up

Enable(40K), 5 V Tolerance.
GPIO
Schmitt trigger, 4mA Output / Sink Current, Input / Output / Pull Up Enable(40K
GPIO
), 5 V Tolerance
BQCW16HIV
Schmitt trigger, 16mA Output / Sink Current, 5 V Tolerance, Input / Output / Pull
Up Enable
ESB_CLK/
ESB_DAT/
SPI_CLK
BCC16HI
16mA Output / Sink Current , 5 V Tolerance, Input / Output Enable
LPC I/F
BQC04HI
Schmitt trigger, 4mA Output / Sink Current, 5 V Tolerance, Input / Output

Enable
GPIO
IQTHI
Mixed mode IO, ADC Enable, with GPI, Input Enable
ADC, GPI
OCT04H
Mixed mode IO, DAC Enable, with GPO, 4mA Output Current, Output Enable
DAC, GPO
(For GPO function, it is not recommended to control the device powered

before KBC chip.)
* 5V Tolerance, only if pull-high disable and output disable.
** Please note, the total current in each side of chip can not exceed over 48mA.
14
3. Pin Descriptions
3.1 Hardware Trap
Hardware trap pins are used to latch external signal at rising edge of ECRST#. The hardware
trap pins are for some special purpose which should be defined while boot-up. The following table
gives the collection of hardware trap pins. Please note, all the following hardware trap pins are
pull-high internally after reset.
Trap Name
TP_TEST
Pin No.
Description
39
While this trap is asserted to be low, the internal DPLL circuit uses other clock source
for reference, instead of 32KHz oscillator.
Low: test clock mode enable
High: normal mode using 32KHz oscillator.
TP_PLL
40
While this trap is asserted to be low, some DPLL related signals can be output for
test.
Low: DPLL test mode enable.
High: DPLL test mode disable
TP_ANA_TEST
41
While this trap is asserted to be low, some ADC related signals can be output for
test.
Low: ADC test mode enable.
High: ADC test mode disable
TP_ISP
42
While this trap is asserted to be low, SPI Flash can be programmed via RS232 I/F,
i.e., TX and RX. Please note, while entering ISP mode, the TX/RX pins are linked to
GPIO30/GPIO2F
Low: SPI flash programming in ISP mode enable
High: SPI flash programming in ISP mode disable
Please note while TP_ANA_TEST and TP_ISP keep low at the same time, a mechanism called FlashDirectAccess will
enable. That is, users can flush and program a SPI flash via specific IKB pins with external tool.
FlashDirectAccess:
The KBC provides a new interface to program SPI flash via IKB interface. With this feature, users can easily utilize 4 pins
from keyboard matrix (IKB) without disassembly whole machine. These 4 pins are connected directly to external SPI
programmer. The following table shows the pins mapping while entering FlashDirectAccess mode.
Pin No.
Normal Mode
FlashDirectAccess Mode
47
KSO8 (O)
FDA_SPICLK (I)
48
KSO9 (O)
FDA_SPICS
(I)
49
KSO10 (O)
FDA_SPIDI
(I)
50
KSO11 (O)
FDA_SPIDO (O)
Comment
15
3.2 Pin Descriptions by Functions

3.2.1 Low Pin Count I/F Descriptions.
Pin Name
Pin No.
Direction
5, 7,8,10
I/O
LFARAME#
LPC frame control signal.
PCIRST#
13
LPC module reset by this signal.
PCICLK
12
33MHz PCI clock input.
SERIRQ
I/O
CLKRUN#
38
I/OD
LAD[3:0]
Description
LPC address bus.
Serial IRQ
Clock run control
3.2.2 SPI Flash I/F Descriptions

Pin Name
Pin No.
Direction
Description
MISO
119
SPI read control signal
MOSI
120
SPI write control signal
SPICLK
126
SPI clock output
SPICS#
128
SPI chip select signal
These pins are input/output disable during reset phase.
3.2.3 PS/2 I/F Descriptions

Pin Name
Pin No.
Direction
PSCLK0
83
I/OD
PS/2 port 0 clock
PSDAT0
84
I/OD
PS/2 port 0 data
PSCLK1
85
I/OD
PS/2 port 1 clock
PSDAT1
86
I/OD
PS/2 port 1 data
PSCLK2
87
I/OD
PS/2 port 2 clock
PSDAT2
88
I/OD
PS/2 port 2 data
Description
16
3.2.4 Internal Keyboard Encoder (IKB) Descriptions

Pin Name
KSO[17:0]
KSI[7:0]
Pin No.
Direction
Description
82,81,54-39
Keyboard Scan Out
62-55
Keyboard Scan In
3.2.5 SMBus Descriptions

Pin Name
Pin No.
Direction
Description
SCL0
77
I/OD
SMBus clock (interface 0)
SDA0
78
I/OD
SMBus data (interface 0)
SCL1
79
I/OD
SMBus clock (interface 1)
SDA1
80
I/OD
SMBus data (interface 1)
3.2.6 FAN Descriptions

Pin Name
Pin No.
Direction
Description
FANPWM0
26
FANPWM0 output
FANPWM1
27
FANPWM1 output
FANFB0
28
FAN0 tachometer input
FANFB1
29
FAN1 tachometer input
3.2.7 Pulse Width Modulation (PWM) Descriptions

Pin Name
PWM[1:0]
Pin No.
Direction
23, 21
Description
PWM pulse output
3.2.8 Analog-to-Digital Converter Descriptions

Pin Name
Pin No.
Direction
Description
AD[3:0]
66-63
10bit A/D converter input
AD[5:4]
76,75
10bit A/D converter input
3.2.9 Digital-to-Analog Converter Descriptions

Pin Name
DA[3:0]
Pin No.
Direction
72-70,68
Description
8bit D/A converter output
17
3.2.10 8051 External I/F Descriptions

Pin Name
Pin No.
Direction
Description
E51TXD
30
8051 serial port, transmit port.
E51RXD
31
8051 serial port, receive port.
E51CLK
31
For different serial scheme, E51CLK will shift out clock.
E51CS#
90
E51TMR0
92
E51INT0
93
E51TMR1
91
E51INT1
95
3.2.11 External Clock Descriptions

Pin Name
Pin No.
Direction
Description
XCLKI
122
32.768KHz input
XCLKO
123
32.768KHz output
3.2.12 Miscellaneous Signals Descriptions

Pin Name
Pin No.
Direction
Description
GA20
KBC will gate A20 address line
KBRST#
KBRST# is used to generate system reset.
SCI#
20
SCI# asserts to the system for requesting service while

related events occur.
ECRST#
37
While ECRST# asserted, the KBC will reset globally.
3.2.13 Power Pins Descriptions

Pin Name
Pin No.
Direction
Description
VCC
9,22,33,96,111,125
Power supply for digital circuit.
GND
11,24,35,94,113
Power ground for digital circuit.
AVCC
67
Power supply for analog circuit.
AGND
69
Power ground for analog circuit.
18
4. Module Descriptions
4.1 Chip Architecture
4.1.1 Power Planes
Two power planes are in the KBC. One is for digital logic and the other is for analog
circuit. Both power planes are 10% tolerance for recommend operation condition, The KBC
provides V1.8 power plane for different generation.
Power Plane
Description
Power
Ground
Digital Plane
This power provides power for all digital logic no matter what
power mode is.
VCC
GND
Analog Plane
This power provides power for all analog logic, such as A/D
and D/A converter.
AVCC
AGND
Digital V1.8
The system inputs 3.3V power and the internal regulator

outputs 1.8V voltage. The 1.8V output should connect a
capacitor for stable purpose.
V1.8
GND
19
4.1.2 Clock Domains

Three clock sources, PCICLK, DPLL_CLK and XCLKI will be discussed in this section. A
summary is list in the following table.
Clock
Description
PCICLK
PCI clock 33MHz for LPC I/F.
DPLL_CLK
Main clock for 8051/peripheral. DPLL clock can be generated with or without XCLK for
reference. DPLL clock can be divided for different applications. Fig. 4-1 gives an example for
illustration.
XCLKI
External 32.768KHz for reference.
The following figure shows more detail about the operation in the KBC. The external
32.768KHz is provided for two purposes. One is to provide an accurate reference for internal DPLL
module, and the other one is to provide another clock source for watchdog timer.
The possible (X,Y,Z) combination is summarized as the following table.

CLKCFG[6]=0(default)
CLKCFG[6]=1
(X,Y,Z)=(4,8,16) *
(X,Y,Z)=(1,8,16)
CLKCFG[3:2]=1
(X,Y,Z)=(2,4,8)
(X,Y,Z)=(1,4,8)
CLKCFG[3:2]=2
(X,Y,Z)=(2,3,8)
(X,Y,Z)=(1,3,8)
CLKCFG[3:2]=3
(X,Y,Z)=(2,2,4)
(X,Y,Z)=(1,2,4)
CLKCFG[3:2]=0(default)
* While power on default, no matter what value of CLKCFG[3:2] and CLKCFG[6] are,
the (X,Y,Z) is always (4, 8, 16)
20
4.1.3 PCICLK and CLKRUN#

While system power-on, the host starts to drive CLKRUN# low for a while to inform the slaves
that a 33MHz PCICLK will be given. At this moment, CLKRUN# of KBC is in input mode. If the host
tries to stop the PCICLK for some purpose, the CLKRUN# will be de-asserted. In the current design,
the KBC needs PCICLK for normal operation. Therefore the KBC keeps CLKRUN# for 2 clock
cycles and releases it. This forces the host to start driving PCICLK. The following figure gives the
explanation. For more detail please refer to PCI Mobile Design Guide version 1.1.
21
4.1.4 Internal Memory Map

No
Module
Descriptions
Address Range
Size (Byte)
Flash
Space mapped to system BIOS
0x0000~0xF3FF
61K
XRAM
Embedded SRAM
0xF400~0xFBFF
2K
GPIO
General purpose I/O
0xFC00~0xFC7F
128
KBC
Keyboard controller
0xFC80~0xFC8F
16
ESB
ENE serial bus controller
0xFC90~0xFC9F
16
IKB
Internal keyboard matrix
0xFCA0~0xFCAF
16
RSV
Reserved
0xFCB0~0xFCBF
16
RSV
Reserved
0xFCC0~0xFCCF
16
RSV
Reserved
0xFCD0~0xFCDF
16
10
RSV
Reserved
0xFCE0~0xFCEF
16
11
RSV
Reserved
0xFCF0~0xFDFF
272
12
PWM
Pulse width modulation
0xFE00~0xFE1F
32
13
FAN
Fan controller
0xFE20~0xFE4F
48
14
GPT
General purpose timer
0xFE50~0xFE6F
32
15
SDI
SPI device interface
0xFE70~0xFE7F
16
16
WDT
Watchdog timer
0xFE80~0xFE8F
16
17
LPC
Low pin count interface
0xFE90~0xFE9F
16
18
XBI
X-bus interface
0xFEA0~0xFEBF
32
19
CIR
Consumer IR controller
0xFEC0~0xFECF
16
20
RSV
Reserved
0xFED0~0xFEDFh
16
21
PS2
PS/2 interface
0xFEE0~0xFEFF
32
22
EC
Embedded controller
0xFF00~0xFF1F
32
23
GPWU
General purpose wakeup event
0xFF20~0xFF7F
96
24
SMBus
System management bus controller
0xFF80~0xFFFF
128
22
1K
4.2 GPIO
4.2.1 GPIO Function Description
The GPIO module is flexible for different applications. Each GPIO pin can be configured
as alternative input or alternative output mode. The alternative function can be selected by register
setting. A summary table is given as below for more detail.
GPIO
Alt. Output
GPIO00
GPIO01
Default Alt. Output
Alt. Selection Reg.
GA20
GPIO00
GPIOFS00.[0]
KBRST#
GPIO01
GPIOFS00.[1]
GPIO02
GPIO02
GPIOFS00.[2]
GPIO03
GPIO03
GPIOFS00.[3]
GPIO04
GPIO04
GPIOFS00.[4]
GPIO05
GPIOFS00.[5]
GPIO06
GPIOFS00.[6]
GPIO05
Alt. Input
PCIRST#
GPIO06
GPIO07
i_clk(8051)
GPIO07
GPIOFS00.[7]
GPIO08
i_clk(peripheral)
GPIO08
GPIOFS08.[0]
GPIO09
GPIOFS08.[1]
GPIO09
GPIO0A
RLC_RX2
GPIO0A
GPIOFS08.[2]
GPIO0B
GPIOFS08.[3]
GPIO0C
GPIOFS08.[4]
RLC_TX2
GPIO0D
GPIOFS08.[5]
GPIO0E
SCI#
GPIO0E
GPIOFS08.[6]
GPIO0F
PWM0
GPIO0F
GPIOFS08.[7]
GPIO10
PWM1
GPIO10
GPIOFS10.[0]
GPIO11
PWM2
GPIO11
GPIOFS10.[1]
GPIO12
FANPWM0
GPIO12
GPIOFS10.[2]
GPIO13
FANPWM1
GPIO13
GPIOFS10.[3]
GPIO0B
ESB_CLK
GPIO0C
ESB_DAT
GPIO0D
ESB_DAT_I
GPIO14
FANFB0
GPIO14
GPIOFS10.[4]
GPIO15
FANFB1
GPIO15
GPIOFS10.[5]
GPIO16
GPIOFS10.[6]
GPIO17
GPIOFS10.[7]
GPIO16
E51TXD
GPIO17
E51CLK
E51RXD
GPIO18
GPIO18
GPIOFS18.[0]
GPIO19
PWM3
GPIO19
GPIOFS18.[1]
GPIO1A
NUMLED#
GPIO1A
GPIOFS18.[2]
GPIO1B
GPIO1B
GPIOFS18.[3]
GPIO1C
GPIO1C
GPIOFS18.[4]
GPIO1D
GPIOFS18.[5]
GPIO1E
GPIO1E
GPIOFS18.[6]
GPIO1F
GPIO1F
GPIOFS18.[7]
GPIO1D
CLKRUN#
CLKRUN#
GPIO20
KSO00
TP_TEST
GPIO20
GPIOFS20.[0]
GPIO21
KSO01
TP_PLL
GPIO21
GPIOFS20.[1]
GPIO22
KSO02
TP_ANA_TEST
GPIO22
GPIOFS20.[2]
23

GPIO
Alt. Output
Alt. Input
Default Alt. Output
Alt. Selection Reg.
GPIO23
KSO03
TP_ISP
GPIO23
GPIOFS20.[3]
GPIO24
KSO04
GPIO24
GPIOFS20.[4]
GPIO25
KSO05
GPIO25
GPIOFS20.[5]
GPIO26
KSO06
GPIO26
GPIOFS20.[6]
GPIO27
KSO07
GPIO27
GPIOFS20.[7]
GPIO28
KSO08
GPIO28
GPIOFS28.[0]
GPIO29
KSO09
GPIO29
GPIOFS28.[1]
GPIO2A
KSO10
GPIO2A
GPIOFS28.[2]
GPIO2B
KSO11
GPIO2B
GPIOFS28.[3]
GPIO2C
KSO12
GPIO2C
GPIOFS28.[4]
GPIO2D
KSO13
GPIO2D
GPIOFS28.[5]
GPIO2E
KSO14
GPIO2E
GPIOFS28.[6]
GPIO2F
KSO15
E51_RXD(ISP)
GPIO2F
GPIOFS28.[7]
GPIO30
E51_TXD(ISP)
KSI0
GPIO30
GPIOFS30.[0]
GPIO31
KSI1
GPIO31
GPIOFS30.[1]
GPIO32
KSI2
GPIO32
GPIOFS30.[2]
GPIO33
KSI3
GPIO33
GPIOFS30.[3]
GPIO34
KSI4
GPIO34
GPIOFS30.[4]
GPIO35
KSI5
GPIO35
GPIOFS30.[5]
GPIO36
KSI6
GPIO36
GPIOFS30.[6]
GPIO37
KSI7
GPIO37
GPIOFS30.[7]
GPI38
AD0
GPIOFS38.[0]
GPI39
AD1
GPIOFS38.[1]
GPI3A
AD2
GPIOFS38.[2]
GPI3B
AD3
GPIOFS38.[3]
GPO3C
DA0
GPIO3C
GPIOFS38.[4]
GPO3D
DA1
GPIO3D
GPIOFS38.[5]
GPO3E
DA2
GPIO3E
GPIOFS38.[6]
GPO3F
DA3
GPIO3F
GPIOFS38.[7]
GPIO40
GPIOFS40.[0]
GPIO41
GPIOFS40.[1]
GPIO40
GPIO41
CIR_RX
CIR_RLC_TX
GPIO42
AD4
GPIOFS40.[2]
GPIO43
AD5
GPIOFS40.[3]
GPIO44
SCL0
GPIO44
GPIOFS40.[4]
GPIO45
SDA0
GPIO45
GPIOFS40.[5]
GPIO46
SCL1
GPIO46
GPIOFS40.[6]
GPIO47
SDA1
GPIO47
GPIOFS40.[7]
GPIO48
KSO16
GPIO48
GPIOFS48.[0]
GPIO49
KSO17
GPIO49
GPIOFS48.[1]
GPIO4A
PSCLK0/P80CLK
GPIO4A
GPIOFS48.[2]
GPIO4B
PSDAT0/P80DAT
GPIO4B
GPIOFS48.[3]
GPIO4C
PSCLK1
GPIO4C
GPIOFS48.[4]
24

GPIO
Alt. Output
GPIO4D
Alt. Input
Default Alt. Output
Alt. Selection Reg.
PSDAT1
GPIO4D
GPIOFS48.[5]
GPIO4E
PSCLK2
GPIO4E
GPIOFS48.[6]
GPIO4F
PSDAT2
GPIO4F
GPIOFS48.[7]
GPIO50
GPIO50
GPIOFS50.[0]
GPIO51
GPIO51
GPIOFS50.[1]
GPIO52
GPIOFS50.[2]
GPIO52
E51CS#
GPIO53
CAPSLED#
E51TMR1
GPIO53
GPIOFS50.[3]
GPIO54
WDT_LED#
E51TMR0
GPIO54
GPIOFS50.[4]
GPIO55
SCORLED#
E51INT0
GPIO55
GPIOFS50.[5]
E51INT1
GPIO56
GPIOFS50.[6]
GPIO56
GPIO57
XCLK32K
GPIO57
GPIOFS50.[7]
GPIO58
SPICLK
GPIO58
GPIOFS58.[0]
GPIO59
TEST_CLK/SPICLK
GPIO59
GPIOFS58.[1]
GPXIOA00
SDICS#
GPIO_MISC.[2]
GPXIOA01
SDICLK
GPIO_MISC.[2]
GPXIOA02
SDIDO
GPIO_MISC.[2]
GPXIOA03
GPXIOA04
GPXIOA05
GPXIOA06
GPXIOA07
GPXIOA08
GPXIOA09
GPXIOA10
GPXIOA11
GPXIOA12
GPXIOA13
GPXIOA14
GPXIOA15
GPXIOA16
GPXIOA17
GPXIOA18
GPXIOD00
SDIDI
GPXIOD01
GPXIOD02
GPXIOD03
GPXIOD04
GPXIOD05
GPXIOD06
GPXIOD07
In KB926D, these GPIO pins no more exist. The corresponding register bits do not work.
If DAC function selected, please do not set this register bit.
25
4.2.2 GPIO Structures

In this section, the GPIO structure is illustrated as following diagram. The upper part is
alternative output circuit and the lower part is alternative input circuit. In the figure, GPIOFS is used
to enable alternative output. GPIOOD is for open-drain setting with output function. GPIOOE is the
switch for data output. As shown in the figure, the alternative input embedded with pull-high and
interrupt feature.
26
4.2.3 GPIO Attribution Table

GPIO
Alt.
Alt.
Default
Alt. Selection
Input
Output
Pull Up
Open
Output
Output
Input
Alt. Output
Reg.
Enable
Enable
(40K)
Drain
Current
GPIO00
GA20
GPIO00
GPIOFS00.[0]
2-4mA
GPIO01
KBRST#
GPIO01
GPIOFS00.[1]
2-4mA
GPIO02
GPIO02
GPIOFS00.[2]
GPIO03
GPIO03
GPIOFS00.[3]
GPIO04
GPIOFS00.[4]
2-4mA
GPIO05
GPIOFS00.[5]
8-16mA
GPIO06
GPIOFS00.[6]
GPIO04
GPIO05
PCIRST#
GPIO06
GPIO07
i_clk(8051)
GPIO07
GPIOFS00.[7]
2-4mA
GPIO08
i_clk(peripheral)
GPIO08
GPIOFS08.[0]
2-4mA
2-4mA
GPIO09
GPIOFS08.[1]
RLC_RX2
GPIO0A
GPIOFS08.[2]
GPIO0B
GPIOFS08.[3]
8-16mA
ESB_DAT_I
GPIO0C
GPIOFS08.[4]
2-4mA
GPIOFS08.[5]
2-4mA
GPIO09
GPIO0A
GPIO0B
ESB_CLK
GPIO0C
ESB_DAT
GPIO0D
RLC_TX2
GPIO0D
GPIO0E
SCI#
GPIO0E
GPIOFS08.[6]
2-4mA
GPIO0F
PWM0
GPIO0F
GPIOFS08.[7]
2-4mA
GPIO10
PWM1
GPIO10
GPIOFS10.[0]
2-4mA
GPIO11
PWM2
GPIO11
GPIOFS10.[1]
2-4mA
GPIO12
FANPWM0
GPIO12
GPIOFS10.[2]
2-4mA
GPIO13
FANPWM1
GPIO13
GPIOFS10.[3]
2-4mA
2-4mA
GPIO14
FANFB0
GPIO14
GPIOFS10.[4]
GPIO15
FANFB1
GPIO15
GPIOFS10.[5]
2-4mA
GPIO16
GPIOFS10.[6]
2-4mA
GPIO16
E51TXD
GPIO17
E51CLK
E51RXD
GPIO18
GPIO17
GPIOFS10.[7]
GPIO18
GPIOFS18.[0]
2-4mA
2-4mA
GPIO19
PWM3
GPIO19
GPIOFS18.[1]
8-16mA
GPIO1A
NUMLED#
GPIO1A
GPIOFS18.[2]
8-16mA
GPIO1B
GPIOFS18.[3]
GPIO1C
GPIOFS18.[4]
GPIO1D
GPIOFS18.[5]
8-16mA
GPIO1B
GPIO1C
GPIO1D
CLKRUN#
CLKRUN#
GPIO1E
GPIO1E
GPIOFS18.[6]
GPIO1F
GPIO1F
GPIOFS18.[7]
GPIO20
KSO00
TP_TEST
GPIO20
GPIOFS20.[0]
2-4mA
GPIO21
KSO01
TP_PLL
GPIO21
GPIOFS20.[1]
2-4mA
GPIO22
KSO02
TP_ANA_TEST
GPIO22
GPIOFS20.[2]
2-4mA
GPIO23
KSO03
TP_ISP
GPIO23
GPIOFS20.[3]
2-4mA
GPIO24
KSO04
GPIO24
GPIOFS20.[4]
2-4mA
GPIO25
KSO05
GPIO25
GPIOFS20.[5]
2-4mA
GPIO26
KSO06
GPIO26
GPIOFS20.[6]
2-4mA
GPIO27
KSO07
GPIO27
GPIOFS20.[7]
2-4mA
GPIO28
KSO08
GPIO28
GPIOFS28.[0]
2-4mA
GPIO29
KSO09
GPIO29
GPIOFS28.[1]
2-4mA
GPIO2A
KSO10
GPIO2A
GPIOFS28.[2]
2-4mA
GPIO2B
KSO11
GPIO2B
GPIOFS28.[3]
2-4mA
GPIO2C
KSO12
GPIO2C
GPIOFS28.[4]
2-4mA
GPIO2D
KSO13
GPIO2D
GPIOFS28.[5]
2-4mA
27

GPIO
Alt.
Alt.
Default
Alt. Selection
Input
Output
Pull Up
Open
Output
Output
Input
Alt. Output
Reg.
Enable
Enable
(40K)
Drain
Current
GPIO2E
KSO14
GPIO2E
GPIOFS28.[6]
2-4mA
GPIO2F
KSO15
E51_RXD(ISP)
GPIO2F
GPIOFS28.[7]
2-4mA
GPIO30
E51_TXD(ISP)
KSI0
GPIO30
GPIOFS30.[0]
2-4mA
GPIO31
KSI1
GPIO31
GPIOFS30.[1]
2-4mA
GPIO32
KSI2
GPIO32
GPIOFS30.[2]
2-4mA
GPIO33
KSI3
GPIO33
GPIOFS30.[3]
2-4mA
GPIO34
KSI4
GPIO34
GPIOFS30.[4]
2-4mA
GPIO35
KSI5
GPIO35
GPIOFS30.[5]
2-4mA
GPIO36
KSI6
GPIO36
GPIOFS30.[6]
2-4mA
GPIO37
KSI7
GPIO37
GPIOFS30.[7]
2-4mA
GPI38
AD0
GPIOFS38.[0]
GPI39
AD1
GPIOFS38.[1]
GPI3A
AD2
GPIOFS38.[2]
GPI3B
AD3
GPIOFS38.[3]
GPO3C
DA0
GPO3C
GPIOFS38.[4]
2-4mA
GPO3D
DA1
GPO3D
GPIOFS38.[5]
2-4mA
GPO3E
DA2
GPO3E
GPIOFS38.[6]
2-4mA
GPO3F
DA3
GPO3F
GPIOFS38.[7]
CIR_RX
GPIO40
GPIOFS40.[0]
GPIO41
GPIO42
AD4
GPIO42
GPIO43
AD5
GPIO43
GPIO40
GPIO41
CIR_RLC_TX
2-4mA
GPIOFS40.[1]
GPIOFS40.[2]
2-4mA
GPIOFS40.[3]
2-4mA
2-4mA
2-4mA
GPIO44
SCL0
GPIO44
GPIOFS40.[4]
GPIO45
SDA0
GPIO45
GPIOFS40.[5]
2-4mA
2-4mA
GPIO46
SCL1
GPIO46
GPIOFS40.[6]
2-4mA
GPIO47
SDA1
GPIO47
GPIOFS40.[7]
2-4mA
GPIO48
KSO16
GPIO48
GPIOFS48.[0]
2-4mA
GPIO49
KSO17
GPIO49
GPIOFS48.[1]
2-4mA
GPIO4A
PSCLK0/
GPIO4A
GPIOFS48.[2]
2-4mA
GPIO4B
GPIOFS48.[3]
2-4mA
P80CLK
GPIO4B
PSDAT0/
P80DAT
GPIO4C
PSCLK1
GPIO4C
GPIOFS48.[4]
8-16mA
GPIO4D
PSDAT1
GPIO4D
GPIOFS48.[5]
8-16mA
GPIO4E
PSCLK2
GPIO4E
GPIOFS48.[6]
2-4mA
GPIO4F
PSDAT2
GPIO4F
GPIOFS48.[7]
2-4mA
GPIO50
GPIOFS50.[0]
2-4mA
GPIO51
GPIOFS50.[1]
GPIO50
GPIO51
GPIO52
E51CS#
GPIO52
GPIO53
CAPSLED#
GPIOFS50.[2]
8-16mA
E51TMR1
GPIO53
GPIOFS50.[3]
8-16mA
GPIO54
GPIO55
WDT_LED#
E51TMR0
GPIO54
GPIOFS50.[4]
8-16mA
SCORLED#
E51INT0
GPIO55
GPIOFS50.[5]
8-16mA
2-4mA
GPIO56
GPIO56
GPIOFS50.[6]
GPIO57
XCLK32K
E51INT1
GPIO57
GPIOFS50.[7]
2-4mA
GPIO58
SPICLK
GPIO58
GPIOFS58.[0]
8-16mA
GPIO59
GPIOFS58.[1]
8-16mA
GPIO59
TEST_CLK/
SPICLK
GPXIOA00
SDICS#
GPIO_MISC.[2]
2-4mA
GPXIOA01
SDICLK
GPIO_MISC.[2]
2-4mA
28

GPIO
GPXIOA02
Alt.
Alt.
Default
Alt. Selection
Input
Output
Pull Up
Open
Output
Output
Input
Alt. Output
Reg.
Enable
Enable
(40K)
Drain
Current
2-4mA
GPXIOA03
SDIDO
GPIO_MISC.[2]
2-4mA
GPXIOA04
2-4mA
GPXIOA05
2-4mA
GPXIOA06
2-4mA
GPXIOA07
2-4mA
GPXIOA08
8-16mA
GPXIOA09
8-16mA
GPXIOA10
8-16mA
GPXIOA11
8-16mA
2-4mA
GPXIOD01
2-4mA
GPXIOD02
2-4mA
GPXIOD03
2-4mA
GPXIOD04
2-4mA
GPXIOD05
2-4mA
GPXIOD06
2-4mA
GPXIOD07
2-4mA
GPXIOA12
GPXIOA13
GPXIOA14
GPXIOA15
GPXIOA16
GPXIOA17
GPXIOA18
GPXIOD00
SDIDI
denotes that these pins do not exist in KB926D.
29
4.2.3 GPIO Registers Descriptions

Function Selection Register
Offset
0x00
Name
GPIOFS00
Type.
R/W
Description
GPIO00~GPIO07 Function Selection
Default
Bank
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x02
0xFC
0x00
0xFC
bit[0]~bit[7] stand for GPIO00~GPIO07 separately

0: General purpose output function selected
1: Alternative output function selected.
0x01
GPIOFS08
R/W
GPIO08~GPIO0F Function Selection

bit[0]~bit[7] stand for GPIO08~GPIO0F separately
0x02
GPIOFS10
R/W

0x03
GPIOFS18
R/W

0x04
GPIOFS20
R/W

0x05
GPIOFS28
R/W

0x06
GPIOFS30
R/W

0x07
GPIOFS38
R/W
GPIO3C~GPIO3F Function Selection

bit[4]~bit[7] stand for GPIO3C~GPIO3F separately
If DAC selected, please do not set these related bits to 1.
GPI38~GPI3B without alternative output function.

0x08
GPIOFS40
R/W

GPI42~GPI43 without alternative output function.

0x09
GPIOFS48
R/W

0x0A
GPIOFS50
R/W

0x0B
GPIOFS58
R/W

30
Output Enable Register

Offset
0x10
Name
GPIOOE00
Type.
R/W
Description
GPIO00~GPIO07 Output Enable
Default
Bank
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x02
0xFC

0: Output Disable
1: Output Enable
0x11
GPIOOE08
R/W
GPIO08~GPIO0F Output Enable

0: Output Disable
1: Output Enable
0x12
GPIOOE10
R/W

0: Output Disable
1: Output Enable
0x13
GPIOOE18
R/W

0: Output Disable
1: Output Enable
0x14
GPIOOE20
R/W

0: Output Disable
1: Output Enable
0x15
GPIOOE28
R/W

0: Output Disable
1: Output Enable
0x16
GPIOOE30
R/W

0: Output Disable
1: Output Enable
0x17
GPIOOE38
R/W
GPIO3C~GPIO3F Output Enable

bit[4]~bit[7] stand for GPIO3C~GPIO3F separately
0: Output Disable
1: Output Enable
* GPI38~GPI3A without output enable feature.
0x18
GPIOOE40
R/W

0: Output Disable
1: Output Enable
GPI42~GPI43 without output enable.

0x19
GPIOOE48
R/W

0: Output Disable
1: Output Enable
0x1A
GPIOOE50
R/W

0: Output Disable
1: Output Enable
31
0x1B
GPIOOE58
R/W
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC

0: Output Disable
1: Output Enable
0x1C
GPXAOE00
R/W
GPXIOA00~GPXIOA07 Output Enable

bit[0]~bit[7] stand for GPXIOA00~GPXIOA07 separately
0: Output Disable
1: Output Enable
0x1D
GPXAOE08
R/W

0: Output Disable
1: Output Enable
0x1E
GPXAOE16
R/W

0: Output Disable
1: Output Enable
0x1F
GPXDOE00
R/W
GPXIOD00~GPXIOD07 Output Enable

bit[0]~bit[7] stand for GPXIOD00~GPXIOD07 separately
0: Output Disable
1: Output Enable
32
Output Data Port Register

Offset
Name
Type.
0x20
GPIOD00
R/W
Description
GPIO00~GPIO07 Output Data Port for output function.
Default
Bank
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
Bit[0]~bit[7] stand for GPIO00~GPIO07 separately

0x21
GPIOD08
R/W
GPIO08~GPIO0F Output Data Port for output function.

Bit[0]~bit[7] stand for GPIO08~GPIO0F separately
0x22
GPIOD10
R/W
0x23
GPIOD18
R/W

0x24
GPIOD20
R/W

0x25
GPIOD28
R/W

0x26
GPIOD30
R/W

0x27
GPIOD38
R/W
GPIO3C~GPIO3F Output Data Port for output function.

Bit[4]~bit[7] stand for GPIO3C~GPIO3F separately
* GPI38~GPI3B have no output data ports.
0x28
GPIOD40
R/W

0x29
GPIOD48
R/W

0x2A
GPIOD50
R/W

0x2B
GPIOD58
R/W

0x2C
GPXAD00
R/W
GPXIOA00~GPXIOA07 Output Data Port for output function.

Bit[0]~bit[7] stand for GPXIOA00~GPXIOA07 separately
0x2D
GPXAD08
R/W
0x2E
GPXAD16
R/W
0x2F
GPXDD00
R/W
GPXIOD00~GPXIOD07 Output Data Port for output function.

Bit[0]~bit[7] stand for GPXIOD00~GPXIOD07 separately
33
Input Data Port Register

Offset
0x30
Name
GPIOIN00
Type.
R
Description
GPIO00~GPIO07 Input Data Port for input function.
Default
Bank
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC
0xFF
0xFC

0x31
GPIOIN08
GPIO08~GPIO0F Input Data Port for input function.

0x32
GPIOIN10

0x33
GPIOIN18

0x34
GPIOIN20

0x35
GPIOIN28

0x36
GPIOIN30
0x37
GPIOIN38

GPIO38~GPIO3B Input Data Port for input function.
Bit[0]~bit[3] stand for GPIO38~GPIO3B separately
* GPO3C~GPO3F have no input data ports.
0x38
GPIOIN40

0x39
GPIOIN48
0x3A
GPIOIN50
0x3B
GPIOIN58

0x3C
GPXAIN00
GPXIOA00~GPXIOA07 Input Data Port for input function.

0x3D
GPXAIN08

0x3E
GPXAIN16

0x3F
GPXDIN00
GPXIOD00~GPXIOD07 Input Data Port for input function.

Bit[0]~bit[7] stand for GPXIOD00~GPXIOD07 separately
34
Pull-up Enable Register

Offset
Name
Type.
Description
Default
Bank
0x40
GPIOPU00
R/W
GPIO00~GPIO07 Internal Pull-Up Resistor Enable for input

function
0x00
0xFC
0x08
0xFC
0x00
0xFC
0x00
0xFC
0x0F
0xFC
0x00
0xFC
0xFF
0xFC

0: Pull-Up resistor disable
1: Pull-Up resistor enable
0x41
GPIOPU08
R/W
GPIO08~GPIO0F Internal Pull-Up Resistor Enable for input

function
0x42
GPIOPU10
R/W

function
0x43
GPIOPU18
R/W

function
1: Pull-Up resistor enable.
0x44
GPIOPU20
R/W

function
0x45
GPIOPU28
R/W

function
0x46
GPIOPU30
R/W

function
0x47
RSV
RSV
Reserved
0x48
GPIOPU40
R/W

function
0xFC
0x00
0xFC
0x00
0xFC

0x49
GPIOPU48
R/W

function
35
0x4A
GPIOPU50
R/W

function
0x00
0xFC
0x00
0xFC

0x4B
GPIOPU58
R/W

function
36
Open Drain Enable Register

Offset
Name
Type.
0x50
GPIOOD00
R/W0C
Description
GPIO00~GPIO07 Open Drain Enable for output function
Default
Bank
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC

0: Open drain disable
1: Open drain enable.
0x51
GPIOOD08
R/W0C
GPIO08~GPIO0F Open Drain Enable for output function

0x52
GPIOOD10
R/W0C

0x53
GPIOOD18
R/W0C

0x54
GPIOOD20
R/W0C

0x55
GPIOOD28
R/W0C

0x56
GPIOOD30
R/W0C

0x57
RSV
RSV
0x58
GPIOOD40
R/W0C
RSV
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC

0x59
GPIOOD48
R/W0C

0x5A
GPIOOD50
R/W0C

0x5B
GPIOOD58
R/W0C

37
Input Enable Register

Offset
Name
Type.
0x60
GPIOIE00
R/W
Description
GPIO00~GPIO07 Input Enable for input function
Default
Bank
0x20
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x0F
0xFC
0x00
0xFC
0xFF
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC

0: GPIO input mode disable
1: GPIO input mode enable.
0x61
GPIOIE08
R/W
GPIO08~GPIOF Input Enable for input function

0x62
GPIOIE10
R/W

0x63
GPIOIE18
R/W
GPIO18~GPIO1F Input Enable for input function

0x64
GPIOIE20
R/W

0x65
GPIOIE28
R/W

0x66
GPIOIE30
R/W

0x67
GPIOIE38
R/W
GPIO38~GPIO3B Input Enable for input function

bit[0]~bit[3] stand for GPIO38~GPIO3B separately
* GPO3C~GPO3F have no input functions.
0x68
GPIOIE40
R/W

0x69
GPIOIE48
R/W

0x6A
GPIOIE50
R/W

38

0x6B
GPIOEE58
R/W
0x03
0xFC
0x01
0xFC
0x00
0xFC
0x00
0xFC
0x00
0xFC

0x6C
GPXAIE00
R/W
GPXIOA00~GPXIOA07 Input Enable for input function

0x6D
GPXAIE08
R/W

0x6E
GPXAIE16
R/W

0x6F
GPXDIE00
R/W
GPXIOD00~GPXIOD07 Input Enable for input function

39
GPIO_MISC Control Register

Offset
Name
Bit
Type
0x70
GPIO_MISC
R/W
Description
ESB_DAT(GPIO0C) output current selection
0: 8mA
1: 16mA
R/W
SPICLK(GPIO58) output current selection

0: 8mA
1: 16mA
R/W
ESB_CLK(GPIO0B) output current selection

0: 8mA
1: 16mA
RSV
Reserved
R/W
GPIO17 / GPIO18 are featured with signal bypass function.

Signal input via GPIO17 can be directly passed through
GPIO18.
0: Pass through function disable
1: Pass through function enable
R/W
Alternative functions select for GPXIOA00~GPXIOA02.

0: GPXIOA00~GPXIOA02 remain default output function
1: GPXIOA00~GPXIOA02 become SDICS#, SDICLK, and
SDIDO functions.
R/W
Debug port80 interface selection.

0: Debug port80 interface using P80CLK/P80DAT
1: Debug port80 interface using PSCLK0/PSDAT0 as
P80CLK/P80DAT
R/W
Beep glue logic switch.

GPIO12 can be output a specific function as following formula.
GPIO12 = PWM2
GPIO16(input) GPIO17(input)
0: Beep glue logic function disable

1: Beep glue logic function enable
40
Default
Bank
0x0
0xFC
4.2.4 GPIO Programming Sample

In this section gives some programming sample to control GPIO module. Please note,
ENE does not guarantee these codes in every field application. The following table describes
scenario of GPIO filed application.
Example
PIN
Function
GPIO00 (GA20)
Output
GPIO01 (KBRST#)
Output
GPIO02 (GPIO)
Input
GPIO03 (GPIO)
Input
GPIO04 (GPIO)
Output
GPIO05 (PCIRST#)
Input
GPIO06 (GPIO)
Input
GPIO07 (GPIO)
Output
Programming model
1. set function selection register.
GPIOFS00 (0xFC00) = 0x03
2. set related pins to be output enable.
GPIOOE00 (0xFC10) = 0x93
3. set related pins to be input enable.
GPIOIE00 (0xFC60) = 0x6C
41
4.3 Keyboard and Mouse Control Interface (KBC)

4.3.1 KBC I/F Function Description
The KBC is compatible with i8042 and responsible for keyboard/mouse accessing via
legacy 60h/64h ports. The port 60h is the data port and port 64h is the command port. The legacy
IRQ1 for keyboard devices and IRQ12 for mouse devices can be generated. The KBC interface
provides fast GA20 control for legacy application.
KBC data register can be accessed by host or KBC firmware. Writing this register will setup a
OBF (Output Buffer Full) flag, which can be clear by firmware. While the host issues I/O write to
60h/64h port, an IBF (Input Buffer Full) flag will assert. The interrupts can be programmed to issue
while the flag of IBF/OBF asserting.
The following table gives a summary about port 60h/64h accessing.
Port
Access
Type
Register
Flag
Comment
60h
I/O Write
Data
KBCDAT (0xFC85)
IBF
Write data to keyboard/mouse
64h
I/O Write
Command
KBCCMD (0xFC84)
IBF
Write command to keyboard/mouse
60h
I/O Read
Data
KBCDAT (0xFC85)
OBF
Read data from keyboard/mouse
64h
I/O Read
Status
KBCSTS (0xFC86)
Read status from keyboard/mouse
KBC data register, KBCDAT, keeps data from host or data written by KBC firmware.
Bit
Name
4
3
2
Keyboard/Mouse Data Register
KBC command register, KBCCMD, is used to keep the command from host. This register is
read only.
Bit
Name
5
4
3
2
Keyboard/Mouse Command Register
KBC status register, KBCSTS, keeps the status as the following table. For more detail please
refer to the section, KBC Registers Description.
Bit
Name
Parity Error
Time Out
Aux. Data Flag
Uninhibited
Address (A2)
System Flag
IBF
OBF
42
4.3.2 KBC Registers Description

KBC Command Byte Register (KBC command 20h/60h)
Offset
Name
Bit
Type
0x80
KBCCB
R/W
Description
PS/2 hardware mode enable.
0: Disable
1: Enable
If the host issues command 20h via port 64h, and the KBC
returns data via port 60h. This bit will always be read as zero.
R/W
Scan code set2 conversion enable (PS/2 scan code set2

converts to set 1)
0: Disable
1: Enable
R/W
Disable Auxiliary device

0: Enable
1: Disable
R/W
Disable Keyboard device

0: Enable
1: Disable
R/W
Inhibit Override
0: Disable
1: Enable
R/W
System Flag (warm boot flag)

0: cold boot
1: warm boot
R/W
IRQ12 Enable
While KBCSTS[5]=1(Auxiliary Data Flag) and KBCSTS[0]=1
(OBF), then IRQ12 will issue.
0: Disable
1: Enable
R/W
IRQ1 Enable
While KBCSTS[5]=0 (Auxiliary Data Flag) and KBCSTS[0]=1
(OBF), then IRQ1 will issue.
0: Disable
1: Enable
43
Default
Bank
0x40
0xFC
KBC Configuration
Offset
Name
Bit
Type
0x81
KBCCFG
R/W
Description
Keyboard lock enable
0: Disable
1: Enable
R/W
Fast gate A20 control

0: Disable gate A20 control
1: Enable gate A20 control
R/W
KBC hardware command sets (90h~93h, D4h) enable.

0: Disable
1: Enable
R/W
KBC hardware command sets (60h, A7h~ABh, ADh~AEh)

enable.
0: Disable
1: Enable
R/W
Keyboard lock flag status

0: keyboard not lock or not inhibit
1: keyboard lock or inhibit
R/W
KBC hardware command sets (A4h, A6h) enable.

0: Disable
1: Enable
R/W
IBF (KBCSTS[1]) interrupt enable.
(IBF from 0 to 1)
0: Disable
1: Enable
0
R/W
OBF (KBCSTS[0]) interrupt enable

0: Disable
1: Enable
44
(OBF from 1 to 0)
Default
Bank
0x00
0xFC
KBC Interrupt Pending Flag

Offset
Name
Bit
Type
0x82
KBCIF
7-3
RSV
R/W1C
Description
Reserved
Status of KBC command handled by firmware
While receiving KBC commands which need firmware to
handle, the hardware will set this bit. Then the firmware will
deal with all the following command until this bit is clear by
firmware.
R/W1C
IBF interrupt pending flag

0: no IBF interrupt occurs
1: IBF interrupt occurs
R/W1C
OBF interrupt pending flag

0: no OBF interrupt occurs
1: OBF interrupt occurs
45
Default
Bank
0x00
0xFC
KBC Hardware Command Enable

Offset
Name
Bit
Type
0x83
KBCHWEN
R/W
Description
KBC hardware command set (FEh) enable
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
0: Disable
1: Enable
6
R/W
KBC hardware command set (E0h) enable

0: Disable
1: Enable
R/W
KBC hardware command set (D3h) enable

0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W
KBC hardware command set (C0h) enable

0: Disable
1: Enable
R/W
KBC hardware command set (20h) enable

0: Disable
1: Enable
KBC Command Buffer

Offset
Name
Bit
Type
0x84
KBCCMD
7-0
RO
Description
Command written to port 64h will be stored in this register
KBC Data Input/Output Buffer

Offset
Name
Bit
Type
0x85
KBCDAT
7-0
R/W
Description
Data written to this register to make OBF set (OBF=1).
The host read this register via port 60h.
46
KBC Host Status

Offset
Name
Bit
Type
0x86
KBCSTS
R/W
Description
Parity error
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
0: No parity error occurs in PS/2 protocol

1: Parity error occurs in PS/2 protocol.
6
R/W
Timeout
0: No timeout occurs in PS/2 protocol
1: Timeout occurs in PS/2 protocol.
R/W
Auxiliary data flag
RO
Uninhibited
0: keyboard inhibited
1: keyboard not inhibited
RO
Address (A2)
0: output buffer data from 60h
1: output buffer data from 64h
RO
System flag
R/W1C
IBF
R/W1C
OBF
Reserved
Offset
Name
Bit
Type
0x88
RSV
7-0
RSV
Offset
Name
Bit
Type
0x88
RSV
7-0
RSV
Offset
Name
Bit
Type
0x89
RSV
7-0
RSV
Description
Reserved
Reserved
Description
Reserved
Reserved
Description
Reserved
KBC Write Data

Offset
Name
Bit
Type
0x8A
KBCDATR
7-0
RO
Description
Read back port of KBCDAT, 0xFC85
47
4.4 ENE Serial Bus Controller (ESB)

4.4.1 ESB Function Description
To extend the usage of the current design, an ENE serial bus interface is introduced. An
external ESB device can be controlled by firmware transparently. As the following table, 4 memory
address ranges are reserved for ESB devices.
Memory Range
Range1
0xFCA0~0xFCAF
Range2
0xFCB0~0xFCBF
Range3
0xFCC0~0xFCCF
Range4
0xFEE0~0xFEFF
In the ESB architecture, external ESB devices are supported. And each device can be
configured with interrupt capability. A figure gives the topology of ENE Serial Bus as following.
48
4.4.2 ESB Registers Description

ESB Configuration
Offset
0x90
Name
ESBCFG
Bit
Type
R/W
Description
Loop back test enable
0: Disable
1: Enable
6-5
R/W
ESB clock selection.

00: (main clock) / 8
R/W
External device access mode.

0: Access external device via 4 predefined memory ranges.
(automatic mode)
1: Access external devices via ESBCA, ESBCD and ESBRD
registers. (byte mode)
R/W
ESB clock output enable

0: Disable
1: Enable
R/W
ESB interrupt enable

0: Disable
1: Enable
R/W
ESB host queries device interrupt status automatically. (when

ESBCFG[3]=1)
0: Disable
1: Enable
R/W
ESB function enable

0: Disable
1: Enable
49
Default
Bank
0x00
0xFC
ESB Command and Status

Offset
Name
Bit
Type
0x91
ESBCS
RSV
R/W1C
Description
Reserved
Device resume signal flag.
0: no event
1: event occurs.
R/W1C
ESB bus timeout status

0: no timeout event
1: bus timeout
R/W1C
Device data received status.

0: no data received
1: data received.
ESB host busy flag.

0: not busy
1: host busy
Start to send command, command byte in ESBCD, 0xFC94

Please write 0 will not work.
1: send command
1-0
R/W
ESB access command type (while ESBCFG[3]=1)

00: interrupt query
01: read
10: write
11: Reserved
50
Default
Bank
0x00
0xFC
ESB Interrupt Enable of External Device

Offset
Name
Bit
Type
Description
0x92
ESBINTE
RSV
Reserved
R/W
Device resume signal interrupt enable
Default
Bank
0x00
0xFC
0: Disable
1: Enable
5
R/W
Bus timeout interrupt enable

0: Disable
1: Enable
R/W
Device data received interrupt enable

0: Disable
1: Enable
R/W
Interrupt enable (IRQ3) of external ESB device.

0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W

0: Disable
1: Enable
ESB Command Address

Offset
Name
Bit
0x93
ESBCA
7-0
Type
R/W
Description
External ESB device address to be accessed. (when
ESBCFG[3]=1)
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
The address is predefined according to different device.
ESB Command Data

Offset
0x94
Name
ESBCD
Bit
Type
7-0
R/W
Bit
Type
7-0
R/W
Description
Write data port to external ESB device (when ESBCFG[3]=1)
ESB Received Data

Offset
0x95
Name
ESBRD
Description
Read data port to external ESB device (when ESBCFG[3]=1)
If loop back test enabled, ESBCFG[7]=1, the register will be
writable, otherwise, read-only.
51
ESB Enable for External Device

Offset
Name
Bit
Type
0x96
ESBED
7-5
RSV
R/W
Description
Reserved
Low clock mode enable (clock source 32KHz)
For performance and power saving consideration, while low
clock mode enabled, please set the query function off.
0: Disable
1: Enable
R/W
Enable external ESB device decoding address

0xFEE0~0xFEFF
0: Disable
1: Enable
R/W

0xFCC0~0xFCCF
0: Disable
1: Enable
R/W

0xFCB0~0xFCBF
0: Disable
1: Enable
R/W

0xFD00~0xFDFF.
0: Disable
1: Enable
52
Default
Bank
0x00
0xFC
ESB Interrupt Event Pending Flag for External Chip

Offset
Name
Bit
Type
0x97
ESBINT
R/W1C
Description
Interrupt event pending flag of IRQ7 (cascade mode only)
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
0: no event
1: event occurs
6
R/W1C

0: no event
1: event occurs
R/W1C
I Interrupt event pending flag of IRQ5 (cascade mode only)

0: no event
1: event occurs
R/W1C

0: no event
1: event occurs
R/W1C
Interrupt event pending flag of IRQ3

0: no event
1: event occurs
R/W1C

0: no event
1: event occurs
R/W1C

0: no event
1: event occurs
R/W1C

0: no event
1: event occurs
ESB Cascade Mode Configuration

Offset
Name
Bit
Type
0x98
ESBCAS
R/W
Description
Interrupt enable of IRQ7 for external chip
0: disable
1: enable
R/W

0: disable
1: enable
R/W

0: disable
1: enable
R/W

0: disable
1: enable
3-1
RSV
Reserved
R/W
Cascade mode enable

0: disable
1: enable
53
4.4.3 ESB Programming Sample

In this section gives some programming sample to control ESB module. Please
note, ENE does not guarantee these codes in every field application. The following table describes
scenario of ESB filed application.
Example
A device connecting to ESB master.
Programming model
GPIOFS08[4:3] (0xFC01[4:3])= 11b
; ESB function selection pin
GPIOIE08[4] (0xFC61[4]) = 1b
; set related pin as an input
ESBCFG (0xFC90) = 0x69
; ESB clock=32MHz / EPB mode enable
ESBED (0xFC96) = 0x02
; enable ESB
Now F/W can access register 0xFCC0~0xFCCF
54
4.5 Internal KeyBoard (IKB) Encoder

4.5.1 IKB Function Description
The KBC supports internal keyboard encoder (IKB) in the notebook system. Here is the
feature highlight of IKB module.
- Support 18x8 matrix.
- Keyboard scan output (KSO) 18 lines.
- Keyboard scan input (KSI) 8 lines
- KSO/KSI can be programmed to be GPIO
- KSO/KSI internal programmable pull-high feature supported.
55
4.5.2 IKB Registers Description

IKB Configuration
Offset
Name
Bit
Type
Description
0xA0
IKBCFG
R/W
IKB scan controller test mode enable.

0: Disable
1: Enable
R/W
IKB PS/2 wait time setting. The IKB makes sure PS/2 bus idle
for specific time and then transmit the scan codes.
0: 8 s
1: 64s
RSV
Reserved
WO
Force controller to scan key matrix. Write 1 to start.
RSV
Reserved
R/W
IKB scan repeat enable.

Set this bit force the IKB controller to scan every 30ms.
0: Disable
1: Enable
R/W
Standard KB command hardware mode enable.

Once the IKB received standard KB command, the hardware
will handle it.
0: Disable
1: Enable
R/W
IKB scan controller enable.

0: Disable
1: Enable
56
Default
Bank
0x00
0xFC
IKB LED Control

Offset
Name
Bit
Type
0xA1
IKBLED
R/W
Description
NumLock key
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
0: Fn-Lock
1: NumLock =Fn-Lock
6
R/W
Flag of Fn-Shift (in hardware mode)

0: Fn-Shift not pressed
1: Fn-Shift pressed
R/W
Flag of Fn-Lock (in hardware mode)

0: Fn-Lock not pressed
1: Fn-Lock pressed
R/W
LED output polarity, CapLock/NumLock/ScrLock output

0: positive logic
1: negative logic
RSV
Reserved
R/W
CapLock LED driving

Once EC firmware gets the command to light up CapLock
LED, F/W will setup this bit.
R/W
NumLock LED driving

Once EC firmware gets the command to light up NumLock
R/W
ScrLock LED driving

Once EC firmware gets the command to light up ScrLock
IKB Typematic Control

Offset
Name
Bit
Type
0xA2
IKBTYPEC
RSV
6-5
R/W
Description
Reserved
st
1 key repeat delay time selection.

00b: 250ms
01b: 500ms
10b: 750ms
11b: 1 sec
4-0
R/W
Typematic repeat characters per second.

1Fh: 2 char/sec
10h: 10 char/sec
1Bh: 3 char/sec
0Dh: 12 char/sec
18h: 4 char/sec
0Bh: 15 char/sec
17h: 5 char/sec
08h: 16 char/sec
15h: 6 char/sec
05h: 20 char/sec
13h: 8 char/sec
00h: 30 char/sec
57
IKB Interrupt Enable

Offset
Name
Bit
Type
Description
0xA3
IKBIE
7-6
RSV
Reserved
R/W
Interrupt enable. While the following commands handled by

hardware occur.
KB reset / KB disable / Non-standard hardware mode
command
0: Disable
1: Enable
R/W
IKB RX finished interrupt enable.

0: Disable
1: Enable
R/W
IKB TX finished interrupt enable.

0: Disable
1: Enable
R/W
IKB typmatic repeat timeout interrupt enable.

0: Disable
1: Enable
R/W
IKB scan code finished interrupt enable. (IKBHCFG[0]=0)

0: Disable
1: Enable
Or IKB break key (hotkey) interrupt enable. (IKBHCFG[0]=1)
0: Disable
1: Enable
R/W
IKB make key interrupt enable. (IKBHCFG[0]=0)

0: Disable
1: Enable
Or IKB make key (hotkey) interrupt enable. (IKBHCFG[0]=1)
0: Disable
1: Enable
58
Default
Bank
0x00
0xFC
IKB Interrupt Pending Flag

Offset
Name
Bit
Type
0xA4
IKBPF
WO
Description
Force the IKB controller enter idle mode.
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
Write 1 to enter idle mode.

6
R/W1C
IKBSADR (0xFCA9) valid flag.

0: no more valid IKBSADR
1: IKBSADR valid
R/W1C
Interrupt flag. While the following commands handled by

hardware occur.
KB reset / KB disable
0: event is not active
1: event is active
R/W1C
IKB RX finished and non-standard hardware mode command

occurring interrupt flag.
1: event is active
R/W1C
IKB TX finished interrupt flag.

1: event is active
R/W1C
IKB typmatic repeat timeout interrupt flag

1: event is active
R/W1C
IKB scan code finished interrupt flag. (IKBHCFG[0]=0)

IKB break key (hotkey) interrupt flag. (IKBHCFG[0]=1)
1: event is active
R/W1C
IKB make key interrupt flag. (IKBHCFG[0]=0)

IKB make key (hotkey) interrupt flag. (IKBHCFG[0]=1)
0: Disable
1: Enable
IKB PS/2 TX Data Byte

Offset
Name
Bit
Type
0xA5
IKBTXDAT
7-0
R/W
Description
The IKB port to transmit data to PS/2 controller
Writing to this port, the data will be delivered to PS/2 controller.
After transmission completes and a TX finished interrupt
issues.
IKB PS/2 RX Data Byte

Offset
Name
Bit
Type
0xA6
IKBRXDAT
7-0
R/W
Description
The IKB port to receive data from PS/2 controller.
After receiving data from PS/2 controller, a RX finished
interrupt issues.
59
IKB Hardware Mode Configuration

Offset
Name
Bit
Type
Description
0xA7
IKBHCFG
7-3
RSV
Reserved
R/W
IKB hotkey flag while hardware mode enable (IKBCFG[0]=1)
Default
Bank
0x00
0xFC

1: event is active
1
R/W
IKB hotkey finish indicator

While KBC recognizes a hotkey, the KBC setup the hotkey flag
(IKBCFG[2]) to invoke firmware to handle. Firmware will write
1 to this bit after completing the hotkey event.
R/W
IKB hardware mode enable

0: Disable
1: Enable
IKB Scan Inputs

Offset
Name
Bit
Type
0xA8
IKBKSI
7-0
RO
Description
IKB scan input buffer
Default
Bank
0x00
0xFC
IKB Scan Address

Offset
Name
Bit
Type
0xA9
IKBSADR
7-0
RO
Description
IKB scan address of current key
Default
Bank
0x00
0xFC
Default
Bank
0xF7
0xFC
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
IKB Scan Timing Control

Offset
Name
Bit
Type
0xAA
IKBSDB
7-4
R/W
3-0
R/W
Description
KSO release (floating) time
Time = (value + 1) * 8s
KSO drive low time
Time = (value + 1) * 8s
IKB Make Key (hardware mode)

Offset
0xAB
Name
IKBMK
Bit
Type
7-0
RO
Description
The scan controller places make key in this register.
If hotkey occurs, the register contains the matrix value.
IKB Break Key (hardware mode)

Offset
Name
Bit
Type
0xAC
IKBBK
7-0
RO
Description
The scan controller places break key in this register.
If hotkey occurs, the register contains the matrix value.
Reserved
Offset
Name
Bit
Type
0xAD
RSV
7-0
RSV
Description
Reserved
60
IKB Matrix Table Address (hardware mode)

Offset
0xAE
Name
IKBMTA
Bit
Type
7-3
RSV
RSV
Description
2-0
R/W
IKB Matrix Table Address = 0xF400 + (IKBMTA * 0x100)

0: 0xF400~0xF4FF
4: 0xF800~0xF8FF
1: 0xF500~0xF5FF
5: 0xF900~0xF9FF
2: 0xF600~0xF6FF
6: 0xFA00~0xFAFF
3: 0xF700~0xF7FF
7: 0xFB00~0xFBFF
Default
Bank
0x00
0xFC
Default
Bank
0x00
0xFC
IKB Key Generation Flag

Offset
Name
Bit
Type
0xAF
IKBKGENFG
7-3
RSV
RO
Description
IKB code buffer full flag. When the code buffer full, this flag will
be set.
0: not over 8 keys in the code buffer.
1: 8 keys in the code buffer..
R/W1C
Ghost key identification flag (IKBHCFG[0]=1)

0: No ghost key
1: Ghost key found
R/W1C
IKB make key scan flag. If this bit is set to 1, all the make
keys will be ignored.
0: not over 5 make key occur at a time
1: over 5 make key occur at a time
61
4.5.3 IKB Matrix Value Mapping Table

In this section, the following tables show the mapping information between matrix value
and PS/2 set1 scan code. The first one is the standard keys mapping, and the second one is for
multimedia keys mapping.
Standard Keys
Matrix
Value
Description
(set 2)
Scan Code
(set 1)
Matrix
Value
Description
(set 2)
(set 1)
00h
Error(overrun)
FFh
40h
01h
F9
43h
41h
02h
F7
41h
42h
25h
03h
F5
3Fh
43h
17h
04h
F3
3Dh
44h
18h
05h
F1
3Bh
45h
0Bh
06h
F2
3Ch
46h
0Ah
07h
F12
58h
47h
Reserved
60h
08h
Reserved
64h
48h
Reserved
6Ch
09h
F10
44h
49h
>
34h
0Ah
F8
42h
4Ah
35h
0Bh
F6
40h
4Bh
0Ch
F4
3Eh
4Ch
0Dh
Tab
0Fh
4Dh
0Eh
29h
4Eh
0Fh
Reserved
59h
4Fh
Reserved
61h
10h
Reserved
65h
50h
Reserved
6Dh
11h
Left Alt
38h
51h
Reserved
73h
12h
Left Shift
2Ah
52h
13h
Reserved
70h
53h
14h
Left Ctrl
1Dh
54h
1Ah
15h
10h
55h
0Dh
02h
56h
Reserved
62h
16h
Reserved
Scan Code
<
L
:
33h
26h
;
27h
0Ch
P
_
6Bh
19h
Reserved
28h
74h
17h
Reserved
5Ah
57h
Reserved
6Eh
18h
Reserved
66h
58h
Caps Lock
3Ah
19h
Reserved
71h
59h
Right Shift
36h
1Ah
2Ch
5Ah
Return
1Ch
1Bh
1Fh
5Bh
1Ch
1Eh
5Ch
Reserved
75h
1Dh
11h
5Dh
|\(US only) ~#(102-key)
2Bh
03h
5Eh
Reserved
63h
1Eh
1Bh
1Fh
Reserved
5Bh
5Fh
Reserved
76h
20h
Reserved
67h
60h
Fn (PTL)
55h
21h
2Eh
61h
|\(102-key)
56h
62

22h
2Dh
62h
Reserved
77h
23h
20h
63h
Reserved
78h
24h
12h
64h
Reserved
79h
25h
5Ch
65h
Reserved
7Ah
26h
04h
66h
Backspace
0Eh
27h
Reserved
05h
67h
Reserved
7Bh
28h
Reserved
68h
68h
Reserved
7Ch
29h
Space
39h
69h
2Ah
2Fh
6Ah
Reserved
2Bh
21h
6Bh
2Ch
14h
6Ch
2Dh
13h
2Eh
End
4Fh
7Dh
Left Arrow
4Bh
Home
47h
6Dh
Reserved
7Eh
06h
6Eh
Reserved
7Fh
Reserved
6Fh
2Fh
Reserved
5Dh
6Fh
30h
Reserved
69h
70h
Ins
52h
31h
31h
71h
Del
53h
32h
30h
72h
Down Arrow
50h
33h
23h
73h
34h
22h
74h
35h
15h
75h
36h
^ 6
07h
37h
Reserved
38h
39h
5
6
4Ch
Right Arrow
4Dh
Up Arrow
48h
76h
ESC
01h
5Eh
77h
Num Lock
45h
Reserved
6Ah
78h
F11
57h
Reserved
72h
79h
4Eh
3Ah
32h
7Ah
PgDn
51h
3Bh
24h
7Bh
4Ah
3Ch
16h
7Ch
37h
PgUp
49h
3Dh
&
08h
7Dh
3Eh
09h
7Eh
Scroll Lock
46h
5Fh
7Fh
Sys Req (84-key)
54h
3Fh
Reserved
63
Multimedia Keys
Matrix
Value
Description
(set 2)
Scan Code
(set 1)
Matrix
Value
Description
(set 2)
Scan Code
(set 1)
00h 7Fh
Standard Keys
See table
above
9Ah
ACPI Sleep
E0 5F
80h
Left Shift
2Ah
9Bh
ACPI Wake
E0 63
81h
Left Ctrl
1Dh
9Ch
Left Window
E0 5B
82h
Left Alt
38h
9Dh
Right Window
E0 5C
83h
F7
41h
9Eh
Windows App
E0 5D
84h
SysReq
54h
9Fh
Break
1D E0 46
85h
Right Shift
36h
A0h
Volume Up
E0h 30h
86h
Right Ctrl
E0h 1Dh
A1h
Volume Down
E0h 2Eh
87h
Right Alt
E0h 38h
A2h
Next
E0h 19h
88h
Print Screen
E0h 2Ah E0h

37h
A3h
Previous
E0h 10h
89h
Pause
E1h 1Dh 45h
A4h
Stop
E0h 24h
8Ah
Insert
E0h 52h
A5h
Play/Pause
E0h 22h
8Bh
Home
E0h 47h
A6h
Mute
E0h 20h
8Ch
Page Up
E0h 49h
A7h
Media Select
E0h 6Dh
8Dh
Delete
E0h 53h
A8h
Email Reader
E0h 6Ch
8Eh
End
E0h 4Fh
A9h
Calculator
E0h 21h
8Fh
Page Down
E0h 51h
Aah
My Computer
E0h 6Bh
90h
Up Arrow
E0h 48h
Abh
WWW Search
E0h 65h
91h
Left Arrow
E0h 41h
Ach
WWW Home
E0h 32h
92h
Down Arrow
E0h 50h
Adh
WWW Back
E0h 6Ah
93h
Right Arrow
E0h 4Dh
Aeh
WWW Forward
E0h 69h
94h
E0h 35h
Afh
WWW Stop
E0h 68h
95h
Enter
E0h 1Ch
B0h
WWW Refresh
E0h 67h
96h
Fn Shift
No scan
code
B1h
WWW Favor
E0h 66h
97h
Fn Lock
No scan
code
B2h
OADG
45h/46h
98h
Num/Fn Lock
45h
B3h
Empty Key
No scan
code
99h
ACPI Power
E0h 5Eh
B4h FFh
Hot Key
64
4.6 Pulse Width Modulation (PWM)

4.6.1 PWM Function Description
Pulse width modulation (PWM) is a powerful technique for controlling analog circuits with
a processors digital outputs. PWM is employed in a wide variety of applications, ranging from
measurement and communications to power control and conversion.
The KBC supports 4 PWM channels. 2 channels (PWM0/PWM1) are for 8-bit resolution
and 2 channels (PWM2/PWM3) are for 14-bit resolution. The PWM provides clock source selection
which is defined in the register description.
. The duty cycle of PWM can be illustrated as the above figure. The following
summarizes the relationship about the applications with the definition in the PWM registers
description.
Definition
Duty Cycle
Cycle Length
Cycle Length
Formula
Comment
(PWM High Period Length+1)/(PWM Cycle Period Length+1) *100%

( PWM Cycle Length Register +1) * (PWM clock source)
( PWMCYC + 1 ) * 2 * ( 1 + Prescaler )/(Peripheral clock or fixed 1 MHz)
For 8-bit
For 14-bit
For the limitation of current design, in some critical cases, the PWM output will be the
one as the following table.
Condition
PWM Output
H>C
Always 1 (High)
H=0x00 and C=0x00
Always 1 (High)
H=0x00 and C=0xFF
A Short Pulse
H=0xFF and C=0x00
Always 1 (High)
Switch to GPIO mode and output low
Always 0 (Low)
H= High Period Length (PWMHIGH) , C= Cycle Period Length (PWMCYCL)
65
4.6.2 PWM Registers Description

PWM Configuration
Offset
0x00
Name
PWMCFG
Bit
Type
7-6
R/W
Description
PWM1 clock source selection
Default
Bank
0x00
0xFE
0: 0.976s (1s)
1: 62.5s (64s)
2: 250s (2561s)
3: 3.99ms (4ms)
5
RSV
R/W
Reserved
PWM1 Enable
0: Disable
1: Enable
3-2
R/W
PWM0 clock source selection

0: 0.976s (1s)
1: 62.5s (64s)
2: 250s (2561s)
3: 3.99ms (4ms)
RSV
Reserved
R/W
PWM0 Enable
0: Disable
1: Enable
PWM0 High Period Length

Offset
Name
Bit
Type
Description
Default
Bank
0x01
PWMHIGH0
7-0
R/W
High Period Length of PWM0. This should be smaller than

Cycle Length.
0x00
0xFE
Bit
Type
Description
Default
Bank
7-0
R/W
0x00
0xFE
PWM0 Cycle Length

Offset
0x02
Name
PWMCYC0
Cycle Length of PWM0.
PWM1 High Period Length

Offset
0x03
Name
PWMHIGH1
Bit
Type
Description
Default
Bank
7-0
R/W
High Period Length of PWM1. This should be smaller than

Cycle Length.
0x00
0xFE
Description
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
PWM1 Cycle Length

Offset
Name
Bit
Type
0x04
PWMCYC1
7-0
R/W
Cycle Length of PWM1
Reserved
Offset
Name
Bit
Type
0x05
RSV
7-0
RSV
Description
RSV
66
PWM2 Configuration
Offset
Name
Bit
Type
0x06
PWMCFG2
R/W
Description
PWM2 Enable
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0: Disable
1: Enable
6
R/W
PWM2 prescaler clock selection

0: peripheral clock
1: 1MHz clock (fixed)
5-0
R/W
The 6-bit prescaler of PWM2

The precaler value = register value + 1
PWM3 Configuration
Offset
0x07
Name
PWMCFG3
Bit
Type
R/W
Description
PWM3 Enable
0: Disable
1: Enable
R/W
PWM3 prescaler clock selection

0: peripheral clock
1: 1MHz clock (fixed)
5-0
R/W
The 6-bit prescaler of PWM3

The precaler value = register value + 1
PWM2 High Period Length (14-bit)

Offset
Name
Bit
Type
Description
0x08
PWMHIGH2H
5-0
R/W
Higher 6 bits (of 14-bit)
0x00
0xFE
0x09
PWMHIGH2L
7-0
R/W
Lower 8 bits (of 14-bit)
0x00
0xFE
Default
Bank
PWM2 Cycle Length (14-bit)

Offset
Name
Bit
Type
Description
0x0A
PWMCYC2H
5-0
R/W
0x00
0xFE
0x0B
PWMCYC2L
7-0
R/W
0x00
0xFE
Default
Bank
PWM3 High Period Length (14-bit)

Offset
Name
Bit
Type
Description
0x0C
PWMHIGH3H
5-0
R/W
0x00
0xFE
0x0D
PWMHIGH3L
7-0
R/W
0x00
0xFE
PWM3 Cycle Length (14-bit)

Offset
Name
0x0E
PWMCYC3H
0x0F
PWMCYC3L
Bit
Type
Default
Bank
5-0
R/W
0x00
0xFE
7-0
R/W
0x00
0xFE
Description
67
4.6.3 PWM Programming Sample

In this section gives some programming sample to control PWM module. Please note,
scenario of PWM filed application.
Example
Programming PWM0 with a period 100ms and high period 40ms, that is,
duty cycle is 40%.
100 m s
40 m s
Programming model
1. set related GPIO function selection register.
GPIOFS08[7] (0xFC01[7]) = 1b
2. clock selection = 4ms
PWMCFG[3:0] (0xFE00[3:0]) = 1101b
3. cycle = 4ms * (24+1)
PWMCYCL0 (0xFE02) = 0x18
4. duty cycle = (9+1)/(24+1) = 40%
PWMHIGH0 (0xFE01) = 0x09
68
4.7 Fan Controller

4.7.1 Fan Function Description
The KBC provides 2 interfaces with speed monitor for fan control. Two clock selections
for fan controller, one is main clock base and the other is fixed 62.5s. The fan controller can be
configured as a PWM function, as known as FANPWM.
4.7.1.1 Fan Tachometer Monitor

The fan tachometer is implemented by a 12-bit counter with two clock selections,
system clock or fixed 62.5s. The following figure gives an example for fan speed monitor and
control. The KBC uses the pin FANPWM0/1 to drive external fan device, and the fan device
feedback the speed via the pin FANFB0/1. The fan controller keeps the speed in the monitor
register. The fan controller will compare the speed and check if the current speed is higher or
slower than the expected one. If slower, then the controller will increase the frequency to drive
FANPWM0/1 automatically, otherwise decrease the frequency. The expected speed can be
programmable by F/W.
Here a RPM table is given for programmers. In this table, the information between RPM
and value for fan speed set is shown.
RPM
Round/1min
Round/1sec
s/Round
Value (Set Counter)
6000
6000
100
10000
160 (10000/62.5)
5000
5000
83.33
12000
192 (12000/62.5)
4000
4000
66.667
15000
240 (15000/62.5)
3000
3000
50
20000
320 (20000/62.5)
2000
2000
33.333
30000
480 (30000/62.5)
1000
1000
16.667
60000
960 (60000/62.5)
500
500
8.3
120000
1920(120000/62.5)
RPM (round/min) = 60,000,000 / (FANMON *62.5)
69
4.7.1.2 FANPWM Function

The fan controller can be used as a 12-bit PWM function. While PWM function
applied, the fan controller will refer to the peripheral clock, and the PWM high period and cycle time
can be determined as the following formula:
Cycle Length = (PWM cycle register + 1 ) * peripheral clock
PWM High Period = (PWM high period register + 1 ) * peripheral clock
Please note, to program the high pulse width of PWM (FANPWMH0/FANPWML0
and FANPWMH1/FANPWML1, i.e., 0xFE26/0xFE27 and 0xFE36/0xFE37), high-byte first and
then low-byte in order.
70
4.7.2 Fan Registers Description

Fan0 Configuration
Offset
0x20
Name
FANCFG0
Bit
Type
R/W
Description
FAN0 monitor clock selection.
0: peripheral clock
1: fixed 62.5s (64s)
R/W
FAN0 speed monitor counter edge selection.

Fan speed monitor counts the high period number between
edges.
0: count between two rising edges.
1: count between one rising and one falling edge.
R/W
FANPWM0 cycle width enable

0: Disable
1: Enable
R/W
FANPWM0 enable.
0: Disable
1: Enable
R/W
FAN0 speed monitor interrupt enable

0: Disable
1: Enable
R/W
FAN0 speed monitor timeout error interrupt enable

0: Disable
1: Enable
R/W
Automatic FANPWM control enable. FANCFG0[0] and

FANCFG0[4] should be set at the same time to make it work.
Please note, once enabled, if fan speed monitor counter
smaller than 128, i.e., feedback frequency smaller than 3ms,
the automatic fan control will take it as noise.
0: Disable
1: Enable
R/W
FAN0 tachometer monitor enable.

0: Disable
1: Enable
71
Default
Bank
0x00
0xFE
Fan0 Control and Status Register

Offset
Name
Bit
Type
0x21
FANSTS0
R/W
Description
Fan auto-load FANCPWM function enable. (FAN0)
Default
Bank
0x00
0xFE
0: Disable
1: Enable
6-5
RSV
Reserved
R/W
FAN0 digital noise filter enable.

0: Disable
1: Enable
3-2
RSV
R/W1C
Reserved
Flag of FAN0 speed monitor timeout error
0: no timeout error
1: timeout error event
R/W1C
Flag of FAN0 speed monitor update event.

0: no update event.
1: update event
Fan0 Speed Monitor Counter Value (12-bit)

Offset
Name
Bit
Type
Default
Bank
High 4 bits of FAN0 speed monitor counter value
0x0F
0xFE
Low 8 bits of FAN0 speed monitor counter value
0xFF
0xFE
Default
Bank
0x22
FANMONH0
3-0
RO
0x23
FANMONL0
7-0
RO
Description
Fan0 Speed Set Counter Value (12-bit)

Offset
Name
Bit
Type
Description
0x24
FANSETH0
3-0
R/W
High 4 bits of target FAN0 speed counter value.
0x00
0xFE
0x25
FANSETL0
7-0
R/W
Low 8 bits of target FAN0 speed counter value.
0x00
0xFE
FANPWM0 High Pulse Width Bits (12-bit)

Offset
Name
Bit
Type
Description
Default
Bank
0x26
FANPWMH0
3-0
R/W
High 4 bits of FANPWM0 high pulse width. (FANCFG0[1]=0

only)
0x00
0xFE
0x00
0xFE
PWM high period =

(PWM high pulse register + 1) * peripheral clock
0x27
FANPWML0
7-0
R/W
Low 8 bits of FANPWM0 high pulse width. (FANCFG0[1]=0

only)
PWM high period =
Current FANPWM0 High Pulse Width Bits (12-bit)

Offset
Name
Bit
Type
Default
Bank
0x28
FANCPWMH0
3-0
RO
High 4 bits of current FANPWM0 high pulse width.

(FANCFG0[1]=0 only)
0x00
0xFE
0x29
FANCPWML0
7-0
RO
Low 8 bits of current FANPWM0 high pulse width.

(FANCFG0[1]=0 only)
0x00
0xFE
Description
72
FANPWM0 Cycle Length (12-bit)

Offset
Name
0x2A
FANPWMCH0
Bit
Type
3-0
R/W
Description
High 4 bits of Cycle length of FANPWM0 (FANCFG0[5]=1)
Default
Bank
0x00
0xFE
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Cycle length = (PWM cycle register + 1 ) * peripheral clock

0x2B
FANPWMCHL0
7-0
R/W
Low 8 bits of Cycle length of FANPWM0 (FANCFG0[5]=1)

FANPWM0 Auto-Load High Pulse Width Bits

Offset
Name
Bit
Type
Description
0x2C
FANUPWM0
7-4
RSV
Reserved
3-0
R/W
If auto-load feature enabled (FANSTS0[7]=1), this register

value will be auto-loaded into FANCPWMH0 registers and
FANCPWML0 will be forced to be zero while monitor timeout
occurs
Bit
Type
R/W
Fan1 Configuration
Offset
0x30
Name
FANCFG1
Description
FAN1 monitor clock selection.
0: peripheral clock
1: fixed 64s
R/W
FAN1 speed monitor counter edge selection.

Fan speed monitor counts the high period number between
edges.
0: count between two rising edges.
1: count between one rising and one falling edge.
R/W
FANPWM1 cycle width enable

0: Disable
1: Enable
R/W
FANPWM1 enable.
0: Disable
1: Enable
R/W
FAN1 speed monitor interrupt enable

0: Disable
1: Enable
R/W
FAN1 speed monitor timeout error interrupt enable

0: Disable
1: Enable
R/W
Automatic FANPWM control enable. FANCFG1[0] and

FANCFG1[4] should be set at the same time to make it work.
Please note, once enabled, if fan speed monitor counter
smaller than 128, i.e., feedback frequency smaller than 3ms,
the automatic fan control will take it as noise.
0: Disable
1: Enable
R/W
FAN1 tachometer monitor enable.

0: Disable
1: Enable
73
Fan1 Control and Status Register

Offset
Name
Bit
Type
0x31
FANSTS1
R/W
Description
Fan auto-load FANCPWM function enable. (FAN1)
Default
Bank
0x00
0xFE
0: Disable
1: Enable
6-5
R/W
Reserved
R/W
FAN1 digital noise filter enable.

0: Disable
1: Enable
3-2
R/W
Reserved
R/W
Flag of FAN1 speed monitor timeout error

0: no timeout error
1: timeout error event
R/W
Flag of FAN1 speed monitor update event.

0: no update event.
1: update event
Fan1 Speed Monitor Counter Value (12-bit)

Offset
Name
Bit
Type
Default
Bank
High 4 bits of FAN1 speed monitor counter value
0x0F
0xFE
Low 8 bits of FAN1 speed monitor counter value
0xFF
0xFE
Default
Bank
0x32
FANMONH1
3-0
R/W
0x33
FANMONL1
7-0
R/W
Description
Fan1 Speed Set Counter Value (12-bit)

Offset
Name
Bit
Type
Description
0x34
FANSETH1
3-0
R/W
High 4 bits of target FAN1 speed counter value.
0x00
0xFE
0x35
FANSETL1
7-0
R/W
Low 8 bits of target FAN1 speed counter value.
0x00
0xFE
FANPWM1 High Pulse Width Bits (12-bit)

Offset
Name
Bit
Type
Description
Default
Bank
0x36
FANPWMH1
3-0
R/W
High 4 bits of FANPWM1 high pulse width. (FANCFG1[1]=0

only)
0x00
0xFE
0x00
0xFE
PWM high period =

0x37
FANPWML1
7-0
R/W
Low 8 bits of FANPWM1 high pulse width. (FANCFG1[1]=0

only)
PWM high period =
Current FANPWM1 High Pulse Width Bits (12-bit)

Offset
Name
Bit
Type
Default
Bank
0x38
FANCPWMH1
3-0
RO
High 4 bits of current FANPWM0 high pulse width.

(FANCFG1[1]=0 only)
0x00
0xFE
0x39
FANCPWML1
7-0
RO
Low 8 bits of current FANPWM0 high pulse width.

(FANCFG1[1]=0 only)
0x00
0xFE
Description
74
FANPWM1 Cycle Length (12-bit)

Offset
Name
Bit
Type
0x3A
FANPWMCH1
3-0
R/W
Description
High 4 bits of Cycle length of FANPWM1 (FANCFG1[5]=1)
Default
Bank
0x00
0xFE
0x00
0xFE
Default
Bank
0x00
0xFE

0x3B
FANPWMCHL1
7-0
R/W
Low 8 bits of Cycle length of FANPWM1 (FANCFG1[5]=1)

FANPWM1 Update High Pulse Width Bits

Offset
Name
Bit
Type
0x3C
FANUPWM1
7-4
RSV
Reserved
3-0
R/W
If auto-load feature enabled (FANSTS1[7]=1), this register

value will be auto-loaded into FANCPWMH1 registers and
FANCPWML1 will be forced to be zero while monitor timeout
occurs
Description
75
4.7.3 Fan Programming Sample

In this section gives some programming sample to control FAN module. Please note, ENE
does not guarantee these codes in every field application. The following table describes scenario of
FAN filed application.
Example
FAN0 @ 4000 rpm with automatic PWM control
FAN1 @ some rpm with fixed PWM control
Programming model
For FAN0:
1. set related GPIO function select register to enable alternative output.
GPIOFS10[2] (0xFC02[2]) = 1b
2. set related GPIO input enable.
GPIOIE10[4] (0xFC62[4]) = 1b
3. set FAN0 configuration register
FANCFG0 (0xFE20) = 0x93
4. set FAN0 speed monitor counter value
FANMONH0 (0xFE24) = 0x00
FANMONL0 (0xFE25) = 0xF0
For FAN1:
1. set related GPIO function select register to enable alternative output.
GPIOFS10[3] (0xFC02[3]) = 1b
2. set FAN1 configuration register
FANCFG1 (0xFE30) = 0x90
3. set FAN1 speed monitor counter value
FANPWMH1 (0xFE36) = 0x03
FANPWML2 (0xFE37) = 0xE8
76
4.8 General Purpose Timer (GPT)

4.8.1 GPT Function Description
The KBC provides 4 GPTs (General Purpose Timers), two 16-bit timers and two 8-bit
timers. These 4 GPTs operate based on 32.768KHz and all timers have the interrupt capability. The
GPT is simply a free run counter. While the timer meets the specific value in count register, for
instance, 0xFE53 and 0xFE55, an interrupt issues (if interrupt enabled) and the counter reset to be
zero.
- GPT0 and GPT1 are 8-bit timers.
- GPT2 and GPT3 are 16-bit timers.
4.8.2 GPT Registers Description

GPT Configuration
Offset
0x50
Name
GPTCFG
Bit
Type
7-5
RSV
Reserved
Description
R/W
GPT test mode enable.
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
In test mode, the GPT runs with main clock.

0: Disable
1: Enable
3
R/W
GPT3 counting and interrupt enable.

0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W

0: Disable
1: Enable
GPT Pending Flag

Offset
Name
Bit
Type
0x51
GPTPF
WO
Writing 1 to this bit forces GPT3 restart.
WO
WO
WO
R/W1C
Interrupt pending flag of GPT3.
R/W1C
R/W1C
R/W1C
Description
77
Reserved
Offset
Name
Bit
Type
0x52
RSV
7-0
RSV
Description
Reserved
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
0x00
0xFE
Default
Bank
0x00
0xFE
0x00
0xFE
GPT0 Counter Value

Offset
Name
Bit
Type
0x53
GPT0
7-0
R/W
Description
Once GPT0 counter meets this value, an interrupt issues.
GPT0 restart to count from zero.
Reserved
Offset
Name
Bit
Type
0x54
RSV
7-0
RSV
Description
Reserved
GPT1 Counter Value

Offset
Name
Bit
Type
0x55
GPT1
7-0
R/W
Description
Once GPT1 counter meets this value, an interrupt issues.
GPT2 Counter Value (16-bit)

Offset
Name
Bit
Type
0x56
GPT2H
7-0
R/W
Description
High byte of GPT2 counter value.
Once GPT2 counter meets this 16-bit value, an interrupt
issues.
0x57
GPT2L
7-0
R/W
Low byte of GPT2 counter value.

issues.
GPT3 Counter Value (16-bit)

Offset
0x58
Name
GPT3H
Bit
Type
7-0
R/W
Description
High byte of GPT3 counter value.
issues.
0x59
GPT3L
7-0
R/W
Low byte of GPT3 counter value.

issues.
78
4.8.3 GPT Programming Sample

In this section gives some programming sample to control GPT module. Please note,
scenario of GPT filed application.
Example
Programming GPT0 to issue an interrupt every 5ms
Programming model
1. set GPT configuration register, enable GPT0 interrupt.
GPTCFG[0] (0xFE50[0]) = 1b
2. fill the GPT counter value.
GPT0 (0xFE53) = 0xA6 ; 5000/30 = 0xA6
79
4.9 Serial Device Interface Controller (SDI)

4.9.1 SDI Function Description
The Serial Peripheral Interface Bus or SPI (often pronounced spy) bus is a
synchronous serial data link standard designed by Motorola that operates in full duplex mode.
Devices communicate in master/slave mode where the master device initiates the data frame.
Multiple slave devices are allowed with individual slave select (chip select) lines. The following
figure gives an example of how a SPI master works with 3 SPI slaves.
Where
SDICLK Serial Clock (output from master)
SDIMOSI Master Output, Slave Input (output from master)
SDIMISO Master Input, Slave Output (output from slave)
SDICS# Slave Select (active low; output from master, or said CS, Chip Select)
To support more SPI applications, the KBC introduces a SPI master interface, called SDI
(Serial Device Interface). With simple programming interface, the F/W can easily communicate with
SPI slave devices.
80
4.9.2 SDI Registers Description

SDI Control/Status Register
Offset
0x70
Name
SDICSR
Bit
Type
RO
Description
SDI Idle flag. If this bit set, the SDI is in an idle state.
Default
Bank
0x00
0xFE
0: busy
1: idle
6-4
RSV
3-2
R/W
Reserved
SDICCLK divider.
SDICLK frequency = peripheral clock / [( divider +1)*2]
R/W
SDIDO/SDIDI Timing.
0: SDIDO changes data at rising edge of SDICLK. (device
latches at falling edge of SDICLK)
SDIDI latch data at rising edge of SDICLK. (device changes
at falling edge of SDICLK).
1: SDIDO changes data at falling edge of SDICLK. (device
latches at rising edge of SDICLK)
SDIDI latch data at falling edge of SDICLK. (device
changes at rising edge of SDICLK).
R/W
SDICS# / SDI data port enable.

0: Disable
1: Enable
SDI Data Byte Output Port

Offset
0x71
Name
SDIBO
Bit
Type
Description
Default
Bank
7-0
R/W
While SDICSR[7]=0 (SDI not busy), writing to this register

forces data output to SDIDO in continuously serial 8 bits. MSB
first.
0x00
0xFE
Description
Default
Bank
0x00
0xFE
SDI Data Byte Input Port

Offset
Name
Bit
Type
0x72
SDIBI
7-0
RO
SDIDI reading port.
81
4.9.3 SDI Programming Sample

In this section gives some programming sample to control SDI module. Please note,
scenario of SDI filed application.
Example
A SPI device is attached. Here is a READ STATUS command.
Programming model
GPXAFS00[2:0] (0xFC0C[2:0]) = 111b;
//Select SDI function pins
GPXDIE00[0] (0xFC6C[0]) = 1b;
//Enable SDI data input
SDICSR (0xFE70) = 0x01;
//Set CE# low, SPI clock = Peripheral //clock/2
SDIBO (0xFE71) = 0x05;
//Transfer CMD(0x05) to device
Wait SDICSR[7]
//Wait bus idle
(0xFE70[7]) = 1b;
SDIBO (0xFE71) = 0x00;
//Transfer dummy byte to device and //device sends status byte to SDI
Wait SDICSR[7] (0xFE70[7]) = 1b;
//Wait bus idle
SDICSR (0xFE70) = 0x00;
//Set CE# high
Read SDIBI (0xFE72);
//Get device status
82
4.10 Watchdog Timer (WDT)

4.10.1 WDT Function Description
A Watchdog Timer (WDT) is a hardware timing device that triggers a system reset while
the system encounters any unrecoverable situation. The WDT utilizes 32.768KHz for operation.
The WDT triggers the system reset in two ways.
- Reset the 8051 microprocessor only.
- Reset the whole logic, except GPIO modules.
Here gives the highlight of WDT features:
- 20 bit Watchdog
- Watchdog password protection.
- Interrupt support.
- WDT LED blinking support.
- New 24 bit timer (TMR) support.
4.10.2 WDT Registers Description

WDT Configuration
Offset
Name
Bit
Type
0x80
WDTCFG
R/W
Description
WDT clock source selection
0: internal 32.768KHz
1: external 32.768KHz OSC.
6-3
R/W
WDT disable password

Writing 1001b to this field will force WDT disable
R/W
WDT test mode enable.

0: normal mode
1: test mode, clock driven by internal 32MHz. (WDTCFG[7]
ignore)
R/W
WDT interrupt enable.

0: Disable
1: Enable
R/W
WDT reset enable.

Once WDT resets, two WDT pending flags are clear.
0: Disable
1: Enable
83
Default
Bank
0x00
0xFE
WDT Pending Flag

Offset
Name
Bit
Type
0x81
WDTPF
7-5
RSV
R/W1C
Description
Reserved
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
WDT interrupt flag

Once the timer counts to half of WDT (0xFE82), an interrupt
occurs. If the timer counts to WDT(0xFE82), a WDT reset
occurs.
0: no event
1: event occurs
R/W1C
WDT reset flag

Once the timer counts to WDT (0xFE82), a WDT reset occurs
and this flag is set.
0: no event
1: event occurs
WDT High 8-bit Counter Value (for WDT reset system)

Offset
Name
Bit
Type
Description
0x82
WDT
7-0
R/W
The high 8-bits of WDT counter value.

The WDT timer unit is 128ms.
Please note, fill this value at least greater than or equal 3 (>=3)
for hardware limitation.
WDT Blinking LED Configuration

Offset
Name
Bit
Type
0x83
LEDCFG
7-3
RSV
2-0
R/W
Description
Reserved
LED Blinking configuration.
0: LED output keeps high
1: LED output keeps low 500ms for every 1 sec.
2: LED output keeps low 500ms for every 2 sec
84
WDT TMR (24-bit Timer) Configuration

Offset
Name
Bit
Type
0x84
TMR_CFG
R/W
Description
TMR enable
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
0: Disbale/reset TMR
1:Enable TMR
6:3
RSV
Reserved
RO
TMR interrupt pending flag overflow.

While TMR interrupt flag (TMR_CFG[1]) is set and an interrupt
event occurs again. This bit will be set and can be clear via
writing TMR_CFG[7] with 0.
0: no event
1: event occurs
R/W1C
TMR interrupt flag.

When TMR counter[23:16] is equal to TMR_MATCH register.
This bit will be set.
0: no event
1: event occurs
R/W
TMR counter start control.

0: stop counting
1: start counting
WDT TMR (24-bit Timer) Counter Match Value

Offset
Name
0x85
TMR_MATCH
Bit
Type
7-0
R/W
Description
WDT TMR (24-bit Timer) Counter Value 1

Offset
0x86
Name
TMR_V1
Bit
Type
7-0
RO
Description
Value for TMR counter[23:16]
WDT TMR (24-bit Timer) Counter Value 2

Offset
0x87
Name
TMR_V2
Bit
Type
7-0
RO
Description
Value for TMR counter[15:8]
85
4.10.3 WDT Programming Sample

In this section gives some programming sample to control WDT module. Please note,
scenario of WDT filed application.
Example
Set WDT=512ms to reset system, and an interrupt occurs while
WDT=256ms (half of WDT)
Programming model
WDT (0xFE82) = 0x04
; set WDT=512ms
WDTCFG (0xFE80) = 0x03 ; enable interrupt and WDT reset
86
4.11 Low Pin Count Interface (LPC)

4.11.1 LPC Function Description
The Low Pin Count (LPC) is an interface for modern ISA-free system. The KBC
connects to the system via LPC interface. The following LPC cycle types are supported.
Type
Address
Data
LPC I/O Read
16-bit
8-bit
LPC I/O Write
16-bit
8-bit
LPC Memory Read
32-bit
8-bit
LPC Memory Write
32-bit
8-bit
FWH Read
28-bit
8-bit
FWH Write
28-bit
8-bit
4.11.2 LPC I/O Decode Range

Item
Port
Comment
Keyboard Controller
60h/64h
Embedded Controller
62h/66h (default)
Legacy I/O
68h/6Ch, 2Eh/2Fh
EC Index-I/O
FF29h~FF2Bh/FF2Dh~FF2Fh(default)
2 Sets, Programmable.
Debug Port
80h
Only write cycle support interrupt
Programmable
4.11.3 LPC Memory Decode Range

Memory Address (hex)
Size
Setting
(LPCSCFG[3],LPCFWH[7:6])
000C_0000 ~ 000F_FFFF
256K (default)
0b,00b
512K
0b,01b
1M
0b,10b
2M
0b,11b
4M
1b,00b
FFFC_0000 ~ FFFF_FFFF
000C_0000 ~ 000F_FFFF
FFF8_0000 ~ FFFF_FFFF
000C_0000 ~ 000F_FFFF
FFF0_0000 ~ FFFF_FFFF
000C_0000 ~ 000F_FFFF
FFE0_0000 ~ FFFF_FFFF
000C_0000 ~ 000F_FFFF
FFC0_0000 ~ FFFF_FFFF
LPC module decodes low memory address only in 256K range.
87
4.11.4 FWH Memory Decode Range

Memory Address (hex)
Size
Setting
(LPCSCFG[3],LPCFWH[7:6])
00C_0000 ~ 00F_FFFF
256K (default)
0b,00b
512K
0b,01b
1M
0b,10b
2M
0b,11b
4M
1b,00b
FFC_0000 ~ FFF_FFFF
00C_0000 ~ 00F_FFFF
FF8_0000 ~ FFF_FFFF
00C_0000 ~ 00F_FFFF
FF0_0000 ~ FFF_FFFF
00C_0000 ~ 00F_FFFF
FE0_0000 ~ FFF_FFFF
00C_0000 ~ 00F_FFFF
FC0_0000 ~ FFF_FFFF
LPC module decodes low memory address only in 256K range.
4.11.5 Index-I/O Port

The KBC provides a method to communicate with the host via legacy I/O port. The host
can access the XRAM space inside the KBC. The I/O port is called Index-I/O. Two Index-I/Os are
supported and programmable. The registers, LPCIBAH and LPCIBAL (0xFE92 and 0xFE93), are
used to specify the desired I/O port base. To enable the 2nd Index-I/O, the LPCSCFG[5],
(0xFE90[5]) should be set. The index-I/O base address will be 8 bytes align if the LPCSCFG[5] set,
otherwise 4 bytes alignment . For example, while the base address is 0xFF2C and LPCSCFG[5]
set, the 1st index-I/O address will be 0xFF29 (io_base +1).
The following table collects the port definition for the host. The base address of
Index-I/O is assumed to be io_base.
1st Index-I/O
2nd Index-I/O (LPCSCFG[5]=1)
XRAM address (high)
io_base+1
XRAM address (high)
io_base+5
XRAM address (low)
io_base+2
XRAM address (low)
io_base+6
XRAM data (high)
io_base+3
XRAM data (high)
io_base+7
88
Here is an example how to use an Index-I/O.

EC F/W
1.
2.
EC F/W setups the base address, for instance,

0x380. That is, LPCIBAH=0x03 and
LPCIBAL=0x80.
If the 2nd Index-I/O is needed, turn on the enable
bit. That is, LPCSCFG[5]=1 (0xFE90[5]=1).
Host software
1.
Host setups the desired XRAM address:

Port 0x381 = high byte of XRAM address
Port 0x382 = low byte of XRAM address
2.
And then the host can access the content/data

via Port 0x383.
3.
If the 2
nd
Index-I/O required.
Port 0x385 = high byte of XRAM address

Port 0x386 = low byte of XRAM address
Port 0x387 = content/data of XRAM address
4.11.6 Extended I/O Port (Debug Port, Port80)

Developers may use legacy I/O port, 0x80 for debug. The KBC provides a debug
interface for this application, called extended I/O port (debug port). The port address can be
programmable in the KBC. The host software can use this interface not only for debug but also for
special communication with the EC F/W. This interface provides interrupt capability as well. That is,
while host accesses this I/O port, an interrupt to 8051 occurs. There is one thing should be
reminded. The interrupt feature is only for I/O-write to this port, not for I/O-read. Please note, the
interrupt capability is controlled in the register ECCFG[2] (0xFF04[2]).
89
4.11.7 LPC Registers Description

LPC SIRQ Configuration for Quiet Mode
Offset
0x90
Name
LPCSCFG
Bit
Type
7-6
RSV
Reserved
Description
R/W
Enable 2 index-I/O mode
R/W
Switch of CIR/User IRQ
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
nd
Switch between CIR and User defined SIRQ, and the SIRQ
channel is defined in LPCTCFG[3:0]
0: User defined SIRQ
1: CIR SIRQ
3
R/W
Memory size 4MB enable (LPC/FWH).

If this bit enable, please make sure LPCFWH[7:6]=00b
0: Disable
1: Enable
R/W
LPC I/O 2Eh/2Fh decode enable.

If enabled, 0xFE9A/0xFE9B are configured to take in charge of
LPC I/O 2Eh/2Fh.
0: Disable
1: Enable
R/W
LPC SIRQ mode selection.

0: Continuous mode
1: Quiet mode
WO
Force LPC SIRQ cycle start.

Writing 1 to this bit forces SIRQ signal low for a pulse.
LPC SIRQ Configuration

Offset
0x91
Name
LPCSIRQ
Bit
Type
R/W
Description
Ignore A22 of FWH cycle.
0: Disable
1: Enable
R/W
SCI SIRQ enable

0: Disable
1: Enable
R/W
IRQ12 SIRQ enable

0: Disable
1: Enable
R/W
IRQ1 SIRQ enable

0: Disable
1: Enable
3-0
R/W
SCI SIRQ channel.

0x00: no SIRQ
0x01: IRQ1
0x02: SMI#
0x03: IRQ3
0x04: IRQ4
.
0x0F: IRQ15
90
LPC Index-I/O Base Address (16-bit)

Offset
0x92
0x93
Name
LPCIBAH
LPCIBAL
Bit
Type
Default
Bank
7-0
R/W
High byte of LPC index-I/O address
Description
0xFF
0xFE
7-0
R/W
Low byte of LPC index-I/O address (8-byte alignment required)
0x2C
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x80
0xFE
LPC Firmware Hub Configuration

Offset
0x94
Name
LPCFWH
Bit
Type
7-6
R/W
Description
Memory size selection (LPC/FWH)
00b: 256KB
01b: 512KB
10b: 1MB
11b: 2MB
R/W
FWH memory cycle enable

0: Disable
1: Enable
R/W
FWH IDSEL check enable

0: Disable
1: Enable
3-0
R/W
FWH ID
LPC Configuration
Offset
Name
Bit
Type
0x95
LPCCFG
R/W
Description
LPC memory write protection (including FWH)
0: Disable
1: Enable
R/W
Index-I/O port enable

0: Disable
1: Enable
R/W
KBC 60h/64h I/O port enable

0: Disable
1: Enable
R/W
Debug port (port 80) enable

0: Disable
1: Enable
R/W
EC I/O port enable (default port 62h/66h)

0: Disable
1: Enable
R/W
LPC memory cycle enable (not including FWH)

0: Disable
1: Enable
R/W
SIRQ always in continuous mode enable

0: Disable
1: Enable
R/W
LPC CLKRUN# enable

0: Disable
1: Enable
91
LPC Extended (Debug) I/O Base Address (16-bit)

Offset
Name
Bit
Type
0x96
LPCXBAH
7-0
R/W
0x97
LPCXBAL
7-0
R/W
Description
Default
Bank
High byte of Extended I/O (debug port)
0x00
0xFE
Low byte of Extended I/O (debug port)
0x80
0xFE
Default
Bank
LPC EC I/O Base Address (16-bit)

Offset
Name
Bit
Type
Description
0x98
LPCEBAH
7-0
R/W
High byte of EC I/O
0x00
0xFE
0x99
LPCEBAL
7-0
R/W
Low byte of EC I/O
0x62
0xFE
Default
Bank
0x00
0xFE
LPC I/O 0x2E/0x2F Configuration and Status (LPCSCFG[2]=1)

Offset
Name
Bit
Type
Description
0x9A
LPC2ECFG
7-4
RSV
Reserved
RO
The previous access type of 2Eh/2Fh

0: Read
1: Write
R/W1C
Interrupt flag of accessing 2Fh I/O.

0: no event
1: event occurs
R/W
2Fh I/O interrupt enable

If this bit set, while host accesses 2Fh I/O, an interrupt will
issue.
0: Disable
1: Enable
R/W
Decode 2Eh/2Fh I/O enable.

0: Disable
1: Enable
92
LPC User Defined SIRQ Configuration (LPCSCFG[2]=0)

Offset
Name
Bit
Type
Description
0x9B
LPCTCFG
7-6
RSV
Reserved
R/W
User defined SIRQ Setting.
Default
Bank
0x00
0xFE
0: Low
1: High
4
R/W
User defined SIRQ channel enable

0: Disable
1: Enable
3-0
R/W
User defined SIRQ channel number

0x00: no SIRQ
0x01: IRQ1
0x02: SMI#
0x03: IRQ3
0x04: IRQ4
.
0x0F: IRQ15
LPC I/O 0x2E Read Port Register (LPCSCFG[2]=1)

Offset
Name
Bit
Type
Description
Default
Bank
0x9B
LPCTCFG
7-0
RO
Host writes data to I/O port 0x2E, EC F/W could read data from
this register.
0x00
0xFE
LPC Read/Write Data of I/O 0x2F (LPCSCFG[2]=1)

Offset
Name
Bit
Type
Description
Default
Bank
0x9C
LPC2FDAT
7-0
Host writes data to I/O port 0x2F, EC F/W could read data from
this register.
0x00
0xFE
7-0
If host issue any read access to I/O port 0x2F, the host will get
the data which kept in this register
0x9C
LPC I/O 0x68/0x6C Configuration

Offset
Name
Bit
Type
Description
0x9D
LPC68CFG
R/W
LPC decode I/O port 68h/6Ch enable

0: Disable
1: Enable
6-2
RSV
Reserved
R/W
IBF interrupt enable

Interrupt issues while IBF rising (LPC write I/O 68h/6Ch)
0: Disable
1: Enable
R/W
OBF interrupt enable

Interrupt issues while OBF falling (LPC read I/O 68h)
0: Disable
1: Enable
93
Default
Bank
0x00
0xFE
LPC I/O 0x68/0x6C Configuration and Status Register

Offset
Name
Bit
Type
0x9E
LPC68CSR
R/W1C
Description
I/O 68h/6Ch busy flag.
Default
Bank
0x00
0xFE
EC F/W can write 1 to clear this flag.

A write cycle to port 6Ch with data 0xFF also clear this flag
0: not busy
1: busy
6
RO
Indicator of write port.

0: write 68h occurs
1: write 6Ch occurs.
5-4
RSV
R/W1C
Reserved
IBF interrupt flag
Interrupt flag while IBF rising (LPC write I/O 68h/6Ch)
0: no event
1: event occurs
R/W1C
OBF interrupt flag

Interrupt flag while OBF falling (LPC read I/O 68h)
0: no event
1: event occurs
R/W1C
IBF of port 68h/6Ch
R/W1C
OBF of port 68h/6Ch
LPC I/O 0x68/0x6C Data Register

Offset
Name
Bit
Type
Description
Default
Bank
0x9F
LPC68DAT
7-0
Host writes data to I/O port 68h/6Ch, EC F/W could read data
from this register.
0x00
0xFE
7-0
If host issue any read access to I/O port 68h/6Ch, the host will
get the data which kept in this register
0x9F
94
4.12 X-Bus Interface (XBI)

4.12.1 XBI Function Description
The KBC implements a XBI module to handle the related request from 8051/LPC to
flash device. The following figure gives the illustration.
The XBI module also takes the responsibility for the In-System-Programming (ISP)
mechanism to update system BIOS. The detail steps to update system BIOS via ISP mode, please
refer to the section of ISP. Here gives the feature of XBI module.
- Two 8051 code segments, one for 16K and the other for 48K.
- XBI arbiter to handle the transaction of 8051 and LPC request.
- XBI pre-fetch code mechanism support for better performance.
- Flash write-protection support.
- ISP flash update support.
4.12.2 XBI SPI Enhancement

The 8051 microprocessor executes machine codes from SPI flash and the performance
is determined by the read operation. To enhance the performance of SPI flash fetching, 3 special
read protocols are introduced. They are Offset_Read, Short_Read and Dual_Input protocols. The
following sections give a brief introduction.
95
4.12.2.1 Original Read Protocol

An original SPI read protocol to read flash is as the following figure. A chip select
is asserted to the specific flash device and the SPI flash controller drives clock out. A 24-bit address
phase follows 8-bit command phase. After a dummy phase, the SPI flash device returns data.
Please note, the KBC currently supports 2MB (20bit) size SPI flash, therefore, address bit,
A23~A21 are all zero.
96
4.12.2.2 Short Read Protocol

The 8051 microprocessor supports 16-bit address (64KB) internally. If the code
fetching is within 64KB or 128KB, a Short_Read command will enhance the performance by
reducing address phase to be 16-bit. The protocol is transparent to EC F/W. The F/W just takes
care of the segment switch by XBISEG0 and XBISEG1 (0xFEA0 and 0xFEA1). The high nibble
of command Short_Read is programmable. Two command bytes are defined, 0x30 and 0x31,
by default, that is, the high nibble is 0x3. The command 0x30 is used while the 1st 64KB code
segment is selected and 0x31 is for the 2nd 64KB code segment. Please note, the Short_Read
command is not a generic SPI flash command and SPI flash device should support it as well.
Command byte=0x30, A23~A17=0 and A16=0. (1st 64KB code segment selected)
Command byte=0x31, A23~A17=0 and A16=1. (2nd 64KB code segment selected)
97
4.12.2.3 Offset Read Protocol

To shorten the address phase and to improve the SPI flash performance, another
new protocol is introduced. If branch instruction used often, an Offset_Read protocol will improve
the performance while fetching code. Once the protocol is used, the address phase will be 8-bit
long. If the branch is over 128-byte long, the Offset_Read will not be utilized. Just like Short_Read
command, the Offset_Read is also transparent to EC F/W. By default, the command byte is 0x32
and the high nibble of this command is programmable. Please note, the Offset_Read command is
not a generic SPI flash command and SPI flash device should support it as well.
98
4.12.2.4 Dual Input Protocol

Besides the two new protocols mentioned before, an improvement of data phase
to increase performance is introduced. The method is called Dual Input mode. In this mode, data
output pin works as another input. The bit stream is shown as the following figure. Please note, the
high nibble of this protocol is fixed to be 0x3. This is not a standard protocol and SPI flash devices
should implement this feature to make it work.
99
4.12.3 XBI Registers Description

8051 Address Segment 0 Mapping Configuration (0x0000~0x3FFF)
Offset
0xA0
Name
XBISEG0
Bit
Type
R/W
Description
8051 code segment SEG0 remapping enable.
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
0: Disable
1: Enable
6
RSV
5-0
R/W
Reserved
SEG0 XBI Address
SEG0 XBI Address = XBISEG0[5:0]*16K + 8051 Address[13:0]
8051 Address Segment 1 Mapping Configuration (0x4000~0xFFFF)

Offset
Name
Bit
Type
0xA1
XBISEG1
R/W
Description
8051 code segment SEG1 remapping enable.
0: Disable
1: Enable
6-4
RSV
3-0
R/W
Reserved
SEG1 XBI Address
SEG1 XBI Address = XBISEG1[3:0]*64K + 8051 Address[15:0]
Reserved
Offset
Name
Bit
Type
0xA2
RSV
7-0
RSV
Description
Reserved
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
LPC Read Buffer Configuration

Offset
Name
Bit
Type
0xA3
XBI_LPBCFG
R/W
Description
LPC buffer read enable
0: disable (default)
1: enable
R/W
LPC buffer auto pre-fetch next 16-byte

0: disable (default)
1: enable
5-0
RSV
Reserved
Bit
Type
7-0
RSV
Bit
Type
RSV
Reserved
R/W
8051 instruction fetch (sustaining access)
XBI XIO Enable

Offset
0xA4
Name
RSV
Description
Reserved
XBI Configuration
Offset
0xA5
Name
XBICFG
Description
0: Disable
1: Enable
5-0
RSV
Reserved
100
101
XBI E51CS# Configuration

Offset
Name
Bit
Type
Description
0xA6
XBICS
7-6
RSV
Reserved
R/W
XBI arbitration priority.
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0: Disable
1: Enable
4
R/W
Reset code segment enable.

Once the 8051 reset, the code segment SEG0 or SEG1 can be
reset if the corresponding code segment enabled.
(XBISEG0[7]/XBISEG1[7])
0: Disable
1: Enable
R/W
2K-XRAM as code memory enable.

To enhance the code fetching, users can use 2K-XRAM as
code memory. Please note, users should move codes from
flash to XRAM, jump to XRAM and then enable this bit.
0: Disable
1: Enable
R/W
Reset XBI arbiter while in idle/stop mode.

0: Disable
1: Enable
R/W
EHB fast accessing enable.

Enable this bit gets better performance in EHB.
0: Disable
1: Enable
RSV
Bit
Type
7-0
R/W
Reserved
XBI Write Enable

Offset
0xA7
Name
XBIWE
Description
XBI write command.
00h: exit SRAM test mode
C5h: enter SRAM test mode
XBI SPI Flash Address (22-bit) = [SPIA2(6bit) : SPIA1(8bit) : SPIA0(8bit)]

Offset
Name
Bit
Type
Description
0xA8
SPIA0
7-0
R/W
SPI Address lowest 8-bits (A7:A0)
0x00
0xFE
0xA9
SPIA1
7-0
R/W
SPI Address middle 8-bits (A15:A8)
0x00
0xFE
0xAA
SPIA2
5-0
R/W
SPI Address upper 6-bits (A21:A16)
0x00
0xFE
Default
Bank
0x00
0xFE
XBI SPI Flash Output/Input Data Port

Offset
Name
Bit
Type
0xAB
SPIDAT
7-0
R/W
Description
Input (read) / Output (write) data port of SPI flash interface.
102
XBI SPI Flash Command Port

Offset
Name
Bit
Type
Description
Default
Bank
0xAC
SPICMD
7-0
R/W
Commands support for SPI flash. Writing this register will force
the SPI protocol start. Please note, the address phases must
be prior to command phase.
0x00
0xFE
SPI command support:

01h: Write Status Register
02h: Byte Program
03h: Read
04h: Write Disable
05h: Read Status Register
06h: Write Enable
0Bh: High Speed Read
20h: Sector Erase (SST)
3Bh: Fast Read Dual Output (Windbond, AMIC)
50h: Enable Write Status Register (SST)
52h: Block Erase (SST)
60h: Chip Erase (SST)
B9h: Power Down
C7h: Chip Erase (PMC, NexFlash)
D7h: Sector Erase (PMC)
D8h: Block Erase (PMC, NexFlash)
103
XBI SPI Flash Configuration/Status Register

Offset
Name
Bit
Type
0xAD
SPICFG
R/W
Description
Fast read dual output mode enable.
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x03
0xFE
Please note, if this bit set, the SPICFG[2] will be ignored.

0: Disable
1: Enable
6
R/W
SPI flash offset read command enable. (32h)

0: Disable
1: Enable
R/W
SPI flash short read command enable. (31h, 30h)

0: Disable
1: Enable
R/W
SPICS# force low

0: SPICS# high
1: SPICS# low
R/W
Write enable of SPICMD register,0xFEAC.

0: Disable
1: Enable
R/W
Dummy byte of read command.

0: Disable
1: Enable
RO
SPI busy flag.

0: not busy
1: busy
R/W
Automatic SPI status check after a SPICMD issued, until SPI

busy flag, clear, i.e., (SPICFG[1]=0).
0: Disable
1: Enable
XBI SPI Flash Output Data Read Back Port

Offset
0xAE
Name
SPIDATR
Bit
Type
7-0
R/W
Description
Reflection of SPIDAT ,0xFEAB register.
XBI SPI Flash Configuration 2

Offset
0xAF
Name
SPICFG2
Bit
Type
7-4
RSV
Reserved
3-0
R/W
High nibble of Offset Command / Short Read Command
Description
104
4.13 Consumer IR Controller (CIR)

4.13.1 CIR Function Description
The KBC embeds with a native hardware Consumer IR controller, which connects to
system via LPC interface. Popular protocols are supported, such as RC-5/RC-6/NEC/RLC. The CIR
controller handles the protocol of RC-5/RC-6/NEC/RLC for receiving, and only RLC for transmit.
IRQ and I/O port are implemented. An extended function is implemented to support learning
application. The basic features are list as the following table.
RX carrier demodulation
TX carrier modulation
RX protocol support
TX protocol support
RX carrier frequency measurement
925B/926B
V
X
RC5/RC6/NEC/RLC
RLC
X
926D
V
V
RC5/RC6/NEC/RLC
RLC
V
A SIRQ channel can be assigned for CIR application. The related programming registers
are summarized as following table.
Register
LPCSCFG[4] (0xFE90[4])
Description
SIRQ selection for LPCTCFG[3:0] (0xFE9B[3:0])
0: User defined IRQ
1: CIR IRQ enable
LPCTCFG[3:0] (0xFE9B[3:0])
SIRQ channel number.

0x00: IRQ0
0x01: IRQ1
0x0F: IRQ15
Here is the features highlight.

-
Native hardware protocol decoder, such as RC5/RC6/NEC and RLC.
I/O and IRQ resource for CIR controller.
Support 2 sets of RX/TX in one chip, and RX/TX works simultaneously.
RX carrier demodulation/ TX carrier modulation support.
Wide range of carrier frequency support, 15K~1MHz. (The carrier frequency is 30K~60KHz in
normal application)
More flexible in carrier sample frequency, 1s.~128s (The sample frequencies are 25, 50
and 100s for normal application).
Remote controller learning support.
105
The following figure shows an example how a CIR controller works with narrow band receiver.
Here gives the guidance for programming CIR.

For Receive
For Transmit
1.
Select protocol via setting CIRCFG2, i.e.,

0xFEC1
1.
Select RLC protocol and enable via setting

CIRCFG, .i.e., 0xFEC0.
2.
According to the selected protocol, setup

CIRHIGH/CIRBIT/CIRSTART/CIRSTART2, i.e.,
0xFEC3~0xFEC6
2.
Writing to CIRRLC_OUT0, 0xFEC9, will start to

transmit.
3.
3.
Enable protocol and other configuration setting

via CIRCFG, .i.e., 0xFEC0
4.
EC F/W waits for data-in by pooling or interrupt.
If CIRRLC_OUT0 (0xFEC9) and CIRRLC_OUT1

(0xFECA) are written at the same time, it start to
transmit CIRRLC_OUT0 and then
CIRRLC_OUT1.
4.
If only CIRRLC_OUT0 (0xFEC9) is written, the

hardware will transmit CIRRLC_OUT0 first and
then CIRRLC_OUT1.
5.
Each byte transmit completion, an interrupt will

fire.
106
4.13.2 CIR Block Diagram

The CIR controller supports two RX ports (GPIO40/GPIO0A) and two TX ports
(GPIO41/GPIO0D). A register bit, CIRCFG2[5] (0xFEC1[5]), is used to determine RX source. For
example, if CIRCFG2[5]=0, GPIO40 is the RX source, otherwise GPIO0A. The TX port is selected
according to the GPIO function selection register. The following table gives an example of RX/TX
combination.
GPIOFS08[5]=0b, GPIOFS[1]=1b
GPIOFS08[5]=1b, GPIOFS[1]=0b
CIRCFG2[5]=0b
(RX,TX)=(GPIO40,GPIO41 )
(RX,TX)=(GPIO40,GPIO0D )
CIRCFG2[5]=1b
(RX,TX)=(GPIO0A, GPIO41)
(RX,TX)=(GPIO0A, GPIO0D )
The CIR controller could detect the carrier frequency and demodulate the carrier. This
provides a learning feature for CIR application. The frequency detection range is from 15.75KHz to
1MHz. After demodulation, the CIR controller handles remote signals with hardware decoder which
supports RC5/RC6/NEC/RLC protocols. If transmit function needed, the CIR controller could
modulate the carrier and send it out via GPIO41/GPIO0D. The output carrier frequency range is the
same as input, that is, 15.75KHz~1MHz. The RX and TX can work simultaneously in the current
design. The following diagram gives more detail about CIR controller.
107
4.13.3 CIR Remote Protocol

In this section, brief introduction of protocols supported in the CIR is given. Four
protocols are supported, Philips RC5/RC6, NEC and Run-Length-Code. Only features and protocol
definition listed. For more detail please refer to the related specifications.
4.13.3.1 Philips RC5 Protocol

Here highlights the features of Philips RC5 protocol.
- Manufacturer Philips.
- Carrier frequency 36KHz.

- Bi-phase coding.
- 5 bits address / 6 bits command lengths
RC5 Protocol
Bit1
Bit2
Bit3
S1
S2
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Address
Bit12
Command
S1/S2: start bits, always 1

T: toggle bit, This bit is inverted every time a key is released and pressed again.
Address: IR device address, MSB first.
Command: IR command, MSB first.
Bit11
108
Bit13
Bit14
4.13.3.2 Philips RC6 Protocol

Here highlights the features of Philips RC6 protocol.
- Manufacturer Philips.

- Bi-phase coding.
- 5 bits address
- Variable command lengths based on the operation mode.
RC6 Protocol
LS
SB
MB2
MB1
MB0
A
7
A
6
A
5
Header
A
4
A
3
A
2
A
1
Control
Header Phase (ENE CIR)
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
Information
SF
Data Phase (ENE CIR)
LS: Leader symbol

SB: Start bit, always 1
MB2-MB0: Mode bits, operation mode selection.
T: Trailer bit, this bit can be served as a toggle bit.
A7-A0: Address
C7-C0: Command
SF: Signal free time, 2.666ms.
4.13.3.3 NEC Protocol

Here highlights the features of NEC protocol.
- Manufacturer NEC.

- Pulse distance modulation.
- 8 bit address / 8 bit command length
- Address/Command transmitted twice.
- Total transmit time is constant.
NCE Protocol
AGC burst
space
Address
Address
Command
Command
9ms
4.5ms
8bit
8bit
8bit
8bit
AGC burst: set gain of IR remote controller, 9ms long

Space:
follow by AGC burst, 4.5ms.
Address: 8-bit address, LSB first.

~Address: inverted 8-bit address, LSB first.
Command: 8-bit command, LSB first.
~Command: inverted 8-bit command, LSB first
109
4.13.4 CIR Automatic Carrier Frequency Detection and Modulation

To support learning feature, wide-band transmitter and receiver will be used in a system.
The KBC introduces a new mechanism to provide carrier frequency information of wide-band
receiver to the host.
The CIR controller needs to be programmed with two parameters for the detection.
Register, CIRCAR_PULS is used to determine these two parameters. CIRCAR_PULS[7:4] keeps
the discard number of carrier pulse and CIRCAR_PULS[3:0] keeps the average number to detect.
The CIRCAR_PULS[7:4] tells the controller to discard the specific number of carrier pulse from the
beginning. The controller then gets the average number of carriers pulse as sample data and
analyzes. The detection of carrier period is kept in CIRCAR_PRD[6:0], and the valid flag is kept in
CIRCAR_PRD[7]. Please note, the detection range is from 15.75KHz~1MHz. (The general
application is from 30K~60KHz).
Here gives an example as the above waveform. Bit stream with 38KHz carrier is shown as bit-0.
Each bit is 0.56ms in length and 38KHz carrier period is 26.3s, that is, there will be about 21
carrier pulses in a bit. If CIRCAR_PULS[7:4]=5 and CIRCAR_PULS[3:0]=10, once the detection
enabled, the CIR controller will get 6th carrier pulse as the first one and analyze the sequential 10
pluses. The detection result can be obtained via register CIRCAR_PRD.
110
The related registers for automatic carrier frequency detection are listed as following.
Register
Address
CIRCFG2[5:4]
0xFEC1[5:4]
Description
Bit5=1, select wide-band as bit-decoder input.
Bit4=1, enable wide-band frequency detection
CIRCAR_PULS
0xFECB
CIRCAR_PULS[7:4] = discard number of carrier pulse

CIRCAR_PULS[3:0] = average number of carrier pulse
CIRCAR_PRD
0xFECC
Detection of wide-band carrier period
CIRCAR_HPRD
0xFECD
Detection of wide-band carrier period, pulse width high.
The KBC provides the modulation ability for RLC transmit. The carrier frequency of
modulation can be programmable. Before the carrier modulation, the programmer should notice the
modulation polarity. That is, if the data bus (TX) is kept low in idle state, only data in high state will
be modulated and the bit, CIRMOD_PRD[7], should be 1.
The related registers for RLC modulation is summarized as below.
Register
Address
Description
CIRCFG[7]
0xFEC0
RLC output modulation enable.
CIRMOD_PRD
0xFECE
CIRMOD_PRD[7] = modulation polarity selection

CIRMOD_PRD[6:0] = modulation carrier period
CIRMOD_HPRD
0xFECF
CIRMOD_HPRD[6:0] = modulation carrier period, pulse

width high.
111
4.13.5 CIR Registers Description

CIR Configuration
Offset
0xC0
Name
CIRCFG
Bit
Type
Description
R/W
Output carrier modulator for RLC (TX)

0: Disable
1: Enable
R/W
Output polarity reversed for RLC. (TX)

0: Disable
1: Enable
R/W
Interrupt while transmit completes with RLC protocol. (TX)

0: Disable
1: Enable
R/W
Output enable for RLC protocol. (TX)

Once the data filled into CIRRLC_OUT1 (0xFECA), the
controller starts the transmit with RLC protocol
0: Disable
1: Enable
R/W
Input carrier demodulator. (RX)

0: Disable
1: Enable
R/W
Input polarity reversed. (RX)

0: Disable
1: Enable
R/W
Interrupt enable. (RX)

Two conditions issue interrupt.
a.
After decode a byte in RX
b.
Once receive the Repeat in NEC protocol
0: Disable
1: Enable
0
R/W
Protocol decode enable. (RX)

0: Disable
1: Enable, protocol is determined by CIRCFG2[3:0], 0xFEC1.
112
Default
Bank
0x00
0xFE
CIR Configuration 2
Offset
Name
Bit
Type
Description
Default
Bank
0xC1
CIRCFG2
R/W
Fast sample (data phase, not leader phase) enable for input
signal. If this bit set, the sample period changes.
0x00
0xFE
For RC5/RC6, period changes from 30s to 16s

For NEC, period changes from 64s to 30s
0: Disable
1: Enable
6
R/W
Fast sample (leader phase) enable for input signal.

If this bit set, the sample period changes.
For RC6, period changes from 64s to 30s
0: Disable
1: Enable
R/W
Input selection for protocol decoder (bit-decoder)

0: from GPIO40
1: from GPIO0A
R/W
Frequency detection enable.

0: Disable
1: Enable
3-0
R/W
CIR Protocol selection. (valid while CIRCFG[0]=1)

0: RLC
1: RC5
2: RC6
3: NEC
others: reserved.
113
CIR Pending Flag and Status

Offset
Name
Bit
Type
0xC2
CIRPF
RO
Description
Hardware RX idle state.
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
0: not idle state

1: idle state
6
R/W
Hardware TX (RLC) idle state.

0: not idle state
1: idle state
5-4
RSV
R/W1C
Reserved
Pending flag of RLC transmit complete
0: no event
1: event occurs
R/W1C
Pending flag of RLC receive counter overflow

0: no event
1: event occurs
R/W1C
Pending flag of NEC repeat protocol

0: no event
1: event occurs
R/W1C
Pending flag of data-in

This bit is set while data received and stored in CIRDAT_IN.
0: no event
1: event occurs
Value for High Pulse Width

Offset
Name
Bit
Type
0xC3
CIRHIGH
5-0
R/W
Description
This register determines the high pulse width of a logic bit.
High pulse width = Decoder sample period * CIRHIGH
Value for Bit Width(RC5/RC6) / Logic Bit-One (NEC)

Offset
0xC4
Name
CIRBIT
Bit
Type
Description
Default
Bank
6-0
R/W
This register determines the bit width of a logic bit. (RC5/RC6)
0x00
0xFE
Default
Bank
0x00
0xFE
Bit width = Decoder sample period * CIRBIT

This register determines the logic bit-one. (NEC)
Logic bit-one = Decoder sample period * CIRBIT
Value for Leader Pulse Width (RC6/NEC) for Normal Packet

Offset
Name
Bit
Type
0xC5
CIRSTART
6-0
R/W
Description
This register determines the leader pulse width for normal
packet (RC6/ENC)
Leader pulse width = Decoder sample period * CIRSTART
114
Value for Tailer Bit Width (RC6) / Leader Width of Repeat Packet (NEC)
Offset
Name
Bit
Type
0xC6
CIRSTART2
6-0
R/W
Description
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x44
0xFE
This register determines the bit width of trailer (RC6)

trailer bit width = Decoder sample period * CIRSTART2
This register determines the leader width of repeat packet
(NEC)
Leader width(repeat) = Decoder sample period * CIRSTART2
CIR Decode Data Byte

Offset
Name
Bit
Type
0xC7
CIRDAT_IN
7-0
RO
Description
Received data to decode.
CIR Counter Value for RLC Sample Period

Offset
Name
Bit
Type
0xC8
CIRRLC_CFG
R/W
Description
Counter overflow control bit.
0: if overflow, the counter will stop.
1: if overflow, an interrupt issues and the counter keeps
counting.
6-0
R/W
CIR RLC sample period, The unit is 1s.

Please note CIRRLC_CFG[6:0] can not be zero.
CIR RLC Output 1st Byte

Offset
Name
0xC9
CIRRLC_OUT0
Bit
Type
Description
7-0
R/W
Output (TX) 1 byte for RLC protocol.
st
CIR RLC Output 2nd Byte

Offset
Name
0xCA
CIRRLC_OUT1
Bit
Type
Description
7-0
R/W
Output (TX) 2 byte for RLC protocol.
nd
CIR Carrier Discard/Average Pulse Number Setting for Automatic Carrier Detection.
Offset
Name
0xCB
CIRCAR_PULS
Bit
Type
7-4
R/W
Description
Discard carrier pulse number
F/W should specify the number of pulse to discard
3-0
R/W
Average carrier pulse number

F/W should specify the average number to calculate the carrier
period.
115
CIR Detected Carrier Period

Offset
Name
Bit
Type
0xCC
CIRCAR_PRD
RO
Description
Detected carrier period valid.
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
0: carrier detection not completed.

1: carrier detection completed.
6-0
RO
Detected carrier period.

Detected carrier period = CIRCAR_PRD[6:0] x 500ns
CIR Detected Pulse Width High of Carrier

Offset
Name
Bit
Type
0xCD
CIRCAR_HPRD
Description
RSV
Reserved
6-0
R/W
Detected pulse width high of carrier

Pulse width high = CIRCAR_HPRD[6:0] x 500ns
CIR Modulation Carrier Period (RLC only)

Offset
Name
Bit
Type
0xCE
CIRMOD_PRD
R/W
Description
Carrier modulation selection.
0: If TX idle state is high, Low signal in TX will be modulated.
1: If TX idle state is low, High signal in TX will be modulated
6-0
R/W
Modulation carrier period.

This register determines the modulation carrier period. The unit
is 500ns. The value can be chosen from 0x02 to 0x7F, i.e., the
period is from 15.87KHz~1MHz.
The period = CIRMOD_PRD[6:0] x 500 ns.
CIR Pulse Width High of Modulation Carrier (RLC only)

Offset
Name
Bit
Type
Description
0xCF
CIRMOD_HPRD
R/W
Reserved
6-0
R/W
Pulse width high of modulation carrier.

This register determines the pulse width high of modulation
carrier. The unit is 500ns. The value can be chosen from 0x01
to 0x7E. Please note, the pulse width high can not be larger
than the carrier period.
The pulse width high = CIRMOD_HPRD[6:0] x 500 ns.
116
4.13.3 CIR Programming Sample

In this section gives some programming sample to control CIR module. Please note,
scenario of CIR filed application.
Example
A RC6 receiver which filters out carrier is connected to CIR RX pin.
Programming model
GPIOIE40[0] (0xFC68[0])
= 1;
//Enable CIR Rx input
CIRCFG (0xFEC0) = 0x07;
//Enable Rx interrupt and protocol
CIRCFG2 (0xFEC1) = 0x02;
//Select RC-6 protocol
CIRHIGH (0xFEC3) = 0x0B;
//High width = 32*11 = 352 us
CIRBIT
//Bit width = 32*34 = 1088 us
CIRSTART
(0xFEC4) = 0x22;
(0xFEC5) = 0x3B;
CIRSTART2 (0xFEC6) = 0x4A;

When CIRPF[0] (0xFEC2[0])
//Leader width = 64*59 = 3776 us

//Trailer width = 32*74 = 2368 us
= 1, Read CIRDAT_IN (0xFEC7) to get data.
117
4.14 PS/2 Interface (PS/2)

4.14.1 PS/2 Interface Function Description
The PS/2 protocol is a two-wire bi-direction interface in the industrial standard. This
supports many PS/2 human interface devices, such as keyboard, mouse or touchpad device. Here
gives the highlights of PS/2 features in the KBC.
- 3 external PS/2 channels supported.
- 1 internal PS/2 channel for IKB.
- Each PS/2 channel is with interrupt capability.
- Each PS/2 channel can be enabled/disabled individually.
- Both hardware and flexible firmware mode support for PS/2 protocol.
- Each PS/2 channel can be programmed to be GPIO function.
4.14.2 PS/2 Interface Registers Description

PS/2 Configuration
Offset
0xE0
Name
PS2CFG
Bit
Type
R/W
Description
PS/2 port3 (TX/RX) enable. If disable, PS3CLK will be low.
0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W
PS/2 port0 IKB(TX/RX) enable. If disable, IKB clock will be low.

0: Disable
1: Enable
R/W
PS/2 parity error interrupt

0: Disable
1: Enable
R/W
PS/2 TX timeout interrupt.

TX timeout condition:
(a)ps2clk keeps high over 210s~240s during TX.
(b)Host requests bus and waits over 120ms~150ms
0: Disable
1: Enable
R/W
PS/2 transmit-one-byte interrupt.

0: Disable
1: Enable
R/W
PS/2 receive-one-byte interrupt.

0: Disable
1: Enable
118
Default
Bank
0x00
0xFE
PS/2 Interrupt Pending Flag

Offset
Name
Bit
Type
0xE1
PS2PF
RO
Description
Flag of PS/2 port3 received one byte.
0: no event
1: event occurs
RO

0: no event
1: event occurs
RO

0: no event
1: event occurs
RO
Flag of PS/2 port0 (IKB) received one byte.

0: no event
1: event occurs
R/W1C
Interrupt flag of PS/2 parity error

0: no event
1: event occurs
R/W1C
Interrupt flag of PS/2 TX timeout.

0: no event
1: event occurs
R/W1C
Interrupt flag of PS/2 transmit-one-byte

0: no event
1: event occurs
R/W1C
Interrupt flag of PS/2 receive-one-byte

0: no event
1: event occurs
119
Default
Bank
0x00
0xFE
PS/2 Transmitter/Receiver Control

Offset
Name
Bit
Type
0xE2
PS2CTRL
R/W
Description
Data port
PS2DATA (0xFEE3) connects to PS/2 port3
Default
Bank
0x00
0xFE
Default
Bank
0x00
0xFE
0: Disconnect
1: Connect
6
R/W
Data port
0: Disconnect
1: Connect
5
R/W
Data port
0: Disconnect
1: Connect
4
R/W
Data port
0: Disconnect
1: Connect
3
WO
Write 1 to force PS/2 TX reset.
WO
Write 1 to force PS/2 RX reset.
RO
PS/2 RX timeout flag.

The flag may implies the followings.
RSV
(a)
ps2clk keeps high over 210s~240s during RX
(b)
host issues reset command and the device does not

response.
(c)
General PS/2 packet timeout defined in the protocol.
Reserved
PS/2 Data Port

Offset
Name
Bit
Type
0xE3
PS2DATA
7-0
R/W
Description
EC F/W gets/writes data from/to host via this register.
120
PS/2 Configuration 2
Offset
Name
Bit
Type
0xE4
PS2CFG2
R/W
Description
PS/2 port3 hardware mode enable.
Default
Bank
0x00
0xFE
0: Disable
1: Enable
6
R/W

0: Disable
1: Enable
R/W

0: Disable
1: Enable
R/W
PS/2 port0 (IKB) hardware mode enable.

0: Disable
1: Enable
R/W
PS/2 hardware mode enable.

0: Disable
1: Enable
R/W
PS/2 host request timeout control. (in PS/2 hardware mode

only)
0: Host request timeout 120ms~150ms
1: Host request timeout 15ms~16ms
RSV
Reserved.
R/W
PS/2 clock/data input debounce control

0: 1s
1: 2s
PS/2 Pin Input Status

Offset
Name
Bit
Type
0xE5
PS2PINS
RO
PS/2 port3 clock pin status
RO
RO
RO
PS/2 port0 (IKB) clock pin status
RO
PS/2 port3 data pin status
RO
RO
RO
PS/2 port0 (IKB) data pin status
Description
121
Default
Bank
0x00
0xFE
PS/2 Pin Output

Offset
Name
Bit
Type
0xE6
PS2PINO
RO
RO
RO
RO
PS/2 port0 (IKB) clock pin status
RO
RO
RO
RO
Reserved
Description
122
Default
Bank
0x00
0xFE
4.15 Embedded Controller (EC)

4.15.1 EC Function Description
The ACPI specification defined for the embedded controller (EC) interface requires
either three separate host interfaces (KBC, SCI, SMI) or two interfaces (KBC, and shared SCI/SMI).
The ENE KBC supports KBC and SCI interface, and SMI interface can be shared with SCI or use a
dedicated GPIO. The embedded controller also provides some features which are collected as
following:
- Handles EC standard commands from host, firmware mode support.
- Handles EC extended commands from host, only firmware mode support.
- SCI generation capability.
- Extended I/O write interface, i.e., debug port (port 80) support.
- KBC/EC clock configuration.
- A/D and D/A control.
- Power management control.
- Miscellaneous control.
The host queries (read) EC status and issues (write) EC command via port 66h. The EC data
port is 62h. The status of EC is defined as the below table:
Status Bit
Name
Description
RSV
Reserved
RSV
Reserved
SCI
SCI event flag. Please note, this bit will not be set if standard EC commands
(80h~84h) issued by host.
0: No SCI event occurs
1: SCI event occurs
Burst Enable
The burst enable flag

0: Disable
1: Enable
Command/Data Flag
0: Previous access port is data port. (EC_DAT)

1: Previous access port is command/status port. (EC_CMD/EC_STS)
RSV
Reserved
IBF
Input Buffer Full flag of EC
OBF
Output Buffer Full flag of EC
The EC commands are defined as following, for more detail please refer to ACPI, Advanced
Configuration Power Interface Specification. 2.0
Value
Command
Description
80h
EC Read
Read EC space registers
81h
EC Write
Write EC space registers
82h
EC Burst Enable
Enable EC operation in burst mode
83h
EC Burst Disable
Disable EC operation in burst mode
84h
EC Query
Query SCI events
Firmware Command
Extended commands and handled with F/W mode.
Others
123
4.15.2 EC Command Program Sequence

The following table summarizes the standard EC commands programming flow. Port
66h is the EC command and status port and port 62h is the EC data port.
Command Byte
Command
80h
EC Read
81h
82h
83h
84h
EC Write
Burst Enable
Burst Disable
Query EC
Program Sequence
1.
Host writes command byte 80h (EC_Read) to port 66h.
2.
EC will issue SCI to host while IBF=0
3.
Host writes address to port 62h.
4.
EC will issue SCI to host while OBF=1
5.
Host reads data via port 62h.
1.
Host writes command byte 81h (EC_Write) to port 66h.
2.
3.
Host writes address to port 62h.
4.
5.
Host writes data to port 62h.
6.
1.
Host writes command byte 82h (Burst_Enable) to port 66h.
2.
EC will issue SCI to host while OBF=1.
3.
Host reads via port62h. If 90h obtained, its Burst Ack.
1.
Host writes command byte 83h (Burst_Disable) to port 66h.
2.
1.
Host writes command byte 84h (Query_EC) to port 66h.
2.
EC will issue SCI to host while OBF=1.
3.
Host reads data via port 62h. The data obtained is SCI_ID number.
124
4.15.3 EC SCI Generation

The EC can generate SCI with independent enable control and status flag. Plenty of
hardware SCI events are predefined, and a firmware SCI event gives more flexible use for different
applications. There is a F/W SCI command port located at SCID (0xFF0B). As the F/W writes any
non-zero value to this port, and corresponding enable bit (SCIE0[6]) is set. A hardware SCI signal
will issue to host in sequence. Then the host uses standard EC_Query (84h) command to get the
SCI ID which is written by F/W before. The below table summarizes the information about SCI
events, SCI IDs and the priorities.
SCI ID
Event
Switch
Applications
Priority
00h
Nothing
N/A
01h-07h
RSV
N/A
Reserved
08h
WDT
SCIE0[0]
Watchdog
09h
LPC_IO2F
SCIE0[1]
LPC I/O 0x2F R/W accessing interrupt
0Ah
PS2
SCIE0[2]
PS/2 event
0Bh
KBC
SCIE0[3]
IBF rising (LPC write I/O 60h/64h)
0(Highest)
OBF falling (LPC read I/O 60h)

0Ch
IKB
SCIE0[4]
IKB
0Dh
LPC_IO686C
SCIE0[5]
IBF rising (LPC write I/O 68h/6Ch)

0Eh
LPC_IO6266
SCIE0[6]
IBF rising (LPC write I/O 62h/66h)

FW_SCIID
FW_SCI
SCIE0[7]
EC F/W SCI event
10h
FAN0
SCIE1[0]
FAN0 monitor event (update/overflow)
10
11h
FAN1
SCIE1[1]
11
12h
SMBus
SCIE1[2]
SMBus events
12
13h
CIR
SCIE1[3]
CIR events
13
14h
GPT0
SCIE1[4]
GPT0 event
14
15h
GPT1
SCIE1[5]
GPT1 event
15
16h
GPT2
SCIE1[6]
GPT2 event
16
17h
GPT3
SCIE1[7]
GPT3 event
17
18h
EXTWIO
SCIE3[0]
Write extended I/O (LPC I/O port 80)
18
19h
GPIO00~GPIO0F
SCIE3[1]
GPIO00~GPIO0F
19
1Ah
GPIO10~GPIO1F
SCIE3[2]
GPIO10~GPIO1F
20
1Bh
GPIO20~GPIO2F
SCIE3[3]
GPIO20~GPIO2F
21
1Ch
GPIO30~GPIO3F
SCIE3[4]
GPIO30~GPIO3F
22
1Dh
GPIO40~GPIO4F
SCIE3[5]
GPIO40~GPIO4F
23
1Eh
GPIO50~GPIO5F
SCIE3[6]
GPIO50~GPIO59 / GPXIOD00~GPXIOD07
24
1Fh
ADC
SCIE3[7]
ADC update
125
25(Lowest)
The SCI pulse width is programmable for different applications. Two unit basis, 16s and 64
s can be chosen. To change the SCI pulse width, register PXCFG[2] (0xFF14) is for the unit
selection and the width can be controlled via register SCICFG[3:0] (0xFF03). The equation shows
the relationship. For more detail please refer to these 2 registers description.
SCI Pulse Width = SCICFG[3:0] * Unit ( 16s or 64 s)
4.15.4 EC/KBC Clock Configuration

The EC provides programmable interface to adjust the microprocessor and peripheral
frequency. By default, the microprocessor runs at 8MHz and peripherals are at 4MHz. The
microprocessor can operate at the 32MHz as the highest frequency, and the peripheral runs up to
7.2 MHz. The programming interface is located at register CLKCFG1/CLKCFG2 (0xFF0D/0xFF1E)
and PLLCFG/PLLCFG2 (0xFF0F/0xFF1F). The figure 4-1 illustrates the clock scheme applied in
the KBC.
4.15.5 A/D Converter Control

The control interface of A/D is in the EC space. Features of the A/D converters are
highlighted as following:
- Analog input range: 0.1*VCCA ~0.9*VCCA
- INL: 2 LSB (Typical)
- DNL: 1LSB (Typical)
- Resolution: 10-bit.
- Gain error: 1.5 LSB, Offset error: 1.5 LSB
- Six channels support.
- All A/D converters can be programmed to be General Purpose Input pins.
The following table summarizes the related registers of these 6 A/D converters.
Name
Address
ADDAEN[3:0]
0xFF15
Description
ADC Function Enable bits of ADC3~ADC0
Bit3: ADC3
Bit2: ADC2
Bit1: ADC1
Bit0: ADC0
ADCTRL[6:5]
0xFF18
ADC Function Enable bits of ADC5~ADC4

Bit6: ADC5
Bit5: ADC4
ADCTRL[4:2]
0xFF18
Select ADC channels to convert and output data in ADCDAT and ECIF[7:6]
ADCDAT
0xFF19
This stands for bit9~bit2 of 10bit A/D result.
ECIF[7:6]
0xFF1A
This stands for bit1~bit0 of 10bit A/D result.
126
The following gives the programming sample to control a ADC.

Example
Using ADC0 to get input analog signal
Programming model
1. set the related pin to be alternative output.
GPIOIE38[0] (0xFC67[0]) = 1b
2. enable ADC function
ADDAEN[6] (0xFF15[0]) = 1b
3. enable ADC control
ADCTRL (0xFF18) = 0x01
Waiting ADC interrupr.
4. read ADCDAT (0xFF19) and ECIF (0xFF1A)
127
4.15.6 D/A Converter Control

The control interface of D/A is in the EC space. Features of the D/A converters are
highlighted as following:
- Output range: AGND to VCCA
- Resolution: 8-bit.
- 4 channels support.
- All D/A converters are non-driving capability.
- All D/A converters can be programmed to be General Purpose Output pins.
The following table summarizes the related registers of these 4 D/A converters.
Name
Address
ADDAEN[7:4]
0xFF15
Description
DAC Function Enable bits of DAC3~DAC0
Bit7: DAC3
Bit6: DAC2
Bit5: DAC1
Bit4: DAC0
If DAC selected, please do not set related GPIO function selection register.
DAC0
0xFF10
DAC0 Output Value
DAC1
0xFF11
DAC1 Output Value
DAC2
0xFF12
DAC2 Output Value
DAC3
0xFF13
DAC3 Output Value
The following gives the programming sample to control a DAC.

Example
Using DAC2
Programming model
1. set the related pin to be alternative output.
GPIOFS38[6] (0xFC07[6]) = 0b
2. enable DAC function
ADDAEN[6] (0xFF15[6]) = 1b
3. fill the value to be convert.
DAC2 (0xFF12) = specific value to convert
128
4.15.7 Power Management Control

Two power modes are defined, one is STOP mode and the other is IDLE mode. The
register PMUCFG (0xFF0C) is used to configure the power management. The following table gives
more detail about the definition for these two power modes.
Mode
Description
STOP
All clock sources stop, except external PCI clock and 32.768KHz.
IDLE
Only clock of 8051 microprocessor stops.
RUN
System operations in normal mode.
OFF
All power supply removed, including AC and battery
The diagram below shows the relationship between each power mode.
129
4.15.8 EC Registers Description

EC Hardware Revision ID
Offset
0x00
Name
ECHV
Bit
Type
7-0
RO
Description
EC Hardware version
Default
Bank
0xD2
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x0F
0xFF
Default
Bank
0x90
0xFF
EC Firmware Revision ID
Offset
0x01
Name
ECFV
Bit
Type
7-0
R/W
Description
EC firmware version
This register will be a data port, ADC_test_data[7:0]
test mode (ADCTR[1]=1).
in ADC
EC High Address
Offset
Name
Bit
Type
Description
0x02
ECHA
7-6
R/W
These two bits will be a data port, ADC_test_data[9:8]

ADC test mode (ADCTR[1]=1).
R/W
Write protection of PXCFG[1].
in
0: writable.
1: write protection.
4
R/W
Index-I/O mode access control.

0: access range 0xF400~0xFFFF
1: access range 0xF400~0xF403 and 0xFC00~0xFFFF
3-0
RSV
Reserved
EC SCI Configuration
Offset
0x03
Name
SCICFG
Bit
Type
R/W
Description
Standard EC commands generate SCI.
0: Disable
1: Enable
R/W
SCIID port enable. (F/W SCI write port enable)

0: Disable
1: Enable
R/W
SCI polarity
0: Low active (default)
1: High active
R/W
SCIE0/SCIE1/SCIE2 (0xFF05~0xFF07) enable.

0: Disable
1: Enable
3-0
R/W
SCI pulse width. (max. 1ms)

SCI pulse width = SCICFG[3:0] * (time unit)
where time unit is determined by PXCFG[2], 64s or 16s
If SCICFG[3:0]=0, SCI pulse width = width of system clock.
130
EC Configuration
Offset
Name
Bit
Type
0x04
ECCFG
R/W
Description
EPB fast access enable. To enhance EPB performance.
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
0x00
0xFF
0x00
0xFF
0: Disable
1: Enable
6
R/W
Test mode selection

0: Normal mode
1: Test mode.
5-3
RSV
Reserved
R/W
Extended I/O (debug I/O, port 80) interrupt enable. Only

available while write cycle to port 80 from the host.
0: Disable
1: Enable
R/W
IBF interrupt enable.

EC command port interrupt enable.
CPU writes command/data to EC command/data port.
0: Disable
1: Enable
R/W
OBF interrupt enable.

EC data port interrupt enable.
CPU reads data from EC data port.
0: Disable
1: Enable
EC SCI Interrupt Enable (SCIE0,SCIE1,SCIE3)

Offset
Name
Bit
Type
0x05
SCIE0
7-0
R/W
Description
SCI Event0 enable
0: Disable
1: Enable
0x06
SCIE1
7-0
R/W
SCI Event1 enable

0: Disable
1: Enable
0x07
SCIE3
7-0
R/W
SCI Event2 enable

0: Disable
1: Enable
131
EC SCI Flag (SCIF0,SCIF1,SCIF3)

Offset
Name
Bit
Type
0x08
ECIF0
7-0
R/W1C
Description
SCI Event0 flag
Default
Bank
0x00
0xFF
0x00
0xFF
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x2F
0xFF
0: no event
1: event occurs
0x09
ECIF1
7-0
R/W1C
SCI Event1 flag

0: no event
1: event occurs
0x0A
ECIF3
7-0
R/W1C
SCI Event3 flag

0: no event
1: event occurs
EC SCI ID Write Port (to Generate SCI Event)

Offset
Name
Bit
Type
0x0B
SCID
7-0
R/W
Description
Firmware SCI write port
EC PMU Control/Configuration
Offset
Name
Bit
Type
Description
0x0C
PMUCFG
WO
Write 1 to enter STOP mode.
WO
Write 1 to enter Idle mode.
R/W
LPC cycle wakeup system from STOP mode.

0: Disable
1: Enable
R/W
Reset 8051 while in STOP mode.

0: Disable
1: Enable
R/W
SCI wakeup system

0: Disable
1: Enable
R/W
WDT wakeup system from STOP mode.

0: Disable
1: Enable
R/W
GPWU wakeup system from STOP mode.

0: Disable
1: Enable
R/W
Interrupt wakeup system from Idle mode.

0: Disable
1: Enable
132
EC Clock Configuration
Offset
Name
Bit
Type
0x0D
CLKCFG
R/W
Description
Flash clock from external clock (GPIO59).
Default
Bank
0x00
0xFF
0: Disable
1: Enable
6
R/W
Flash clock control.

0: Half speed. (DPLL_CLK/2)
1: Full speed (DPLL_CLK)
please note, while CLKCFG[6]=0 and CLKCFG[3:2]=0
( power-on default ), the SPI flash clock is always 16MHz.
R/W
DPLL generates 32.768 MHz

0: Disable
1: Enable
R/W
DPLL enters low power state while in STOP mode.

0: Disable
1: Enable
3-2
R/W
8051/Peripheral clock selection.

11b: 32 MHz / 16 MHz
10b: 22 MHz / 11 MHz
01b: 16 MHz / 8 MHz
00b:
R/W
8 MHz / 4 MHz (default)
Peripheral slow down to 1MHz automatically.

If no host access, the peripheral clock will slow down to 1MHz
automatically.
0: Disable
1: Enable
R/W
Clock slow down to 2MHz / 1MHz (8051 / Peripheral) in Idle

mode. If this bit set, the clock of flash will be stopped in idle
mode.
0: Disable
1: Enable
EC Extended I/O (Debug Port) Write Data

Offset
0x0E
Name
EXTIOW
Bit
Type
Description
Default
Bank
7-0
R/W
If the host write data to extended I/O (debug port, port80), an

interrupt occurs, and then the firmware read it back via this
register.
0x00
0xFF
Description
Default
Bank
0xE0
0xFF
EC PLL Configuration
Offset
Name
Bit
Type
0x0F
PLLCFG
7-0
R/W
DPLL initial value. (low 8-bit)

After reset, the DPLL will output frequency about 32MHz with
default value 0xE0.
DPLL initial value is 10-bit, the reset of two high bits are
located at 0xFF1F, PLLCFG2[7:6].
133
EC DAC0 Output Value (ECMISC[1:0]=00b) / Extended Command (ECMISC[1:0]=11b)

Offset
Name
Bit
Type
0x10
DAC0
7-0
R/W
0x10
EXTCMD
7-0
R/W
Description
Default
Bank
The digital data to be converted in DAC0.
0x00
0xFF
8051 extended command port.
0x00
0xFF
Once the command is filled, two events may occur.

-
if non-zero command written, 8051 interrupt issues.
If zero command written, SCI event issues.
Please note, EXTARG0/EXTARG1/EXTARG2 must be ready

before filling this register.
EC DAC1 Output Value (ECMISC[1:0]=00b)/ Extended Command Argument 0(ECMISC[1:0]=11b)

Offset
0x11
0x11
Name
DAC1
EXTARG0
Bit
Type
Default
Bank
7-0
R/W
Description
0x00
0xFF
7-0
R/W
Extended command argument0
0x00
0xFF

Offset
0x12
0x12
Name
DAC2
EXTARG1
Bit
Type
Default
Bank
7-0
R/W
Description
0x00
0xFF
7-0
R/W
0x00
0xFF

Offset
Name
Bit
Type
Default
Bank
0x00
0xFF
0x00
0xFF
Default
Bank
0x00
0xFF
0x13
DAC3
7-0
R/W
0x13
EXTARG2
7-0
R/W
Description
EC 8051 On-Chip Control

Offset
Name
Bit
Type
Description
0x14
PXCFG
7-3
RSV
Reserved
R/W
SCI pulse width time unit.

0: 64s
1: 16s
R/W
WDT timeout reset selection

0: reset whole KBC, except GPIO module.
1: reset 8051 only
To write this bit, please make sure ECHA[5]=0.
R/W
8051 program counter control

0: program counter starts to execute.
1: 8051 reset and pc=0 (program counter).
Pc will keep 0 (reset vector) until this bit is written to 0
134
EC ADC/DAC Function Switch

Offset
Name
Bit
Type
0x15
ADDAEN
7-4
R/W
Description
DAC3~DAC0 Function Enable
Default
Bank
0x00
0xFF
Default
Bank
0x3E
0xFF
Default
Bank
0x83
0xFF
Bit7~Bit4 represents DAC3~DAC0 respectively

0: DAC Disable
1: DAC Enable
If DAC enable, please do not set related GPIO function

selection register.
3-0
R/W
ADC3~ADC0 Function Enable

Bit3~Bit0 represents ADC3~ADC0 respectively
0: ADC Disable
1: ADC Enable.
If ADC enable, please do not set related GPIO bit with

input enable (IE).
EC PLL Frequency Register (High Byte)

Offset
Name
Bit
Type
0x16
PLLFRH
7-0
R/W
Description
DPLL frequency = 32.768KHz(external) * PLLFR
PLLFR[11:0] =( PLLFRH[7:0] : PLLFRL[7:4] )
To generate 32.768MHz, PLLFR = 1000 (decimal) = 0x3E8
i.e., PLLFRH=0x3E
EC PLL Frequency Register (Low Byte)

Offset
Name
Bit
Type
0x17
PLLFRL
7-4
R/W
Description
DPLL frequency = 32.768KHz * PLLFR
PLLFR[11:0] =( PLLFRH[7:0] : PLLFRL[7:4] )
To generate 32.768MHz, PLLFR = 1000 (decimal) = 0x3E8
i.e., PLLFRL[7:4]=0x8
R/W
DPLL lock value presented in CHIPID (0xFF1E~0xFF1F).

0: Disable
1: Enable.
R/W
DPLL test mode enable

0: Disable
1: Enable.
1-0
RSV
Reserved
135
EC ADC Control Register

Offset
Name
Bit
Type
Description
0x18
ADCTRL
RSV
Reserved
6-5
R/W
ADC5, ADC4 enable.
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
Bit6 and Bit5 represent for ADC5 and ADC4 respectively.

0: Disable
1: Enable.
R/W
4-2
R/W
Convert ADC channel selection.

0: ADC0
1: ADC1
2: ADC2
3: ADC3
4: ADC4
5: ADC5
ADC test mode enable.

0: Disable
1: Enable.
R/W
ADC convert start and force interrupt after converting.

0: ADC stops converting, interrupt disable
1: ADC starts converting, interrupt enable
EC ADC Data Output Port

Offset
Name
Bit
Type
0x19
ADCDAT
7-0
RO
Description
Converted data by ADC. ADC output[9:2]=ADCDAT[7:0]
EC Interrupt Pending Flag

Offset
Name
Bit
Type
Description
0x1A
ECIF
7-6
RO
Converted data by ADC. ADC output[1:0]=ECIF[7:6]
5-3
RSV
Reserved
R/W1C
EC firmware mode flag.

If EC command handled by F/W, this flag will be set
R/W1C
EC IBF interrupt pending flag

0: no event
1: event occurs
R/W1C
EC OBF interrupt pending flag

0: no event
1: event occurs
EC Data Port
Offset
Name
Bit
Type
0x1B
ECDAT
7-0
R/W
Description
EC data port.
If ECDAT written, ECSTS[0] (OBF) becomes 1.
EC Command Port
Offset
0x1C
Name
ECCMD
Bit
Type
7-0
RO
Description
This register keeps EC command issued by the host.
136
EC Control and Status Port

Offset
Name
Bit
Type
Description
0x1D
ECSTS
R/W
Reserved
R/W
Reserved
RO
SCI pending flag
Default
Bank
0x00
0xFF
Default
Bank
0: no event
1: event occurs
4
R/W
Burst enable status.

0: EC burst mode disable
1: EC burst mode enable.
R/W
EC I/O write port indicator

0: host writes for data (writes I/O port 62h)
1: host writes for command
R/W
(writes I/O port 66h)
Register 0xFF1E and 0xFF1F function selection.

0: CHIPID display selected
1: CLKCFG2/PLLCFG2 function selected
R/W1C
IBF (Input Buffer Full)

0: buffer not full
1: buffer full
R/W1C
OBF (Output Buffer Full)

0: buffer not full
1: buffer full
EC Clock Configuration 2
Offset
Name
Bit
Type
0x1E
CHIPID_H
7-0
R/W
CHIPID high byte. (ECSTS[2]=0)
0x39
0xFF
7-0
R/W
Divider of (DPLL Freq)/2
0x1F
0xFF
0x1E
CLKCFG2
Description
to generate 1s (ECSTS[2]=1)
For example, DPLL outputs 64MHz (by default), to generate 1

s, the divider should be 32. That is the CLKCFG2 will be
0x1F.
137
EC PLL Configuration 2
Offset
Name
Bit
Type
0x1F
CHIPID_L
7-0
R/W
0x1F
PLLCFG2
7-6
R/W
Description
Default
Bank
CHIPID low byte. (ECSTS[2]=0)
0x26
0xFF
High 2 bits of DPLL initial value. (ECSTS[2]=1)
0x21
0xFF
Default
Bank
0x00
0xFF
DPLL initial value is 10-bit, the low 8 bits are located at

0xFF0F, PLLCFG[7:0].
5
R/W
DPLL reference selection.

0: PCI clock selected. (default)
1: External 32.768KHz.
R/W
DPLL source clock divider.

0: Disable
1: Enable. (default).
If PLLCFG2[5]=1, then this bit should be 1.
If PLLCFG2[5]=0, this bit should be 0.
3-0
R/W
DPLL low speed state setting in Idle mode.

The default value is 0001b, the DPLL will provide 2MHz
(8051)/ 1MHz (Peripheral) clock.
EC MISC Configuration
Offset
0x20
Name
ECMISC
Bit
Type
R/W
Description
8051 state.
0: Idle state
1: Normal state
6-3
R/W
Reserved
R/W
8051 extended command (ExtCMD, 0xFF10) interrupt enable.

0: Disable
1: Enable
R/W
Register function select of 0xFF10~0xFF13 for LPC index-I/O

0: DAC
1: 8051 Extended command related registers
R/W
Register function select of 0xFF10~0xFF13 for 8051.

0: DAC
1: 8051 Extended command related registers
EC Extended I/O (Debug I/O) Data Port by Host

Offset
Name
Bit
Type
Description
Default
Bank
0x21
EXTIOR
7-0
R/W
The host reads extended I/O port and gets data from this
register. No interrupt occurs.
0x00
0xFF
Default
Bank
0x00
0xFF
Embedded Debug Interface Feature Register

Offset
Name
Bit
Type
0x22
EDIF
R/W
Description
EDI feature enable
0: disable
1: enable
6-0
RSV
Reserved
138
Embedded Debug Interface Active Status Register

Offset
Name
Bit
Type
0x23
EDIAS
R/W
Description
EDI active status
Default
Bank
0x00
0xFF
Default
Bank
0x01
0xFF
0: not active
1: active
6-0
RSV
Reserved
Embedded Debug Version ID

Offset
0x24
Name
EDIID
Bit
Type
7-0
RO
Description
EDI version
139
4.16 General Purpose Wake-up Controller (GPWU)

4.16.1 GPWU Function Description
The GPIO module provides flexible methods to wakeup the KBC or to generate
interrupt. Once the input function is determined, plenty of features for wakeup can be setup. Here is
the table to summarize all the features.
Wakeup Enable
Polarity
Edge/Level
Toggle
0: Disable
0:/ L
0: Edge
0: Disable
1: Enable
1:/ H
1: Level
1: Enable
No wakeup events occur
Signal toggle trigger
Falling edge trigger
Low level trigger
Rising edge trigger
High level trigger
140
Description
4.16.2 GPWU Registers Description

GPIO Wakeup Event Enable
Offset
0x30
Name
GPWUEN00
Bit
Type
7-0
R/W
Description
GPIO00~GPIO07 Wakeup Event Switch
Default
Bank
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF

0: Wakeup event disable
1:Wakeup event enable
0x31
GPWUEN08
7-0
R/W
GPIO08~GPIO0F Wakeup Event Switch

0x32
GPWUEN10
7-0
R/W

0x33
GPWUEN18
7-0
R/W

0x34
GPWUEN20
7-0
R/W

0x35
GPWUEN28
7-0
R/W

0x36
GPWUEN30
7-0
R/W

0x37
GPWUEN38
7-0
R/W
GPIO38~GPIO3B Wakeup Event Switch

0x38
GPWUEN40
7-0
R/W

0x39
GPWUEN48
7-0
R/W

141
0x3A
GPWUEN50
7-0
R/W
0x00
0xFF
0x00
0xFF
0x00
0xFF

0x3B
GPWUEN58
7-0
R/W

0x3C
GPWUEN60
7-0
R/W
GPXIOD00~GPXIOD07 Wakeup Event Switch

142
GPIO Wakeup Event Pending Flag

Offset
Name
Bit
Type
0x40
GPWUPF00
7-0
R/W1C
Description
GPIO00~GPIO07 Wakeup Event Pending Flag
Default
Bank
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF

0: No wakeup event
1:Wakeup event pending
0x41
GPWUPF08
7-0
R/W1C
GPIO08~GPIO0F Wakeup Event Pending Flag

0: No wakeup event
0x42
GPWUPF10
7-0
R/W1C

0: No wakeup event
0x43
GPWUPF18
7-0
R/W1C

0: No wakeup event
0x44
GPWUPF20
7-0
R/W1C

0: No wakeup event
0x45
GPWUPF28
7-0
R/W1C

0: No wakeup event
0x46
GPWUPF30
7-0
R/W1C

0: No wakeup event
0x47
GPWUPF38
7-0
R/W1C
GPIO38~GPIO3B Wakeup Event Pending Flag

0: No wakeup event
0x48
GPWUPF40
7-0
R/W1C

0: No wakeup event
0x49
GPWUPF48
7-0
R/W1C

0: No wakeup event
0x4A
GPWUPf50
7-0
R/W1C

0: No wakeup event
143

0x4B
GPWUPF58
7-0
R/W1C

0: No wakeup event
0x4C
GXWUPF00
7-0
R/W1C
GPXIOD00~GPXIOD07 Wakeup Event Pending Flag

0: No wakeup event
144
0x00
0xFF
GPIO Wakeup Polarity Selection

Offset
Name
Bit
Type
0x50
GPWUPS00
7-0
R/W
Description
GPIO00~GPIO07 Wakeup Polarity Selection
Default
Bank
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF

0: Low active (level trigger) / Falling (edge trigger)
1:High active (high trigger) / Rising (edge trigger)
0x51
GPWUPS08
7-0
R/W
GPIO08~GPIO0F Wakeup Polarity Selection

0x52
GPWUPS10
7-0
R/W

0x53
GPWUPS18
7-0
R/W

0x54
GPWUPS20
7-0
R/W

0x55
GPWUPS28
7-0
R/W

0x56
GPWUPS30
7-0
R/W

0x57
GPWUPS38
7-0
R/W
GPIO38~GPIO3B Wakeup Polarity Selection

0x58
GPWUPS40
7-0
R/W

0x59
GPWUPS48
7-0
R/W

0x5A
GPWUPS50
7-0
R/W

145

0x5B
GPWUPS58
7-0
R/W

0x5C
GXWUPS00
7-0
R/W
GPXIOD00~GPXIOD07 Wakeup Polarity Selection

146
0x00
0xFF
GPIO Wakeup Level/Edge Trigger Selection

Offset
Name
Bit
Type
0x60
GPWUEL00
7-0
R/W
Description
GPIO00~GPIO07 Wakeup Level/Edge Selection
Default
Bank
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF

0: Edge trigger
1: Level trigger
0x61
GPWUEL08
7-0
R/W
GPIO08~GPIO0F Wakeup Level/Edge Selection

0: Edge trigger
1: Level trigger
0x62
GPWUEL10
7-0
R/W

0: Edge trigger
1: Level trigger
0x63
GPWUEL18
7-0
R/W

0: Edge trigger
1: Level trigger
0x64
GPWUEL20
7-0
R/W

0: Edge trigger
1: Level trigger
0x65
GPWUEL28
7-0
R/W

0: Edge trigger
1: Level trigger
0x66
GPWUEL30
7-0
R/W

0: Edge trigger
1: Level trigger
0x67
GPWUEL38
7-0
R/W
GPIO38~GPIO3B Wakeup Level/Edge Selection

0: Edge trigger
1: Level trigger
0x68
GPWUEL40
7-0
R/W

0: Edge trigger
1: Level trigger
0x69
GPWUEL48
7-0
R/W

0: Edge trigger
1: Level trigger
0x6A
GPWUEL50
7-0
R/W

0: Edge trigger
1: Level trigger
147

0x6B
GPWUEL58
7-0
R/W

0: Edge trigger
1: Level trigger
0x6C
GXWUEL00
7-0
R/W
GPXIOD00~GPXIOD07 Wakeup Level/Edge Selection

0: Edge trigger
1: Level trigger
148
0x00
0xFF
GPIO Wakeup Input Change (Toggle) Trigger Selection

Offset
Name
Bit
Type
0x70
GPWUCHG00
7-0
R/W
Description
GPIO00~GPIO07 Wakeup Input Change (Toggle) Trigger
Default
Bank
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF

This setting will ignore the corresponding bit of GPWUELxx.
0: Toggle trigger disable
1: Toggle trigger enable
0x71
GPWUCHG08
7-0
R/W
GPIO08~GPIO0F Wakeup Input Change (Toggle) Trigger

0x72
GPWUCHG10
7-0
R/W

0x73
GPWUCHG18
7-0
R/W

0x74
GPWUCHG20
7-0
R/W

0x75
GPWUCHG28
7-0
R/W

0x76
GPWUCHG30
7-0
R/W

0x77
GPWUCHG38
7-0
R/W
GPIO38~GPIO3B Wakeup Input Change (Toggle) Trigger

149
0x78
GPWUCHG40
7-0
R/W
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF

0x79
GPWUCHG48
7-0
R/W

0x7A
GPWUCHG50
7-0
R/W

0x7B
GPWUCHG58
7-0
R/W

0x7C
GXWUCHG00
7-0
R/W
GPXIOD00~GPXIOD07 Wakeup Input Change (Toggle) Trigger

150
4.16.3 GPWU Programming Sample

In this section gives some programming sample to control GPWU module. Please note,
scenario of GPWU filed application.
Example
PIN
Function
GPIO02
Low level trigger
GPIO03
Rising edge trigger
GPIO05
Falling edge trigger
GPIO06
Edge change trigger
Programming model
1. set related wakeup enable register.
GPIWUEN00 (0xFF30) = 0x6C
2. set related wakeup polarity register
GPWUPS00 (0xFF50) = 0x08
3. set related wakeup edge/level trigger register
GPWUEL00 (0xFC60) = 0x04
4.
set related wakeup input change register

GPWUCHG00 (0xFF70) = 0x40
151
4.17 System Management Bus Controller (SMBus)

4.17.1 SMBus Function Description
The SMBus is a two wire interface design based on I2C bus. The SMBus controller in
the KBC supports SMBus 2.0 and supports both master and slave mode with 2 channels. The
SMBus controller supports 12 command protocols as following table. For more detail about each
command protocol, please refer to the System Management Bus Specification 2.0.
Command Byte
Command
Command Byte
Command
02h
Quick Write
08h
Write Word
03h
Quick Read
09h
Read Word
04h
Send Byte
0Ah
Write Block
05h
Receive Byte
0Bh
Read Block
06h
Write Byte
0Ch
Word Process
07h
Read Byte
0Dh
Block Process
The SMBus introduces new mechanism to communicate with I2C devices, called Byte
mode. If the SMBus operates in this mode, only 3 protocols are supported, 05h (Receive Byte),
0Ah (Write Block) and 0Bh (Read Block). Here gives the brief programming guide of how to use
Byte mode as following table.
05h, Receive Byte
0Ah, Write Block
0Bh, Read Block
1.
Set the address in SMBADR

(0xFF9A).
1.

(0xFF9A).
1.

(0xFF9A).
2.
Set the ACK or NACK bit in

SMBPF (0xFF96[6]).
2.
Set the data array in SMBDAT

(0xFF9C).
2.
Set the count number in

SMBCNT (0xFFBC).
3.
Set the protocol in SMBPRTCL

(0xFF98).
3.
Set the count number in

SMBCNT (0xFFBC).
3.

(0xFF98).
4.
Once one byte data received, the

interrupt pending flag will be set
(0xFF96[5]). And the F/W could
obtain the data via pooling or
interrupt method.
4.

(0xFF98).
5.
If more than one byte received,

the F/W must set the ACK or
NACK response in advance. (the
same as step 2), then continue to
the step 4 until all bytes
complete.
152
The SMBus controller works as a host (master). The controller can be programmed to
enable slave mode. In slave mode, the controller will response to its slave address which is
programmable. A slave device could communicate with the SMBus host controller via SMBus Alert
or Host Notify protocols. The SMBus Alert protocol can be implemented via optional SMBAlert#
signal or periodical ARA (Alert Response Address) command. As to Host Notify protocol, The
controller provides registers for F/W to achieve different applications. The following gives the brief
summary between Host Notify protocol and SMBus register interface.
1bit
7bit
1bit
1bit
7bit
1bit
8bit
1bit
8bit
1bit
1bit
SMB Host Addr.
Wr
Device Addr.
Data Low Byte
Data High Byte
SMB Host Addr : stored in SMBAADR, 0xFFBD.

Device Addr : stored in SMBAADR, 0xFFBD.
Data Low Byte: stored in SMBADAT0, 0xFFBE.
Data High Byte: stored in SMBADAT1, 0xFFBF.
S: Start bit
P: Stop bit
Slave (SMBus device) to Master

Master (SMBus host) to Slave
153
4.17.2 SMBus Register Description

SMBus CRC Value
Offset
0x92
Name
SMBTCRC
Bit
Type
7-0
RO
Bit
Type
R/W
Description
SMBus CRC value.
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x06
0xFF
SMBus Pin Control

Offset
0x93
Name
SMBPIN
Description
SMBus data line forced to low.
Write 0 to force SDA0 or SDA1 low.
R/W
SMBus clock line forced to low.

Write 0 to force SCL0 or SCL1 low.
RO
Status of SDA0 or SDA1 or SDA0 wired SDA1..
RO
Status of SCL0 or SCL1 or SCL0 wired SCL1.
R/W
Byte mode function enable
3 protocols support, Write Block/Read Block/Receive Byte.

Protocols are defined via register SMBPRTCL[6:0]
0: Disable
1: Enable
2
R/W
SCL/SDA input debounce enable.

0: Disable
1: Enable
R/W
SCL1/SDA1 pin connected to SMBus controller.

0: Disable
1: Enable
R/W
SCL0/SDA0 pin connected to SMBus controller.

0: Disable
1: Enable
SMBus Configuration
Offset
Name
Bit
Type
0x94
SMBCFG
R/W
Description
SMBus master disable
0: Enable master function.
1: Disable master function
R/W
SMBus host alarm protocol disable (0xFFBD~0xFFBF disable)

0: Enable slave function.
1: Disable slave function
RSV
Reserved
4-0
R/W
SMBus clock period

If SMBCFG[4:0]>0 and SMBPIN[2]=1, the period is
SMBus clock period = (SMBCFG[4:0]+1) * 4s
If SMBCFG[4:0]>0 and SMBPIN[2]=0, the period is
SMBus clock period = SMBCFG[4:0] * 4s
Please do not set these bits to 0.
154
SMBus Interrupt Enable

Offset
Name
Bit
Type
0x95
SMBEN
RO
Description
SMBus host controller status
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
0: not busy
1: busy
6-4
RSV
Reserved
R/W
SMBus slave protocol selection.

0: word read/write
1: byte read/write
R/W
SMBus slave mode enable.

0: Disable
1: Enable
R/W
SMBus alert (host notify protocol) interrupt

0: Disable
1: Enable
R/W
SMBus protocol completion interrupt

0: Disable
1: Enable
SMBus Interrupt Pending Flag

Offset
Name
Bit
Type
Description
0x96
SMBPF
RSV
Reserved
R/W
ACK bit of Receive Byte (Byte Mode) protocol

0: ACK, the Receive Byte protocol keeps going
1: NACK, once the F/W ready to obtain the last Receive Byte,
F/W set this bit in advance. After this last byte transferred,
the controller issues NACK to device and the protocol stop.
R/W1C
Read data interrupt flag of Receive Byte (Byte Mode) protocol

0: no event
1: event occurs
RO
Read protocol interrupt flag of SMBus slave

0: no event
1: event occurs
R/W1C
Interrupt flag of SMBus slave

0: no event
1: event occurs
2-0
RSV
Reserved
SMBus Received CRC Value

Offset
0x97
Name
SMBRCRC
Bit
Type
7-0
RO
Description
The CRC value received from SMBus slave device.
155
SMBus Protocol
Offset
Name
Bit
Type
0x98
SMBPRTCL
R/W
Description
SMBus transaction with PEC (Packet Error Check)
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
0: Disable
1: Enable.
6-0
R/W
Command protocol.
02h: Quick Write
03h: Quick Read
04h: Send Byte
05h: Receive Byte / Receive Byte (Byte Mode)
06h: Write Byte
07h: Read Byte
08h: Write Word
09h: Read Word
0Ah: Write Block / Write Block (Byte Mode)
0Bh: Write Read / Read Block (Byte Mode)
0Ch: Word Process
0Dh: Block Process
others: Reserved
SMBus Status
Offset
Name
Bit
Type
0x99
SMBSTS
R/W
Description
SMBus command done flag
0: no event (Write 0 to clear)
1: event occurs
R/W
SMBus alarm (host notify protocol) interrupt flag

0: no event (Write 0 to clear)
1: event occurs
R/W
SMBus block data array protocol control. F/W could control the
protocol progress via this bit.
0: Block Data Array protocol keeps going.
1: Block Data Array protocol stops
4-0
R/W
Error code.
00h: no error
07h: unknown address failure.
10h: device address no ACK
12h: command no ACK
13h: device data no ACK
17h: device access deny
18h: SMBus timeout
19h: unsupported protocol
1Ah: SMBus busy
1Fh: PEC (Packet Error Check) error
others: Reserved
156
SMBus Address Port

Offset
Name
Bit
Type
Description
0x9A
SMBADR
7-0
R/W
SMBus address (7-bits long), bit0 ignored.
0x9A
SMBADR
7-1
R/W
SMBus address (7-bits long).
(SMBPIN[3]=1)
R/W
Data direction bit
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
0: Write
1: Read
SMBus Command Port

Offset
0x9B
Name
SMBCMD
Bit
Type
7-0
R/W
Description
SMBus command port
SMBus Data Array (8 Bytes)

Offset
0x9C
Name
SMBDAT0
Bit
Type
7-0
R/W
Data port for Send/Receive/Read Byte/Write Byte protocol
Description
Data port for Read Word/Write Word protocol
0x9D
SMBDAT1
7-0
R/W
0x00
0xFF
0x9E
SMBDAT2
7-0
R/W
Data port for Block protocol
0x00
0xFF
0x9F
SMBDAT3
7-0
R/W
0x00
0xFF
0xA0
SMBDAT4
7-0
R/W
0x00
0xFF
0xA1
SMBDAT5
7-0
R/W
0x00
0xFF
0xA2
SMBDAT6
7-0
R/W
0x00
0xFF
0xA3
SMBDAT7
7-0
R/W
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
Default
Bank
0x00
0xFF
SMBus Slave Address (SMBEN[2]=1)

Offset
Name
Bit
Type
0xA4
SMBRSA
7-0
R/W
Description
SMBus slave address (7-bits long), bit0 ignores.
SMBus Block Count

Offset
Name
Bit
Type
0xBC
SMBCNT
7-0
R/W
Description
Smbus block count.
If 0x00, it means 32-byte length in a block transfer.
Bit7~Bit5 are ignored
SMBus Alarm (Host Notify Protocol) Address

Offset
0xBD
Name
SMBAADR
Bit
Type
7-0
R/W
Description
This register is alarm address.
SMBus Alarm Data 0 (Low Byte)

Offset
0xBE
Name
SMBDAT0
Bit
Type
7-0
R/W
Description
Alarm data (low byte)
157
SMBus Alarm Data 1 (High Byte)

Offset
Name
Bit
Type
0xBF
SMBDAT1
7-0
R/W
Description
Alarm data (high byte)
158
Default
Bank
0x00
0xFF
4.17.3 SMBus Programming Sample

In this section gives some programming sample to control SMBus module. Please note,
scenario of SMBus filed application.
Example
Reading status of a battery (address 0x0A)
Programming model
SMBADR (0xFF9A) = 0x0A
; battery address
SMBCMD (0xFF9B) = 0x12

SMBPTCL (0xFF98) = 0x07
Wait SMBSTS (0xFF99[7]) = 1b
; command complete
Check if SMBSTS[4:0] = 0000b
; no error
Read SMBDAT (0xFF9C)
; the current status
159
4.18 8051 Microprocessor

4.18.1 8051 Microprocessor Function Description
The Microprocessor inside KBC is an industrial compatible i8051. The 8051 is featured
with 128bytes Special Function Register (SFR), Serial port, 2 16-bit Timers and 3 I/O ports with
interrupt capability. The 8051 operates based on external crystal and runs at 8MHz by default. The
following figure gives an illustration of the 8051 architecture.
160
4.18.1.1 8051 Instruction

The instruction of 8051 microprocessor is fully compatible with industrial i8051.
The instruction sets are as following table. The OpCode is in Hexadecimal and (b) means Binary. B
stands for byte number of instruction. C stands for number of cycle needed.
Mnemonic
OpCode
Arithmetic
Mnemonic
OpCode
INC
DPTR
A3
AB
ADD
A, #data
24
MUL
A4
ADD
A, direct
25
SUBB
A, #data
94
ADD
A, @ R0
26
SUBB
A, direct
95
ADD
A, @ R1
27
SUBB
A, @ R0
96
ADD
A, R0
28
SUBB
A, @ R1
97
ADD
A, R1
29
SUBB
A, R0
98
ADD
A, R2
2A
SUBB
A, R1
99
ADD
A, R3
2B
SUBB
A, R2
9A
ADD
A, R4
2C
SUBB
A, R3
9B
ADD
A, R5
2D
SUBB
A, R4
9C
ADD
A, R6
2E
SUBB
A, R5
9D
ADD
A, R7
2F
SUBB
A, R6
9E
ADDC A, #data
34
SUBB
A, R7
9F
ADDC A, direct
35
ADDC A, @ R0
36
Logic & Byte Operation
ADDC A, @ R1
37
ANL
direct, A
52
ADDC A, R0
38
ANL
direct, #data
53
ADDC A, R1
39
ANL
A, #data
54
ADDC A, R2
3A
ANL
A, direct
55
ADDC A, R3
3B
ANL
A, @ R0
56
ADDC A, R4
3C
ANL
A, @ R1
57
ADDC A, R5
3D
ANL
A, R0
58
ADDC A, R6
3E
ANL
A, R1
59
ADDC A, R7
3F
ANL
A, R2
5A
DEC
14
ANL
A, R3
5B
DEC
direct
15
ANL
A, R4
5C
DEC
@ R0
16
ANL
A, R5
5D
DEC
@ R1
17
ANL
A, R6
5E
DEC
R0
18
ANL
A, R7
5F
DEC
R1
19
CLR
E4
DEC
R2
1A
CPL
F4
DEC
R3
1B
ORL
direct, A
42
DEC
R4
1C
ORL
direct, #data
43
DEC
R5
1D
ORL
A, #data
44
DEC
R6
1E
ORL
A, direct
45
DEC
R7
1F
ORL
A, @ R0
46
161

Mnemonic
OpCode
Mnemonic
OpCode
DIV
AB
84
ORL
A, @ R1
47
DA
D4
ORL
A, R0
48
INC
04
ORL
A, R1
49
INC
direct
05
ORL
A, R2
4A
INC
@ R0
06
ORL
A, R3
4B
INC
@ R1
07
ORL
A, R4
4C
INC
R0
08
ORL
A, R5
4D
INC
R1
09
ORL
A, R6
4E
INC
R2
0A
ORL
A, R7
4F
INC
R3
0B
RL
23
INC
R4
0C
RLC
33
INC
R5
0D
RR
03
INC
R6
0E
RRC
13
INC
R7
0F
SWAP A
C4
Logic & Byte Operation
Data Movement
XRL
direct, A
62
MOV
direct, R7
8F
XRL
direct, #data
63
MOV
@ R0, direct
A6
XRL
A, #data
64
MOV
@ R1, direct
A7
XRL
A, direct
65
MOV
R0, direct
A8
XRL
A, @ R0
66
MOV
R1, direct
A9
XRL
A, @ R1
67
MOV
R2, direct
AA
XRL
A, R0
68
MOV
R3, direct
AB
XRL
A, R1
69
MOV
R4, direct
AC
XRL
A, R2
6A
MOV
R5, direct
AD
XRL
A, R3
6B
MOV
R6, direct
AE
XRL
A, R4
6C
MOV
R7, direct
AF
XRL
A, R5
6D
MOV
A, direct
E5
XRL
A, R6
6E
MOV
A, @ R0
E6
XRL
A, R7
6F
MOV
A, @ R1
E7
MOV
A, R0
E8
MOV
A, R1
E9
Bit Operation
ANL
C, bit
82
MOV
A, R2
EA
ANL
C, /bit
B0
MOV
A, R3
EB
CLR
bit
C2
MOV
A, R4
EC
CLR
C3
MOV
A, R5
ED
CPL
bit
B2
MOV
A, R6
EE
CPL
B3
MOV
A, R7
EF
20
MOV
direct, A
F5
10
MOV
@ R0, A
F6
40
MOV
@ R1, A
F7
JB
bit, relative
JBC
JC
bit, relative
relative
JNB
bit, relative
30
MOV
R0, A
F8
JNC
relative
50
MOV
R1, A
F9
MOV
C, bit
92
MOV
R2, A
FA
162

Mnemonic
OpCode
Mnemonic
OpCode
MOV
bit, C
A2
MOV
R3, A
FB
ORL
C, bit
72
MOV
R4, A
FC
ORL
C, /bit
A0
MOV
R5, A
FD
SETB
bit
D2
MOV
R6, A
FE
SETB
D3
MOV
R7, A
FF
MOV
DPTR, #data16
90
MOVC
A, @ A+PC
83
>33
A, @ A+DPTR
93
>33
Data Movement
MOV
A, #data
74
MOVC
MOV
direct, #data
75
MOVX
A, @ DPTR
E0
>=5
MOV
@ R0, #data
76
MOVX
A, @ R0
E2
>=5
MOV
@ R1, #data
77
MOVX
A, @ R1
E3
>=5
MOV
R0, #data
78
MOVX
@ DPTR, A
F0
>=4
MOV
R1, #data
79
MOVX
@ R0, A
F2
>=4
MOV
R2, #data
7A
MOVX
@ R1, A
F3
>=4
MOV
R3, #data
7B
POP
D0
MOV
R4, #data
7C
PUSH
direct
C0
MOV
R5, #data
7D
XCH
A, direct
C5
MOV
R6, #data
7E
XCH
A, @ R0
C6
MOV
R7, #data
7F
XCH
A, @ R1
C7
MOV
direct, direct
85
XCH
A, R0
C8
MOV
direct, @ R0
86
XCH
A, R1
C9
MOV
direct, @ R1
87
XCH
A, R2
CA
MOV
direct, R0
88
XCH
A, R3
CB
MOV
direct, R1
89
XCH
A, R4
CC
MOV
direct, R2
8A
XCH
A, R5
CD
MOV
direct, R3
8B
XCH
A, R6
CE
MOV
direct, R4
8C
XCH
A, R7
CF
MOV
direct, R5
8D
XCHD
A, @ R0
D6
MOV
direct, R6
8E
XCHD
A, @ R1
D7
DJNZ
direct, relative
D5
Program Branching
ACALL
address11
direct
bbb1 0001
DJNZ
R0, relative
D8
bbb0 0001
DJNZ
R1, relative
D9
AJMP
address11
CJNE
A, #data, relative
B4
DJNZ
R2, relative
DA
CJNE
A, direct, relative
B5
DJNZ
R3, relative
DB
CJNE @ R0, #data, relative
B6
DJNZ
R4, relative
DC
CJNE @ R1, #data, relative
B7
DJNZ
R5, relative
DD
CJNE
R0, #data, relative
B8
DJNZ
R6, relative
DE
CJNE
R1, #data, relative
B9
DJNZ
R7, relative
DF
CJNE
R2, #data, relative
BA
JMP
@ A+DPTR
73
CJNE
R3, #data, relative
BB
JNZ
relative
70
CJNE
R4, #data, relative
BC
JZ
relative
60
CJNE
R5, #data, relative
BD
LCALL
12
CJNE
R6, #data, relative
BE
LJMP
02
163

Mnemonic
OpCode
BF
RET
22
RETI
32
CJNE
R7, #data, relative
Mnemonic
SJMP
80
00
Special Instruction
NOP
OpCode
164
4.18.1.2 Interrupt Controller

In order to support more application, the 8051 in KBC extends interrupt channel
to 24 for internal peripherals, that is, I/O port P0, P1 and P3 are with interrupt capability. The
interrupt priority for each channel is fixed and no nested interrupt is supported. Here is the table to
summarize the implementation of the interrupt controller.
Int. Source
Vector Address
Applications
IE0
0x0003
8051 external interrupt 0
TF0
0x000B
8051 Timer 0
IE1
0x0013
8051 external interrupt 1
TF1
0x001B
8051 Timer 1
RI & TI
0x0023
8051 Serial port TX/RX interrupt
P0I[0]
0x0043
Watchdog
P0I[1]
0x004B
LPC I/O 0x2F R/W accessing interrupt
P0I[2]
0x0053
PS/2 event
P0I[3]
0x005B
KBC
P0I[4]
0x0063
IKB
P0I[5]
0x006B
68h/6Ch ports
10
P0I[6]
0x0073
EC
11
P0I[7]
0x007B
ESB events
12
P1I[0]
0x0083
13
P1I[1]
0x008B
14
P1I[2]
0x0093
SMBus events
15
P1I[3]
0x009B
CIR events
16
P1I[4]
0x00A3
GPT0 event
17
P1I[5]
0x00AB
GPT1 event
18
P1I[6]
0x00B3
GPT2 event
19
P1I[7]
0x00BB
GPT3 event
20
P3I[0]
0x00C3
Write extended I/O (LPC I/O port 80)
21
P3I[1]
0x00CB
GPIO00~GPIO0F
22
P3I[2]
0x00D3
GPIO10~GPIO1F
23
P3I[3]
0x00DB
GPIO20~GPIO2F
24
P3I[4]
0x00E3
GPIO30~GPIO3F
25
P3I[5]
0x00EB
GPIO40~GPIO4F
26
P3I[6]
0x00F3
GPIO50~GPIO59 / GPXIOD00~GPXIOD07
27
P3I[7]
0x00FB
ADC update
Priority
0(Highest)
28(Lowest)
165
4.18.1.3 Interrupt Enable/Flag Table

Interrupt Enable
Pending Flag
address
bit
behavior
address
bit
type
8051 external interrupt0

(GPIO1A)
A8h
88h
8051 Timer0
A8h
88h
8051 external interrupt0

(GPIO1B)
A8h
88h
8051 Timer1
A8h
88h
8051 Serial Port
A8h
98h
1~0
FE80h
FE81h
FE81h
WDT
RTC
FE84h
7,0
FE84h
LPC I/O R/W 0x2F
FF20h
FF9Ah
FE9Ah
PS/2
FEE0h
3~0
FEE1h
3~0
KBC
FC81h
1,0
FC82h
1,0
IKB
FCA3h
5~0
FCA4h
5~0
LPC 68h/6Ch
IBF_Rising
OBF_Falling
FE9Dh
1,0
FE9Eh
1,0
FE9Eh
3,2
EC host interrupt
FF04h
FF1Ah
FF04h
FF1Ah
FC90h
FC92h
6~4
FC91h
6~4
FC92h
3~0
FC97h
7~0
FC98h
7~4
FC97h
FE20h
3,2
FE21h
1,0
FE30h
3,2
FE31h
1,0
FF95h
FF99h
7,5
FF96h
ESB
FAN
SMBus
FF95h
FF99h
FF95h
FF96h
CIR TX
FEC0h
FEC2h
CIR RX
FEC0h
FEC2h
2~0
GPT0~GPT3
FE50h
3~0
FE51h
3~0
Wrute Extended I/O
FE95h
GPWU
FF3Xh
7~0
FF4Xh
7~0
ADC
FF18h
behavior
Interrupt Behavior => (Interrupt Occurs)

(1) IE bit = 1, interrupt asserts when trigger event occurs
(2) IE bit = 1, interrupt asserts when trigger event occurs
but if PF not clear, interrupt will continue asserting
166

(3) IE = 1, interrupt asserts when trigger event occurs
or IE bit is from low to high(0 -> 1) when Pending Flag(PF) is = 1
(4) No matter IE bit = 1 or 0, interrupt asserts when trigger event occurs
type
Pending Flag(PF)
=>
(1) When trigger event occurs, PF will be set to 1.

PF cleared to 0 by WC1/WC0
(2) IE bit = 1, when event occurs, PF will be set to 1.
PF is cleared to 0 by WC1/WC0
Interrupt Enable = (IE)
Pending Flag = (PF)
WC1 = Write 1 clear
WC0 = Write 1 clear
167
4.18.1.4 8051 Special Function Register (SFR)

The Special Function Registers are located in the internal RAM of 8051
microprocessor. The internal address are from 0x80 to 0xFF, sized with 128 bytes. All the SFRs are
compatible with the standard ones. Just few SFRs are redesigned with new features for flexible
application. The following table gives a brief summary. For more detail, please refer to the section
of register description.
80
P0IE
SP
DPL
DPH
PCON2
88
TCON
TMOD
TL0
TL1
90
P1IE
98
SCON
A0
P2
A7
A8
IE
AF
B0
P3IE
B7
B8
IP
BF
TH0
TH1
PCON
87
8F
97
SBUF
SCON2
SCON3
9F
C0
C7
C8
CF
D0
PSW
D7
D8
P0IF
DF
E0
ACC
E7
E8
P1IF
EF
F0
F7
F8
P3IF
FF
1. The blue parts are changed from standard features and the green ones are the new design for special features.
And all the others are the standard features of conventional 8051.
2. The registers listed in the column with
mark are all bit addressable.
168
4.18.2 8051 Microprocessor Register Description

The SFR registers are located at internal RAM 0x80 ~ 0xFF.
P0 Interrupt Enable Register
Address
Name
Bit
Type
0x80
P0IE
7-0
R/W
Description
P0 interrupt enable.
Default
0x00
Bit0~bit7 stand for corresponding P0[0]~P0[7].

0: Disable
1: Enable
Stack Pointer
Address
Name
Bit
Type
0x81
SP
7-0
R/W
Description
8051 stack pointer register
Default
0x07
Data Pointer Low Byte

Address
Name
Bit
Type
0x82
DPL
7-0
R/W
Description
Low byte of DPTR
Default
0x00
Data Pointer High Byte

Address
Name
Bit
Type
0x83
DPH
7-0
R/W
Address
Name
Bit
Type
0x84
RSV
7-0
RSV
Address
Name
Bit
Type
0x85
RSV
7-0
RSV
Description
High byte of DPTR
Default
0x00
Reserved
Description
Reserved
Default
0x00
Reserved
Description
Reserved
Default
0x00
169
Processor Control Register 2

Address
Name
Bit
Type
Description
0x86
PCON2
R/W
Reserved but this bit should be 0.
R/W
Timer0/Timer1 test mode enable.
Default
0x20
0: Disable
1: Enable
5
R/W
Reserved
R/W
KBC modules write control.

Once this bit set, 8051 could issue write access to external
modules.
0: Disable
1: Enable
R/WC0
Same interrupt source pending flag.

If the 8051 is handling some interrupt event, at the same time,
the same source asserting the interrupt again, this flag will be
set. If this flag set, the 8051 will re-enter ISR again once
executing IRET. Writing 0 to clear this flag.
2-1
RSV
R/W
Reserved
Not fetching instruction while in idle loop.
0: Disable
1: Enable
Processor Control Register

Address
Name
Bit
Type
0x87
PCON
7-6
RSV
Reserved
Description
R/W
Interrupt vector offset address1
0x00
0: Interrupt vector address offset adding 0x0

4
R/W
Interrupt vector offset address2

Please note, if PCON[5]=1 and PCON[4]=1 then the result of
interrupt vector address will be added 0xC000.
R/W
General purpose flag 1

0: no event
1: event occurs
R/W
General purpose flag 2

0: no event
1: event occurs
WO
Stop mode enable.

All clock stop except the external 32.768K OSC and PCICLK.
1: Enable (write 0 no work)
WO
Idle mode enable.

The clock of 8051 stops.
1: Enable (write 0 no work)
Default
170
Timer/Counter Control Register

Address
Name
Bit
Type
0x88
TCON
R/W1C
Description
TF1, Timer1 overflow flag
0: no event
1: event occurs
R/W
TR1, Timer1 start control.

0: stop to count
1: start to count
R/W1C
TF0, Timer0 overflow flag

0: no event
1: event occurs
R/W
TR0, Timer0 start control.

0: stop to count
1: start to count
R/W1C
IE1, External interrupt 1 flag

0: no event
1: event occurs
R/W
IT1, External interrupt 1 trigger selection

0: low level trigger
1: falling edge trigger
R/W1C
IE0, External interrupt 0 flag

0: no event
1: event occurs
R/W
IT0, External interrupt 0 trigger selection

0: low level trigger
1: falling edge trigger
171
Default
0x00
Timer Mode Register

Address
Name
Bit
Type
0x89
TMOD
R/W
Description
GATE1, this bit is the gate control of TR1 and INT1
Default
0x00
0: Disable
1: Enable
6
R/W
CT1, Timer1 timer/counter selection

0: Timer
1: Counter
5-4
R/W
TM1, Timer1 mode selection

0: 13-bit timer
1: 16-bit timer
2: 8-bit auto reload timer
3: Timer 1 stops.
R/W
GATE0, this bit is the gate control of TR0 and INT0

0: Disable
1: Enable
R/W
CT0, Timer0 timer/counter selection

0: Timer
1: Counter
1-0
R/W
TM0, Timer0 mode selection

0: 13-bit timer
1: 16-bit timer
2: 8-bit auto reload timer
3: TL0 and TH0 are two 8-bit timers.
Timer 0 Low Byte

Address
Name
Bit
Type
0x8A
TL0
7-0
R/W
Description
Low byte of timer 0
Default
0x00
Timer 1 Low Byte

Address
Name
Bit
Type
0x8B
TL1
7-0
R/W
Description
Low byte of timer 1.
Default
0x00
Timer 0 High Byte

Address
Name
Bit
Type
0x8C
TH0
7-0
R/W
Description
High byte of timer 0
Default
0x00
Timer 1 High Byte

Address
Name
Bit
Type
0x8D
TH1
7-0
R/W
Description
High byte of timer 1
Default
0x00
172
Port1 Interrupt Enable Register

Address
Name
Bit
Type
0x90
P1IE
7-0
R/W
Description
Port 1 interrupt enable.
Default
0x00
Bit0~Bit7 stand for P1[0]~P1[7] respectively

0: Disable
1: Enable
Reserved
Address
Name
Bit
Type
0x91-0x97
N/A
7-0
RSV
Description
Reserved
Default
0x00
Serial Port Control Register

Address
Name
Bit
Type
0x98
SCON
7-6
R/W
Description
SM1,SM0, serial port mode
Default
0x50
00: 8-bit shift register, E51RX will be shift clock of E51CLK.

01: 8-bit serial port (variable)
5
RSV
Reserved
R/W
REN, serial port receive function enable.

0: Disable
1: Enable
th
R/W
TB8, The 9 bit of transmit data in mode2 and mode3.
R/W
RB8, The 9 bit of receive data
R/W0C
th
TI, TX interrupt flag

0: no event
1: event occurs
R/W0C
RI, RX interrupt flag

0: no event
1: event occurs
Serial Port Data Buffer Register

Address
0x99
Name
SBUF
Bit
Type
7-0
R/W
Description
Serial port data buffer
Default
0x00
Serial Port Control Register 2

Address
0x9A
Name
SCON2
Bit
Type
7-0
R/W
Description
High byte of 16-bit counter for baud rate
Default
0x00
Serial Port Control Register 3

Address
0x9B
Name
SCON3
Bit
Type
7-0
R/W
Description
Low byte of 16-bit counter for baud rate
173
Default
0x00
Port 2 Register
Address
0xA0
Name
P2
Bit
Type
7-0
R/W
Description
Port 2 register
Default
0x00
Interrupt Enable Register

Address
0xA8
Name
IE
Bit
Type
R/W
Description
EA, all interrupts enable.
Default
0x00
0: Disable
1: Enable
6-5
RSV
Reserved
R/W
ES, serial port interrupt enable

0: Disable
1: Enable
R/W
ET1, timer1 overflow interrupt enable

0: Disable
1: Enable
R/W
EX1, external interrupt 1 enable.

0: Disable
1: Enable
R/W
ET0, timer0 overflow interrupt enable

0: Disable
1: Enable
R/W
EX0, external interrupt 0 enable.

0: Disable
1: Enable
Interrupt Enable Register

Address
Name
Bit
Type
0xB0
P3IE
7-0
R/W
Description
Port 3 interrupt enable.
Bit0~Bit7 stand for P3[0]~P3[7] respectively
0: Disable
1: Enable
174
Default
0x00
Interrupt Priority Register

Address
Name
Bit
Type
Description
0xB8
IP
7-5
RSV
Reserved
R/W
Serial port interrupt priority
Default
0x00
0: Low
1: High
3
R/W
Timer1 interrupt priority

0: Low
1: High
R/W
External interrupt 1 priority

0: Low
1: High
R/W
Timer 0 interrupt priority

0: Low
1: High
R/W
External interrupt 0 priority

0: Low
1: High
Processor Status Word Register

Address
Name
Bit
Type
Description
0xD0
PSW
R/W
CY, carry flag
R/W
AC, auxiliary carry flag.
R/W
F0, for user general purpose.
R/W
RS1, register bank selector 1.
R/W
RS0, register bank selector 0.
R/W
OV, overflow flag
R/W
F1, flag 1 for user general purpose
R/W
P, parity flag
Default
0x00
Port0 Interrupt Flag Register

Address
0xD8
Name
P0IF
Bit
Type
7-0
R/W
Bit
Type
7-0
R/W
Description
Port 0 interrupt flag.
Default
0x00
Accumulator, ACC
Address
0xE0
Name
ACC
Description
Accumulator
Default
0x00
175

Address
Name
Bit
Type
0xE8
P1IF
7-0
R/W
Address
Name
Bit
Type
0xF0
7-0
R/W
Description
Default
0x00
B Register
Description
B register, for MUL and DIV instructions.
Default
0x00

Address
Name
Bit
Type
0xF8
P3IF
7-0
R/W
Description
Default
0x00
176
5. Electrical Characteristics
5.1 Absolute Maximum Rating
Symbol
VCC
Parameter
Power Source Voltage
Condition
All voltages are referred to GND.
Rating
Unit
-0.3 ~ 3.6
Vi
Input Voltage
-0.3 ~ 3.6
Vo
Output Voltage
-0.3 ~ 3.6
Storage Temperature
-65 ~ 150
TSTG
ESD Tolerance
CZAP = 100pF
RZAP = 1.5K
5.2 DC Electrical Characteristics

Parameter
Symbol
Min
Input Low Voltage
VIL
Input High Voltage
Max
Unit
Condition
-0.3
VCC*0.3
VCC=3.0~3.6V
VIH
VCC*0.7
VCC*1.1
VCC=3.0~3.6V
Input High Voltage(5V Tolerant)
VIH
VCC*0.7
5.5
VCC=3.0~3.6V
Output Low Voltage
VOL
0.4
Output High Voltage
VOH
2.8
Input Low Threshold
Vt-
1.14
Input High Threshold
Vt+
1.94
Hysteresis
VTH
0.8
Input Leakage Current
IIL
No pull-up
Tri-state Leakage Current
IOZ
No pull-up
Input Pull-Up Resistance
RPU
VI=0V
Input Capacitance
CPU
5.5
pF
Output Capacitance
COUT
5.5
pF
Bi-directional Capacitance
CBID
5.5
pF
Typ.
30K
40K
177
50K
5.3 A/D Characteristics

Parameter
Limits
Min
Typ
Unit
Max
Resolution
10
Bit
Integral Non-linearity Error (INL)
LSB
Differential Non-linearity Error (DNL)
LSB
Offset Error
LSB
Gain Error
LSB
A/D Input Voltage Range
0.1Vcca
0.9Vcca
A/D Input Leakage Current

A/D Input Resistance
<0.1
V
uA
10
A/D Input Capacitance
pF
A/D Clock Frequency
MHz
Voltage Conversion Time
us
178
5.4 Recommend Operation Condition

Symbol
Parameter
Limits
Unit
Min
Typ
Max
Power Source Voltage
3.0
3.3
3.6
GND
Ground Voltage
-0.3
0.3
VCCA
Analog Reference Voltage
3.0
3.3
3.6
Vcc
(for A/D and D/A)

AGND
Analog Ground Voltage
Top
Operating Temperature
0
0
25
V
70
5.5 Operating Current

Symbol
Parameter
Limits
Unit
Typ
Icc
Typical current
consumption in operating
state under Windows
environment. All clock
domains are running, and
no keyboard/mouse
activities.
20
mA
5.6 Package Thermal Information

Thermal resistance (degrees C/W). ThetaJA values for KB926D.
ThetaJA @ 0 m/s
ThetaJA @ 1 m/s
ThetaJA @ 2 m/s
128-Pin LQFP
59.1
53.3
51.4
128 LFBGA
50.9
48.7
45.5
179
5.7 AC Electrical Characteristics

5.7.1 SPI Flash Timing
tSCLK
(duty cycle 50/50)
tCLL
SPICLK
tCLH
tOSU
MOSI
tOH
tDSU
MISO
tDH
tSLCH
tCHSH
tSHSL
SPICS#
Parameter
Symbol
Spec.
Typ.
Min.
Max.
Condition
Unit
SPICLK period
tSCLK
SPICLK High Period
tCLH
SPICLK Low Period
tCLL
MOSI Setup Time
tOSU
MOSI Hold Time
15.2
*1
--
4
4
tOH
--
ns
--
--
--
--
tSCLK/2
*2
-5
tSCLK/2
*2
+5
--
--
---
SPICS# Active Setup Time
tSLCH
--
tSCLK
--
SPICS# Not Active Hold Time
tCHSH
--
tSCLK/2
--
SPICS# Deselect Time
tSHSL
110
--
--
MISO Setup Time
tDSU
--
--
tSCLK/2 4
--
--
MISO Hold Time
tDH
1.
Tolerance +/- 3% (need to count in the DPLL tolerance)
2.
For characteristic only.
180
= 15.2ns,
CL=12pF
tSCLK = 15.2ns,
CL=12pF
tSCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL=12pF
CL=12pF
6. Package Information
6.1 LQFP 128-Pin Outline Diagram
6.1.1 Top View
181
6.1.2 Side View
182
6.1.3 Lead View
183
6.1.4 LQFP Outline Dimensions

DIM
Min.
Typ.
Max.
DIM
Min.
Typ.
Max.
1.6
E1
A1
0.05
0.15
A2
1.35
1.4
1.45
L1
0.13
0.16
0.23
R1
0.08
b1
0.13
0.19
R2
0.08
0.2
0.09
0.2
0.2
c1
0.09
0.16
14 BSC
0.45
0.6
0.75
1 REF
3.5
16 BSC
D1
14 BSC
11
12
13
0.4 BSC
11
12
13
16 BSC
Unit
Package
mm
14x14x1.4
Pitch POD
0.4
Footprint
2mm
184
6.2 LFBGA 128-Pin Outline Diagram

6.2.1 Top View
185
6.2.2 Side View
186
6.2.3 Bottom View
187
6.2.4 LFBGA Outline Dimensions

DIM
Min.
Nor.
1.3
A1
0.16
0.26
A2
0.21
A3
0.7
0.27
0.37
0.5
D1
E1
Unit
mm
Package
7mm * 7 mm
Max.
188
6.3 Part Number Description

Part Number
Package Size
Lead Free Process
KB926QF D2
14mm * 14mm 128 pins LQFP
Lead Free
KB926QF D3
14mm * 14mm 128 pins LQFP
Lead Free
189

Keyboard Controller Data Sheet: Revision 1.1 Dec. 2008

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Keyboard Controller Data Sheet: Revision 1.1 Dec. 2008

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KB926D

KB926D Keyboard Controller Datasheet

ENE Technology Inc.

This document is issued for

only. Please do not transfer it to other companies.

THIS DOCUMENT CONTAINS CONFIDEMTIAL

This document issued to:

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

1. Adding interrupt enable/pending flag table In 4.18.1.3

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

KB926D Keyboard Controller Datasheet

4. MODULE DESCRIPTIONS ................................................................................ 19

KB926D Keyboard Controller Datasheet

4.9.3 SDI Programming Sample ................................................................... 82

KB926D Keyboard Controller Datasheet

4.15.3 EC SCI Generation ........................................................................... 125

KB926D Keyboard Controller Datasheet

6.1.4 LQFP Outline Dimensions ................................................................. 184

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

X-bus Bus Interface (XBI) : Flash Interface

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

8042 Keyboard Controller

Internal Keyboard Matrix (IKB)

Embedded Controller (EC)

SMBus Host Controller

Digital-to-Analog Converter (DAC)

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

Analog-to-Digital Converter (ADC)

Pulse Width Modulator (PWM)

WatchDog Timer (WDT)

Real Time Clock

General Purpose Timer (GPT)

General Purpose Wakeup (GPWU)

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

General Purpose Input/Output (GPIO)

ENE Serial Bus Interface (ESB)

ENE Debug Interface (EDI)

SPI Device Interface (SDI)

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

1.3 Comparison (KB926C vs. KB926D )

External PS/2 I/F

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

1.4 Block Diagram

Copyright2008, ENE Technology Inc.

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

2. Pin Assignment and Description

KB926D Keyboard Controller Datasheet

2.2 KB926D 128 LFBGA Ball Map

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

2.3 KB926D Pin Assignment Side A

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

2.4 KB926D Pin Assignment Side B

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

2.5 KB926D Pin Assignment Side C

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

2.6 KB926D Pin Assignment Side D

Copyright2008, ENE Technology Inc.

KB926D Keyboard Controller Datasheet

2.7 I/O Cell Descriptions