Microcontrolador Del Ups Cyber
Microcontrolador Del Ups Cyber
Microcontrolador Del Ups Cyber
ST7263BKx ST7263BEx
Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM,
DFU capability, 8-bit ADC, WDG, timer, SCI and IC
Features
Memories
4, 8, 16 or 32 Kbytes Program memory:
high density Flash (HDFlash), or ROM with
Readout and Write Protection
In-application Programming (IAP) and incircuit programming (ICP)
384, 512 or 1024 bytes RAM memory (128byte stack)
Clock, reset and supply management
Run, Wait, Slow and Halt CPU modes
12 or 24 MHz oscillator
RAM retention mode
Optional low voltage detector (LVD)
Universal serial bus (USB) interface
DMA for low speed applications compliant
with USB 1.5 Mbs (version 2.0) and HID
specifications (version 1.0)
Integrated 3.3 V voltage regulator and
transceivers
Supports USB DFU class specification
Suspend and Resume operations
3 endpoints with programmable In/Out
configuration
Up to 27 I/O ports
Up to 8 high sink I/Os (10 mA at 1.3 V)
2 very high sink true open drain I/Os
(25 mA at 1.5 V)
Up to 8 lines individually programmable as
interrupt inputs
1 analog peripheral
8-bit A/D converter with 8 or 12 channels
2 timers
Programmable watchdog
16-bit timer with 2 input Captures, 2 output
Compares, PWM output and clock input
June 2009
LQFP48 (7x7)
SDIP32
24
SO34(Shrink)
QFN40 (6x6)
SO24
2 communication Interfaces
Asynchronous serial communications interface
IC multimaster interface up to 400 kHz
Instruction set
63 basic instructions
17 main addressing modes
8 x 8 unsigned multiply instruction
True bit manipulation
Development tools
Versatile development tools (under
Windows) including assembler, linker, Ccompiler, archiver, source level debugger,
software library, hardware emulator,
programming boards and gang
programmers, HID and DFU software
layers
Table 1.
Device summary
Reference
Part number
ST7263BHx
ST7263BH2, ST7263BH6
ST7263BDx
ST7263BD6
ST7263BKx
ST7263BK1, ST7263BK2,
ST7263BK4, ST7263BK6
ST7263BEx
ST7263BE1, ST7263BE2,
ST7263BE4, ST7263BE6
1/186
www.st.com
Contents
ST7263Bxx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
2.2
2.3
VDD/VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
VDDA/VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1
4.4
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5
4.6
4.7
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2
2/186
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1.1
6.1.2
Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1.3
External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 7516 Rev 8
ST7263Bxx
Contents
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.2
External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1
6.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.2
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3.2
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3.3
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.3.4
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3.5
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3.6
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10
Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.4
11.1.5
11.1.6
11.1.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.1.8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Contents
ST7263Bxx
11.3
11.4
11.5
11.6
4/186
11.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.2.4
11.2.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.2.6
11.2.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.3.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.3.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.3.5
11.3.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.3.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4.4
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.4.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.6.2
11.6.3
11.6.4
11.6.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.6.6
ST7263Bxx
12
Contents
12.2
13
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.1.2
12.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.1.4
12.1.5
12.1.6
12.1.7
13.1.2
13.1.3
13.1.4
13.1.5
13.2
13.3
13.4
13.5
13.6
13.7
13.7.2
13.7.3
13.8
13.9
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Contents
ST7263Bxx
14
15
14.2
14.3
15.2
15.3
15.4
16
17
6/186
15.3.1
15.3.2
15.3.3
15.3.4
16.2
16.3
16.4
16.5
16.6
ST7263Bxx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device pin description (QFN40, LQFP48, SO34 and SDIP32). . . . . . . . . . . . . . . . . . . . . . 17
Device pin description (SO24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interrupt vector map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Hardware register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Recommended Values for 24 MHz crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Port A0, A3, A4, A5, A6, A7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PA1, PA2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Port B description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port C description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port D description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I/O ports register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Watchdog timing (fCPU = 8 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
IC/R register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
OC/R register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock Control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Prescaling factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TR dividing factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
RR dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
TP bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
STAT_TX bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
STAT_RX bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Slave Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Master Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
IC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7/186
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 57.
Table 56.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
8/186
ST7263Bxx
ST7263Bxx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
9/186
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
10/186
ST7263Bxx
ST7263Bxx
Introduction
Introduction
The ST7263B microcontrollers form a sub-family of the ST7 MCUs dedicated to USB
applications. The devices are based on an industry-standard 8-bit core and feature an
enhanced instruction set. They operate at a 24 MHz or 12 MHz oscillator frequency. Under
software control, the ST7263B MCUs may be placed in either Wait or Halt modes, thus
reducing power consumption. The enhanced instruction set and addressing modes afford
real programming potential. In addition to standard 8-bit data management, the ST7263B
MCUs feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes. The devices include an ST7 core, up to 32 Kbytes of program memory, up to
1024 bytes of RAM, 27 I/O lines and the following on-chip peripherals:
USB low speed interface with 3 endpoints with programmable in/out configuration using
the DMA architecture with embedded 3.3 V voltage regulator and transceivers (no
external components are needed).
Watchdog
16-bit Timer featuring an External clock input, 2 input Captures, 2 output Compares
with Pulse Generator capabilities
Low voltage reset (LVD) ensuring proper power-on or power-off of the device
The ST72F63B devices are Flash versions. They support programming in IAP mode (Inapplication programming) via the on-chip USB interface.
Table 2.
Device overview
Features
Program
memory Kbytes (Flash /
ROM)
RAM (stack) bytes
ST7263BHx
32
16
ST7263BDx
32
32
1024 (128)
Standard
Peripherals
1024 512
(128 (128)
384
(128)
32
16
SCI,
ADC
AD
27 (10)
SCI, IC
19 (10)
14 (6)
4.0 V to 5.5 V
8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
Operating
temp.
Packages
Operating
Supply
CPU frequency
16
ST7263BEx
Other
Peripherals
I/Os (high
current)
ST7263BKx
0 C to +70 C
LQFP48 (7x7)
QFN40
(6x6)
SDIP32/
SO34
QFN40
(6x6)
SDIP32/
SO34
SO24
11/186
Introduction
Figure 1.
ST7263Bxx
General block diagram
INTERNAL
CLOCK
OSC/3
OSCIN
OSCOUT
OSCILLATOR
IC
OSC/4 or OSC/2
for USB2)
VDD
VSS
PORT A
POWER
SUPPLY
PA[7:0]
(8 bits)
16-BIT TIMER
WATCHDOG
CONTROL
8-BIT CORE
ALU
LVD
USB DMA
RESET
PORT B
ADC(1)
PORT D
VDDA
PROGRAM
MEMORY
(32K Bytes)
(UART)
USB SIE
VSSA
RAM
(1024 Bytes)
PD[7:0]
(8 bits)
PORT C
SCI
VPP/TEST
PB[7:0]
(8 bits)
PC[2:0]
(3 bits)
USBDP
USBDM
USBVCC
1. ADC channels:
12 on 48-pin devices (Port B and Port D[3:0])
8 on 34 and 32-pin devices (Port B)
None on 24-pin devices
2. 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock.
3. The drive from USBVCC is sufficient to only drive an external pull-up in addition to the internal transceiver.
12/186
ST7263Bxx
Pin description
Pin description
2.1
Note:
Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to VDD
and VSS) will significantly improve product electromagnetic susceptibility performance.
2.2
2.3
VDD/VSS
Main power supply and ground voltages
Note:
To enhance the reliability of operation, it is recommended that VDDA and VDD be connected
together on the application board. This also applies to VSSA and VSS.
2.4
VDDA/VSSA
Power supply and ground voltages for analog peripherals.
Note:
To enhance the reliability of operation, it is recommended that VDDA and VDD be connected
together on the application board. This also applies to VSSA and VSS.
2.5
Alternate functions
Several pins of the I/O ports assume software programmable alternate functions as shown
in the pin description.
Note:
The USBOE alternate function is mapped on Port C2 in 32/34/48 pin devices. In SO24
devices it is mapped on Port B1.
The timer OCMP1 alternate function is mapped on Port A6 in 32/34/48 pin devices. In SO24
devices it is not available.
13/186
Pin description
48-pin LQFP pinout
PA0/MCO
PA1(25mA)/SDA/ICCD
PD7
PD6
PD5
PD4
PD3/AIN11
PD2/AIN10
PD1/AIN9
PD0/AIN8
PA2(25mA)/SCL/ICCC
NC
Figure 2.
ST7263Bxx
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
TDO/PC1
RDI/PC0
RESET
NC
NC
NC
NC
NC
NC
NC
AIN7/IT8/PB7(10mA)
AIN6/IT7/PB6(10mA)
VSSA
USBDP
USBDM
USBVCC
VDDA
VDD
OSCOUT
OSCIN
VSS
USBOE/PC2
NC
NC
14/186
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
PB1(10mA)/AIN1
PB2(10mA)/AIN2
PB3(10mA)/AIN3
PB4(10mA)/AIN4/IT5
PB5(10mA)/AIN5/IT6
VPP/TEST
ST7263Bxx
Pin description
40-lead QFN package pinout
PA1(25mA)/SDA/ICCD
PD71)
PD61)
PD51)
PD41)
PD31)/AIN11
PD21)/AIN10
PD11)/AIN9
PD01)/AIN8
PA2(25mA)/SCL/ICCC
Figure 3.
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
10
21
13
14
15
16
17
18
19
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
PB1(10mA)/AIN1
PB2(10mA)/AIN2
PB3(10mA)/AIN3
PB4(10mA)/AIN4/IT5
20
IT8/AIN7/PB7(10mA)
IT7/AIN6/PB6(10mA)
VPP/TEST
IT6/AIN5/PB5(10mA)
12
NC
NC
USBOE/PC2
11
TDO/PC1
RDI/PC0
RESET
PA0/MCO
VSSA
USBDP
USBDM
USBVCC
VDDA
VDD
OSCOUT
OSCIN
VSS
1. Port D functions are not available on the 8 Kbyte version of the QFN40 package (ST7263BK2) and should
not be connected.
15/186
Pin description
Figure 4.
ST7263Bxx
34-pin SO package pinout
VDD
OSCOUT
OSCIN
VSS
PC2/USBOE
PC1/TDO
PC0/RDI
RESET
NC
AIN7/IT8/PB7(10mA)
AIN6/PB6/IT7(10mA)
VPP/TEST
AIN5/IT6/PB5(10mA)
AIN4/IT5/PB4(10mA)
AIN3/PB3(10mA)
AIN2/PB2(10mA)
AIN1/PB1(10mA)
Figure 5.
34
33
32
31
30
29
28
27
26
10
25
11
24
12
23
13
22
14
21
15
20
16
19
17
18
32
31
30
29
28
27
26
25
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
USBDP
VSSA
PA0/MCO
PA1(25mA)/SDA/ICCDATA
NC
NC
NC
PA2(25mA)/SCL/ICCCLK
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
VDDA
USBVCC
USBDM
USBDP
VSSA
PA0/MCO
PA1(25mA)/SDA/ICCDATA
NC
NC
PA2(25mA)/SCL/ICCCLK
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
16/186
VDDA
USBVCC
USBDM
Figure 6.
24
23
22
21
20
19
18
17
16
10
15
11
14
12
13
USBVcc
USBDM
USBDP
VSSA
PA0/MCO
PA1(25mA)/SDA/ICCDATA
PA2(25mA)/SCL/ICCCLK
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA7/OCMP2/IT4
PB0(10mA)
ST7263Bxx
Pin description
The RESET configuration of each pin is shown in bold. This configuration is kept as long as
the device is under reset state.
Table 3.
6 VDD
7 OSCOUT
Oscillator output
8 OSCIN
Oscillator input
4 10 9 VSS
Digital ground
5 11 10 PC2/USBOE
I/O
CT
Port C2
6 12 13 PC1/TDO
I/O
CT
Port C1
7 13 14 PC0/RDI
I/O CT
Port C0
8 14 15 RESET
I/O
9 15 16 NC
--
Not connected
--
Not connected
18 NC
--
Not connected
19 NC
--
Not connected
20 NC
--
Not connected
21 NC
--
Not connected
22 NC
--
Not connected
16 17 NC
PP
OD
Output
ana
int
wpu
Input
float
Input
Pin name
Output
QFN40
Main
function
(after
reset)
SO34
Port /control
SDIP32
Type
Pin n
Alternate function
Reset
9 10 17 23 PB7/AIN7/IT8
I/O CT 10mA X
Port B7
10 11 18 24 PB6/AIN6/IT7
I/O CT 10mA X
Port B6
11 12 19 25 VPP/TEST
Programming supply
12 13 20 26 PB5/AIN5/IT6
I/O CT 10mA X
Port B5
13 14 21 27 PB4/AIN4/IT5
I/O CT 10mA X
Port B4
14 15 22 28 PB3/AIN3
I/O CT 10mA X
Port B3
17/186
Pin description
Device pin description (QFN40, LQFP48, SO34 and SDIP32) (continued)
Port /control
PP
OD
Output
ana
int
wpu
Input
float
Output
Pin name
Type
Level
LQFP48
QFN40
SO34
SDIP32
Pin n
Input
Table 3.
ST7263Bxx
Main
function
(after
reset)
Alternate function
15 16 23 29 PB2/AIN2
I/O CT 10mA X
Port B2
16 17 24 30 PB1/AIN1
I/O CT 10mA X
Port B1
17 18 25 31 PB0/AIN0
I/O CT 10mA X
Port B0
18 19 26 32 PA7/OCMP2/IT4
I/O
CT
Port A7
Timer output
Compare 2
19 20 27 33 PA6/OCMP1/IT3
I/O
CT
Port A6
Timer output
Compare 1
20 21 28 34 PA5/ICAP2/IT2
I/O
CT
Port A5
Timer input
Capture 2
21 22 29 35 PA4/ICAP1/IT1
I/O
CT
Port A4
Timer input
Capture 1
22 23 30 36 PA3/EXTCLK
I/O
CT
Port A3
Timer External
clock
23 24 31 38 PA2/SCL/ICCCLK
I/O
CT 25mA X
Port A2
IC serial clock,
ICC clock
32 39 PD0(1)/AIN8
I/O
CT
Port D0
33 40
PD1(1)/AIN9
I/O
CT
Port D1
34 41 PD2(1)/AIN10
I/O
CT
Port D2
35 42 PD3(1)/AIN11
I/O
CT
Port D3
36 43 PD4(1)
I/O
CT
Port D4
37 44
PD5(1)
I/O
CT
Port D5
38 45 PD6(1)
I/O
CT
Port D6
(1)
I/O
CT
Port D7
25
NC
--
Not connected
24 26
NC
--
Not connected
25 27
NC
--
Not connected
39 46 PD7
26 28 40 47 PA1/SDA/ICCDATA
I/O CT 25mA X
27 29 1 48 PA0/MCO
I/O
CT
T
X
Port A1
Port A0
28 30 2
1 VSSA
29 31 3
2 USBDP
I/O
30 32 4
3 USBDM
I/O
18/186
Analog ground
ST7263Bxx
Pin description
Device pin description (QFN40, LQFP48, SO34 and SDIP32) (continued)
Port /control
PP
OD
Output
ana
float
wpu
Input
Output
Pin name
Input
Type
LQFP48
Level
QFN40
SO34
SDIP32
Pin n
int
Table 3.
Main
function
(after
reset)
Alternate function
31 33 5
4 USBVCC(2)
32 34 6
5 VDDA
1. Port D functions are not available on the 8 Kbyte version of the QFN40 package (ST7263BK2) and should not be
connected.
2. The drive from USBVcc is sufficient to only drive an external pull-up in addition to the internal transceiver.
PP
OD
Output
ana
int
Input
float
Output
SO24
Pin name
Input
Level
Type
Pin n
wpu
Table 4.
Main
function
(after
reset)
Alternate function
VDD
OSCOUT
Oscillator output
OSCIN
Oscillator input
VSS
Digital ground
PC1/TDO
I/O
PC0/RDI
Port C1
I/O CT
Port C0
RESET
I/O
PB6/IT7
I/O CT 10mA
VPP/TEST
10
PB3
I/O CT 10mA
Port B3
11
PB2
I/O CT 10mA
Port B2
12
PB1/USBOE
I/O CT 10mA
Port B1
13
PB0
I/O CT 10mA
Port B0
14
PA7/OCMP2/IT4
I/O
CT
Port A7
15
PA5/ICAP2/IT2
I/O
CT
Port A5
16
PA4/ICAP1/IT1
I/O
CT
Port A4
17
PA3/EXTCLK
I/O
CT
Port A3
18
PA2/SCL/
ICCCLK
I/O
CT 25mA
Port A2
IC serial clock,
ICC clock
19
PA1/SDA/ICCDATA
I/O CT 25mA
Port A1
CT
X
X
Reset
X
Port B6
Programming supply
19/186
Pin description
Device pin description (SO24) (continued)
CT
PP
OD
ana
int
wpu
Output
Port A0
Alternate function
PA0/MCO
21
VSSA
22
USBDP
I/O
23
USBDM
I/O
24
USBVCC
Main
function
(after
reset)
20
20/186
I/O
Input
float
Type
SO24
Pin name
Port /control
Output
Level
Pin n
Input
Table 4.
ST7263Bxx
Analog ground
ST7263Bxx
Caution:
Memory locations noted Reserved must never be accessed. Accessing a reserved area
can have unpredictable effects on the device.
Figure 7.
Memory map
0040h
0000h
HW registers
(See Table 5)
003Fh
0040h
00FFh
0100h
RAM
(384 / 512 / 1024 Bytes)
16-bit Addressing
RAM
Reserved
7FFFh
8000h
8000h
Program memory
(4 / 8 / 16 / 32 KBytes)
FFFFh
Table 5.
Stack
(128 Bytes)
017Fh
0180h
FFDFh
FFE0h
Short Addressing
RAM (192 bytes)
32 KBytes
C000h
16 KBytes
E000h
8 KBytes
F000h
FFDFh
4 KBytes
Vector address
Description
Masked
Remarks
FFE0h-FFEDh
FFEEh-FFEFh
FFF0h-FFF1h
FFF2h-FFF3h
FFF4h-FFF5h
FFF6h-FFF7h
FFF8h-FFF9h
FFFAh-FFFBh
FFFCh-FFFDh
FFFEh-FFFFh
Reserved area
USB interrupt vector
SCI interrupt vector
IC interrupt vector
TIMER interrupt vector
IT1 to IT8 interrupt vector
USB End Suspend mode interrupt vector
Flash start programming interrupt vector
TRAP (software) interrupt vector
RESET vector
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
None
None
Internal interrupt
Internal interrupt
Internal interrupt
Internal interrupt
External interrupt
External interrupts
Internal interrupt
CPU interrupt
No
No
No
No
Yes
Yes
Yes
No
Yes
21/186
ST7263Bxx
Register label
Register name
Reset
status
Remarks
0000h
0001h
Port A
PADR
PADDR
00h
00h
R/W
R/W
0002h
0003h
Port B
PBDR
PBDDR
00h
00h
R/W
R/W
0004h
0005h
Port C
PCDR
PCDDR
1111 x000b
1111 x000b
R/W
R/W
0006h
0007h
Port D
PDDR
PDDDR
00h
00h
R/W
R/W
0008h
ITC
ITIFRE
Interrupt register
00h
R/W
0009h
MISC
MISCR
Miscellaneous register
00h
R/W
000Ah
000Bh
ADC
ADCDR
ADCCSR
00h
00h
Read only
R/W
000Ch
WDG
WDGCR
7Fh
R/W
000Dh to
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
22/186
Reserved (4 bytes)
TIM
TCR2
TCR1
TCSR
TIC1HR
TIC1LR
TOC1HR
TOC1LR
TCHR
TCLR
TACHR
TACLR
TIC2HR
TIC2LR
TOC2HR
TOC2LR
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
R/W
Read only
R/W
Read only
Read only
R/W
R/W
SCI
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
C0h
xxh
00h
x000 0000b
00h
Read only
R/W
R/W
R/W
R/W
ST7263Bxx
Table 6.
Address
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
USB
Register label
USBPIDR
USBDMAR
USBIDR
USBISTR
USBIMR
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB
Register name
USB PID register
USB DMA address register
USB Interrupt/DMA register
USB Interrupt Status register
USB Interrupt Mask register
USB Control register
USB Device Address register
USB Endpoint 0 register A
USB Endpoint 0 register B
USB Endpoint 1 register A
USB Endpoint 1 register B
USB Endpoint 2 register A
USB Endpoint 2 register B
Reset
status
Remarks
x0h
xxh
x0h
00h
00h
06h
00h
0000 xxxxb
80h
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
R/W
IC Data register
Reserved
IC (7 Bits) Slave Address register
IC Clock Control register
IC 2nd Status register
IC 1st Status register
IC Control register
00h
00h
00h
00h
00h
00h
R/W
0032h to
Reserved (5 bytes)
0036h
0032h
0036h
Reserved (5 Bytes)
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Flash
FCSR
Reserved (1 byte)
I2CDR
IC
I2COAR
I2CCCR
I2CSR2
I2CSR1
I2CCR
R/W
R/W
Read only
Read only
R/W
23/186
ST7263Bxx
4.1
Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external VPP supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
Main features
4.3
Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased.
ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board.
IAP (in-application programming). In this mode, all sectors except Sector 0, can be
programmed or erased without removing the device from the application board
and while the application is running.
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
Readout protection
Structure
The Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Table 7). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 8). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).
Table 7.
24/186
Available sectors
Sector 0
Sectors 0,1
>8
Sectors 0,1, 2
ST7263Bxx
4.3.1
Readout protection
Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased and the device can be reprogrammed.
Readout protection selection depends on the device type:
In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
Figure 8.
8K
10K
16K
24K
32K
48K
60K
1000h
FLASH
MEMORY SIZE
3FFFh
7FFFh
9FFFh
SECTOR 2
BFFFh
D7FFh
DFFFh
2 Kbytes
8 Kbytes
EFFFh
FFFFh
4.4
SECTOR 1
SECTOR 0
ICC interface
ICC (In-circuit communication) needs a minimum of four and up to six pins to be connected
to the programming tool (see Figure 9). These pins are:
25/186
ST7263Bxx
Typical ICC interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
(See Note 3)
ICC CONNECTOR
HE10 CONNECTOR TYPE
OPTIONAL
(See Note 4)
10
2
APPLICATION
RESET SOURCE
See Note 2
10k
CL1
ICCDATA
RESET
ST7
ICCCLK
See Note 1
ICCSEL/VPP
OSC1
OSC2
VDD
CL2
VSS
APPLICATION
POWER SUPPLY
APPLICATION
I/O
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by
the application, isolation such as a serial resistor has to implemented in case another device forces the
signal. Refer to the Programming Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET
circuit in this case. When using a classical RC network with R > 1K or a reset management IC with open
drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.
3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be
connected when using most ST Programming Tools (it is used to monitor the application power supply).
Please refer to the Programming Tool manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the
application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case.
4.5
26/186
ST7263Bxx
4.6
4.7
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.8
Register description
Flash Control/status register (FCSR)
This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.
Reset value: 0000 0000 (00h)
7
Read/write
27/186
ST7263Bxx
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
5.2
5.3
Main features
63 basic instructions
CPU registers
The six CPU registers shown in Figure are not present in the memory mapping and are
accessed by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
28/186
ST7263Bxx
Read/write
The 8-bit Condition Code register contains the interrupt mask and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 H Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instruction. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
Bit 3 I Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the
JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I
is cleared. By default an interrupt routine is not interruptible because the I bit
is set by hardware at the start of the routine and reset by the IRET
instruction at the end of the routine. If the I bit is cleared by software in the
interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
29/186
ST7263Bxx
Bit 2 N Negative
This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a
logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 Z Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and
JRNC instructions. It is also affected by the bit test and branch, shift and rotate
instructions.
14
13
12
11
10
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Read/write
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 10).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
30/186
ST7263Bxx
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 10. Stack manipulation example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0100h
SP
SP
Y
CC
A
CC
A
CC
A
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 017Fh
SP
SP
SP
0
ACCUMULATOR
0
X INDEX REGISTER
0
Y INDEX REGISTER
PCH
8 7
PCL
0
PROGRAM COUNTER
1 1 1 H I
N Z C
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
31/186
ST7263Bxx
6.1
Reset
The Reset procedure is used to provide an orderly software start-up or to exit low power
modes.
Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an
external reset at the RESET pin.
A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to
be loaded into the PC and with program execution starting from this point.
An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator
becomes active.
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
6.1.1
During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other
devices.
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from Reset, to ensure the application functions properly.
6.1.2
Watchdog reset
When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset
other devices in the same way as the low voltage reset (Figure 12).
6.1.3
External reset
The external reset is an active low input signal applied to the RESET pin of the MCU.
As shown in Figure 15, the RESET signal must stay low for a minimum of one and a half
CPU clock cycles.
An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.
32/186
ST7263Bxx
LOW VOLTAGE
DETECTOR
VDD
INTERNAL
RESET
FROM
WATCHDOG
RESET
VIT+
VIT-
VDD
RESET
VIT+
Addresses
$FFFE
33/186
ST7263Bxx
OSCIN
tOXOV
fCPU
FFFE
PC
RESET
WATCHDOG RESET
FFFF
4096 CPU
CLOCK
CYCLES
DELAY
1. Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+, VIT- and Vhys
34/186
ST7263Bxx
6.2
Clock system
6.2.1
General description
The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive
the internal oscillator. The internal clock (fCPU) is derived from the external oscillator
frequency (fOSC), which is divided by 3 (and by 2 or 4 for USB, depending on the external
clock used). The internal clock is further divided by 2 by setting the SMS bit in the
miscellaneous register.
Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be
used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for
the USB (refer to Figure 18).
The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock
signal consists of a square wave with a duty cycle of 50%.
The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or
ceramic resonator in the frequency range specified for fosc. The circuit shown in Figure 17 is
recommended when using a crystal, and Table 8 lists the recommended capacitance. The
crystal and associated components should be mounted as close as possible to the input
pins in order to minimize output distortion and start-up stabilization time.
Table 8.
RSMAX(1)
20
25
70
COSCIN
56pF
47pF
22pF
COSCOUT
56pF
47pF
22pF
RP
1-10 M
1-10 M
1-10 M
1. RSMAX is the equivalent serial resistor of the crystal (see crystal specification).
6.2.2
External clock
An external clock may be applied to the OSCIN input with the OSCOUT pin not connected,
as shown on Figure 16. The tOXOV specifications do not apply when using an external clock
input. The equivalent specification of the external clock source should be used instead of
tOXOV (see Table 62: Control timing characteristics).
Figure 16. External clock source connections
OSCIN
OSCOUT
NC
EXTERNAL
CLOCK
35/186
ST7263Bxx
OSCOUT
OSCIN
RP
COSCIN
COSCOUT
%2
%3
8, 4 or 2 MHz
CPU and
peripherals)
1
SMS
1
24 or
12 MHz
Crystal
%2
%2
%2
0
OSC24/12
36/186
6 MHz (USB)
ST7263Bxx
Interrupts
Interrupts
The ST7 core may be interrupted by one of two different methods: maskable hardware
interrupts as listed in Table 9 and a non-maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 19.
The maskable interrupts must be enabled clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed when they are enabled (see external
interrupts subsection).
When an interrupt has to be serviced:
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 9 for vector
addresses).
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
As a consequence of the IRET instruction, the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case several interrupts are simultaneously pending, a hardware priority defines which
one will be serviced first (see Table 9).
External interrupts
The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising
edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7)
can generate an interrupt when a falling edge occurs on this pin.
Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE
register and if the I bit of the CC is reset.
37/186
Interrupts
ST7263Bxx
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by one of the two following operations:
Note:
Accessing the status register while the flag is set followed by a read or write of an
associated register.
The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be
enabled) will therefore be lost if the clear sequence is executed.
All interrupts allow the processor to leave the Wait low power mode.
Exit from Halt mode may only be triggered by an external interrupt on one of the ITi ports
(PA4-PA7 and PB4-PB7), an end suspend mode interrupt coming from USB peripheral, or a
reset.
Figure 19. Interrupt processing flowchart
FROM RESET
BIT I SET
N
N
IRET
Y
EXECUTE INSTRUCTION
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
38/186
INTERRUPT
ST7263Bxx
Table 9.
N
Interrupts
Interrupt mapping
Source block
RESET
Register
label
Description
Priority
order
Reset
Exit
from
Halt
Vector
address
yes
FFFEh-FFFFh
no
FFFCh-FFFDh
yes
FFFAh-FFFBh
N/A
TRAP
Software interrupt
FLASH
USB
Highest
Priority
ISTR
FFF8h-FFF9h
yes
ITi
TIMER
IC
External interrupts
ITRFRE
FFF6h-FFF7h
TIMSR
FFF4h-FFF5h
ICSR1
IC Peripheral interrupts
ICSR2
Lowest
Priority
FFF2h-FFF3h
no
SCI
SCISR
FFF0h-FFF1h
USB
ISTR
FFEEh-FFEFh
7.1
0
IT7E
IT6E
IT5E
IT4E
IT3E
IT2E
IT1E
Read/write
39/186
ST7263Bxx
8.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, two
main power saving modes are implemented in the ST7.
After a Reset, the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided by 3 (fCPU).
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
8.2
Halt mode
The MCU consumes the least amount of power in Halt mode. The Halt mode is entered by
executing the Halt instruction. The internal oscillator is then turned off, causing all internal
processing to be stopped, including the operation of the on-chip peripherals.
When entering Halt mode, the I bit in the Condition Code register is cleared. Thus, all
external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs,
the CPU clock becomes active.
The MCU can exit Halt mode on reception of either an external interrupt on ITi, an end
suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then
turned on and a stabilization time is provided before releasing CPU operation. The
stabilization time is 4096 CPU clock cycles.
After the start up delay, the CPU continues operation by servicing the interrupt which wakes
it up or by fetching the reset vector if a reset wakes it up.
40/186
ST7263Bxx
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
OFF
OFF
OFF
CLEARED
I-BIT
N
RESET
N
EXTERNAL
INTERRUPT*
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
ON
ON
SET
1. Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt
routine and cleared when the CC register is popped.
8.3
Slow mode
In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the
Miscellaneous register. The CPU and peripherals are clocked at this lower frequency. Slow
mode is used to reduce power consumption, and enables the user to adapt the clock
frequency to the available supply voltage.
8.4
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the WFI ST7 software instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is forced to 0 to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches
to the starting address of the interrupt or Reset service routine.
41/186
ST7263Bxx
The MCU will remain in Wait mode until a Reset or an interrupt occurs, causing it to wake
up. Refer to Figure 21.
Related documentation
AN 980: ST7 Keypad Decoding Techniques, Implementing Wakeup on Keystroke
AN1014: How to Minimize the ST7 Power Consumption
AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode
Figure 21. Wait mode flowchart
WFI INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
ON
OFF
CLEARED
N
RESET
N
INTERRUPT
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
ON
ON
SET
IF RESET
4096 CPU CLOCK
CYCLES DELAY
1. Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt
routine and cleared when the CC register is popped.
42/186
ST7263Bxx
I/O ports
I/O ports
9.1
Introduction
The I/O ports offer different functional modes:
Transfer of data through digital inputs and outputs and for specific pins
An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital
input (with or without interrupt generation) or a digital output.
9.2
Functional description
Each port is associated to 2 main registers:
Each I/O pin may be programmed using the corresponding register bits in DDR register: bit
X corresponding to pin X of the port. The same correspondence is used for the DR register.
Table 10.
Mode
Input
Output
Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Note:
When switching from input mode to output mode, the DR register should be written first to
output the correct value as soon as the port is configured as an output.
Interrupt function
When an I/O is configured as an input with interrupt, an event on this I/O can generate an
external interrupt request to the CPU. The interrupt sensitivity is given independently
according to the description mentioned in the ITRFRE interrupt register.
Each pin can independently generate an interrupt request.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see interrupts
section). If more than one input pin is selected simultaneously as an interrupt source, this is
logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are
masked.
43/186
I/O ports
ST7263Bxx
Output mode
The pin is configured in output mode by setting the corresponding DDR register bit (see
Table 7).
In this mode, writing 0 or 1 to the DR register applies this digital value to the I/O pin
through the latch. Therefore, the previously saved value is restored when the DR register is
read.
Note:
Input pull-up configuration can cause an unexpected value at the input of the alternate
peripheral input.
When the on-chip peripheral uses a pin as input and output, this pin must be configured as
an input (DDR = 0).
Caution:
The alternate function must not be activated as long as the pin is configured as an input with
interrupt in order to avoid generating spurious interrupts.
Warning:
44/186
ST7263Bxx
9.3
I/O ports
9.3.1
Port A
Table 11.
PORT A
Input(1)
Alternate function
Output
Signal
Condition
PA0
with pull-up
push-pull
MCO = 1 (MISCR)
PA3
with pull-up
push-pull
Timer EXTCLK
CC1 =1
CC0 = 1 (Timer CR2)
PA4
with pull-up
Timer ICAP1
Push-pull
PA5
with pull-up
Push-pull
PA6(2)
with pull-up
Push-pull
OC1E = 1
PA7
with pull-up
Push-pull
OC2E = 1
1. Reset state.
2. Not available on SO24
Figure 22. PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration
ALTERNATE ENABLE
ALTERNATE 1
OUTPUT
VDD
P-BUFFER
VDD
DR
PULL-UP
DATA BUS
LATCH
ALTERNATE ENABLE
DDR
LATCH
PAD
DDR SEL
N-BUFFER
DR SEL
ALTERNATE INPUT
DIODES
ALTERNATE ENABLE
VSS
45/186
I/O ports
Table 12.
ST7263Bxx
PA1, PA2 description(1)
I/O
Port A
Input1
Alternate function
Output
Signal
Condition
PA1
without pull-up
IC enable
PA2
without pull-up
IC enable
1. Reset state.
DDR
LATCH
DATA BUS
PAD
DDR SEL
N-BUFFER
DR SEL
ALTERNATE ENABLE
VSS
0
CMOS SCHMITT TRIGGER
46/186
ST7263Bxx
I/O ports
9.3.2
Port B
Table 13.
Port B description
I/O
Port B
PB0
PB1
Input(1)
without pull-up
without pull-up
Alternate function
Output
push-pull
Signal
Condition
CH[3:0] = 000
(ADCCSR)
CH[3:0] = 001
(ADCCSR)
USBOE =1 (MISCR)
push-pull
PB2
without pull-up
push-pull
CH[3:0]= 010
(ADCCSR)
PB3
without pull-up
push-pull
CH[3:0]= 011
(ADCCSR)
CH[3:0]= 100
(ADCCSR)
PB4
without pull-up
push-pull
IT5 Schmitt triggered
IT5E = 1 (ITIFRE)
input
Analog input (ADC)
PB5
without pull-up
CH[3:0]= 101
(ADCCSR)
push-pull
IT6 Schmitt triggered
IT6E = 1 (ITIFRE)
input
Analog input (ADC)
PB6
without pull-up
CH[3:0]= 110
(ADCCSR)
push-pull
IT7 Schmitt triggered
IT7E = 1 (ITIFRE)
input
Analog input (ADC)
PB7
without pull-up
CH[3:0]= 111
(ADCCSR)
push-pull
IT8 Schmitt triggered
IT8E = 1 (ITIFRE)
input
1. Reset State
2. On SO24 only
47/186
I/O ports
ST7263Bxx
VDD
1
0
P-BUFFER
DR
LATCH
VDD
ALTERNATE ENABLE
DDR
PAD
LATCH
DATA BUS
ANALOG ENABLE
(ADC)
DDR SEL
ANALOG
SWITCH
N-BUFFER
DR SEL
1
ALTERNATE ENABLE
0
DIGITAL ENABLE
ALTERNATE INPUT
48/186
DIODES
VSS
ST7263Bxx
I/O ports
9.3.3
Port C
Table 14.
Port C description
I/O
Port C
Alternate function
Input(1)
Output
Signal
Condition
PC0
with pull-up
push-pull
PC1
with pull-up
push-pull
SCI enable
PC2(2)
with pull-up
push-pull
USBOE =1
(MISCR)
1. Reset state
2. Not available on SO24
ALTERNATE
OUTPUT
0
P-BUFFER
DR
PULL-UP
LATCH
VDD
ALTERNATE ENABLE
DATA BUS
DDR
PAD
LATCH
DDR SEL
N-BUFFER
DR SEL
DIODES
ALTERNATE ENABLE
VSS
0
ALTERNATE INPUT
49/186
I/O ports
ST7263Bxx
9.3.4
Port D
Table 15.
Port D description
I/O
Port D
Input(1)
Alternate function
Output
Signal
Condition
PD0
without pull-up
push-pull
CH[3:0] = 1000
(ADCCSR)
PD1
without pull-up
push-pull
CH[3:0] = 1001
(ADCCSR)
PD2
without pull-up
push-pull
CH[3:0] = 1010
(ADCCSR)
PD3
without pull-up
push-pull
CH[3:0] = 1011
(ADCCSR)
PD4
with pull-up
push-pull
PD5
with pull-up
push-pull
PD6
with pull-up
push-pull
PD7
with pull-up
push-pull
1. Reset state
9.3.5
Register description
DATA registers (PxDR)
Address
Port A Data register (PADR): 0000h
Port B Data register (PBDR): 0002h
Port C Data register (PCDR): 0004h
Port D Data register (PDDR): 0006h
Reset value
Port A: 0000 0000 (00h)
Port B: 0000 0000 (00h)
Port C: 1111 x000 (FXh)
Port D: 0000 0000 (00h)
Note:
Note:
50/186
When using open-drain I/Os in output configuration, the value read in DR is the digital value
applied to the I/Opin.
ST7263Bxx
I/O ports
.
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Read/write
Table 16.
Address
(Hex.)
00
PADR
MSB
LSB
01
PADDR
MSB
LSB
02
PBDR
MSB
LSB
03
PBDDR
MSB
LSB
04
PCDR
MSB
LSB
05
PCDDR
MSB
LSB
06
PDDR
MSB
LSB
07
PDDDR
MSB
LSB
51/186
I/O ports
9.3.6
ST7263Bxx
Related documentation
AN1045: S/W implementation of I2C bus master
AN1048: Software LCD driver
52/186
ST7263Bxx
10
Miscellaneous register
Miscellaneous register
Miscellaneous register (MISCR)
Address: 0009h
Reset value: 0000 0000 (00h)
7
-
0
-
SMS
USBOE
MCO
Read/write
[7:3]
Reserved
53/186
On-chip peripherals
ST7263Bxx
11
On-chip peripherals
11.1
11.1.1
Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counters contents
before the T6 bit becomes cleared.
11.1.2
11.1.3
Main features
Programmable reset
Functional description
The counter value stored in the CR register (bits T6:T0), is decremented every 49,152
machine cycles, and the length of the timeout period can be programmed by the user in 64
increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle by driving low the reset
pin for tW(RSTL)out (see Table 72).
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This down counter is free-running: it counts down even if
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see Table 17):
54/186
The T5:T0 bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
ST7263Bxx
On-chip peripherals
Figure 26. Watchdog block diagram
RESET
T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
CLOCK DIVIDER
49152
fCPU
Table 17.
Note:
Max
FFh
393.216
Min
C0h
6.144
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
11.1.4
11.1.5
11.1.6
55/186
On-chip peripherals
ST7263Bxx
HALT instruction
If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes
an immediate reset generation if the Watchdog is activated (WDGA bit is set).
11.1.7
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
Before executing the HALT instruction, refresh the WDG counter, to avoid an
unexpected WDG reset immediately after waking up the microcontroller.
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
As the HALT instruction clears the I bit in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external
interrupt routine corresponding to the wakeup event (reset or external interrupt).
Interrupts
None.
56/186
ST7263Bxx
11.1.8
On-chip peripherals
Register description
Control register (CR)
Reset value: 0111 1111 (7Fh)
7
WDGA
T6
T5
T4
T3
T2
T1
T0
Read/write
Table 18.
Address Register
Label
(Hex.)
0Ch
WDGCR
Reset
value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
57/186
On-chip peripherals
ST7263Bxx
11.2
16-bit timer
11.2.1
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after a MCU reset as long as the timer
clock frequencies are not modified.
This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
11.2.2
Main features
External clock input (must be at least four times slower than the CPU clock speed) with
the choice of active edge
58/186
Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the
device pin out description.
When reading an input signal on a non-bonded pin, the value will always be 1.
ST7263Bxx
11.2.3
On-chip peripherals
Functional description
Counter
The main block of the Programmable Timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the
Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM
mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 24. The value in the counter register repeats every 131072, 262144 or 524288 CPU
clock cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
59/186
On-chip peripherals
ST7263Bxx
MCU-PERIPHERAL INTERFACE
8 low
8
8
low
high
low
high
low
high
EXEDG
high
8-bit
buffer
low
8 high
16
1/2
1/4
1/8
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
COUNTER
REGISTER
ALTERNATE
COUNTER
EXTCLK
pin
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16
REGISTER
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
6
EDGE DETECT
CIRCUIT1
ICAP1
pin
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
OCMP1
pin
LATCH2
OCMP2
pin
(Control/Status register)
CSR
CC1
(See note)
TIMER INTERRUPT
1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device
Interrupt Vector Table).
60/186
ST7263Bxx
On-chip peripherals
Figure 28. 16-bit read sequence (from either the Counter register or the Alternate
Counter register)
Beginning of the sequence
At t0
Read
MS Byte
LS Byte
is buffered
Other
instructions
Read
At t0 +t LS Byte
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS Byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
Note:
1.
2.
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a Reset).
External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
61/186
On-chip peripherals
ST7263Bxx
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 29. Counter timing diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
0001
0002
0003
1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
FFFC
FFFD
0000
0001
1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
FFFC
FFFD
0000
1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
62/186
ST7263Bxx
On-chip peripherals
Input Capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the
free running counter after a transition is detected on the ICAPi pin (see Figure 32).
Table 19.
IC/R register
ICiR
MS Byte
LS Byte
ICiHR
ICiLR
2.
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
3.
Set the ICIE bit to generate an interrupt after an input capture coming from either
the ICAP1 pin or the ICAP2 pin
b)
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without
interrupt if this configuration is available).
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 33).
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
63/186
On-chip peripherals
Note:
ST7263Bxx
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The two input capture functions can be used together even if the timer also uses the two
output compare functions.
In One Pulse mode and PWM mode only input Capture 2 can be used.
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
Figure 32. Input Capture block diagram
ICAP1
pin
ICAP2
pin
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status register) SR
IC2R register
IC1R register
ICF1
ICF2
CC1
CC0
FF02
FF03
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
64/186
16-BIT
COUNTER REGISTER
IEDG2
ST7263Bxx
On-chip peripherals
Output Compare
In this section, the index, i, may be 1 or 2 because there are two output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the output Compare register and the free running counter,
the output compare function:
Two 16-bit registers output Compare register 1 (OC1R) and output Compare register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle.
Table 20.
OC/R register
MS Byte
LS Byte
OCiHR
OCiLR
OCiR
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
To use the output compare function, select the following in the CR2 register:
1.
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
2.
3.
Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
b)
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
OCiR =
t * fCPU
PRESC
Where:
t = Output compare period (in seconds)
65/186
On-chip peripherals
ST7263Bxx
PRESC= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 24)
OCiR = t * fEXT
Where:
t = Output compare period (in seconds)
2.
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
Note:
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 35 on page 67 for an example with fCPU/2 and
Figure 36 on page 67 for an example with fCPU/4). This behavior is the same in OPM or
PWM mode.
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
Forced Compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both One Pulse mode and PWM mode.
66/186
ST7263Bxx
On-chip peripherals
Figure 34. Output Compare block diagram
OC1E OC2E
CC1
CC0
16-bit
OCIE
OLVL1
16-bit
Latch
1
Latch
2
OC1R register
OCF1
OCF2
OCMP1
Pin
OCMP2
Pin
OC2R register
(Status register) SR
2ECF 2ED0
2ECF 2ED0
67/186
On-chip peripherals
ST7263Bxx
Load the OC1R register with the value corresponding to the length of the pulse (see the
formula in the opposite column).
2.
3.
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
Set the OC1E bit, the OCMP1 pin is then dedicated to the output Compare 1
function.
When
event occurs
on ICAP1
ICR1 = Counter
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
68/186
1.
2.
ST7263Bxx
On-chip peripherals
The OC1R register value required for a specific timing application can be calculated using
the following formula:
t * fCPU
OCiR Value =
-5
PRESC
Where:
t = Pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC=
Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 24)
Where:
t = Pulse period (in seconds)
fEXT = External timer clock frequency (in hertz)
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (See Figure 38).
Note:
The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate
an output Compare interrupt.
When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the One Pulse mode.
Figure 38. One Pulse mode timing example
COUNTER
2ED3
01F8
IC1R
01F8
FFFC FFFD
2ED3
ICAP1
OCMP1
OLVL2
OLVL1
OLVL2
compare1
69/186
On-chip peripherals
ST7263Bxx
Figure 39. Pulse Width modulation mode timing with 2 output Compare functions
OLVL2
OCMP1
compare2
OLVL1
compare1
34E2
FFFC
OLVL2
compare2
On timers with only one output Compare register, a fixed frequency PWM signal can be
generated using the output compare and the counter overflow to define the pulse length.
Load the OC2R register with the value corresponding to the period of the signal using
the formula in the opposite column.
2.
Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.
3.
4.
70/186
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register.
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
ST7263Bxx
On-chip peripherals
Figure 40. Pulse width modulation cycle
Pulse Width Modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using
the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t = Signal or pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC=
Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 24)
Where:
t = Signal or pulse period (in seconds)
fEXT = External timer clock frequency (in hertz)
The output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 39)
Note:
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
71/186
On-chip peripherals
11.2.4
ST7263Bxx
Table 21.
Mode
11.2.5
Description
WAIT
No effect on 16-bit Timer. Timer interrupts cause the device to exit from Wait mode.
HALT
Interrupts
The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts
chapter). These events generate an interrupt if the corresponding Enable Control Bit is set
and the interrupt mask in the CC register is reset (RIM instruction).
Table 22.
Interrupts
Interrupt Event
Event flag
ICF1
ICF2
OCF1
Enable Control
bit
Exit from
Wait
Exit from
Halt
Yes
No
ICIE
OCIE
Output Compare 2 event (not available in PWM mode)
OCF2
11.2.6
TOF
TOIE
Input
Capture 1
Input Capture 2
Output
Compare 1
Output
Compare 2
Yes
Yes
Yes
Yes
Not recommended(3)
72/186
Partially(2)
No
No
ST7263Bxx
11.2.7
On-chip peripherals
Register description
Each Timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
0
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
Read/write
73/186
On-chip peripherals
ST7263Bxx
0
OC2E
OPM
PWM
CC1
CC0
IEDG2
EXEDG
Read/write
[3:2]
74/186
ST7263Bxx
On-chip peripherals
Table 24.
CC1
fCPU / 4
CC0
0
fCPU / 2
fCPU / 8
0
1
ICF1
OCF1
TOF
ICF2
OCF2
Read only
0
TIMD
Read/write
75/186
On-chip peripherals
ST7263Bxx
MSB
LSB
Read only
MSB
LSB
Read only
MSB
LSB
Read/write
76/186
ST7263Bxx
On-chip peripherals
MSB
LSB
Read/write
MSB
LSB
Read/write
MSB
LSB
Read/write
MSB
LSB
Read only
MSB
LSB
Read only
77/186
On-chip peripherals
ST7263Bxx
MSB
LSB
Read only
MSB
LSB
Read only
MSB
LSB
Read only
MSB
LSB
Read only
78/186
ST7263Bxx
Table 25.
Address
On-chip peripherals
16-bit timer register map and reset values
Register
label
11
CR2
Reset value
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
12
CR1
Reset value
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
13
CSR
Reset value
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
TIMD
0
0
0
0
0
14
IC1HR
Reset value
MSB
LSB
15
IC1LR
Reset value
MSB
LSB
16
OC1HR
Reset value
MSB
1
LSB
0
17
OC1LR
Reset value
MSB
0
LSB
0
18
CHR
Reset value
MSB
1
LSB
1
19
CLR
Reset value
MSB
1
LSB
0
1A
ACHR
Reset value
MSB
1
LSB
1
1B
ACLR
Reset value
MSB
1
LSB
0
1C
IC2HR
Reset value
MSB
LSB
1D
IC2LR
Reset value
MSB
LSB
1E
OC2HR
Reset value
MSB
1
LSB
0
1F
OC2LR
Reset value
MSB
0
LSB
0
(Hex.)
79/186
On-chip peripherals
ST7263Bxx
11.3
11.3.1
Introduction
The Serial Communications Interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.
11.3.2
Main features
Receive buffer full, Transmit buffer empty and End of Transmission flags
11.3.3
Parity control:
Transmits parity bit
Checks parity of received data byte
General description
The interface is externally connected to another device by two pins (see Figure 42):
80/186
TDO: Transmit Data output. When the transmitter and the receiver are disabled, the
output pin returns to its I/O port configuration. When the transmitter and/or the receiver
are enabled and nothing is to be transmitted, the TDO pin is at high level.
RDI: Receive Data input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
ST7263Bxx
On-chip peripherals
Through these pins, serial data is transmitted and received as frames comprising:
A start bit
Write
Read
(DATA REGISTER) DR
CR1
R8
TRANSMIT
WAKE
UP
CONTROL
UNIT
T8
SCID
M WAKE PCE PS
PIE
RECEIVER
CLOCK
RECEIVER
CONTROL
CR2
SR
ILIE
TE
RE RWU SBK
NF
FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
fCPU
CONTROL
/16
/PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
BAUD RATE GENERATOR
81/186
On-chip peripherals
11.3.4
ST7263Bxx
Functional description
The block diagram of the Serial Control Interface, is shown in Figure 41 It contains 6
dedicated registers:
Refer to the register descriptions in Section 11.3.7 for the definitions of each bit.
Data Frame
Start
Bit
Bit0
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Start
Bit
Break Frame
Extra
1
Possible
Parity
Bit
Data Frame
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Bit0
Bit8
Idle Frame
Start
Bit
Bit7
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Next
Start
Bit
Idle Frame
Start
Bit
Break Frame
Extra Start
Bit
1
Start
Bit
ST7263Bxx
On-chip peripherals
Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
Character Transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 41).
Procedure
1.
2.
Select the desired baud rate using the SCIBRR and the SCIETPR registers.
3.
Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame
as first transmission.
4.
Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1.
2.
The next data can be written in the SCIDR register without overwriting the previous
data.
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CC register.
When a transmission is taking place, a write instruction to the SCIDR register stores the
data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit or after the break frame) the TC
bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CC
register.
Clearing the TC bit is performed by the following software sequence:
Note:
1.
2.
The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break frame length
depends on the M bit (see Figure 42).
83/186
On-chip peripherals
ST7263Bxx
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the
recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
Note:
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in
the SCIDR.
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see Figure 41).
Procedure
1.
2.
Select the desired baud rate using the SCIBRR and the SCIERPR registers.
3.
Set the RE bit, this enables the receiver which begins searching for a start bit.
The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register.
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
1.
2.
The RDRF bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When a idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the ILIE bit is set and the I bit is cleared in the CC register.
Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
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ST7263Bxx
On-chip peripherals
When a overrun error occurs:
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit
detection, the NF flag is set on the basis of an algorithm combining both valid edge
detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set
during start bit reception, there should be a valid edge detection as well as three valid
samples.
When noise is detected in a frame:
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read
operation.
During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid
frame is received.
Note:
If the application Start Bit is not long enough to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also Section .
Framing error
A framing error is detected when:
The stop bit is not recognized on reception at the expected time, following either a
de-synchronization or excessive noise.
A break is received.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
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On-chip peripherals
ST7263Bxx
Tx =
fCPU
Rx =
(16*PR)*TR
fCPU
(16*PR)*RR
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If fCPU is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and
receive baud rates are 38400 baud.
Note:
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Receiver wakes-up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
Receiver wakes-up by Address Mark detection when it received a 1 as the most significant
bit of a word, thus indicating that the message is an address. The reception of this particular
word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the
receiver to receive this word normally and to use it as an address word.
Caution:
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In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the
read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before
the write operation, the RWU bit will be set again by this write operation. Consequently the
address byte is lost and the SCI is not woken up from Mute mode.
ST7263Bxx
On-chip peripherals
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 26.
Table 26.
Frame formats(1)
M bit
PCE bit
SCI frame
Note:
In case of wakeup by an address mark, the MSB bit of the data is taken into account and not
the parity bit
Even parity: the parity bit is calculated to obtain an even number of 1s inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an odd number of 1s inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data
register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte
has an even number of 1s if even parity is selected (PS=0) or an odd number of 1s if odd
parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register
and an interrupt is generated if PIE is set in the SCICR1 register.
The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64s), then the 8th, 9th and 10th samples will be at 28s, 32 s & 36 s
respectively (the first sample starting ideally at 0 s). But if the falling edge of the internal
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On-chip peripherals
ST7263Bxx
clock occurs just before the pin value changes, the samples would then be out of sync by
~4 s. This means the entire bit length must be at least 40 s (36 s for the 10th sample + 4
s for synchronization with the internal sampling clock).
DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the
transmitter is transmitting at a different baud rate).
DREC: Deviation of the local oscillator of the receiver: This deviation can occur during
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
DTCL: Deviation due to the transmission line (generally due to the transceivers)
All the deviations of the system should be added and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75%
A valid falling edge is not detected. A falling edge is considered to be valid if the 3
consecutive samples before the falling edge occurs are detected as '1' and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a 1.
2.
Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag
getting set.
Data bits
The noise flag (NF) is set during normal data bit reception if the following condition occurs:
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not
the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag getting set.
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ST7263Bxx
On-chip peripherals
Figure 43. Bit sampling in reception mode
RDI LINE
sampled values
Sample
clock
10
11
12
13
14
15
16
6/16
7/16
7/16
One bit time
11.3.5
Mode
Description
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
WAIT
11.3.6
Interrupts
Table 28.
Interrupts
Interrupt event
Event flag
Enable
Control
bit
Exit
from
Wait
Exit
from
Halt
TDRE
TIE
Yes
No
Transmission Complete
TC
TCIE
Yes
No
RDRF
Yes
No
Yes
No
RIE
Overrun Error Detected
OR
IDLE
ILIE
Yes
No
Parity Error
PE
PIE
Yes
No
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
89/186
On-chip peripherals
11.3.7
ST7263Bxx
Register description
Status register (SCISR)
Reset value: 1100 0000 (C0h)
7
TDRE
0
TC
RDRF
IDLE
OR
NF
FE
PE
Read only
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ST7263Bxx
On-chip peripherals
3 OR Overrun error.
This bit is set by hardware when the word currently being received in the shift
register is ready to be transferred into the RDR register while RDRF=1. An interrupt
is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will not be lost but the shift register
will be overwritten.
2 NF Noise flag.
This bit is set by hardware when noise is detected on a received frame. It is cleared
by a software sequence (an access to the SCISR register followed by a read to the
SCIDR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt.
1 FE Framing error.
This bit is set by hardware when a de-synchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt. If the word currently being
transferred causes both frame error and overrun error, it will be transferred
and only the OR bit will be set.
0 PE Parity error.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared
by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error
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On-chip peripherals
ST7263Bxx
0
T8
SCID
WAKE
PCE
PS
PIE
Read/write
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ST7263Bxx
On-chip peripherals
0
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Read/write
93/186
On-chip peripherals
ST7263Bxx
2 RE Receiver enable.
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
1 RWU Receiver wakeup.
This bit determines if the SCI is in mute mode or not. It is set and cleared by
software and can be cleared by hardware when a wakeup sequence is
recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
Note: Before selecting Mute mode (setting the RWU bit), the SCI must
receive some data first, otherwise it cannot function in Mute mode with
wakeup by idle line detection.
0 SBK Send break.
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to 1 and then to 0, the transmitter will send a
BREAK word at the end of the current word.
0
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Read/write
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 41).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 41).
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ST7263Bxx
On-chip peripherals
0
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
Read/write
Table 29.
Table 30.
Table 31.
Prescaling factors
PR prescaling factor
SCP1
SCP0
13
TR dividing factors
TR dividing factor
SCT2
SCT1
SCT0
16
32
64
128
RR dividing factor
SCR2
SCR1
SCR0
RR dividing factor
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On-chip peripherals
Table 31.
Table 32.
96/186
ST7263Bxx
RR dividing factor
RR dividing factor
SCR2
SCR1
SCR0
16
32
64
128
Address
(Hex.)
Register
label
20
SCISR
Reset value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
21
SCIDR
Reset value
DR7
x
DR6
x
DR5
x
DR4
x
DR3
x
DR2
x
DR1
x
DR0
x
22
SCIBRR
Reset value
SCP1
0
SCP0
0
SCT2
x
SCT1
x
SCT0
x
SCR2
x
SCR1
x
SCR0
x
23
SCICR1
Reset value
R8
x
T8
x
SCID
0
M
x
WAKE
x
PCE
0
PS
0
PIE
0
24
SCICR2
Reset value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
ST7263Bxx
On-chip peripherals
11.4
11.4.1
Introduction
The USB Interface implements a low-speed function interface between the USB and the
ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3
voltage regulator, SIE and DMA. No external components are needed apart from the
external pull-up on USBDM for low speed recognition by the USB host. The use of DMA
architecture allows the endpoint definition to be completely flexible. Endpoints can be
configured by software as in or out.
11.4.2
11.4.3
Main features
Two or Three Endpoints (including default one) depending on the device (see device
feature list and register map)
Functional description
The block diagram in Figure 44, gives an overview of the USB interface hardware.
For general information on the USB, refer to the Universal Serial Bus Specifications
document available at http//:www.usb.org.
Endpoints
The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how
many bytes need to be transmitted.
DMA
When a token for a valid Endpoint is recognized by the USB interface, the related data
transfer takes place, using DMA. At the end of the transaction, an interrupt is generated.
Interrupts
By reading the Interrupt Status register, application software can know which USB event has
occurred.
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On-chip peripherals
ST7263Bxx
ENDPOINT
CPU
REGISTERS
USBDM
Transceiver
SIE
Address,
DMA
USBDP
data buses
and interrupts
USBVCC
3.3 V
Voltage
Regulator
INTERRUPT
REGISTERS
MEMORY
USBGND
11.4.4
Register description
DMA Address register (DMAR)
Reset value: undefined
7
DA15
0
DA14
DA13
DA12
DA11
DA10
DA9
DA8
Read.write
Software must write the start address of the DMA memory area whose most significant bits
are given by DA15-DA6. The remaining 6 address bits are set by hardware. See the
description of the IDR register and Figure 45.
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ST7263Bxx
On-chip peripherals
0
DA6
EP1
EP0
CNT3
CNT2
CNT1
CNT0
Read.write
Endpoint 1 TX
Endpoint 1 RX
Endpoint 0 TX
001000
000111
Endpoint 0 RX
DA15-6,000000
000000
99/186
On-chip peripherals
ST7263Bxx
TP3
TP2
RX_
SEZ
RXD
Read only
Table 33.
100/186
TP bit definition
TP3
TP2
PID Name
OUT
IN
SETUP
ST7263Bxx
On-chip peripherals
0
DOVR
CTR
ERR
IOVR
ESUSP
RESET
SOF
Read.write
When an interrupt occurs these bits are set by hardware. Software must read them to
determine the interrupt type and clear them after servicing.
Note:
101/186
On-chip peripherals
ST7263Bxx
Note:
To avoid spurious clearing of some bits, it is recommended to clear them using a load
instruction where all bits which must not be altered are set, and all bits to be cleared are
reset. Avoid read-modify-write instructions like AND, XOR.
0
DOVRM
CTRM
ERRM
IOVRM
Read.write
102/186
ESUSPM
RESETM
SOFM
ST7263Bxx
On-chip peripherals
0
0
RESUME
PDWN
FSUSP
FRES
Read/write
0
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Read.write
103/186
On-chip peripherals
ST7263Bxx
Endpoint 2 and the EP2RA register are not available on some devices (see device feature
list and register map).
Reset value: 0000 xxxx (0xh)
7
ST_
OUT
DTOG
_TX
STAT
_TX1
STAT
_TX0
TBC3
TBC2
TBC1
TBC0
Read.write
Table 34.
104/186
STAT_TX1
STAT_TX0
Meaning
ST7263Bxx
On-chip peripherals
Endpoint 2 and the EP2RB register are not available on some devices (see device feature
list and register map).
Reset value: 0000 xxxx (0xh)
7
0
DTOG
_RX
CTRL
STAT
_RX1
STAT
_RX0
EA3
EA2
EA1
EA0
Read.write
7 CTRL Control.
This bit should be 0.
Note: If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a
control Endpoint, but it is possible to have more than one control Endpoint).
6 DTOG_RX Data toggle, for reception transfers.
It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next
data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a
control transfer (SETUP transactions start always with DATA0 PID). The receiver
toggles DTOG_RX only if it receives a correct data packet and the packets data
PID matches the receiver sequence bit.
[5:4] STAT_RX [1:0] Status bits, for reception transfers.
These bits contain the information about the endpoint status, which are listed in
Table 35.
These bits are written by software. Hardware sets the STAT_RX bits to NAK when a
correct transfer has occurred (CTR=1) related to an OUT or SETUP transaction
addressed to this endpoint, so the software has the time to elaborate the received
data before acknowledging a new transaction.
[3:0] EA[3:0] Endpoint address.
Software must write in this field the 4-bit address used to identify the transactions
directed to this endpoint. Usually EP1RB contains 0001 and EP2RB contains
0010.
Table 35.
STAT_RX1
STAT_RX0
Meaning
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On-chip peripherals
ST7263Bxx
0
DTOG
RX
STAT
RX1
STAT
RX0
Read.write
7 Forced by hardware to 1.
[6:4] Refer to the EPnRB register for a description of these bits.
[3:0] Forced by hardware to 0.
11.4.5
Programming considerations
The interaction between the USB interface and the application program is described below.
Apart from system reset, action is always initiated by the USB interface, driven by one of the
USB events associated with the Interrupt Status register (ISTR) bits.
Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of
DMA buffers). Refer the paragraph titled initializing the DMA Buffers.
2.
Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and
endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint
Initialization.
3.
When addresses are received through this channel, update the content of the DADDR.
4.
If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB
register.
Endpoint Initialization
To be ready to receive, set STAT_RX to VALID (11b) in EP0RB to enable reception.
To be ready to transmit:
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1.
2.
In register EPnRA, specify the number of bytes to be transmitted in the TBC field
3.
Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA.
ST7263Bxx
Note:
On-chip peripherals
Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB
(respectively) must not be modified by software, as the hardware can change their value on
the fly.
When the operation is completed, they can be accessed again to enable a new operation.
Interrupt handling
Start of Frame (SOF)
The interrupt service routine may monitor the SOF events for a 1 ms synchronization event
to the USB bus. This interrupt is generated at the end of a resume sequence and can also
be used to detect this event.
USB Reset (RESET)
When this event occurs, the DADDR register is reset, and communication is disabled in all
endpoint registers (the USB interface will not respond to any packet). Software is
responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the
STAT_RX bits in the EP0RB register to VALID.
Suspend (SUSP)
The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend
request. The software should set the USB interface to suspend mode and execute an ST7
HALT instruction to meet the USB-specified power constraints.
End Suspend (ESUSP)
The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7
automatically terminates Halt mode.
Correct Transfer (CTR)
Table 36.
Address
1.
When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to
NAK. Every valid endpoint is NAKed until software clears the CTR bit in the ISTR
register, independently of the endpoint number addressed by the transfer which
generated the CTR interrupt. If the event triggering the CTR interrupt is a SETUP
transaction, both STAT_TX and STAT_RX are set to NAK.
2.
Read the PIDR to obtain the token and the IDR to get the endpoint number related to
the last transfer. When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register
and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR
register is cleared.
3.
25
PIDR
Reset
value
TP3
x
TP2
x
0
0
0
0
0
0
RX_SEZ
0
RXD
0
0
0
26
DMAR
Reset
value
DA15
x
DA14
x
DA13
x
DA12
x
DA11
x
DA10
x
DA9
x
DA8
x
(Hex.)
107/186
On-chip peripherals
Table 36.
Address
ST7263Bxx
27
IDR
Reset
value
DA7
x
DA6
x
EP1
x
EP0
x
CNT3
0
CNT2
0
CNT1
0
CNT0
0
28
ISTR
Reset
value
SUSP
0
DOVR
0
CTR
0
ERR
0
IOVR
0
ESUSP
0
RESET
0
SOF
0
29
IMR
Reset
value
SUSPM
0
DOVRM
0
CTRM
0
ERRM
0
IOVRM
0
ESUSP
M
0
RESETM
0
SOFM
0
2A
CTLR
Reset
value
0
0
0
0
0
0
0
0
RESUM
E
0
PDWN
1
FSUSP
1
FRES
0
2B
DADDR
Reset
value
0
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
2C
EP0RA
Reset
value
TBC3
x
TBC2
x
TBC1
x
TBC0
x
2D
EP0RB
Reset
value
0
0
0
0
0
0
0
0
2E
EP1RA
Reset
value
TBC3
x
TBC2
x
TBC1
x
TBC0
x
2F
EP1RB
Reset
value
EA3
x
EA2
x
EA1
x
EA0
x
30
EP2RA
Reset
value
TBC3
x
TBC2
x
TBC1
x
TBC0
x
31
EP2RB
Reset
value
EA3
x
EA2
x
EA1
x
EA0
x
(Hex.)
108/186
DTOG_RX
0
STAT_RX
1
0
STAT_RX
0
0
DTOG_RX
0
STAT_RX
1
0
STAT_RX
0
0
DTOG_RX
0
STAT_RX
1
0
STAT_RX
0
0
ST7263Bxx
On-chip peripherals
11.5
IC bus interface
11.5.1
Introduction
The IC bus interface serves as an interface between the microcontroller and the serial IC
bus. It provides both multimaster and slave functions, and controls all IC bus-specific
sequencing, protocol, arbitration and timing. It supports fast IC mode (400 kHz).
11.5.2
Main features
Multimaster capability
7-bit addressing
Transmitter/receiver flag
IC master features
Clock generation
Transmitter/Receiver Flag
IC slave features
11.5.3
Transmitter/Receiver flag
General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa, using either an interrupt or polled handshake. The interrupts are
enabled or disabled by software. The interface is connected to the IC bus by a data pin
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard IC bus and a
Fast IC bus. This selection is made by software.
109/186
On-chip peripherals
ST7263Bxx
Mode selection
The interface can operate in the four following modes:
Slave transmitter/receiver
Master transmitter/receiver
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the
start condition is the address byte; it is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to Figure 46.
Figure 46. IC bus protocol
SDA
ACK
MSB
SCL
1
START
CONDITION
9
STOP
CONDITION
VR02119B
ST7263Bxx
On-chip peripherals
When the IC cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 47. IC interface block diagram
DATA REGISTER (DR)
SDA or SDAI
DATA CONTROL
DATA SHIFT REGISTER
COMPARATOR
CLOCK CONTROL
SCL or SCLI
CONTROL LOGIC
INTERRUPT
11.5.4
Functional description
Refer to the CR, SR1 and SR2 registers in Section 11.5.7. for the bit definitions.
By default the IC interface operates in Slave mode (M/SL bit is cleared) except when it
initiates a transmit or receive sequence.
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
Address not matched: the interface ignores it and waits for another Start condition.
Address matched
The interface generates in sequence:
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 48 Transfer sequencing EV1).
Next, software must read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
Slave receiver
111/186
On-chip peripherals
ST7263Bxx
Following the address reception and after SR1 register has been read, the slave receives
bytes from the SDA line into the DR register via the internal shift register. After each byte the
interface generates in sequence:
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 48 Transfer sequencing EV2).
Slave transmitter
Following the address reception and after the SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 48 Transfer sequencing EV3).
When the acknowledge pulse is received, the EVF and BTF bits are set by hardware with an
interrupt if the ITE bit is set.
Closing Slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets EVF and STOPF bits with an interrupt if the ITE bit
is set.
Then the interface waits for a read of the SR2 register (see Figure 48 Transfer sequencing
EV4).
Error cases
Note:
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop, then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start, then the interface discards the data and waits for the next slave address
on the bus.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
In case of errors, SCL line is not held low; however, the SDA line can remain low if the last
bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF flags
that are set at the same time. It is then necessary to release both lines by software.
How to Release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
Master mode
To switch from default Slave mode to Master mode, a Start condition generation is needed.
Start condition
112/186
ST7263Bxx
On-chip peripherals
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if
the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address byte, holding the SCL line low (see Figure 48 Transfer sequencing
EV5).
Slave address transmission
Then the slave address byte is sent to the SDA line via the internal shift register.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set), the
EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see Figure 48 Transfer sequencing
EV6).
Next the master must enter Receiver or Transmitter mode.
Master receiver
Following the address transmission and after the SR1 and CR registers have been
accessed, the master receives bytes from the SDA line into the DR register via the internal
shift register. After each byte the interface generates in sequence:
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 48 Transfer sequencing EV7).
To close the communication: before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
Note:
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends
bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 48 Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets, EVF and BTF bits with an interrupt
if the ITE bit is set.
To close the communication: after writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
Error cases
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first or second pulse of
113/186
On-chip peripherals
ST7263Bxx
Note:
114/186
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
In all these cases, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF
flags that are set at the same time. It is then necessary to release both lines by software.
ST7263Bxx
On-chip peripherals
Figure 48. Transfer sequencing
Table 37. Slave receiver
S
Addres
s
Data1
Data2
DataN
.....
EV
1
Table 38.
S
EV
2
EV
2
EV
2
EV
4
Slave Transmitter
Addres
A
s
Data1
Data2
DataN
N
A
.....
EV EV
1
3
Table 39.
EV
3
EV3
-1
EV
4
Master receiver
Addres
s
EV
3
Data1
Data2
DataN
N
A
.....
EV
5
EV
6
Table 40.
EV
7
EV
7
Master Transmitter
Addres
A
s
EV
7
Data1
Data2
DataN
.....
EV
5
EV EV
6
8
EV
8
EV
8
EV
8
1. Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.
EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR
register.
EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR
register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared
by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).
Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.
EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.
EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register
(for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR
register.
EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR
register.
115/186
On-chip peripherals
11.5.5
ST7263Bxx
Mode
11.5.6
Description
WAIT
No effect on IC interface.
IC interrupts cause the device to exit from Wait mode.
HALT
Interrupts
Figure 49. Event flags and interrupt generation
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
ITE
INTERRUPT
EVF
(1)
1. EVF can also be set by EV6 or an error from the SR2 register.
Table 42.
Interrupts
Exit
from
Wait
Exit
from
Halt
BTF
Yes
No
ADSL
Yes
No
SB
Yes
No
AF
Yes
No
Interrupt event
End of Byte Transfer Event
Address Matched Event (Slave mode)
Event
flag
Enable
control
bit
ITE
STOPF
Yes
No
ARLO
Yes
No
BERR
Yes
No
The IC interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the
CC register is reset (RIM instruction).
116/186
ST7263Bxx
11.5.7
On-chip peripherals
Register description
IC Control register (CR)
Reset value: 0000 0000 (00h)
7
0
0
0
PE
ENGC
START
ACK
STOP
ITE
Read/write
117/186
On-chip peripherals
ST7263Bxx
118/186
ST7263Bxx
On-chip peripherals
0
0
TRA
BUSY
BTF
ADSL
M/SL
SB
Read only
119/186
On-chip peripherals
ST7263Bxx
120/186
ST7263Bxx
On-chip peripherals
0
0
AF
STOPF
ARLO
BERR
GCAL
Read only
121/186
On-chip peripherals
ST7263Bxx
0
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Read/write
122/186
ST7263Bxx
On-chip peripherals
Transmitter mode: byte transmission start automatically when the software writes in the
DR register.
Receiver mode: the first data byte is received automatically in the DR register using the
least significant bit of the address. The following data bytes are then received one by
one after reading the DR register.
0
D6
D5
D4
D3
D2
D1
D0
Read/write
0
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Read/write
123/186
On-chip peripherals
Table 43.
ST7263Bxx
IC register map
Address Register
name
(Hex.)
Note:
124/186
39
DR
DR7 .. DR0
3B
OAR
ADD7 .. ADD0
3C
CCR
3D
SR2
3E
SR1
3F
CR
FM/SM
EVF
CC6 .. CC0
AF
STOPF
ARLO
BERR
GCAL
TRA
BUSY
BTF
ADSL
M/SL
SB
PE
ENGC
START
ACK
STOP
ITE
Refer to Section 16: Known limitations for information regarding a limitation on the alternate
function on pin PA2 (SCL).
ST7263Bxx
On-chip peripherals
11.6
11.6.1
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 16
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 8-bit Data register. The A/D converter is controlled
through a Control/Status register.
11.6.2
Main features
8-bit conversion
11.6.3
Functional description
Analog power supply
VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to
device pin out description) they are internally connected to the VDD and VSS pins.
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
See electrical characteristics section for more details.
125/186
On-chip peripherals
ST7263Bxx
COCO
ADON
fADC
DIV 4
CH3
CH2
CH1
CH0
ADCCSR
AIN0
HOLD CONTROL
AIN1
ANALOG
MUX
RADC
ANALOG TO DIGITAL
CONVERTER
CADC
AINx
ADCDR
D7
D6
D5
D4
D3
D2
D1
D0
While the ADC is on, these two phases are continuously repeated.
At the end of each conversion, the sample capacitor is kept loaded with the previous
measurement load. The advantage of this behavior is that it minimizes the current
consumption on the analog pin in case of single input channel measurement.
126/186
ST7263Bxx
On-chip peripherals
Software procedure
Refer to the control/status register (CSR) and data register (DR) in Section 11.6.6 for the bit
definitions and to Figure 51 for the timings.
ADC configuration
The total duration of the A/D conversion is 12 ADC clock periods (1/fADC=4/fCPU).
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the
I/O ports chapter. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the CSR register:
ADC conversion
In the CSR register:
Set the ADON bit to enable the A/D converter and to start the first conversion. From this
time on, the ADC performs a continuous conversion of the selected channel.
No interrupt is generated.
The result is in the DR register and remains valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO
bit and starts a new conversion.
Figure 51. ADC conversion timings
ADON
ADCCSR WRITE
OPERATION
tCONV
HOLD
CONTROL
tLOAD
11.6.4
Mode
Note:
Description
WAIT
HALT
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
127/186
On-chip peripherals
11.6.5
ST7263Bxx
Interrupts
None
11.6.6
Register description
Control/Status register (CSR)
Reset value: 0000 0000 (00h)
7
COCO
0
0
ADON
CH3
CH2
CH1
CH0
Read/write
Table 45.
Channel selection
Channel pin(1)
CH3(2)
CH2
CH1
CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
1. The number of pins AND the channel selection varies according to the device. Refer to the device pinout.
128/186
ST7263Bxx
On-chip peripherals
2. For SDIP/SO34 devices, the CH3 bit is always at 0. If, however, set to 1 on error, channel (11:8)
becomes enabled which may result in a higher and unnecessary level of consumption.
0
D6
D5
D4
D3
D2
D1
D0
Read only
Note:
Address Register
name
(Hex.)
0Ah
DR
0Bh
CSR
CH2
CH1
CH0
AD7 .. AD0
COCO
ADON
CH3
129/186
Instruction set
ST7263Bxx
12
Instruction set
12.1
Addressing modes
Addressing mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two sub-modes
called long and short:
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 48.
Destination/
source
Syntax
Pointer
address
Pointer size
(Hex.)
Length
(bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+ 0 (with X
register)
+ 1 (with Y
register)
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
+2
Short
Indirect
ld A,[$10]
00..FF
130/186
00..FF
byte
+2
ST7263Bxx
Table 48.
Instruction set
ST7 addressing mode overview (continued)
Mode
Syntax
Destination/
source
Pointer
address
Pointer size
(Hex.)
Length
(bytes)
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
Relative
Direct
jrne loop
PC128/PC+127(1)
Relative
Indirect
jrne [$10]
PC128/PC+127(1)
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt $10,#7,skip
00..FF
Bit
Indirect
Relative
btjt
[$10],#7,skip
00..FF
+1
00..FF
byte
+2
+1
00..FF
byte
+2
+2
00..FF
byte
+3
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
12.1.1
Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 49.
Inherent instructions
Inherent instruction
Function
NOP
No operation
TRAP
S/W interrupt
WFI
HALT
RET
Sub-routine Return
IRET
SIM
RIM
SCF
RCF
RSP
LD
Load
CLR
Clear
PUSH/POP
INC/DEC
Increment/Decrement
TNZ
131/186
Instruction set
Table 49.
12.1.2
ST7263Bxx
Inherent instructions (continued)
Inherent instruction
Function
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SWAP
Swap Nibbles
Immediate instructions
Immediate instructions have two bytes, the first byte contains the opcode, the second byte
contains the operand value.
Table 50.
12.1.3
Immediate instructions
Immediate instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
Logical Operations
Arithmetic Operations
Direct
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two sub-modes:
Direct (short)
The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF
addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
12.1.4
132/186
ST7263Bxx
Instruction set
Indexed (Short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE
addressing space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
12.1.5
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
12.1.6
Function
LD
Load
CP
Compare
Logical Operations
133/186
Instruction set
ST7263Bxx
Table 51.
12.1.7
Function
BCP
Bit Compare
Function
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
SWAP
Swap Nibbles
CALL, JP
Function
JRxx
Conditional Jump
CALLR
Call Relative
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
134/186
ST7263Bxx
12.2
Instruction set
Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 53.
Instruction groups
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
SIM
RIM
SCF
RCF
RSP
RET
Using a pre-byte
The instructions are described with one to four bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC-2End of previous instruction
PC-1Prebyte
PCOpcode
PC+1Additional word (0 to 2) according to the number of bytes required to compute the
effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
PIY 91Replace an instruction using X indirect indexed addressing mode by a Y one.
135/186
Instruction set
Table 54.
ST7263Bxx
Instructions
Mnemo
Description
Function/example
Dst
Src
ADC
A=A+M+C
ADD
Addition
A=A+M
AND
Logical And
A=A.M
BCP
tst (A . M)
BRES
Bit Reset
bres Byte, #3
BSET
Bit Set
bset Byte, #3
BTJF
BTJT
CALL
Call subroutine
CALLR
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
HALT
Halt
IRET
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
JRT
Jump relative
JRF
Never jump
JRIH
JRIL
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
136/186
reg, M
reg, M
reg, M
0
H
reg, M
jrf *
ST7263Bxx
Table 54.
Instruction set
Instructions (continued)
Mnemo
Description
Function/example
Dst
Src
JRUGT
Jump if (C + Z = 0)
Unsigned >
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
reg, M
M, reg
MUL
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
neg $10
reg, M
NOP
No Operation
OR
OR operation
A=A+M
POP
pop reg
reg
pop CC
CC
reg, CC
PUSH
push Y
RCF
C=0
RET
Subroutine Return
RIM
Enable Interrupts
I=0
RLC
reg, M
RRC
reg, M
RSP
S = Max allowed
SBC
A=A-M-C
SCF
C=1
SIM
Disable Interrupts
I=1
SLA
reg, M
SLL
reg, M
SRL
reg, M
SRA
reg, M
SUB
Subtraction
A=A-M
SWAP
SWAP nibbles
reg, M
TNZ
tnz lbl1
TRAP
S/W trap
S/W interrupt
WFI
XOR
Exclusive OR
1
1
1
0
A = A XOR M
137/186
Electrical characteristics
ST7263Bxx
13
Electrical characteristics
13.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
13.1.1
13.1.2
Typical values
Unless otherwise specified, typical data are based on TA=25 C, VDD=5 V. They are given
only as design guidelines and are not tested.
13.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
13.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 52.
Figure 52. Pin loading conditions
ST7 PIN
CL
13.1.5
138/186
ST7263Bxx
Electrical characteristics
Figure 53. Pin input voltage
ST7 PIN
VIN
13.2
Note:
Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an
unintentional internal reset is generated or an unexpected change of the I/O configuration
occurs (for example, due to a corrupted program counter). To guarantee safe operation, this
connection has to be done through a pull-up or pull-down resistor (typical: 4.7 k for
RESET, 10 k for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS
according to their reset configuration.
Table 55.
Voltage characteristics
Symbol
VDD - VSS
VIN(1)(2)
VESD(HBM)
Ratings
Supply voltage
Input voltage on true open drain pins
Maximum value
Unit
6.0
VSS-0.3 to 6.0
VSS-0.3 to VDD+0.3
Section 13.7.3
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7 k for RESET, 10 k for I/Os). Unused I/O pins must be tied in the same
way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected.
139/186
Electrical characteristics
Table 56.
ST7263Bxx
Current characteristics
Symbol
Ratings
Maximum value
IVDD
(1)
80
IVSS
80
25
50
IIO
IINJ(PIN)(2)(3)
- 25
Unit
mA
pin(4)(5)
IINJ(PIN)(2)
20
IINJ(PIN)(2)(3)
- 80
1. All power (VDD) and ground (VSS) lines must be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected.
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject
the current as far as possible from the analog input pins.
4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
5. True open drain I/O port pins do not accept positive injection.
Table 57.
Thermal characteristics
Symbol
TSTG
TJ
140/186
Ratings
Storage temperature range
Value
Unit
-65 to +150
ST7263Bxx
13.3
Electrical characteristics
Operating conditions
Table 58.
Symbol
Parameter
Conditions
Min
Typ
Max
5.5
VDD
VDDA
VDD
VDD
VSSA
VSS
VSS
Operating frequency
fOSC = 24 MHz
fCPU
fOSC = 12 MHz
70
TA
fCPU = 8 MHz
Unit
MHz
C
Figure 54. fCPU maximum operating frequency versus VDD supply voltage
fCPU [MHz]
FUNCTIONALITY
GUARANTEED
FROM 4 TO 5.5 V
4
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
2
0
2.5
13.3.1
3.0
3.5
4.5
Conditions
Min
Typ
Max
Unit
VIT+
3.4
3.7
4.0
VIT-
3.2
3.5
3.8
Vhyst
100
175
220
mV
VtPOR
0.5
50
V/ms
141/186
Electrical characteristics
13.4
ST7263Bxx
Table 60.
Symbol
Conditions
Typ
Max
Unit
10(1)
fCPU = 4 MHz
7.5
(2)(1)
fCPU = 8 MHz
10.5
13(2)
fCPU = 4 MHz
8(1)
fCPU = 8 MHz
8.5
11(2)
LVD disabled
25
40(1)
LVD disabled
100
120
LVD enabled
230
IDD(Ta) Supply current variation vs. temperature Constant VDD and fCPU
CPU Run mode
10
8
6
4
8MHz
4MHz
0
4
4.2
4.4
4.6
4.8
Vdd (V)
5.2
5.4
ai15593
142/186
mA
mA
A
A
ST7263Bxx
Electrical characteristics
Figure 56. Typ. IDD in Wait at fCPU= 4 and 8 MHz
Idd WFI (mA) at fcpu=4 and 8MHz
10
8MHz
4MHz
0
4
4.2
4.4
4.6
4.8
Vdd (V)
5.2
5.4
ai15594
13.5
General timings
Symbol
Parameter
tc(INST)
tv(IT)
Conditions
fCPU=8 MHz
fCPU=8 MHz
Min
Typ(1)
Max
Unit
12
tCPU
250
375
1500
ns
10
22
tCPU
1.25
2.75
Table 62.
Symbol
Parameter
Conditions
Unit
Min
Typ.
Max
fOSC
Oscillator frequency
24
MHz
fCPU
Operating frequency
MHz
2520
ns
tPORL
4096
tCPU
tWDGL
200
300
ns
tRL
143/186
Electrical characteristics
Table 62.
ST7263Bxx
tWDG
Watchdog timeout
tOXOV
tDDR
fCPU = 8MHz
from VDD = 0 to 4 V
49152
3145728
tCPU
6.144
393.216
ms
20(1)
30
40(1)
ms
100
(1)
ms
Table 63.
Symbol
Parameter
VOSCINH
VOSCINL
Conditions
Min
Typ
Max
0.7xVDD
VDD
VSS
0.3xVDD
15
tw(OSCINH)
OSCIN high or low time(1)
tw(OSCINL)
tr(OSCIN)
tf(OSCIN)
IL
see Figure 57
VSSVINVDD
15
1. Data based on design simulation and/or technology characteristics, not tested in production.
10%
VOSCINL
tf(OSCIN)
tw(OSCINH)
OSCOUT
tw(OSCINL)
EXTERNAL
CLOCK SOURCE
OSCIN
IL
ST72XXX
144/186
ns
time(1)
tr(OSCIN)
Unit
ST7263Bxx
Electrical characteristics
i2
fOSC
CL1
OSCIN
RESONATOR
CL2
RF
OSCOUT
ST72XXX
13.6
Memory characteristics
Subject to general operating conditions for fCPU, and TA unless otherwise specified.
Table 64.
Symbol
VRM
Conditions
Min
Typ
Max
Unit
2.0
Min
Typ
Max
Unit
Read mode
Write / Erase
mode, TA=25 C
11.4
12.6
30
mA
10
13.6.1
Flash memory
Operating Conditions: fCPU = 8 MHz.
Table 65.
Symbol
Conditions
fCPU
Operating frequency
MHz
VPP
Programming voltage
IPP
VPP current
Write / Erase
tVPP
tRET
Data retention
TA 5 5C
40
years
NRW
Write/erase cycles
TA=25 C
100
cycles
1. Refer to the Flash programming reference manual for the typical HDFlash programming and erase timing
values.
145/186
Electrical characteristics
ST7263Bxx
VPP
10k
ST72XXX
1. When the ICP mode is not required by the application, VPP pin must be tied to VSS.
146/186
VPP
PROGRAMMING
TOOL
ST72XXX
ST7263Bxx
13.7
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
13.7.1
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Unexpected reset
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 66.
Symbol
EMC characteristics
Parameter
Conditions
Level/
Class
VFESD
4B
VFFTB
4A
147/186
Electrical characteristics
13.7.2
ST7263Bxx
EMI characteristics
Symbol
SEMI
Parameter
Peak level(1)
Monitored
frequency
band
Conditions
Max vs.
[fOSC/fCPU]
Unit
16/8 MHz
0.1 MHz to
30 MHz
36
30 MHz to
130 MHz
39
130 MHz to
1 GHz
26
3.5
dBV
13.7.3
Symbol
VESD(HBM)
Ratings
Conditions
TA=+25 C
Maximum
value(1)
Unit
2000
148/186
ST7263Bxx
Electrical characteristics
Table 69.
Electrical sensitivities
Symbol
LU
Parameter
Static latchup class
Conditions
Class(1)
TA=+25 C
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
13.8
Table 70.
Symbol
General characteristics
Parameter
Conditions
Min
Typ
Max
Unit
VIL
0.3xVDD
VIH
0.7xVDD
6.0
VIN
Input voltage
VDD
Vhys
400
400
50
90
120
pF
25
25
VSSVINVDD
IL
IS
RPU
CIO
tf(IO)out
tr(IO)out
tw(IT)in
VIN=VSS
VDD=5 V
CL=50pF
Between 10% and 90%
VSS
V
mV
ns
tCPU
1. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 60). Static peak current value taken at a fixed VIN value,
based on design simulation and technology characteristics, not tested in production. This value depends on VDD and
temperature values.
2. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in
Figure 61).
3. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
ST72XXX
10k
10k
ST72XXX
149/186
Electrical characteristics
ST7263Bxx
70
60
50
40
30
20
10
0
4
4.2
4.4
4.6
4.8
Vdd (V)
5.2
5.4
ai15595
140
120
Rpu (KOhm)
100
80
60
40
20
0
4
4.2
4.4
4.6
4.8
5.2
5.4
Vdd (V)
ai15596
150/186
ST7263Bxx
Symbol
VOL(1)
Conditions
Max
IIO=+1.6 mA
0.4
IIO=+10 mA
1.3
Min
VDD=5 V
Table 71.
Electrical characteristics
Unit
IIO=+25 mA
1.5
IIO=-10 mA
VDD-1.3(3)
IIO=-1.6 mA
VDD-0.8
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
3. The minimum VOH value (with IIO=-10mA) depends on the chosen device type. For Flash devices, min = VDD - 1.3 V and
for ROM devices, min = VDD - 1.7 V
Vol_2mA (mV)
200
150
100
50
0
1
1.5
2.5
Iio (mA)
3.5
ai15597
151/186
Electrical characteristics
ST7263Bxx
1.6
1.4
Vol_10mA (V)
1.2
1
0.8
0.6
0.4
0.2
5
11
13
Iio (mA)
15
17
19
ai15598
Vol_25mA (V)
0.85
0.75
0.65
0.55
0.45
0.35
15
20
25
Iio (mA)
30
35
ai15599
152/186
ST7263Bxx
Electrical characteristics
Figure 66. VOL standard vs. VDD
Vol_2mA (mV) at Iio=2mA
130
Vol_2mA (mV)
125
120
115
110
105
4
4.2
4.4
4.6
4.8
Vdd (V)
5.2
5.4
ai17200
Vol_10mA (V)
0.57
0.56
0.55
0.54
0.53
0.52
0.51
0.5
4
4.2
4.4
4.6
4.8
Vdd (V)
5.2
5.4
ai17201
153/186
Electrical characteristics
ST7263Bxx
0.8
Vol_25mA (V)
0.75
0.7
0.65
0.6
4
4.2
4.4
4.6
4.8
Vdd (V)
5.2
5.4
ai17202
0.25
0.2
0.15
0.1
0.05
0
1
1.5
2.5
-Iio (mA)
3.5
ai17203
154/186
ST7263Bxx
Electrical characteristics
Figure 70. |VDD-VOH| @ VDD=5 V (high current)
|Vdd - Voh| (V) at Vdd=5V
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2
12
17
-Iio (mA)
ai17704
0.155
0.15
0.145
0.14
0.135
0.13
0.125
0.12
4
4.2
4.4
4.6
4.8
Vdd (V)
5.2
5.4
ai17705
155/186
Electrical characteristics
ST7263Bxx
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4
4.2
4.4
4.6
4.8
Vdd (V)
5.2
5.4
ai17706
13.9
Table 72.
Symbol
Parameter
VIH
VIL
Vhys
VOL
RON
(3)
Conditions
VDD=5 V
VIN=VSS
Min
Typ
Max
Unit
0.7xVDD
VDD
VSS
0.3xVD
400
IIO=5 mA
0.8
IIO=7.5 mA
1.3
50
80
100
6
30
1/fSFOSC
s
VDD=5 V
External pin or
internal reset sources
mV
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, not
tested in production.
4. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on RESET
pin with a duration below th(RSTL)in can be ignored.
156/186
ST7263Bxx
Electrical characteristics
Figure 73 and Figure 74 show the reset circuit which protects the device against parasitic
resets:
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level
on the RESET pin can go below the VIL max. level specified in Section Table 72.:
Asynchronous RESET pin. Otherwise the reset will not be taken into account internally.
Because the reset circuit is designed to allow the internal reset to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin is less than
the absolute maximum value specified for IINJ(RESET) in Section Table 56.: Current
characteristics.
In case a capacitive power supply is used, it is recommended to connect a 1 M pulldown resistor to the RESET pin to discharge any residual voltage induced by the
capacitive effect of the power supply (this will add 5 A to the power consumption of the
MCU).
Check that all recommendations related to ICCCLK and reset circuit have been
applied (see notes above).
b)
Check that the power supply is properly decoupled (100 nF + 10 F close to the
MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to
put a 100 nF + 1 M pull-down on the RESET pin.
c)
The capacitors connected on the RESET pin and also the power supply are key to
avoid any start-up marginality. In most cases, steps a) and b) above are sufficient
for a robust solution. Otherwise: replace 10 nF pull-down on the RESET pin with a
5 F to 20 F capacitor.
Required
Optional
EXTERNAL
RESET
ST72XXX
RON
INTERNAL
RESET
Filter
0.01F
1M
PULSE
GENERATOR
WATCHDOG
LVD RESET
157/186
Electrical characteristics
ST7263Bxx
VDD
ST72XXX
RON
USER
EXTERNAL
RESET
CIRCUIT
INTERNAL
RESET
Filter
0.01F
PULSE
GENERATOR
WATCHDOG
Required
13.10
13.10.1
USB interface
Operating conditions TA = 0 to +70 C, VDD = 4.0 to 5.25 V unless otherwise specified.
Table 73.
USB DC characteristics
Symbol
Parameter
Conditions
Min.
Max.
VDI
I(D+, D-)
0.2
VCM
0.8
2.5
VSE
0.8
2.0
0.3
(2)of
VOL
RL
VOH
RL(2) of 15 K to VSS
2.8
3.6
VDD=5 V
3.00
3.60
USBV
USBVCC: voltage
level(3)
1.5 K to 3.6 V
1. All the voltages are measured from the local ground potential.
2. RL is the load connected on the USB drivers.
3. To improve EMC performance (noise immunity), it is recommended to connect a 100nF capacitor to the USBVCC pin.
Differential
Data Lines
Crossover
points
VCRS
VSS
tf
158/186
tr
Unit
V(1)
ST7263Bxx
Electrical characteristics
Table 74.
Symbol
Parameter
Conditions
Driver characteristics:
tr
Rise time
tf
Fall Time
trfm
VCRS
CL=50 pF
(1)
CL=600 pF
(1)
CL=50 pF(1)
CL=600 pF
(1)
tr/tf
Min
Max
Unit
75
ns
300
ns
75
ns
300
ns
80
120
1.3
2.0
1. For more detailed information, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1).
13.10.2
SCI interface
Subject to general operating condition for VDD, fCPU, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (RDI and TDO).
Table 75.
SCI characteristics
Conditions
Symbol
Parameter
fCPU
fTx
fRx
Communication
frequency
Accuracy
vs.
standard
8 MHz ~0.16%
Standard
Baud
Rate
300
1200
2400
4800
9600
10400
19200
38400
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230.77
~38461.54
Prescaler
Conventional mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
Unit
Hz
159/186
Electrical characteristics
13.10.3
ST7263Bxx
I2C interface
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDAI and SCLI).
The ST7 I2C interface meets the requirements of the standard I2C communication protocol
described in the following table.
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Table 76.
Symbol
I2C characteristics
Parameter
Standard mode
I2C(1)
Min
Max
Min
Max
4.7
1.3
4.0
0.6
250
100
th(SDA)
0(3)
0(4)
900(3)
tr(SDA)
tr(SCL)
1000
20+0.1Cb
300
tf(SDA)
tf(SCL)
300
20+0.1Cb
300
th(STA)
4.0
0.6
tsu(STA)
4.7
0.6
4.0
0.6
tw(STO:S
4.7
1.3
400
400
pF
ns
TA)
Cb
160/186
ST7263Bxx
Electrical characteristics
Figure 76. Typical application with I2C bus and timing diagram
VDD
4.7k
VDD
4.7k
I2C BUS
100
SDAI
100
SCLI
ST72XXX
REPEATED START
START
tsu(STA)
tw(STO:STA)
START
SDA
tr(SDA)
tf(SDA)
tsu(SDA)
STOP
th(SDA)
SCK
th(STA)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
161/186
Electrical characteristics
ST7263Bxx
Table 77 gives the values to be written in the I2CCCR register to obtain the required I2C
SCL line frequency.
Table 77.
SCL frequency(1)(2)(3)(4)
I2CCCR Value
fCPU=4 MHz
fSCL
(kHz)
VDD = 4.1 V
fCPU=8 MHz
VDD = 5 V
VDD = 4.1 V
VDD = 5 V
NA
NA
NA
NA
83h
83
83h
83h
300
NA
NA
NA
NA
85h
85h
85h
85h
200
83h
83h
83h
83h
8Ah
89h
8Ah
8Ah
100
10h
10h
10h
10h
24h
23h
24h
23h
50
24h
24h
24h
24h
4Ch
4Ch
4Ch
4Ch
20
5Fh
5Fh
5Fh
5Fh
FFh
FFh
FFh
FFh
13.11
8-bit ADC
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Table 78.
Symbol
fADC
Conditions
Min
Typ(1)
Max
Unit
MHz
VSSA
VDDA
VAIN
Conversion range
RAIN
10(3)
CADC
pF
tSTAB
tADC
0(4)
s
fCPU=8 MHz,
fADC=2 MHz
6
4
8
1/fADC
1. Unless otherwise specified, typical data are based on TA=25C and VDD-VSS=5V.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than
10k). Data based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable
is then always valid.
162/186
ST7263Bxx
Electrical characteristics
Figure 77. Typical application with ADC
VDD
VT
0.6V
RAIN
AINx
VAIN
ADC
CIO
~2pF
VT
0.6V
IL
1A
VDD
VDDA
0.1F
VSSA
ST72XXX
Table 79.
Symbol
Parameter
Typ
Max(1)(2)
|ET|
1.5
|EO|
Offset error(3)
0.5
0.5
1.5
1.5
1.5
|EG|
|ED|
|EL|
Gain
Error(3)
Differential linearity
Integral linearity
error(3)
error(3)
1. Data based on characterization results over the whole temperature range, not tested in production.
2. Data based on characterization results, to guarantee 99.73% within max value from 0 to 70 C ( 3s
distribution limits).
3. ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is
a loss of 1 LSB for each 10K increase of the external analog source impedance. This effect on the ADC
accuracy has been observed under worst-case conditions for injection:
- negative injection
- injection to an input with analog capability, adjacent to the enabled Analog input
- at 5V VDD supply, and worst case temperature.
163/186
Electrical characteristics
ST7263Bxx
EG
255
254
253
1LSB
IDEAL
V
V
DDA
SSA
= ----------------------------------------256
(2)
ET
(3)
(1)
6
5
4
EO
EL
ED
2
1 LSBIDEAL
1
0
1
VSSA
Vin (LSBIDEAL)
1. (1) Example of an actual transfer curve; (2) The ideal transfer curve; (3) End point correlation line.
2. ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual transition and the first ideal one.
EG=Gain Error: deviation between the last ideal transition and the last actual one.
ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation
line.
164/186
ST7263Bxx
14
Package characteristics
Package characteristics
In order to meet environmental requirements, ST offers this device in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
165/186
Package characteristics
14.1
ST7263Bxx
Figure 79. 32-pin plastic dual in-line package, shrink 400-mil width, package outline
E
eC
A2 A
A1
E1
eA
eB
C
b
b1
Table 80.
32-pin plastic dual in-line package, shrink 400-mil width, package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
3.560
3.760
5.080
0.1400
0.1480
0.2000
A1
0.510
A2
3.050
3.560
4.570
0.1200
0.1400
0.1800
0.360
0.460
0.580
0.0140
0.0180
0.0230
b1
0.760
1.020
1.400
0.0300
0.0400
0.0550
0.200
0.250
0.360
0.0080
0.0100
0.0140
27.430
28.450
1.0800
1.1000
1.1200
9.910
10.410
11.050
0.3900
0.4100
0.4350
E1
7.620
8.890
9.400
0.3000
0.3500
0.3700
0.0200
1.780
0.0700
eA
10.160
0.4000
eB
12.700
0.5000
eC
1.400
0.0550
2.540
3.050
3.810
0.1000
Number of pins
N
32
166/186
0.1200
0.15000
ST7263Bxx
Package characteristics
Figure 80. 34-pin plastic small outline package, 300-mil width, package outline
h x 45
L
A1
Table 81.
34-pin plastic small outline package, 300-mil width, package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
2.464
2.642
0.0970
0.1040
A1
0.127
0.292
0.0050
0.0120
0.356
0.483
0.0140
0.0190
0.231
0.318
0.0090
0.0130
17.729
18.059
0.6980
0.7110
7.417
7.595
0.2920
0.2990
1.016
0.0400
10.160
10.414
0.4000
0.4100
0.635
0.737
0.0250
0.0290
0.610
1.016
0.0240
0.0400
Number of pins
N
34
167/186
Package characteristics
ST7263Bxx
Figure 81. 24-pin plastic small outline package, 300-mil width package outline
D
12
h x 45
C
E
13
24
A
ddd
A1
A1
L
9U_ME
Table 82.
24-pin plastic small outline package, 300-mil width package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
2.350
2.650
0.0930
0.1040
A1
0.100
0.300
0.0040
0.0120
0.330
0.510
0.0130
0.0200
0.230
0.320
0.0090
0.0130
15.200
15.600
0.5990
0.6140
7.400
7.600
0.2910
0.2990
1.270
0.0500
10.000
10.650
0.3940
0.4190
0.250
0.750
0.0100
0.0300
0.400
1.270
0.0160
0.0500
ddd
0.100
0.0040
Number of pins
24
168/186
ST7263Bxx
Package characteristics
D1
D3
A
A2
25
36
24
37
L1
b
E3 E1 E
48
13
Pin 1
identification
A1
12
5B_ME
Table 83.
mm
Dim.
Min
Typ
Max
Min
Typ
1.600
A1
0.050
A2
1.350
0.170
0.090
8.800
D1
6.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0530
0.0551
0.0570
0.220
0.270
0.0070
0.0087
0.0110
0.200
0.0040
9.000
9.200
0.3465
0.3543
0.3622
7.000
7.200
0.2677
0.2756
0.2835
5.500
0.0060
0.0080
0.2165
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
5.500
0.2165
0.500
0.0197
0.450
L1
ccc
0.600
0.750
0.0177
1.000
0
3.5
0.0236
0.0295
0.0394
7
0.080
3.5
0.0031
Number of pins
48
169/186
Package characteristics
ST7263Bxx
A2
Figure 83. 40-lead very thin fine pitch quad flat no-lead package outline
A
SEATING
A3
PLANE
A1
D
D2
E2
PIN #1 ID TYPE C
RADIUS
2
1
L
Table 84.
40-lead very thin fine pitch quad flat no-lead package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
0.800
0.900
1.000
0.0315
0.0354
0.0394
A1
0.020
0.050
0.0008
0.0020
A2
0.650
1.000
0.0260
0.0390
A3
0.200
0.0080
0.180
0.250
0.300
0.0070
0.0100
0.0120
5.850
6.000
6.150
0.2300
0.2360
0.2420
D2
2.750
2.90
3.050
0.1080
0.1140
0.1200
5.850
6.000
6.150
0.2300
0.2360
0.2420
E2
2.750
2.900
3.050
0.1080
0.1140
0.1200
e
L
0.500
0.300
0.400
0.0200
0.500
0.0120
Number of pins
N
40
170/186
0.0160
0.0200
ST7263Bxx
14.2
Package characteristics
Thermal characteristics
Table 85.
Thermal characteristics
Symbol
RthJA
PD
TJmax
Ratings
Package thermal resistance (junction to
ambient)
SDIP32
SO34
SO24
LQFP48
QFN40
Power dissipation(1)
Maximum junction
temperature(2)
Value
60
75
70
80
34
Unit
C/W
500
mW
150
1. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation
of an application can be defined by the user with the formula: PD=PINT + PPORT where PINT is the chip
internal power (IDD x VDD) and PPORT the port power dissipation depending on the ports used in the
application.
2. The maximum chip-junction temperature is based on technology characteristics.
14.3
171/186
15
ST7263Bxx
15.1
Option byte
The Option Byte allows the hardware configuration of the microcontroller to be selected.
The Option Byte has no address in the memory map and can be accessed only in
programming mode using a standard ST7 programming tool. The default contents of the
FLASH is fixed to F7h. This means that all the options have 1 as their default value, except
LVD.
In ROM devices, the Option Byte is fixed in hardware by the ROM code.
Option Byte
7
--
--
WDG SW
WD HALT
LVD
--
OSC 24/12
FMP_R
172/186
ST7263Bxx
OPT 2 Reserved.
OPT 1 OSC24/12 Oscillator Selection
This option bit selects the clock divider used to drive the USB interface at 6MHz.
0: 24 MHz oscillator
1: 12 Mhz oscillator
OPT 0 FMP_R Flash memory readout protection
This option indicates if the user flash memory is protected against readout.
Readout protection, when selected, provides a protection against program memory
content extraction and against write access to Flash memory. Erasing the option
bytes when the FMP_R option is selected, causes the whole user memory to be
erased first and the device can be reprogrammed. Refer to the ST7 Flash
Programming Reference Manual and Section 4.3.1: Readout protection for more
details.
0: Readout protection enabled
1: Readout protection disabled
15.2
Sales type(1)(2)
Program memory
(bytes)
RAM
(bytes)
Package
ST72F63BH6T1
LQFP48
ST72F63BD6U1
QFN40
ST72F63BK6M1
32K Flash
1024
SO34
ST72F63BK6B1
SDIP32
ST72F63BE6M1
SO24
ST72F63BH4T1
LQFP48
ST72F63BK4M1
SO34
16K Flash
512
ST72F63BK4B1
SDIP32
ST72F63BE4M1
SO24
173/186
ST7263Bxx
Sales type(1)(2)
Program memory
(bytes)
RAM
(bytes)
Package
ST72F63BH2T1
LQFP48
ST72F63BK2U1
QFN40
ST72F63BK2M1
8K Flash
384
SO34
ST72F63BK2B1
SDIP32
ST72F63BE2M1
SO24
ST72F63BK1M1
SO34
ST72F63BK1B1
4K Flash
384
ST72F63BE1M1
SO24
ST7263BK2M1/xxx
SO34
8K ROM
384
ST7263BK2B1/xxx
SDIP32
ST7263BK1M1/xxx
SO34
4K ROM
384
ST7263BK1B1/xxx
1.
SDIP32
SDIP32
15.3
Development tools
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
15.3.1
15.3.2
174/186
ST7263Bxx
15.3.3
Programming tools
During the development cycle, the ST7-EMU3 series emulators and the RLink provide incircuit programming capability for programming the Flash microcontroller on your application
board.
In addition ST provides dedicated programming tools including the ST7-EPB programming
boards, which include all the sockets required to program any of the devices in a specific
ST7 sub-family.
For production programming of ST7 devices, STs third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
15.3.4
MCU
Starter kit
Evaluation
board
Emulator
In-circuit
debugger/programmer
Dedicated
programmer
ST7263Bx
ST72F63BSK/RAIS
ST7MDTULS
-EVAL
ST7MDTU3EMU3
STX-RLINK
ST7MDTU3EPB
For additional ordering codes for spare parts and accessories, refer to the online product
selector at www.st.com/mcu.
175/186
ST7263Bxx
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176/186
[ ] 24 MHz.
[ ] Disabled
[ ] 12 MHz.
[ ] Enabled
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
ST7263Bxx
15.4
Identification
Description
Application examples
AN1658
AN1720
AN1755
AN1756
AN1812
A High Precision, Low Cost, Single Supply ADC for Positive and Negative input
Voltages
Example drivers
AN 969
AN 971
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
PWM Duty Cycle Switch Implementing True 0% & 100% Duty Cycle
AN1082
AN1083
AN1105
AN1129
AN1130
AN1148
AN1149
AN1180
177/186
ST7263Bxx
Identification
Description
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
Starting a PWM Signal Directly at High Level Using the ST7 16-bit Timer
AN1602
AN1633
AN1712
AN1713
AN1753
AN1947
General purpose
AN1476
AN1526
AN1709
AN1752
Product evaluation
AN 910
Performance Benchmarking
AN 990
AN1077
AN1086
AN1103
Improved B-EMF detection for Low Speed, Low Voltage with ST72141
AN1150
AN1151
AN1278
Product migration
AN1131
AN1322
AN1365
AN1604
AN2200
Product optimization
AN 982
178/186
ST7263Bxx
Identification
Description
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
Extending the Current & Voltage Capability on the ST7265 VDDF Supply
AN1530
AN1605
AN1636
AN1828
AN1946
Sensorless BLDC Motor Control and BEMF Sampling Methods with ST7MC
AN1953
AN1971
AN 983
AN 985
AN 986
AN 987
AN 988
AN1039
AN1071
AN1106
AN1179
AN1446
AN1477
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
Using the ST7 USB Device Firmware Upgrade Development Kit (DFU-DK)
179/186
ST7263Bxx
Identification
Description
AN1635
AN1754
AN1796
Field Updates for FLASH Based ST7 Applications Using a PC Comm Port
AN1900
AN1904
AN1905
System Optimization
180/186
AN1711
AN1827
AN2009
PWM Management for 3-Phase BLDC Motor Drives Using the ST7FMC
AN2030
ST7263Bxx
Known limitations
16
Known limitations
16.1
Note:
16.2
Workaround
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.
16.3
16.4
I2C multimaster
Description
In multimaster configurations, if the ST7 I2C receives a START condition from another I2C
master after the START bit is set in the I2CCR register and before the START condition is
generated by the ST7 I2C, it may ignore the START condition from the other I2C master. In
this case, the ST7 master will receive a NACK from the other device. On reception of the
NACK, ST7 can send a re-start and Slave address to re-initiate communication
181/186
Known limitations
16.5
ST7263Bxx
Workaround
Switch off the ADC by software (ADON=0) before executing a HALT instruction.
16.6
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (fCPU=8MHz and SCIBRR=0xC9), the wrong break duration
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
182/186
1.
Disable interrupts
2.
3.
4.
Re-enable interrupts
ST7263Bxx
Known limitations
Figure 85. Identifying silicon revision from device marking and box label
The silicon revision can be identified either by Rev letter or obtained via a trace code.
1. Identify the silicon revision letter from either the device package or the box label.
For example, B, etc.
2. If the revision letter is not present, obtain the silicon revision by contacting your local
ST office with the trace code information printed on either the box label or the device
Trace code
STMicroelectronics
Silicon Rev
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
TYPE
Total Qty
ST7xxxxxxxxx
xxxxxxxxxxx$x7
XX
Trace code
XXXXXXXXX
Marking
B
XXXXXXXXXXXX
Bulk ID
XX XX
XXXXXXXXXX
Silicon Rev
183/186
Revision history
17
ST7263Bxx
Revision history
Table 89.
Date
Revision
Changes
19-Sep-05
06-Apr-06
27-May-05
184/186
ST7263Bxx
Revision history
Table 89.
Date
03-Oct-06
20-Aug-07
12-Jun-2009
Revision
Changes
185/186
ST7263Bxx
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USERS OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
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