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114

Xilinx
specific

FSM

Xilinx ISE includes a utility program called StateCAD, which allows a user to draw a
state diagram in graphical format. The program then converts the state diagram to HDL
code. It is a good idea to try it first with a few simple examples to see whether the generated
code and its style are satisfactory, particularly for the output signals.

5.3 DESIGN EXAMPLES

5.3.1

Rising-edge detector

The rising-edge detector is a circuit that generates a short, one-clock-cycle pulse (we call it
a tick) when the input signal changes from 0 to 1. It is usually used to indicate the onset
of a slow time-varying input signal. We design the circuit using both Moore and Mealy
machines, and compare their differences.

Moore-based design The state diagram and ASM chart of a Moore machine-based
edge detector are shown in Figure 5.4. The zero and one states indicate that the input
signal has been 0 and 1 for awhile. The rising edge occurs when the input changes to 1
in the zero state. The FSM moves to the edge state and the output, t i c k , is asserted in
this state. A representative timing diagram is shown at the middle of Figure 5.5. The code
is shown in Listing 5.3.
Listing 5.3 Moore machine-based edge detector

library i e e e ;
use i e e e . s t d - l o g i c - 1 1 6 4 . a l l ;
entity edge-detect is
port (
c l k , r e s e t : in s t d - l o g i c ;
l e v e l : in s t d - l o g i c ;
t i c k : out s t d - l o g i c
);

end e d g e - d e t e c t ;
10

15

20

25

a r c h i t e c t u r e moore-arch of e d g e - d e t e c t i s
type s t a t e - t y p e i s ( z e r o , e d g e , o n e ) ;
signal s t a t e - r e g , s t a t e - n e x t : s t a t e - t y p e ;
begin
-- s t a t e
register
process ( c l k ,r e s e t 1
begin
i f ( r e s e t = l ) then
s t a t e - r e g <= z e r o ;
e l s i f ( c l k e v e n t and c l k = l ) then
s t a t e - r e g <= s t a t e - n e x t ;
end i f ;
end p r o c e s s ;
-- n e x t - s t a t e / o u t p u t
logic
process ( s t a t e - r e g , l e v e l )
begin
s t a t e - n e x t <= s t a t e - r e g ;
t i c k <= 0 ;
case s t a t e - r e g is

DESIGN EXAMPLES

(b) ASM chart

(a) State diagram

Edge detector based on a Moore machine.

Figure 5.4

tl

level
r

Moore
machine

state

zero

tick

edge

one

zero

zero

r state (
Mealy
machine

zero

one

tick

Figure 5.5

Timing diagram of two edge detectors.

115

116

FSM

(b) ASM chart

(a) State diagram

Figure 5.6 Edge detector based on a Mealy machine.

30

35

when z e r o = >
i f l e v e l = 'I' t h e n
s t a t e - n e x t <= e d g e ;
end i f ;
when e d g e =>
t i c k <= ' 1 ' ;
i f l e v e l = ' 1 ' then
state-next

<= o n e ;

else
state-next
40

end i f ;
when o n e = >
if l e v e l = '0'
state-next

45

<= z e r o ;

then
<= z e r o ;

end i f ;
end c a s e ;
end p r o c e s s ;
end r n o o r e - a r c h ;

Mealy-based design The state diagram and ASM chart of a Mealy machine-based
edge detector are shown in Figure 5.6. The zero and one states have similar meaning.
When the FSM is in the z e r o state and the input changes to 'l', the output is asserted

DESIGN EXAMPLES

117

tick

level
clk

Figure 5.7 Gate-level implementation of an edge detector.

immediately. The FSM moves to the one state at the rising edge of the next clock and the
output is deasserted. A representative timing diagram is shown at the bottom of Figure 5.5.
Note that due to the propagation delay, the output signal is still asserted at the rising edge
of the next clock (i.e., at t l ) . The code is shown in Listing 5.4.
Listing 5.4 Mealy machine-based edge detector
a r c h i t e c t u r e m e a l y - a r c h of e d g e - d e t e c t i s
type s t a t e - t y p e i s ( z e r o , o n e ) ;
signal s t a t e - r e g , state-next : s t a t e - t y p e ;
begin
5

10

--

_15

state

register

process ( c l k , r e s e t )
begin
i f ( r e s e t = l ) then
s t a t e - r e g <= z e r o ;
e l s i f ( c l k e v e n t and c l k = l ) then
s t a t e - r e g <= s t a t e - n e x t ;
end i f ;
end p r o c e s s ;
next-state /output

logic

process ( s t a t e - r e g , l e v e l )
begin

20

s t a t e - n e x t <= s t a t e - r e g ;
t i c k <= 0 ;
case s t a t e - r e g i s
when z e r o = >
i f l e v e l = 1 then
s t a t e - n e x t <= o n e ;
t i c k <= 1 ;

25

end i f ;
when o n e = >
i f l e v e l = 0 then
state-next

?O

<= z e r o ;

end i f ;
end c a s e ;
end p r o c e s s ;
end m e a l y - a r c h ;

Direct implementation Since the transitions of the edge detector circuit are very simple, it can be implemented without using an FSM. We include this implementation for
comparison purposes. The circuit diagram is shown in Figure 5.7. It can be interpreted that
the output is asserted only when the current input is 1 and the previous input, which is
stored in the register, is 0. The corresponding code is shown in Listing 5.5.

118

FSM

Listing 5.5 Gate-level implementation of an edge detector

lo

15

a r c h i t e c t u r e g a t e - l e v e l - a r c h of edge-detect
s i g n a l delay-reg : std-logic ;
begin
_- d e l a y r e g i s t e r
p r o c e s s (clk,reset 1
begin
i f ( r e s e t = l ) then
d e l a y - r e g <= 0 ;
e l s i f ( c l k e v e n t and c l k = l ) t h e n
d e l a y - r e g <= l e v e l ;
end i f ;
end p r o c e s s ;
-- d e c o d i n g
logic
t i c k <= ( n o t d e l a y - r e g ) and l e v e l ;
end g a t e - l e v e l - a r c h ;

is

Although the descriptions in Listings 5.4 and 5.5 appear to be very different, they describe
the same circuit. The circuit diagram can be derived from the FSM if we assign 0 and 1
to the zero and one states.

Comparison Whereas both Moore machine- and Mealy machine-based designs can
generate a short tick at the rising edge of the input signal, there are several subtle differences.
The Mealy machine-based design requires fewer states and responds faster, but the width
of its output may vary and input glitches may be passed to the output.
The choice between the two designs depends on the subsystem that uses the output
signal. Most of the time the subsystem is a synchronous system that shares the same clock
signal. Since the FSMs output is sampled only at the rising edge of the clock, the width
and glitches do not matter as long as the output signal is stable around the edge. Note that
the Mealy output signal is available for sampling at t l , which is one clock cycle faster than
the Moore output, which is available at t 2 . Therefore, the Mealy machine-based circuit is
preferred for this type of application.
5.3.2

Debouncing circuit

The slide and pushbutton switches on the prototyping board are mechanical devices. When
pressed, the switch may bounce back and forth a few times before settling down. The
bounces lead to glitches in the signal, as shown at the top of Figure 5.8. The bounces
usually settle within 20 ms. The purpose of a debouncing circuit is to filter out the glitches
associated with switch transitions. The debounced output signals from two FSM-based
design schemes are shown in the two bottom parts of Figure 5.8. The first design scheme is
discussed in this subsection and the second scheme is left as an exercise in Experiment 5.5.2.
A better alternative FSMD-based scheme is discussed in Section 6.2.1.
An FSM-based design uses a free-running 10-ms timer and an FSM. The timer generates
a one-clock-cycle enable tick (the m-tick signal) every 10 ms and the FSM uses this
information to keep track of whether the input value is stabilized. In the first design scheme,
the FSM ignores the short bounces and changes the value of the debounced output only
after the input is stabilized for 20 ms. The output timing diagram is shown at the middle
of Figure 5.8. The state diagram of this FSM is shown in Figure 5.9. The z e r o and one
states indicate that the switch input signal, sw,has been stabilized with 0 and 1 values.

DESIGN EXAMPLES

bounces
(last less than 20 ms)

bounces
(last less than 20 ms)

-original
switch output

--

debounced output
(scheme 1)

*Oms

20 ms-

debounced output
(scheme 2)

20 ms

Figure 5.8 Original and debounced waveforms.

Figure 5.9

State diagram of a debouncing circuit.

20ms

119

Assume that the FSM is initially in the zero state. It moves to the w a i t 1-1 state when s w
changes to 1. At the w a i t l - l state, the FSM waits for the assertion of m - t i c k . If s w
becomes 0in this state, it implies that the width of the 1 value does not last long enough
and the FSM returns to the zero state. This action repeats two more times for the w a i t 1-2
and w a i t 1-3 states. The operation from the one state is similar except that the s w signal
must be 0.
Since the 10-ms timer is free-running and the m - t i c k tick can be asserted at any time,
the FSM checks the assertion three times to ensure that the s w signal is stabilized for at least
20 ms (it is actually between 20 and 30 ms). The code is shown in Listing 5.6. It includes
a 10-ms timer and the FSM.
Listing 5.6 FSM implementation of a debouncing circuit

library i e e e ;
use i e e e . s t d - l o g i c - 1 1 6 4 . a l l ;
use i e e e .n u m e r i c - s t d . a l l ;
e n t i t y db-fsm i s
port(
c l k , r e s e t : in s t d - l o g i c ;
sw: in s t d - l o g i c ;
d b : out s t d - l o g i c
);

10

15

end d b - f s m ;
a r c h i t e c t u r e a r c h of db-fsm i s
c o n s t a n t N: i n t e g e r : = 1 9 ; -- 2 * N * 2 0 n s = l O m s
s i g n a l q - r e g , q - n e x t : u n s i g n e d ( N - 1 downto 0 ) ;
signal m-tick: s t d - l o g i c ;
type e g - s t a t e - t y p e i s ( z e r o , w a i t l - l , w a i t l - 2 , w a i t l - 3 ,
one, wait0-1, wait0-2, wait0-3) ;

signal s t a t e - r e g , s t a t e - n e x t : eg-state-type;
begin
20

-- c o u n t e r t o g e n e r a t e l O m s t i c k
-- ( 2 ^ 1 9 * 2 0 n s )

25

30

process ( c l k , r e s e t )
begin
i f ( c l k e v e n t and c l k = l ) th e n
q - r e g <= q - n e x t ;
end i f ;
end p r o c e s s ;
-- n e x t - s t a t e
logic
q - n e x t <= q - r e g + 1 ;
--output
tick
r n - t i c k <= 1 when q - r e g = O e l s e
0.

35

-- d e b o u n c i n g FSM

__
40

state register
process ( c l k , r e s e t 1
begin

DESIGN EXAMPLES

121

if

( r e s e t = l ) then
s t a t e - r e g <= z e r o ;
e l s i f ( c l k e v e n t and c l k = l ) t h e n
s t a t e - r e g <= s t a t e - n e x t ;

45

50

55

65

end i f ;
end p r o c e s s ;
-- n e x t - s t a t e / o u t p u t
logic
p r o c e s s ( s t a t e - r e g , sw , m - t i c k )
begin
s t a t e - n e x t <= s t a t e - r e g ; - - d e f a u l t :
d b <= 0 ;
-- d e f a u l t 0
case s t a t e - r e g is
when z e r o = >
i f s w = l then
s t a t e - n e x t <= w a i t l - 1 ;
end i f ;
when w a i t l - 1 = >
i f sw=O then
s t a t e - n e x t <= z e r o ;
else
i f m - t i c k = l then
s t a t e - n e x t <= w a i t l - 2 ;
end i f ;
end i f ;
when w a i t l - 2 =>
i f s w = O then
state-next

<= z e r o ;

else
if m-tick=l
state-next

then
<= w a i t l - 3 ;

end i f ;
end i f ;
when w a i t l - 3 =>
i f s w = O then
75

s t a t e - n e x t <= z e r o ;
else
i f m - t i c k = l then
state-next

80

db < = l ;
if sw=O

then

state-next
85

<= o n e ;

end i f ;
end i f ;
when o n e = >

<= w a i t 0 - 1 ;

end i f ;
when w a i t 0 - 1 =>
db < = I J ;
i f s w = 1 then
s t a t e - n e x t <= o n e ;

else
if m-tick=l
state-next

end i f ;

then
<= w a i t 0 - 2 ;

b a c k t o same s t a t e

122

FSM

btn(1)

level tick
edge
detector

>

clk

sw
db
debouncing

>

-en

>

q
counter

-4

-level

>

hex0

sseg
an

-hex1

tick -en
9
counter
edge
detector

>

sseg

-an

disp-mux-hex
reset

Figure 5.10 Debouncing testing circuit.

end i f ;
when w a i t 0 - 2 = >

95

db

<=I>;

i f s w = 1 then
s t a t e - n e x t <= o n e ;
else
i f m - t i c k = l J then
s t a t e - n e x t <= w a i t 0 - 3 ;
end i f ;
end i f ;
when w a i t 0 - 3 = >
db

105

<=I>;

i f s w = 1 then

I10

11s

s t a t e - n e x t <= o n e ;
else
i f m - t i c k = l then
s t a t e - n e x t <= z e r o ;
end i f ;
end i f ;
end c a s e ;
end p r o c e s s ;

end a r c h ;

5.3.3 Testing circuit

We use a bounce counting circuit to verify operation of the rising-edge detector and the
debouncing circuit. The block diagram is shown in Figure 5.10. The input of the verification
circuit is from a pushbutton switch. In the lower part, the signal is first fed to the debouncing
circuit and then to the rising-edge detector. Therefore, a one-clock-cycle tick is generated
each time the button is pressed and released. The tick in turn controls the enable input of
an 8-bit counter, whose content is passed to the LED time-multiplexing circuit and shown
on the left two digits of the prototyping boards seven-segment LED display. In the upper
part, the input signal is fed directly to the edge detector without the debouncing circuit,
and the number is shown on the right two digits of the prototyping boards seven-segment
LED display. The bottom counter thus counts one desired 0-to- 1 transition as well as the
bounces.

DESIGN EXAMPLES

123

The code is shown in Listing 5.7. It basically uses component instantiation to realize
the block diagram.
Listing 5.7

Verification circuit for a debouncing circuit and rising-edge detector

l i b r a r y ieee;
use ieee. std-logic-1164 a l l ;
use ieee.numeric-std. a l l ;
e n t i t y debounce-test i s
port(
clk: i n std-logic;
btn: i n std-logic-vector ( 3 downto 0 ) ;
a n : o u t std-logic-vector ( 3 downto 0 ) ;
sseg: o u t std-logic-vector ( 7 downto 0 )
~

10

) ;

end debounce-test ;

IS

2o

a r c h i t e c t u r e arch of debounce-test i s
s i g n a l ql-reg , ql-next : unsigned ( 7 downto 0 ) ;
s i g n a l qO-reg, q0-next : unsigned(7 downto 0 ) ;
s i g n a l b-count , d-count: std-logic-vector (7 downto 0 ) ;
s i g n a l btn-reg , db-reg : std-logic ;
s i g n a l db-level , db-tick, btn-tick , clr: std-logic;
begin
...................................................
__ c o m p o n e n t i n s t a n t i a t i o n

__ ____________________----------------------------__ i n s t a n t i a t e h e x d i s p l a y t i m e - m u 1 t i p 1 e x i n g c i r c u i I
disp-unit : e n t i t y work. disp-hex-mux

____________________-----------------------------

30

p o r t map(
clk=>clk, reset=>'O',
hex3=>b_count(7 downto 4) , hex2=>b_count (3 downto 0) ,
hexl=>d-count (7 downto 4 ) , hexO=>d-count ( 3 downto 0 1 ,
dp-in=>"lOll", an=>an, sseg=>sseg);
-- i n s t a n t i a t e d e b o u n c i n g c i r c u i t
db-unit: e n t i t y work.db-fsm(arch1
p o r t map(
clk=>clk, reset=>'O',
sw=>btn (1) , db=>db-level) ;

__ e d g e

40

JS

detection

circuits

p r o c e s s (clk)
begin
if (clk'event and clk='l') t h e n
btn-reg <= btn(1) ;
db-reg <= db-level;
end i f ;
end p r o c e s s ;
btn-tick <= ( n o t btn-reg) and btn(l);
db-tick <= ( n o t db-reg) a n d db-level;