A Comparative Study of 6T, 8T and 9T SRAM Cell
A Comparative Study of 6T, 8T and 9T SRAM Cell
A Comparative Study of 6T, 8T and 9T SRAM Cell
ABSTRACT
From the last few decades, the scaling down of CMOS
devices have been taking place to achieve better
performance in terms of speed, power dissipation, size
and reliability. The major area of concern in todays
CMOS technology is Data retention and leakage current
reduction. SRAM (Static Random Access Memory) is
memory used to store data. Conventional Static Random
Access Memory (SRAM) cells suffer from an intrinsic
data instability problem due to directly-accessed data
storage nodes during a read operation. Noise margins of
memory cells further shrink with increasing variability
and decreasing power supply voltage in scaled CMOS
technologies. The comparison of different SRAM cell on
the basis of different performance metrics like Read
delay, Write delay, Power dissipation, noise margin, area
is done in this review paper.
Keywords SRAM, SNM,6T, 8T, 9T,delay,DRV
I.
INTRODUCTION
II.
www.ijaert.org
1. 6T SRAM cell
In the conventional 6T SRAM cell the condition of a non
destructive read operation and a reliable write operation
is fulfilled by appropriately sizing all the transistors in
the SRAM cell. Sizing is done according to the cell ratio
(CR) [6] and pull up ratio (PR) [6] of the transistor.
Table 1: Width of transistor used in 6T SRAM cell
Transistor
Width(mm)
M1,M2,M3,M4
120
M5,M6
600
2. 8T SRAM cell
In 8T SRAM cell read noise margin of the sram cell has
been enhanced by isolating the read and write operation.
The 8T SRAM cell consists of 8 transistors. Utilizing
single-ended data access for read operations with an
alternative 8T SRAM circuit structure [8] reduces the
www.ijaert.org
III.
COMPARISION
Parameters
6T
8T
9T
Power
consumption
delay
SNM
PDP
2.0e-6
2.12e-6
501e-3
10.83e-1
596.88
21.66e-1
10.08e-9
550.04
21.97e-1
1.16e-12
541.8
581.16e-1
www.ijaert.org
IV.
CONCLUSION
REFERENCES
[1] N. Dist, Analysis of New Current Mode Sense
Amplifier, pp. 16
[2] A.V Gayatri, Efficient Current Mode Sense
Amplifier for Low Power SRAM, vol. 1, no. 2, pp.147
153, 2011.
[3] J. Zhu, N. Bai, and J. Wu, A Review of Sense
Amplifiers for Static Random Access Memory, vol. 30,
no. 1, 2013.
[4] E. Grossar et al., Read stability and write-ability
analysis of SRAM cells for nanometer technologies,
IEEE J. Solid-State Circuits, vol. 41, no.11, pp. 2577
2588, Nov. 2006.
[5] V. Gupta and M. Anis, Statistical design of the 6T
SRAM bit cell, IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 57, no. 1, pp. 93104, Mar. 2010.
[6] A. Pavlov and M. Sachdev, CMOS SRAM circuit
design and parametric test in Nano scaled technologies,
Springer Netherlands, 2008
[7] Shigeki Ohbayashi, Makoto Yabuuchi, Koji Niiand,
Susumu Imaoka A 65-nm SoC Embedded 6T-SRAM
Designed for Manufacturability With Read and Write
Operation Stabilizing Circuits IEEE journal of solidstate circuits, Vol. 42,April 2007, pp820 -829
[8] L. Chang, D. M. Fried, J. Hergenrother, J. W.
Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J.
McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and
W. Haensch, Stable SRAM cell design for the 32nm
www.ijaert.org