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    Digital System Design Lecture 5: FPGA: Amir Masoud Gharehbaghi Amgh@mehr - Sharif.edu

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    Ali Jasim Ramadhan
    This document summarizes key aspects of field programmable gate arrays (FPGAs), including: 1) FPGAs contain logic blocks, I/O blocks, and interconnect wires and switches in a two-dimensional structure that can be programmed. 2) Logic blocks in FPGAs are based on look-up tables (LUTs) or multiplexers, with LUTs storing truth tables of functions. 3) Programming technologies for FPGAs and CPLDs include SRAM, antifuse, EPROM, EEPROM, and fuse technologies. SRAM allows for in-circuit reprogramming but uses more power.

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    Digital System Design Lecture 5: FPGA: Amir Masoud Gharehbaghi Amgh@mehr - Sharif.edu

    Uploaded by

    Ali Jasim Ramadhan
    51 views19 pages
    This document summarizes key aspects of field programmable gate arrays (FPGAs), including: 1) FPGAs contain logic blocks, I/O blocks, and interconnect wires and switches in a two-dimensional structure that can be programmed. 2) Logic blocks in FPGAs are based on look-up tables (LUTs) or multiplexers, with LUTs storing truth tables of functions. 3) Programming technologies for FPGAs and CPLDs include SRAM, antifuse, EPROM, EEPROM, and fuse technologies. SRAM allows for in-circuit reprogramming but uses more power.

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    FPGA

    Original Title

    FPGA

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    This document summarizes key aspects of field programmable gate arrays (FPGAs), including: 1) FPGAs contain logic blocks, I/O blocks, and interconnect wires and switches in a two-dimensional structure that can be programmed. 2) Logic blocks in FPGAs are based on look-up tables (LUTs) or multiplexers, with LUTs storing truth tables of functions. 3) Programming technologies for FPGAs and CPLDs include SRAM, antifuse, EPROM, EEPROM, and fuse technologies. SRAM allows for in-circuit reprogramming but uses more power.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    51 views19 pages

    Digital System Design Lecture 5: FPGA: Amir Masoud Gharehbaghi Amgh@mehr - Sharif.edu

    Uploaded by

    Ali Jasim Ramadhan
    This document summarizes key aspects of field programmable gate arrays (FPGAs), including: 1) FPGAs contain logic blocks, I/O blocks, and interconnect wires and switches in a two-dimensional structure that can be programmed. 2) Logic blocks in FPGAs are based on look-up tables (LUTs) or multiplexers, with LUTs storing truth tables of functions. 3) Programming technologies for FPGAs and CPLDs include SRAM, antifuse, EPROM, EEPROM, and fuse technologies. SRAM allows for in-circuit reprogramming but uses more power.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 19

    Digital System Design

    Lecture 5: FPGA
    Amir Masoud Gharehbaghi
    [email protected]

    Table of Contents
    {
    {
    {

    FPGA Logic Blocks


    Programming Technologies
    Comparison between Technologies

    Sharif University of Technology

    Field Programmable Gate Array


    {

    {
    {

    Two dimensional
    structure
    Programmable
    Three elements:
    z
    z
    z

    Sharif University of Technology

    Logic blocks
    I/O blocks
    Interconnection
    wires and switches

    FPGA Logic Blocks


    {

    Look Up Table
    (LUT) based

    Multiplexer (MUX)
    based

    Sharif University of Technology

    LUT-Based Logic Cells


    {

    LUT is a memory which contains the


    truth-table of a function
    LUT with n inputs can implement
    any n-bit function
    Truth-table is placed in LUT during
    the FPGA programming
    LUTs are implemented with SRAM

    Sharif University of Technology

    LUT Implementations

    Sharif University of Technology

    Multiplexer-Based Logic Cells


    {

    Every function can be implemented with


    multiplexer only.

    Sharif University of Technology

    PLD Programming Technologies


    {
    {
    {
    {
    {

    SRAM
    Anti-fuse
    EPROM
    EEPROM
    Fuse

    FPGAs use SRAM or Anti-fuse


    CPLDs use (E)EPROM or fuse
    Sharif University of Technology

    SRAM
    {

    Usage:
    z
    z
    z

    Implementing logic (LUT)


    Storage (Embedded RAM)
    Control to routing and configuration
    switches

    The programmable connections are


    made using pass transistors,
    transmission gates, or multiplexers
    that are controlled by SRAM cells.

    Sharif University of Technology

    SRAM (cont.)
    {

    Advantages
    z
    z
    z

    Easily changeable (even dynamic reconfiguration)


    Good density
    Track latest SRAM technology (moving even faster
    than technology for logic)
    Flexible not only good for FSM, also good for
    arithmetic circuits

    Disadvantages
    z
    z

    Volatile
    Generally high power

    Sharif University of Technology

    10

    SRAM Programming Technology


    {

    Pass gate: make


    connection
    between two
    segments
    Multiplexer:
    connect SRAM to
    selection lines

    Sharif University of Technology

    11

    SRAM Controlled Switches

    Sharif University of Technology

    12

    Anti-Fuse Technology
    {
    {

    Invented at Stanford and developed by


    Actel
    Actel PLICE (Programmable Logic
    Interconnect Circuit Element) structure

    Sharif University of Technology

    13

    Anti-Fuse
    {

    Anti-fuse resides in a high-impedance


    state. Can be programmed into lowimpedance or "fused" state.
    Less expensive than the RAM
    technology
    One-Time Programmable (OTP)

    Sharif University of Technology

    14

    EPROM/EEPROM
    {

    Can be reprogrammed without


    external storage of configuration
    EPROM transistors cannot be reprogrammed in-circuit.
    It is used both in SPLD and CPLD
    devices

    Sharif University of Technology

    15

    EPROM/EEPROM Technology
    {

    Transistor between
    two wires
    implement wiredAND functions.

    An input to the AND plane can drive a product wire


    to logic level 0 through an EPROM transistor, if that
    input is part of the corresponding product term.
    For inputs not involved in a product term, the
    appropriate EPROM transistors are programmed as
    permanently turned off.

    Sharif University of Technology

    16

    Programming Technologies
    Volatile

    RP

    Area

    Technolo
    gy

    Yes

    In-circuit

    Large

    CMOS

    Anti-Fuse No

    No

    Small

    CMOS+

    EPROM

    No

    Out of
    circuit

    Small

    UVCMOS

    EEPROM

    No

    Out of
    circuit

    Small (2x EECMOS


    EPROM)

    Fuse

    No

    No

    Small

    SRAM

    Sharif University of Technology

    Bipolar

    17

    Implementation Technologies

    Sharif University of Technology

    18

    Some FPGA Vendors

    Sharif University of Technology

    19

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