NAND and NOR implementation

Digital circuits are more frequently construct with NAND or NOR

gates than with AND and OR gates. NAND and NOR gates are easier to
fabricate with electronic components and are the basic gates used in all IC
digital logic families.

Not equivalent

OR equivalent

AND equivalent
Example: implement the following logic circuit using NAND gates only

DrOdayA.L.ARidha

29

Solution:
Step 1:

Step 2:

Properties of exclusive OR and Equivalence

Exclusive-OR and equivalence, denoted by and , respectively.
The two operations are complements of each other. Each is
commutative and associative.
( A B) C = A ( B C ) = A B C

An n-variable XOR expression is equal to the Boolean function with

n

2 / 2 minterms whose equivalent binary numbers have an odd

numbers of 1s.
n

An n-variable equivalence is equal to the Boolean function with 2 / 2

minterms whose equivalent binary numbers have an even numbers of
0s.
When the number of variables in a function is odd the minterms with
an even number of 0s are the same as the minterms with odd number
DrOdayA.L.ARidha

30

of 1s, therefore an XOR expression is equal to Equivalence

expression when both have the same odd number of variables.
A B C = ABC

When the minterms of a function with an odd number of variables

have an even number of 1s (or equivalently, an odd number of 0s),
the function can be expressed as the complement of either an
exclusive-OR or an equivalence expression.
( A B C ) = A BC = AB C
( ABC ) = AB C = A BC

Complement one of the inputs of XOR or equivalence function is

equal to complement the same function. (Prove that).
Exclusive-OR and Equivalence functions very useful in system
requiring error-detection and error-correction codes. Parity bit is a
scheme for detecting errors during transmission of binary information. A
parity bit is an extra bit included with a binary message to make the
number of 1s either odd or even. The message included the parity bit, is
transmitted and then checked at receiving end for error.

Example: design a 3-bit odd parity generator

3-bit
message
ABC

Parity bit
Generated
P

000
001
010
011
100
101
110
111

1
0
0
1
0
1
1
0

DrOdayA.L.ARidha

BC
A

00 01 11 10
0 1
1
1
1
1

P = ( A B C ) = A B C

31

Example: design an odd parity checker for 4-bit pattern

4-bit message
ABCP

Check
E

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1

AB
CP

00

00

01

01

11
1

11

10

10

1
1

E = ABC P

Parallel adder

A4 B 4
C5

FA
4
S4

A3 B 3
C4

FA
3
S3

A2 B 2
C3

FA
2

A1 B 1
C2

S2

FA
1

C1

S1

4-bit parallel binary adder

DrOdayA.L.ARidha

32

Carry propagation

An
Bn

Cn+1

HA
HA

Cn

FA n

A2
B2

HA

C3
HA

C2

FA 2

A1
B1

HA

Sn

S2

C2
HA

C1

S1

FA 1

Time required to propagate a carry from C1 to Cn+1 in an n-bit parallel

adder is equal to 2n times propagation delay time of one gate.
Look-ahead Carry
The carry propagation time is a limiting factor on the speed with
which two numbers are added in parallel. There are several techniques for
reducing the carry propagation time in a parallel adder. The most widely
used technique employs the principle of look-ahead carry.
Consider the full-adder shown in the figure below. If we define two
new binary variables:

Pi = Ai Bi

Gi = Ai Bi
DrOdayA.L.ARidha

33

The output sum and carry can be expresses as:

Si = Pi Ci
C i +1 = Gi + Pi C i

Now we can write the Boolean function for the carry output of each
stage and substitute for each its value from the previous equations:
C 2 = G1 + P1C1
C3 = G2 + P2C2 = G2 + P2 (G1 + P1C1 ) = G2 + P2G1 + P2 P1C1
C4 = G3 + P3C3 = G3 + P3G2 + P3 P2G1 + P3 P2 P1C1

Since the Boolean function for each output carry is expressed in sum
of products, each function can be implemented with one level of AND gates
follows by an OR gate. Note that Cn does not have to wait for Cn-1, Cn-2, ...,
and C1 to propagate; in fact, Cn is propagated at the same time as C1, and C2.
A4
B4

P4

C5
C4

C5
P4

S4

P3

S3

P2

S2

G4
A3
B3

P3

C3

Lookahead carry
P2 generator C2

G3
A2
B2

G2
A1
B1

P1

P1

S1

G1
C1

C1

BCD adder
Is a circuit that adds two BCD digits with a possible carry from previous
stage, in parallel, and produces a sum digit also in BCD. Since each input
digit doesnt exceed 9, the output sum cannot be greater 19, (9+9+1).
Suppose we apply two BCD digits to a 4-bit binary adder. The adder
will form the sum in binary and produce a result which may range from 0 to
19. These binary numbers are listed in the table below and are labeled by
symbols K, Z8, Z4, Z2, Z1. K is the carry, and subscripts under the letter Z
represent the weights that can be assigned to the four bits in the BCD code.
The first column in the table lists the binary sums as they appear in the
outputs of a 4-bit binary adder. The output sum of two decimal digits must

DrOdayA.L.ARidha

34

be represented in BCD and should appear in the form listed in the second
column of the table.
K
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1

Z8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0

Binary sum
Z4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

Z2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Z1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

C
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1

S8
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1

BCD sum
S4
S2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0

S1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

In examination the contents of the table, it is apparent that when the sum is
equal or less than 9, the corresponding BCD number is identical, and
therefore no conversion is needed. When the binary sum is greater than 9,
we obtain a nonvalid BCD representation. The addition of 6 to the binary
sum converts it to the correct BCD representation and also produces an
output carry as required.
The logic circuit that detects the necessary correction can be derived from
the table entries. It obvious that correction is needed when the binary sum
has an output carry K=1. The other six combinations from 1010 to 1111 that
need a correction have a 1 in position Z8. To distinguish them from binary
1000 and 1001 which also have a 1 in position Z8, we specify further that
either Z4 or Z2 must have a 1. The condition for a correction and an output
carry can be expressed by the Boolean function:
C = K + Z8Z 4 + Z8Z 2

When C=1, it is necessary to add 6 to the binary sum and provide an output
carry for next stage.

DrOdayA.L.ARidha

35

Addend

Augend

Carry in

4-bit binary adder

Z8

Z4

Z2

Z1

0
4-bit binary adder

S8

S4

S2

S1

Output Carry

Magnitude Comparator
The comparison of two numbers is an operation that determines if one
number is greater than, less than, or equal to the other number. A magnitude
comparator is a combinational circuit that compares two numbers, A and B,
and determines their relative magnitude. The outcome of the comparison is
specified by three binary variables that indicate whether A>B, A=B, or A<B.
If
A = A3 A2 A1 A0
B = B3 B2 B1 B0

We define
xi = Ai Bi + AiBi

i=0, 1, 2, 3

Then
( A = B) = x3 x 2 x1 x0
( A > B) = A3 B3 + x3 A2 B2 + x3 x 2 A1 B1 + x3 x 2 x1 A0 B0
( A < B) = A3 B3 + x3 A2 B2 + x3 x 2 A1B1 + x3 x 2 x1 A0 B0

Exercise: draw the logic circuit of 3-bit magnitude binary comparator

DrOdayA.L.ARidha

36

Decoders
Discrete quantities of information are represented in digital system with
binary codes. A binary code of n bits is capable of representing up 2n distinct
elements of the coded information. Decoder is a combinational circuit that
converts binary information from n input lines to a maximum of 2n unique
output lines. If n-bit decoded information has unused or dont-care
conditions, the output decoder will have less than 2n output. The name
decoder is also used in conjunction with some code converters such as BCDto-seven-segment decoder.
Inputs

Outputs

XYZ

D0

D1

D2

D3

D4

D5

D6

D7

000
001
010
011
100
101
110
111

1
0
0
0
0
0
0
0

0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1

Truth table of 3-to-8 lined decoder

Observe that the output variables are mutually exclusive because only one
output can be equal to 1 at any time. The output line whose value is equal to
1 represents the minterm equivalent of the binary number presently available
in the input lines.
We can construct a more big line decoder using small decoders
Example: construct a 4-to-8 (416) line decoder using 3-to-8 decoder.

A
B
C

38
Decoder
En

D0
D1
D2
D3
D4
D5
D6
D7

38
Decoder
En

DrOdayA.L.ARidha

D8
D9
D2
D11
D12
D13
D14
D15

37

Exercise1: Design BCD-to-decimal decoder.

Exercise2: Design BCD-to-seven-segment decoder.
Exercise3: Implement a full-adder circuit using 3-to-8 decoder.
Encoders
An Encoder is a digital function that produces a reverse operation from that
of decoder.
Inputs

Outputs

D7

D6

D5

D4

D3

D2

D1

D0

XYZ

0
0
0
0
0
0
0
1

0
0
0
0
0
0
1
0

0
0
0
0
0
1
0
0

0
0
0
0
1
0
0
0

0
0
0
1
0
0
0
0

0
0
1
0
0
0
0
0

0
1
0
0
0
0
0
0

1
0
0
0
0
0
0
0

000
001
010
011
100
101
110
111

Truth table of 8-to-3 encoder

Multiplexers
Multiplexing means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational
circuit that selects binary information from one of many input lines and
directs it to single output line. The selection of particular input line is
controlled by a set of selection lines. Normally, there are 2n input lines and n
selection lines whose bit combinations determine which input is selected.
I0
I1
Inputs
I2
I3

0
1
2
3

41
MUX

S0 S1

Output

S1

S0

I0

I1

I2

I3

Select

Boolean function implementation using multiplexers

If we have a Boolean function of n+ 1 variables, we take n of these variables
and connect them to the selection lines of the multiplexer. The remaining
single variable of the function is used for the inputs of the multiplexer. If A
is this single variable, the inputs of the multiplexer are chosen to be either A
or A or 1 or 0. By judicious use of these four values for the inputs and by
connecting the other variables to the selection lines, one can implement any

DrOdayA.L.ARidha

38

Boolean function with a multiplexer. In this way it is possible to generate

any function of n+1 variables with a 2n to-1 multiplexer.
Procedure
1) express the function in its sum of minterms form, Assume that the
ordered sequence of variables chosen for minterms is ABCD, where
A is leftmost variable in the ordered sequence of n and BCD are the
remaining n-1 variables. Connect the n-1 variables to the selection lines
of the multiplexer with B connected to high-order selection line, C to
the next lower selection line and so on down to the last variable.
2) List the inputs of the multiplexer and under them list all the minterms in
two rows. The first row lists all those minterms where A is
complemented, and the second row all the minterms with A
uncomplemented.
3) Circle all the minterms of the function and inspect each column
separately.
a) If the two minterms in a column are not circled, apply 0 to the
corresponding multiplexer input.
b) If the two minterms are circled, apply 1 to the corresponding
multiplexer input.
c) If the bottom minterm is circled and the top is not circled, apply
A to the corresponding multiplexer input.
d) If the top minterm is circled and the bottom is not circled, apply
A to the corresponding multiplexer input.
Example: Implement F ( A, B, C , D) = (0,1,3,4,8,9,15) with a multiplexer
Solution
1
I0

I1

I2

I3

I4

I5

I6

I7

10

11

12

13

14

15

I0
I1
I2
I3
I4
I5
I6
I7

81
MUX

B
C
D

DrOdayA.L.ARidha

39

Demultiplexers
It is a combinational logic circuit that receives information on a single line
and transmits this information on one of 2n possible output lines. The
selection of a specific output line is controlled by the bit values of n
selection lines. A decoder with an enable input can function as a
demultiplexer.

14
Demultiplexer

E
Input

D0
D1
D2
D3

A
B
E
Enable

A
B
Select
A
0
0
1
1

B
0
1
0
1

D0
E
0
0
0

D1
0
E
0
0

D2
0
0
E
0

D0
D1
D2
D3

24
Decoder

E
0
1
1
1
1

D3
0
0
0
E

A
X
0
0
1
1

B
X
0
1
0
1

D0
0
1
0
0
0

D1
0
0
1
0
0

D2
0
0
0
1
0

D3
0
0
0
0
1

Read-only memory (ROM)

We know that a decoder can generate 2n minterms of the n input variables.
By inserting OR gates to sum the minterms of Boolean functions, we were
able to generate any desired combinational circuit. A read-only memory
(ROM) is a device that includes both the decoder and the OR gates within a
single IC package. The connections between the outputs of the decoder and
the inputs of the OR gates can be specified for each particular configuration
by programming the ROM. The ROM is very often used to implement a
complex combinational circuit in one IC package and thus eliminate all
interconnecting wires.

n Inputs
(Address)

2nm
ROM

m Outputs
(Data)

Memory size=2nm

DrOdayA.L.ARidha

40

ROM types
1) Mask programming ROM
2) Programmable ROM (PROM)
3) Erasable Programmable ROM (EPROM)
4) Electrically Erasable Programmable ROM (E2PROM)
Example: Design a combinational circuit that accept a 3-bit number and
generates an output binary number equal to the square of the input number.
Use a minimum ROM size.
Solution:
Inputs
XYZ
000
001
010
011
100
101
110
111

Outputs
D5
0
0
0
0
0
0
1
1

DrOdayA.L.ARidha

D4
0
0
0
0
1
1
0
1

D3
0
0
0
1
0
1
0
0

D2
0
0
1
0
0
0
1
0

D1
0
0
0
0
0
0
0
0

D0
0
1
0
1
0
1
0
1

X
Y
Z

D5
D4

2 4
ROM

D3
D2

D1
D0

41