Data Sheet
Data Sheet
Data Sheet
8-Bit Micro-Controller
SN8P2604A
USERS MANUAL
Version 0.3
www.DataSheet4U.com
SN8P2604A
SN8P26042A
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
Page 1
Version 0.3
SN8P2604A
8-Bit Micro-Controller
AMENDENT HISTORY
Version
VER 0.1
VER 0.2
Date
Jun. 2006
Jan.2007
VER 0.3
Jun.2007
Description
Version 0.1 first issue
1. Add Marking Definition.
2. Modify ELECTRICAL CHARACTERISTIC.
3. Modify RST/P0.2/VPP PIN DISCRIPTION.
4. Modify P8 SN8P2604 to SN8P2604A
Update T0 section. The T0C supports read and modify write instruction, e.g. incms,
decms
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Page 2
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
11
PRODUCT OVERVIEW......................................................................................................................... 7
1.1
1.2
1.3
1.4
1.5
FEATURES ........................................................................................................................................ 7
SYSTEM BLOCK DIAGRAM .......................................................................................................... 9
PIN ASSIGNMENT ......................................................................................................................... 10
PIN DESCRIPTIONS....................................................................................................................... 11
PIN CIRCUIT DIAGRAMS............................................................................................................. 12
22
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CENTRAL PROCESSOR
2.1
MEMORY MAP............................................................................................................................... 13
2.1.1
PROGRAM MEMORY (ROM)............................................................................................... 13
2.1.1.1 RESET VECTOR (0000H) .................................................................................................. 14
2.1.1.2 INTERRUPT VECTOR (0008H)......................................................................................... 15
2.1.1.3 LOOK-UP TABLE DESCRIPTION.................................................................................... 17
2.1.1.4 JUMP TABLE DESCRIPTION ........................................................................................... 19
2.1.1.5 CHECKSUM CALCULATION........................................................................................... 21
2.1.2
CODE OPTION TABLE.......................................................................................................... 22
2.1.3
DATA MEMORY (RAM) ....................................................................................................... 23
2.1.4
SYSTEM REGISTER .............................................................................................................. 24
2.1.4.1 SYSTEM REGISTER TABLE ............................................................................................ 24
2.1.4.2 BIT DEFINITION of SYSTEM REGISTER....................................................................... 25
2.1.4.3 ACCUMULATOR ............................................................................................................... 26
2.1.4.4 PROGRAM FLAG ............................................................................................................... 27
2.1.4.5 PROGRAM COUNTER....................................................................................................... 28
2.1.4.6 H, L REGISTERS................................................................................................................. 31
2.1.4.7 Y, Z REGISTERS................................................................................................................. 32
2.1.4.8 R REGISTERS ..................................................................................................................... 33
2.2
ADDRESSING MODE .................................................................................................................... 34
2.2.1
IMMEDIATE ADDRESSING MODE .................................................................................... 34
2.2.2
DIRECTLY ADDRESSING MODE ....................................................................................... 34
2.2.3
INDIRECTLY ADDRESSING MODE ................................................................................... 34
2.3
STACK OPERATION...................................................................................................................... 35
2.3.1
OVERVIEW............................................................................................................................. 35
2.3.2
STACK REGISTERS............................................................................................................... 36
2.3.3
STACK OPERATION EXAMPLE.......................................................................................... 37
33
RESET ..................................................................................................................................................... 38
SONiX TECHNOLOGY CO., LTD
Page 3
Version 0.3
SN8P2604A
8-Bit Micro-Controller
3.1
OVERVIEW..................................................................................................................................... 38
3.2
POWER ON RESET......................................................................................................................... 39
3.3
WATCHDOG RESET...................................................................................................................... 39
3.4
BROWN OUT RESET ..................................................................................................................... 40
3.4.1
BROWN OUT DESCRIPTION ............................................................................................... 40
3.4.2
THE SYSTEM OPERATING VOLTAGE DECSRIPTION ................................................... 41
3.4.3
BROWN OUT RESET IMPROVEMENT .............................................................................. 41
3.5
EXTERNAL RESET ........................................................................................................................ 44
3.6
EXTERNAL RESET CIRCUIT ....................................................................................................... 44
3.6.1
Simply RC Reset Circuit .......................................................................................................... 44
3.6.2
Diode & RC Reset Circuit ........................................................................................................ 45
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3.6.3
Zener Diode Reset Circuit ........................................................................................................ 45
3.6.4
Voltage Bias Reset Circuit ....................................................................................................... 46
3.6.5
External Reset IC...................................................................................................................... 47
44
55
OVERVIEW..................................................................................................................................... 55
SYSTEM MODE SWITCHING....................................................................................................... 56
5.3
WAKEUP ......................................................................................................................................... 58
5.3.1
OVERVIEW............................................................................................................................. 58
5.3.2
WAKEUP TIME ...................................................................................................................... 58
5.3.3
P1W WAKEUP CONTROL REGISTER ................................................................................ 58
66
INTERRUPT........................................................................................................................................... 59
6.1
6.2
6.3
6.4
6.5
OVERVIEW..................................................................................................................................... 59
INTEN INTERRUPT ENABLE REGISTER................................................................................... 60
INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 61
GIE GLOBAL INTERRUPT OPERATION .................................................................................... 61
PUSH, POP ROUTINE .................................................................................................................... 62
Page 4
Version 0.3
SN8P2604A
8-Bit Micro-Controller
6.6
6.7
6.8
6.9
6.10
77
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88
TIMERS ..................................................................................................................................................
72
8.1
WATCHDOG TIMER...................................................................................................................... 72
8.2
TIMER 0 (T0) ................................................................................................................................... 74
8.2.1
OVERVIEW............................................................................................................................. 74
8.2.2
T0M MODE REGISTER ......................................................................................................... 74
8.2.3
T0C COUNTING REGISTER ................................................................................................. 75
8.2.4
T0 TIMER OPERATION SEQUENCE................................................................................... 76
8.3
TIMER/COUNTER 1 (TC1) ............................................................................................................ 77
8.3.1
OVERVIEW............................................................................................................................. 77
8.3.2
TC1M MODE REGISTER....................................................................................................... 78
8.3.3
TC1C COUNTING REGISTER .............................................................................................. 79
8.3.4
TC1R AUTO-LOAD REGISTER............................................................................................ 80
8.3.5
TC1 CLOCK FREQUENCY OUTPUT (BUZZER)................................................................ 81
8.3.6
TC1 TIMER OPERATION SEQUENCE ................................................................................ 82
8.3.7
TC1 TIMER NOTICE .............................................................................................................. 83
8.4
PWM1 MODE .................................................................................................................................. 83
8.4.1
OVERVIEW............................................................................................................................. 84
8.4.2
TC1IRQ AND PWM DUTY.................................................................................................... 85
8.4.3
PWM PROGRAM EXAMPLE ................................................................................................ 86
8.4.4
PWM1 DUTY CHANGING NOTICE..................................................................................... 87
99
1100
10.2
ELECTRICAL CHARACTERISTIC............................................................................................... 90
1111
1122
Page 5
Version 0.3
SN8P2604A
8-Bit Micro-Controller
12.1.1
12.1.2
1133
1144
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14.1
14.2
14.3
14.4
INTRODUCTION ............................................................................................................................ 99
MARKING INDETIFICATION SYSTEM...................................................................................... 99
MARKING EXAMPLE ................................................................................................................. 100
DATECODE SYSTEM .................................................................................................................. 100
Page 6
Version 0.3
SN8P2604A
8-Bit Micro-Controller
PRODUCT OVERVIEW
SN8P2604A is modified from SN8P2604. Good high noisy protecting performance for household
application.
z
z
z
z
1.1 FEATURES
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Memory configuration
OTP ROM size: 4K * 16 bits.
RAM size: 128 * 8 bits.
Eight levels stack buffer
Powerful instructions
One clocks per instruction cycle (1T)
Most of instructions are one cycle only.
All ROM area JMP instruction.
All ROM area CALL address instruction.
All ROM area lookup table function (MOVC)
Operating modes
Normal mode: Both high and low clock active
Slow mode: Low clock only
Sleep mode: Both high and low clock stop
Green mode: Periodical wakeup by T0 timer
Page 7
Version 0.3
SN8P2604A
8-Bit Micro-Controller
CHIP
Timer
ROM RAM Stack T0 TC1
PWM
Wakeup
I/O Green
Buzzer Pin No.
Mode
Package
SN8P2604
4K*16 128
24
11
SK-DIP28/SOP28/SSOP28
SN8P26042
4K*16 128
16
11
P-DIP20/SOP20/SSOP20
SN8P2604A
4K*16 128
24
11
SK-DIP28/SOP28/SSOP28
16
11
P-DIP20/SOP20/SSOP20
Page 8
Version 0.3
SN8P2604A
8-Bit Micro-Controller
PC
OTP
IR
ROM
EXTERNAL
HIGH OSC.
INTERNAL
LOW RC
FLAGS
LVD
(Low Voltage Detector)
WATCHDOG TIMER
TIMING GENERATOR
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ALU
PWM 1
RAM
P0
ACC
SYSTEM REGISTERS
INTERRUPT
CONTROL
P1
P2
BUZZER 1
PWM1
BUZZER1
P5
Page 9
Version 0.3
SN8P2604A
8-Bit Micro-Controller
www.DataSheet4U.com
P0.1/INT1
VDD
P5.4
VSS
P0.0/INT0
P5.0
P5.1
P5.2
P5.3/BZ1/PWM1
P1.0
P1.1
P1.2
P1.3
P1.4
1
U
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
SN8P2604AK
SN8P2604AS
SN8P2604AX
RST/VPP/P0.2
XIN
XOUT/Fcpu
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.7
P1.6
P1.5
Page 10
P5.0
P0.0/INT0
VSS
VDD
P0.1
RST/VPP/P0.2
XIN
XOUT/Fcpu
P2.7
P2.0
Version 0.3
SN8P2604A
8-Bit Micro-Controller
TYPE
P
P0.2/RST/VPP
I, P
XIN
XOUT/Fcpu
I/O
P0.0/INT0
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I/O
P0.1/INT1
I/O
P1.0~P1.1
I/O
P1.2~P1.7
I/O
P2.0~P2.7
I/O
P5.0~P5.2, P5.4
I/O
P5.3/BZ1/PWM1
I/O
DESCRIPTION
Power supply input pins for digital circuit.
P0.2: Input only pin (Schmitt trigger) if disable external reset function.
P0.2 without build-in pull-up resister
P0.2 is input only pin without pull-up resistor under P0.2 mode. Add the 100 ohm
external resistor on P0.2, when it is set to be input pin.
RST: System reset input pin. Schmitt trigger structure, low active, normal stay to high.
VPP: OTP programming pin.
Oscillator input pin while external oscillator enable (crystal and RC).
XOUT: Oscillator output pin while external crystal enable.
Fcpu: Signal output pin while external RC mode enable.
Port 0.0 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
INT0 trigger pin (Schmitt trigger).
Port 0.1 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
INT1 trigger pin (Schmitt trigger).
TC1 event counter clock input pin.
Port 1.0, P1.1 bi-direction pin and open-drain pin. Schmitt trigger structure as input
mode.
Built-in pull-up resisters.
Port 1.2~P1.7 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Port 5 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Port 5.3 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
TC1 2 signal output pin for buzzer or PWM1 output pin.
Page 11
Version 0.3
SN8P2604A
8-Bit Micro-Controller
PnM, PnUR
Input Bus
Pin
Output
Latch
Output Bus
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Port 1.0, P1.1 structure:
Pull-Up
PnM
PnM, PnUR
Input Bus
Pin
Output
Latch
Output Bus
Open-Drain
P1OC
Pin
Int. Rst
Page 12
Version 0.3
SN8P2604A
8-Bit Micro-Controller
4K words ROM
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0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
.
.
000FH
0010H
0011H
.
.
.
.
.
0FFBH
0FFCH
0FFDH
0FFEH
0FFFH
ROM
Reset vector
General purpose area
Page 13
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.1.1
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ORG
JMP
0
START
ORG
10H
START:
ENDP
; 0000H
; Jump to user program address.
; End of program
Page 14
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.1.2
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: PUSH, POP instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
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.CODE
ORG
JMP
0
START
; 0000H
; Jump to user program address.
ORG
PUSH
POP
RETI
; Interrupt vector.
; Save ACC and PFLAG register to buffers.
START:
JMP
ENDP
Page 15
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG
JMP
ORG
JMP
0
START
; 0000H
; Jump to user program address.
8
MY_IRQ
; Interrupt vector.
; 0008H, Jump to interrupt service routine address.
ORG
10H
START:
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JMP
MY_IRQ:
PUSH
POP
RETI
ENDP
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a JMP instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. Users program is a loop routine for main purpose application.
Page 16
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.1.3
In the ROMs data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
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@@:
TABLE1:
B0MOV
B0MOV
MOVC
Y, #TABLE1$M
Z, #TABLE1$L
INCMS
JMP
INCMS
NOP
Z
@F
Y
MOVC
DW
DW
DW
0035H
5105H
2012H
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid look-up table errors. If Z register
overflows, Y register must be added one. The following INC_YZ macro shows a simple method
to process Y and Z registers automatically.
INC_YZ
MACRO
INCMS
JMP
INCMS
NOP
Z
@F
; Z+1
; Not overflow
; Y+1
; Not overflow
@@:
ENDM
Page 17
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Y, #TABLE1$M
Z, #TABLE1$L
INC_YZ
@@:
TABLE1:
MOVC
DW
DW
DW
0035H
5105H
2012H
The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if carry happen.
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Y, #TABLE1$M
Z, #TABLE1$L
B0MOV
B0ADD
A, BUF
Z, A
; Z = Z + BUF.
B0BTS1
JMP
INCMS
NOP
FC
GETDATA
Y
GETDATA:
;
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
MOVC
TABLE1:
DW
DW
DW
0035H
5105H
2012H
Page 18
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.1.4
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesnt support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCLACC, PCH keeps value and
not change.
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ORG
0X0100
B0ADD
JMP
JMP
JMP
JMP
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
Example: If jump table crosses over ROM boundary will cause errors.
@JMP_A
MACRO
IF
JMP
ORG
ENDIF
ADD
ENDM
VAL
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
($ | 0XFF)
($ | 0XFF)
PCL, A
Page 19
Version 0.3
SN8P2604A
8-Bit Micro-Controller
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; BUF0 is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
If the jump table position is across a ROM boundary (0x00FF~0x0100), the @JMP_A macro will adjust the jump table
routine begin from next RAM boundary (0x0100).
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B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; BUF0 is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; BUF0 is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
Page 20
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.1.5
CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
Example: The demo program shows how to calculated Checksum from 00H to the end of users code.
MOV
B0MOV
MOV
B0MOV
CLR
CLR
A,#END_USER_CODE$L
END_ADDR1, A
; Save low end address to end_addr1
A,#END_USER_CODE$M
END_ADDR2, A
; Save middle end address to end_addr2
Y
; Set Y to 00H
Z
; Set Z to 00H
MOVC
B0BSET
ADD
MOV
ADC
JMP
FC
DATA1, A
A, R
DATA2, A
END_CHECK
; Clear C flag
; Add A to Data1
INCMS
JMP
JMP
Z
@B
Y_ADD_1
; Z=Z+1
; If Z != 00H calculate to next address
; If Z = 00H increase Y
MOV
CMPRS
JMP
MOV
CMPRS
JMP
JMP
A, END_ADDR1
A, Z
AAA
A, END_ADDR2
A, Y
AAA
CHECKSUM_END
INCMS
NOP
JMP
; Increase Y
@B
@@:
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; Add R to Data2
; Check if the YZ address = the end of code
AAA:
END_CHECK:
; Check if Z = low end address
; If Not jump to checksum calculate
Y_ADD_1:
CHECKSUM_END:
END_USER_CODE:
Page 21
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.2
Code Option
Content
RC
High_Clk
32K Xtal
12M Xtal
4M Xtal
Always_On
Watch_Dog
Enable
Disable
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Fcpu
Reset_Pin
Security
Noise_Filter
LVD
Fosc/1
Fosc/2
Fosc/4
Fosc/8
Reset
P02
Enable
Disable
Enable
Disable
LVD_L
LVD_M
LVD_H
Function Description
Low cost RC for external high clock oscillator and XOUT becomes to
Fcpu output pin.
Low frequency, power saving crystal (e.g. 32.768KHz) for external high
clock oscillator.
High speed crystal /resonator (e.g. 12MHz) for external high clock
oscillator.
Standard crystal /resonator (e.g. 4M) for external high clock oscillator.
Watchdog timer always on even in power down and green mode.
Enable watchdog timer. Watchdog timer stops in power down mode and
green mode.
Disable Watchdog function.
Instruction cycle is oscillator clock.
Notice: In Fosc/1, Noise Filter must be disabled.
Instruction cycle is 2 oscillator clocks.
Notice: In Fosc/2, Noise Filter must be disabled.
Instruction cycle is 4 oscillator clocks.
Instruction cycle is 8 oscillator clocks.
Enable External reset pin.
Enable P0.2 input only without pull-up resister.
Enable ROM code Security function.
Disable ROM code Security function.
Enable Noise Filter and the Fcpu is Fosc/4~Fosc/8.
Disable Noise Filter and the Fcpu is Fosc/1~Fosc/8.
LVD will reset chip if VDD is below 2.0V
LVD will reset chip if VDD is below 2.0V
Enable LVD24 bit of PFLAG register for 2.4V low voltage indicator.
LVD will reset chip if VDD is below 2.4V
Enable LVD36 bit of PFLAG register for 3.6V low voltage indicator.
Note:
1. In high noisy environment, enable Noise Filter and set Watch_Dog as Always_On
is strongly recommended. Enable Noise_Filter will limit the Fcpu = Fosc/4 ~ Fosc/8.
2. If users define watchdog as Always_On, assembler will Enable Watch_Dog
automatically.
3. Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the
Fosc is internal low clock).
Page 22
Version 0.3
SN8P2604A
8-Bit Micro-Controller
BANK 0
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Address
000h
07Fh
080h
0FFh
RAM location
Page 23
Version 0.3
SN8P2604A
8-Bit Micro-Controller
PFLAG
P0M
PEDGE
P1W
P1M
P2M
P5M
INTRQ
INTEN
OSCM
WDTR
PCL
PCH
P0
P1
P2
P5
T0M
T0C
TC1M
TC1C
TC1R
STKP
P0UR
P1UR
P2UR
P5UR
@HL
@YZ
P1OC
STK7L STK7H
STK3L
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Description
PFLAG =
H, L =
P1W =
PnM =
P1OC =
INTRQ =
OSCM =
T0M =
TC1M =
TC1R =
STKP =
@YZ =
R=
Y, Z =
PEDGE =
Pn =
PnUR =
INTEN =
PCH, PCL =
T0C =
TC1C =
WDTR =
STK0~STK7 =
@HL =
Page 24
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.4.2
Address
Bit7
080H
LBIT7
081H
HBIT7
082H
RBIT7
083H
ZBIT7
084H
YBIT7
086H
NT0
0B8H
0BFH
0C0H
P17W
0C1H
P17M
0C2H
P27M
0C5H
0C8H
0C9H
0CAH
0CCH
WDTR7
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0CEH
PC7
0CFH
0D0H
0D1H
P17
0D2H
P27
0D5H
0D8H
T0ENB
0D9H
T0C7
0DCH
TC1ENB
0DDH
TC1C7
0DEH
TC1R7
0DFH
GIE
0E0H
0E1H
P17R
0E2H
P27R
0E5H
0E6H
@HL7
0E7H
@YZ7
0E9H
0F0H
S7PC7
0F1H
0F2H
S6PC7
0F3H
0F4H
S5PC7
0F5H
0F6H
S4PC7
0F7H
0F8H
S3PC7
0F9H
0FAH
S2PC7
0FBH
0FCH
S1PC7
0FDH
0FEH
S0PC7
0FFH
Bit6
LBIT6
HBIT6
RBIT6
ZBIT6
YBIT6
NPD
Bit5
LBIT5
HBIT5
RBIT5
ZBIT5
YBIT5
P16W
P16M
P26M
P15W
P15M
P25M
TC1IRQ
TC1IEN
WDTR6
PC6
WDTR5
PC5
P16
P26
P15
P25
T0rate2
T0C6
TC1rate2
TC1C6
TC1R6
T0rate1
T0C5
TC1rate1
TC1C5
TC1R5
P16R
P26R
P15R
P25R
@ HL 6
@YZ6
@ HL5
@YZ5
S7PC6
S6PC6
S5PC6
S4PC6
S3PC6
S7PC5
S6PC5
S5PC5
S4PC5
S3PC5
S2PC6
S2PC5
S1PC6
S1PC5
S0PC6
S0PC5
Bit4
LBIT4
HBIT4
RBIT4
ZBIT4
YBIT4
Bit3
LBIT3
HBIT3
RBIT3
ZBIT3
YBIT3
P00G1
P14W
P14M
P24M
P54M
T0IRQ
T0IEN
CPUM1
WDTR4
PC4
P00G0
P13W
P13M
P23M
P53M
CPUM0
WDTR3
PC3
PC11
P13
P23
P53
Bit2
LBIT2
HBIT2
RBIT2
ZBIT2
YBIT2
C
Bit1
LBIT1
HBIT1
RBIT1
ZBIT1
YBIT1
DC
P01M
Bit0
LBIT0
HBIT0
RBIT0
ZBIT0
YBIT0
Z
P00M
P12W
P12M
P22M
P52M
P11W
P11M
P21M
P51M
P01IRQ
P01IEN
STPHX
WDTR1
PC1
PC9
P01
P11
P21
P51
P10W
P10M
P20M
P50M
P00IRQ
P00IEN
T0C1
TC1OUT
TC1C1
TC1R1
STKPB1
P01R
P11R
P21R
P51R
@ HL1
@YZ1
P11OC
S7PC1
S7PC9
S6PC1
S6PC9
S5PC1
S5PC9
S4PC1
S4PC9
S3PC1
S3PC9
S2PC1
S2PC9
S1PC1
S1PC9
S0PC1
S0PC9
T0C0
PWM1OUT
TC1C0
TC1R0
STKPB0
P00R
P10R
P20R
P50R
@ HL0
@YZ0
P10OC
S7PC0
S7PC8
S6PC0
S6PC8
S5PC0
S5PC8
S4PC0
S4PC8
S3PC0
S3PC8
S2PC0
S2PC8
S1PC0
S1PC8
S0PC0
S0PC8
CLKMD
WDTR2
PC2
PC10
P02
P12
P22
P52
P14
P24
P54
T0rate0
T0C4
TC1rate0
TC1C4
TC1R4
T0C3
TC1CKS
TC1C3
TC1R3
T0C2
ALOAD1
TC1C2
TC1R2
STKPB2
P14R
P24R
P54R
@ HL4
@YZ4
P13R
P23R
P53R
@ HL3
@YZ3
P12R
P22R
P52R
@ HL2
@YZ2
S7PC4
S6PC4
S5PC4
S4PC4
S3PC4
S2PC4
S1PC4
S0PC4
-
S7PC3
S7PC11
S6PC3
S6PC11
S5PC3
S5PC11
S4PC3
S4PC11
S3PC3
S3PC11
S2PC3
S2PC11
S1PC3
S1PC11
S0PC3
S0PC11
S7PC2
S7PC10
S6PC2
S6PC10
S5PC2
S5PC10
S4PC2
S4PC10
S3PC2
S3PC10
S2PC2
S2PC10
S1PC2
S1PC10
S0PC2
S0PC10
WDTR0
PC0
PC8
P00
P10
P20
P50
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
W
W
W
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remarks
L
H
R
Z
Y
PFLAG
P0M
PEDGE
P1W
P1M
P2M
P5M
INTRQ
INTEN
OSCM
WDTR
PCL
PCH
P0
P1
P2
P5
T0M
T0C
TC1M
TC1C
TC1R
STKP
P0UR
P1UR
P2UR
P5UR
@ HL
@YZ
P1OC
STK7L
STK7H
STK6L
STK6H
STK5L
STK5H
STK4L
STK4H
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
Note:
1. To avoid system error, please be sure to put all the 0 and 1 as it indicates in the above
table.
2.
3.
4.
5.
Page 25
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.4.3
ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC cant be access by B0MOV instruction during the instant addressing
mode.
BUF, A
A, #0FH
dataa from
w; Write
w wACC
. D
t aBUF
S data
h ememory.
e t 4
MOV
A, BUF
B0MOV
A, BUF
; or
The system doesnt store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to
other data memories. PUSH, POP save and load ACC, PFLAG data into buffers.
INT_SERVICE:
PUSH
POP
RETI
Page 26
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.4.4
PROGRAM FLAG
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.
NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and
watchdog reset. C, DC, Z bits indicate the result status of ALU operation. LVD24, LVD36 bits indicate LVD detecting
power voltage status.
086H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NT0
NPD
LVD36
LVD24
C
DC
Z
PFLAG
Read/Write
R/W
R/W
R
R
R/W
R/W
R/W
After reset
0
0
0
0
0
Bit [7:6]
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Bit 5
LVD36: LVD 3.6V operating flag and only support LVD code option is LVD_H.
0 = Inactive (VDD > 3.6V).
1 = Active (VDD <= 3.6V).
Bit 4
LVD24: LVD 2.4V operating flag and only support LVD code option is LVD_M.
0 = Inactive (VDD > 2.4V).
1 = Active (VDD <= 2.4V).
Bit 2
C: Carry flag
1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic 1, comparison result
0.
0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic 0, comparison
result < 0.
Bit 1
Bit 0
Z: Zero flag
1 = The result of an arithmetic/logic/branch operation is zero.
0 = The result of an arithmetic/logic/branch operation is not zero.
Note: Refer to instruction set table for detailed information of C, DC and Z flags.
Page 27
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.4.5
PROGRAM COUNTER
The program counter (PC) is a 12-bit binary counter separated into the high-byte 4 and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction
is executed, the destination address will be inserted to bit 0 ~ bit 11.
PC
After
reset
Bit 8
PC8
Bit 7
PC7
Bit 6
PC6
Bit 5
PC5
Bit 4
PC4
Bit 3
PC3
Bit 2
PC2
Bit 1
PC1
Bit 0
PC0
PCH
PCL
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There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.
FC
C0STEP
; To skip, if Carry_flag = 1
; Else jump to C0STEP.
C0STEP:
B0BTS1
JMP
NOP
A, BUF0
FZ
C1STEP
C1STEP:
B0MOV
B0BTS0
JMP
NOP
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
C0STEP:
CMPRS
JMP
NOP
A, #12H
C0STEP
Page 28
Version 0.3
SN8P2604A
8-Bit Micro-Controller
If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
C0STEP:
INCS
JMP
NOP
BUF0
C0STEP
INCMS
JMP
NOP
BUF0
C0STEP
INCMS instruction:
C0STEP:
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If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next
instruction.
DECS instruction:
C0STEP:
DECS
JMP
NOP
BUF0
C0STEP
DECMS
JMP
NOP
BUF0
C0STEP
DECMS instruction:
C0STEP:
Page 29
Version 0.3
SN8P2604A
8-Bit Micro-Controller
MULTI-ADDRESS JUMPING
Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate
multi-address jumping function. Program Counter supports ADD M,A, ADC M,A and B0ADD M,A instructions
for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value
by the three instructions and dont care PCL overflow problem.
Note: PCH only support PC up counting result and doesnt support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCLACC, PCH keeps value and
not change.
; PC = 0323H
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MOV
B0MOV
A, #28H
PCL, A
MOV
B0MOV
A, #00H
PCL, A
; PC = 0328H
; PC = 0323H
B0ADD
JMP
JMP
JMP
JMP
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
Page 30
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.4.6
H, L REGISTERS
The H and L registers are the 8-bit buffers. There are two major functions of these registers.
z
z
081H
H
Read/Write
After reset
Bit 7
HBIT7
R/W
X
Bit 6
HBIT6
R/W
X
Bit 5
HBIT5
R/W
X
Bit 4
HBIT4
R/W
X
Bit 3
HBIT3
R/W
X
Bit 2
HBIT2
R/W
X
Bit 1
HBIT1
R/W
X
Bit 0
HBIT0
R/W
X
080H
Bit 7
LBIT7
L
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Read/Write
R/W
After reset
X
Bit 6
LBIT6
R/W
X
Bit 5
LBIT5
R/W
X
Bit 4
LBIT4
R/W
X
Bit 3
LBIT3
R/W
X
Bit 2
LBIT2
R/W
X
Bit 1
LBIT1
R/W
X
Bit 0
LBIT0
R/W
X
Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode to
access data as following.
B0MOV
B0MOV
B0MOV
H, #00H
L, #20H
A, @HL
Example: Clear general-purpose data memory area of bank 0 using @HL register.
CLR
B0MOV
H
L, #07FH
; H = 0, bank 0
; L = 7FH, the last address of the data memory area
CLR
DECMS
JMP
@HL
L
CLR_HL_BUF
CLR
@HL
CLR_HL_BUF:
END_CLR:
Page 31
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.4.7
Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.
z
can be used as general working registers
z
can be used as RAM data pointers with @YZ register
z
can be used as ROM data pointer with the MOVC instruction for look-up table
084H
Y
Read/Write
After reset
Bit 7
YBIT7
R/W
-
Bit 6
YBIT6
R/W
-
Bit 5
YBIT5
R/W
-
Bit 4
YBIT4
R/W
-
Bit 3
YBIT3
R/W
-
Bit 2
YBIT2
R/W
-
Bit 1
YBIT1
R/W
-
Bit 0
YBIT0
R/W
-
083H
Bit 7
ZBIT7
Z
Read/Write
R/W
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After reset
-
Bit 6
ZBIT6
R/W
-
Bit 5
ZBIT5
R/W
-
Bit 4
ZBIT4
R/W
-
Bit 3
ZBIT3
R/W
-
Bit 2
ZBIT2
R/W
-
Bit 1
ZBIT1
R/W
-
Bit 0
ZBIT0
R/W
-
Example: Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0.
B0MOV
B0MOV
B0MOV
Y, #00H
Z, #25H
A, @YZ
Example: Uses the Y, Z register as data pointer to clear the RAM data.
B0MOV
B0MOV
Y, #0
Z, #07FH
; Y = 0, bank 0
; Z = 7FH, the last address of the data memory area
CLR
@YZ
DECMS
JMP
Z
CLR_YZ_BUF
CLR
@YZ
CLR_YZ_BUF:
END_CLR:
Page 32
Version 0.3
SN8P2604A
8-Bit Micro-Controller
2.1.4.8
R REGISTERS
R register is an 8-bit buffer. There are two major functions of the register.
z
Can be used as working register
z
For store high-byte data of look-up table
(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the
low-byte data will be stored in ACC).
082H
R
Read/Write
After reset
Bit 7
RBIT7
R/W
-
Bit 6
RBIT6
R/W
-
Bit 5
RBIT5
R/W
-
Bit 4
RBIT4
R/W
-
Bit 3
RBIT3
R/W
-
Bit 2
RBIT2
R/W
-
Bit 1
RBIT1
R/W
-
Bit 0
RBIT0
R/W
-
Note: Please refer to the LOOK-UP TABLE DESCRIPTION about R register look-up table application.
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Page 33
Version 0.3
SN8P2604A
8-Bit Micro-Controller
www.DataSheet4U.com
A, #12H
B0MOV
R, #12H
Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register.
A, 12H
12H, A
H, #0
L, #12H
A, @HL
Y, #0
Z, #12H
A, @YZ
Page 34
Version 0.3
SN8P2604A
8-Bit Micro-Controller
CALL /
INTERRUPT
PCH
PCL
STACK Level
STACK Buffer
High Byte
STACK Buffer
Low Byte
STKP = 7
STK7H
STK7L
STKP = 6
STK6H
STK6L
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STKP + 1
STKP - 1
STKP = 5
STK5H
STKP
STK5L
STKP
STKP = 4
STK4H
STK4L
STKP = 3
STK3H
STK3L
STKP = 2
STK2H
STK2L
STKP = 1
STK1H
STK1L
STKP = 0
STK0H
STK0L
Page 35
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Bit 6
-
Bit 5
-
Bit 4
-
Bit[2:0]
Bit 7
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointer in the
beginning of the program.
MOV
B0MOV
A, #00000111B
STKP, A
0F0H~0FFH
STKnH
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
SnPC11
R/W
0
Bit 2
SnPC10
R/W
0
Bit 1
SnPC9
R/W
0
Bit 0
SnPC8
R/W
0
0F0H~0FFH
STKnL
Read/Write
After reset
Bit 7
SnPC7
R/W
0
Bit 6
SnPC6
R/W
0
Bit 5
SnPC5
R/W
0
Bit 4
SnPC4
R/W
0
Bit 3
SnPC3
R/W
0
Bit 2
SnPC2
R/W
0
Bit 1
SnPC1
R/W
0
Bit 0
SnPC0
R/W
0
Page 36
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Stack Level
0
1
2
3
4
5
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6
7
8
>8
STKPB2
STKP Register
STKPB1
STKPB0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
Stack Buffer
High Byte Low Byte
Free
STK0H
STK1H
STK2H
STK3H
STK4H
STK5H
STK6H
STK7H
-
Free
STK0L
STK1L
STK2L
STK3L
STK4L
STK5L
STK6L
STK7L
-
Description
Stack Over, error
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
Stack Level
8
7
6
5
4
3
2
1
0
STKP Register
STKPB2
STKPB1
STKPB0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
Stack Buffer
High Byte Low Byte
STK7H
STK6H
STK5H
STK4H
STK3H
STK2H
STK1H
STK0H
Free
Page 37
STK7L
STK6L
STK5L
STK4L
STK3L
STK2L
STK1L
STK0L
Free
Description
-
Version 0.3
SN8P2604A
8-Bit Micro-Controller
RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
z
z
z
z
Power on reset
Watchdog reset
Brown out reset
External reset (only supports external reset pin enable situation)
occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags
indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.
086H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NT0
NPD
LVD36
LVD24
C
DC
Z
PFLAG
Read/Write
R/W
R/W
R
R
R/W
R/W
R/W
After reset
0
0
0
0
0
Bit [7:6]
Description
Watchdog timer overflow.
Power voltage is lower than LVD detecting level.
External reset pin detect low level status.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillators start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
VDD
Power
VSS
VDD
External Reset
VSS
External Reset
Low Detect
External Reset
High Detect
Watchdog
Overflow
Watchdog Reset
Watchdog Stop
System Status
System Stop
Power On
Delay Time
External
Reset Delay
Time
Page 38
Watchdog
Reset Delay
Time
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Power-up: System detects the power voltage up and waits for power stable.
External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
z
z
z
z
Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the
system is reset.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Dont clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Note: Please refer to the WATCHDOG TIMER about watchdog timer detail information.
Page 39
Version 0.3
SN8P2604A
8-Bit Micro-Controller
System Work
Well Area
V1
V2
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V3
System Work
Error Area
VSS
Page 40
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Vdd (V)
Normal Operating
Area
Dead-Band Area
Reset Area
System Reset
Voltage.
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Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is
decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even
higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system
reset voltage.
LVD reset
Watchdog reset
Reduce the system executing rate
External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)
Note:
1. The Zener diode reset circuit, Voltage bias reset circuit and External reset IC can
completely improve the brown out reset, DC low battery and AC slow power down conditions.
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips)
and use external reset ( Zener diode reset circuit, Voltage bias reset circuit, External reset
IC). The structure can improve noise effective and get good EFT characteristic.
Page 41
Version 0.3
SN8P2604A
8-Bit Micro-Controller
LVD reset:
VDD
Power
VSS
Power is below LVD Detect
Voltage and System Reset.
System Status
System Stop
Power On
Delay Time
The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and
is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by
each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to
improve brown out reset is depend on application requirement and environment. If the power variation is very deep,
violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and
make system work error, the LVD cant be the protection and need to other reset methods. More detail LVD information
is in the electrical characteristic section.
The LVD is three levels design (2.0V/2.4V/3.6V) and controlled by LVD code option. The 2.0V LVD is always enable for
power on reset and Brown Out reset. The 2.4V LVD includes LVD reset function and flag function to indicate VDD
status function. The 3.6V includes flag function to indicate VDD status. LVD flag function can be an easy low battery
detector. LVD24, LVD36 flags indicate VDD voltage level. For low battery detect application, only checking LVD24,
LVD36 status to be battery status. This is a cheap and easy solution.
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086H
PFLAG
Read/Write
After reset
Bit 7
NT0
R/W
-
Bit 6
NPD
R/W
-
Bit 5
LVD36
R
0
Bit 4
LVD24
R
0
Bit 3
-
Bit 2
C
R/W
0
Bit 5
LVD36: LVD 3.6V operating flag and only support LVD code option is LVD_H.
0 = Inactive (VDD > 3.6V).
1 = Active (VDD <= 3.6V).
Bit 4
LVD24: LVD 2.4V operating flag and only support LVD code option is LVD_M.
0 = Inactive (VDD > 2.4V).
1 = Active (VDD <= 2.4V).
Page 42
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
Version 0.3
SN8P2604A
8-Bit Micro-Controller
LVD
2.0V Reset
2.4V Flag
2.4V Reset
3.6V Flag
LVD_L
Available
-
LVD_H
Available
Available
Available
LVD_L
If VDD < 2.0V, system will be reset.
Disable LVD24 and LVD36 bit of PFLAG register.
LVD_M
If VDD < 2.0V, system will be reset.
Enable LVD24 bit of PFLAG register. If VDD > 2.4V, LVD24 is 0. If VDD <= 2.4V, LVD24 flag is 1.
Disable LVD36 bit of PFLAG register.
LVD2_H
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If VDD < 2.4V, system will be reset.
Enable LVD24 bit of PFLAG register. If VDD > 2.4V, LVD24 is 0. If VDD <= 2.4V, LVD24 flag is 1.
Enable LVD36 bit of PFLAG register. If VDD > 3.6V, LVD36 is 0. If VDD <= 3.6V, LVD36 flag is 1.
Note:
1. After any LVD reset, LVD24, LVD36 flags are cleared.
2. The voltage level of LVD 2.4V or 3.6V is for design reference only. Dont use the LVD indicator
as precision VDD measurement.
Watchdog reset:
The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear
at one point of program. Dont clear the watchdog timer in several addresses. The system executes normally and the
watchdog wont reset system. When the system is under dead-band and the execution error, the watchdog timer cant
be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of
watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method
also can improve brown out reset condition and make sure the system to return normal mode.
If the system reset by watchdog and the power is still in dead-band, the system reset sequence wont be successful
and the system stays in reset status until the power return to normal range. Watchdog timer application note is as
following.
Reduce the system executing rate:
If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band.
The lower system rate is with lower minimum operating voltage. Select the power voltage thats no dead-band issue
and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue.
This way needs to modify whole program timing to fit the application requirement.
External reset circuit:
The external reset methods also can improve brown out reset and is the complete solution. There are three external
reset circuits to improve brown out reset including Zener diode reset circuit, Voltage bias reset circuit and External
reset IC. These three reset structures use external reset signal and control to make sure the MCU be reset under
power dropping and under dead-band. The external reset information is described in the next section.
Page 43
Version 0.3
SN8P2604A
8-Bit Micro-Controller
External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
The external reset can reset the system during power on duration, and good external reset circuit can protect the
system to avoid working at unusual power condition, e.g. brown out reset in AC power application
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RST
100 ohm
MCU
C1
0.1uF
VSS
VCC
GND
This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into
reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from
the timing difference.
Note: The reset circuit is no any protection against unusual power or brown out reset.
Page 44
Version 0.3
SN8P2604A
8-Bit Micro-Controller
DIODE
R2
RST
MCU
100 ohm
C1
0.1uF
VSS
VCC
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GND
This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal.
The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct
higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can
improve slight brown out reset condition.
Note: The R2 100 ohm resistor of Simply reset circuit and Diode & RC reset circuit is necessary to
limit any current flowing into reset pin from external capacitor C in the event of reset pin
breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).
E
R2
10K ohm
Vz
Q1
C
RST
MCU
R3
40K ohm
VSS
VCC
GND
The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition
completely. Use zener voltage to be the active level. When VDD voltage level is above Vz + 0.7V, the C terminal of
the PNP transistor outputs high voltage and MCU operates normally. When VDD is below Vz + 0.7V, the C terminal of
the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener
specification. Select the right zener voltage to conform the application.
Page 45
Version 0.3
SN8P2604A
8-Bit Micro-Controller
E
B
Q1
C
R2
10K ohm
RST
MCU
R3
2K ohm
VSS
VCC
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GND
The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely.
The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When
VDD voltage level is above or equal to 0.7V x (R1 + R2) / R1, the C terminal of the PNP transistor outputs high
voltage and MCU operates normally. When VDD is below 0.7V x (R1 + R2) / R1, the C terminal of the PNP transistor
outputs low voltage and MCU is in reset mode.
Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the
circuit diagram condition, the MCUs reset pin level varies with VDD voltage variation, and the differential voltage is
0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the
reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external
reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power
system, the current must be considered to whole system power consumption.
Note: Under unstable power condition as brown out reset, Zener diode rest circuit and Voltage bias
reset circuit can protects system no any error occurrence as power dropping. When power drops
below the reset detect voltage, the system reset would be triggered, and then system executes
reset sequence. That makes sure the system work well under unstable power situation.
Page 46
Version 0.3
SN8P2604A
8-Bit Micro-Controller
VDD
Bypass
Capacitor
0.1uF
Reset
IC
RST
RST
MCU
VSS
VSS
VCC
GND
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The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good
effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can
improve all power variation.
Page 47
Version 0.3
SN8P2604A
8-Bit Micro-Controller
SYSTEM CLOCK
4.1 OVERVIEW
The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is
generated from the external oscillator circuit. The low-speed clock is generated from on-chip low-speed RC oscillator
circuit (ILRC 16KHz @3V, 32KHz @5V).
Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock in slow mode is
divided by 4 to be the instruction cycle (Fcpu).
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Fcpu = Flosc/4.
SONIX provides a Noise Filter controlled by code option. In high noisy situation, the noise filter can isolate noise
outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable.
XIN
XOUT
HOSC
Fhosc.
CLKMD
Fosc
Fcpu
Fosc
CPUM[1:0]
Flosc.
z
z
z
z
z
Fcpu = Flosc/4
Page 48
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Bit 7
0
-
Bit 6
0
-
Bit 5
0
-
Bit 4
CPUM1
R/W
0
Bit 3
CPUM0
R/W
0
Bit 2
CLKMD
R/W
0
Bit 1
STPHX
R/W
0
Bit 0
0
-
Bit 1
Bit 2
Bit[4:3]
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FSTPHX
Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal
low-speed oscillator will be stopped.
B0BSET
FCPUM0
Page 49
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Description
The high clock is external RC type oscillator. XOUT pin is general purpose I/O pin.
The high clock is external 32768Hz low speed oscillator.
The high clock is external high speed oscillator. The typical frequency is 12MHz.
The high clock is external oscillator. The typical frequency is 4MHz.
three modules (Crystal/Ceramic, RC and external clock signal). The high clock oscillator
module is controlled by High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different.
RC type oscillators start-up time is very short, but the crystals is longer. The oscillator start-up time decides reset time
length.
4MHz Crystal
32768Hz Crystal
RC
4MHz Ceramic
Page 50
Version 0.3
SN8P2604A
8-Bit Micro-Controller
4.4.1.1
CRYSTAL/CERAMIC
Crystal/Ceramic devices are driven by XIN, XOUT pins. For high/normal/low frequency, the driving currents are
different. High_Clk code option supports different frequencies. 12M option is for high speed (ex. 12MHz). 4M option is
for normal speed (ex. 4MHz). 32K option is for low speed (ex. 32768Hz).
XIN
CRYSTAL
C
20pF
XOUT
MCU
C
VDD
20pF
VSS
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VCC
GND
Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of
micro-controller.
4.4.1.2
RC
Selecting RC oscillator is by RC option of High_Clk code option. RC type oscillators frequency is up to 10MHz. Using
R value is to change frequency. 50P~100P is good value for C. XOUT pin is general purpose I/O pin.
XOUT
XIN
MCU
VDD
VSS
VCC
GND
Note: Connect the R and C as near as possible to the VDD pin of micro-controller.
Page 51
Version 0.3
SN8P2604A
8-Bit Micro-Controller
4.4.1.3
Selecting external clock signal input to be system clock is by RC option of High_Clk code option. The external clock
signal is input from XIN pin. XOUT pin is general purpose I/O pin.
External Clock Input
XIN
XOUT
MCU
VSS
VDD
VCC
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GND
Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller.
Page 52
Version 0.3
SN8P2604A
8-Bit Micro-Controller
www.DataSheet4U.com
Freq. (KHz)
40.00
38.08
35.00
35.40
32.52
30.00
29.20
25.96
25.00
ILRC
22.24
20.00
15.00
14.72
16.00 17.24
18.88
10.64
10.00
7.52
5.00
0.00
2.1 2.5
4.5
5.5
6.5
VDD (V)
The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD.
)
There are two conditions to stop internal low RC. One is power down mode, and the other is green mode of 32K mode
and watchdog disable. If system is in 32K mode and watchdog disable, only 32K oscillator actives and system is under
low power consumption.
FCPUM0
Note: The internal low-speed clock cant be turned off individually. It is controlled by CPUM0, CPUM1
(32K, watchdog disable) bits of OSCM register.
Page 53
Version 0.3
SN8P2604A
8-Bit Micro-Controller
P0M.0
B0BSET
B0BCLR
JMP
P0.0
P0.0
@B
@@:
Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC
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frequency.
Page 54
Version 0.3
SN8P2604A
8-Bit Micro-Controller
5.1 OVERVIEW
The chip is featured with low power consumption by switching around four different modes as following.
z
Normal mode (High-speed mode)
z
Slow mode (Low-speed mode)
z
Power-down mode (Sleep mode)
z
Green mode
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Normal Mode
P0, P1 Wake-up Function Active.
T0 Timer Time Out.
External Reset Circuit Active.
Slow Mode
CLKMD = 0
Green Mode
External Reset Circuit
Active.
NORMAL
SLOW
GREEN
EHOSC
ILRC
CPU instruction
T0 timer
TC1 timer
Running
By STPHX
By STPHX
Running
Running
Running
Executing
Executing
Stop
*Active
*Active
*Active
*Active
*Active
*Active
By Watch_Dog By Watch_Dog By Watch_Dog
Watchdog timer
Code option
Code option
Code option
Internal interrupt
All active
All active
T0, TC1
External interrupt
All active
All active
All active
P0, P1, T0
Wakeup source
Reset
POWER DOWN
(SLEEP)
Stop
Stop
Stop
Inactive
Inactive
By Watch_Dog
Code option
All inactive
All inactive
REMARK
* Active if T0ENB=1
* Active if TC1ENB=1
Refer to code option
description
Page 55
Version 0.3
SN8P2604A
8-Bit Micro-Controller
FCPUM0
; Set CPUM0 = 1.
Note: During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.
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Example: Switch slow mode to normal mode (The external high-speed oscillator is still running)
B0BCLR
FCLKMD
FSTPHX
FCLKMD
Example: Switch slow mode to normal mode (The external high-speed oscillator stops)
If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 20ms for
external clock stable.
@@:
B0BCLR
FSTPHX
B0MOV
DECMS
JMP
Z, #54
Z
@B
B0BCLR
FCLKMD
FCPUM1
; Set CPUM1 = 1.
Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can
wakeup the system backs to the previous operation mode.
Page 56
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Example: Switch normal/slow mode to Green mode and enable T0 wakeup function.
FT0IEN
FT0ENB
A,#20H
T0M,A
A,#74H
T0C,A
B0BCLR
B0BCLR
B0BSET
FT0IEN
FT0IRQ
FT0ENB
FCPUM0
FCPUM1
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Note: During the green mode with T0 wake-up function, the wakeup pins, reset pin and T0 can wakeup
the system back to the last mode. T0 wake-up period is controlled by program and T0ENB must be set.
Page 57
Version 0.3
SN8P2604A
8-Bit Micro-Controller
5.3 WAKEUP
5.3.1 OVERVIEW
Under power down mode (sleep mode) or green mode, program doesnt execute. The wakeup trigger can wake the
system up to normal mode or slow mode. The wakeup trigger sources are external trigger (P0, P1 level change) and
internal trigger (T0 timer overflow).
z
Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0, P1 level change)
z
Green mode is waked up to last mode (normal mode or slow mode). The wakeup triggers are external trigger (P0,
P1 level change) and internal trigger (T0 timer overflow).
Note: Wakeup from green mode is no wakeup time because the clock doesnt stop in green mode.
Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.
Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system goes
into normal mode. The wakeup time is as the following.
The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz)
The total wakeup time = 0.512 ms + oscillator start-up time
Bit 7
P17W
W
0
Bit 6
P16W
W
0
Bit 5
P15W
W
0
Bit 4
P14W
W
0
Bit 3
P13W
W
0
Bit 2
P12W
W
0
Bit 1
P11W
W
0
Bit 0
P10W
W
0
Page 58
Version 0.2
SN8P2604A
8-Bit Micro-Controller
INTERRUPT
6.1 OVERVIEW
This MCU provides three interrupt sources, including two internal interrupt (T0/TC1) and two external interrupt (INT0,
INT1). The external interrupt can wakeup the chip while the system is switched from power down mode to high-speed
normal mode. Once interrupt service is executed, the GIE bit in STKP register will clear to 0 for stopping other
interrupt request. On the contrast, when interrupt service exits, the GIE bit will set to 1 to accept the next interrupts
request. All of the interrupt request signals are stored in INTRQ register.
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INT0 Trigger
INT1 Trigger
T0 Time Out
TC1 Time Out
P00IRQ
INTRQ
4-Bit
Latchs
P01IRQ
Interrupt
T0IRQ
Enable
TC1IRQ
Gating
Note: The GIE bit must enable during all interrupt operation.
Page 59
Version 0.2
SN8P2604A
8-Bit Micro-Controller
Bit 7
-
Bit 6
TC1IEN
R/W
0
Bit 5
-
Bit 4
T0IEN
R/W
0
Bit 3
-
Bit 2
-
Bit 1
P01IEN
R/W
0
Bit 0
P00IEN
R/W
0
Bit 0
Bit 4
Bit 6
Page 60
Version 0.2
SN8P2604A
8-Bit Micro-Controller
0C8H
INTRQ
Read/Write
After reset
Bit 7
-
Bit 6
TC1IRQ
R/W
0
Bit 5
-
Bit 4
T0IRQ
R/W
0
Bit 0
Bit 1
Bit 4
Bit 6
Bit 3
-
Bit 2
-
Bit 1
P01IRQ
R/W
0
Bit 0
P00IRQ
R/W
0
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Bit 7
GIE
R/W
0
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
Bit 6
-
FGIE
; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
Page 61
Version 0.2
SN8P2604A
8-Bit Micro-Controller
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed.
ORG
JMP
0
START
ORG
JMP
8
INT_SERVICE
ORG
10H
START:
INT_SERVICE:
PUSH
POP
RETI
ENDP
Page 62
Version 0.2
SN8P2604A
8-Bit Micro-Controller
0BFH
Bit 7
PEDGE
Read/Write
After
reset
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Bit[4:3]
Bit 6
-
Bit 5
-
Bit 4
P00G1
R/W
1
Bit 3
P00G0
R/W
0
Bit 2
-
Bit 1
-
Bit 0
-
A, #18H
PEDGE, A
B0BSET
B0BCLR
B0BSET
FP00IEN
FP00IRQ
FGIE
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
B0BTS1
JMP
FP00IRQ
EXIT_INT
; Check P00IRQ
; P00IRQ = 0, exit interrupt vector
B0BCLR
FP00IRQ
; Reset P00IRQ
; INT0 interrupt service routine
EXIT_INT:
RETI
Page 63
Version 0.2
SN8P2604A
8-Bit Micro-Controller
FP01IEN
FP01IRQ
FGIE
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
B0BTS1
JMP
FP01IRQ
EXIT_INT
; Check P01IRQ
; P01IRQ = 0, exit interrupt vector
B0BCLR
FP01IRQ
; Reset P01IRQ
; INT1 interrupt service routine
EXIT_INT:
RETI
Page 64
Version 0.2
SN8P2604A
8-Bit Micro-Controller
FT0IEN
FT0ENB
A, #20H
T0M, A
A, #74H
T0C, A
B0BSET
B0BCLR
B0BSET
FT0IEN
FT0IRQ
FT0ENB
B0BSET
FGIE
; Enable GIE
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8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
B0BTS1
JMP
FT0IRQ
EXIT_INT
; Check T0IRQ
; T0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
FT0IRQ
A, #74H
T0C, A
; Reset T0IRQ
; Reset T0C.
; T0 interrupt service routine
EXIT_INT:
RETI
Page 65
Version 0.2
SN8P2604A
8-Bit Micro-Controller
FTC1IEN
FTC1ENB
A, #20H
TC1M, A
A, #74H
TC1C, A
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B0BSET
B0BCLR
B0BSET
FTC1IEN
FTC1IRQ
FTC1ENB
B0BSET
FGIE
; Enable GIE
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
B0BTS1
JMP
FTC1IRQ
EXIT_INT
; Check TC1IRQ
; TC1IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
FTC1IRQ
A, #74H
TC1C, A
; Reset TC1IRQ
; Reset TC1C.
; TC1 interrupt service routine
EXIT_INT:
RETI
Page 66
Version 0.3
SN8P2604A
8-Bit Micro-Controller
6.10
MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag 1 doesnt mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set 1 by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic 1. The IRQ and its trigger event relationship is as the below table.
Interrupt Name
P00IRQ
P01IRQ
T0IRQ
TC1IRQ
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For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
INTP00CHK:
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTP01CHK
FP00IRQ
INTP00
B0BTS1
JMP
B0BTS0
JMP
FP01IEN
INTT0CHK
FP01IRQ
INTP01
B0BTS1
JMP
B0BTS0
JMP
FT0IEN
INTTC1CHK
FT0IRQ
INTT0
B0BTS1
JMP
B0BTS0
JMP
FTC1IEN
INT_EXIT
FTC1IRQ
INTTC1
INTP01CHK:
INTT0CHK:
INTTC1CHK:
INT_EXIT:
RETI
Page 67
Version 0.3
SN8P2604A
8-Bit Micro-Controller
I/O PORT
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
P01M
R/W
0
Bit 0
P00M
R/W
0
0C1H
P1M
Read/Write
After reset
Bit 7
P17M
R/W
0
Bit 6
P16M
R/W
0
Bit 5
P15M
R/W
0
Bit 4
P14M
R/W
0
Bit 3
P13M
R/W
0
Bit 2
P12M
R/W
0
Bit 1
P12M
R/W
0
Bit 0
P10M
R/W
0
0C2H
P2M
Read/Write
After reset
Bit 7
P27M
R/W
0
Bit 6
P26M
R/W
0
Bit 5
P25M
R/W
0
Bit 4
P24M
R/W
0
Bit 3
P23M
R/W
0
Bit 2
P22M
R/W
0
Bit 1
P22M
R/W
0
Bit 0
P20M
R/W
0
0C5H
P5M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P54M
R/W
0
Bit 3
P53M
R/W
0
Bit 2
P52M
R/W
0
Bit 1
P51M
R/W
0
Bit 0
P50M
R/W
0
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Bit[7:0]
Note:
1. Users can program them by bit control instructions (B0BSET, B0BCLR).
2. P0.2 is input only pin, and the P0M.2 keeps 1.
P0M
P2M
P1M
P5M
MOV
B0MOV
B0MOV
B0MOV
B0MOV
A, #0FFH
P0M, A
P1M, A
P2M, A
P5M, A
B0BCLR
P1M.2
B0BSET
P1M.2
Page 68
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
P01R
W
0
Bit 0
P00R
W
0
0E1H
P1UR
Read/Write
After reset
Bit 7
P17R
W
0
Bit 6
P16R
W
0
Bit 5
P15R
W
0
Bit 4
P14R
W
0
Bit 3
P13R
W
0
Bit 2
P12R
W
0
Bit 1
P11R
W
0
Bit 0
P10R
W
0
0E2H
Bit 7
P27R
P2UR
Read/Write
W
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After reset
0
Bit 6
P26R
W
0
Bit 5
P25R
W
0
Bit 4
P24R
W
0
Bit 3
P23R
W
0
Bit 2
P22R
W
0
Bit 1
P21R
W
0
Bit 0
P20R
W
0
Bit 6
-
Bit 5
-
Bit 4
P54R
W
0
Bit 3
P53R
W
0
Bit 2
P52R
W
0
Bit 1
P51R
W
0
Bit 0
P50R
W
0
0E5H
P5UR
Read/Write
After reset
Bit 7
-
Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 keeps 1.
A, #0FFH
P0UR, A
P1UR, A
P2UR, A
P5UR, A
Page 69
Version 0.3
SN8P2604A
8-Bit Micro-Controller
MCU2
MCU1
U
VCC
Pull-up Resistor
Open-drain pin
Open-drain pin
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The pull-up resistor is necessary. Open-drain output high is driven by pull-up resistor. Output low is sunken by MCUs
pin.
0E9H
P1OC
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 0
Bit 1
Bit 4
-
Bit 3
-
Bit 2
-
Bit 0
P10OC
W
0
P1.0
B0BSET
MOV
B0MOV
P10M
A, #01H
P1OC, A
Note: P1OC is write only register. Setting P10OC must be used MOV instructions.
Bit 1
P11OC
W
0
A, #0
P1OC, A
Note: After disable P1.0 open-drain function, P1.0 mode returns to last I/O mode.
Page 70
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
P02
R
0
Bit 1
P01
R/W
0
Bit 0
P00
R/W
0
0D1H
P1
Read/Write
After reset
Bit 7
P17
R/W
0
Bit 6
P16
R/W
0
Bit 5
P15
R/W
0
Bit 4
P14
R/W
0
Bit 3
P13
R/W
0
Bit 2
P12
R/W
0
Bit 1
P11
R/W
0
Bit 0
P10
R/W
0
0D2H
Bit 7
P27
P2
Read/Write
R/W
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After reset
0
Bit 6
P26
R/W
0
Bit 5
P25
R/W
0
Bit 4
P24
R/W
0
Bit 3
P23
R/W
0
Bit 2
P22
R/W
0
Bit 1
P21
R/W
0
Bit 0
P20
R/W
0
Bit 6
-
Bit 5
-
Bit 4
P54
R/W
0
Bit 3
P53
R/W
0
Bit 2
P52
R/W
0
Bit 1
P51
R/W
0
Bit 0
P50
R/W
0
0D5H
P5
Read/Write
After reset
Bit 7
-
Note: The P02 keeps 1 when external reset enable by code option.
P1.3
P5.5
Page 71
Version 0.3
SN8P2604A
8-Bit Micro-Controller
TIMERS
VDD
3V
5V
Note:
1. If watchdog is Always_On mode, it keeps running event under power down mode or green
mode.
2. For S8KD ICE simulation, clear watchdog timer using @RST_WDT macro is necessary. Or
the S8KD watchdog would be error.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
0CCH
WDTR
Read/Write
After reset
Bit 7
WDTR7
W
0
Bit 6
WDTR6
W
0
Bit 5
WDTR5
W
0
Bit 4
WDTR4
W
0
Bit 3
WDTR3
W
0
Bit 2
WDTR2
W
0
Bit 1
WDTR1
W
0
Bit 0
WDTR0
W
0
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
MOV
B0MOV
CALL
CALL
JMP
A, #5AH
WDTR, A
SUB1
SUB2
MAIN
Page 72
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Main:
@RST_WDT
CALL
CALL
JMP
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
www.DataSheet4U.com
z
Dont clear watchdog
timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
Err:
JMP $
; Check I/O.
; Check RAM
; I/O or RAM error. Program jump here and dont
; clear watchdog. Wait watchdog timer overflow to reset IC.
Correct:
B0BSET
CALL
CALL
JMP
FWDRST
SUB1
SUB2
MAIN
Page 73
Version 0.3
SN8P2604A
8-Bit Micro-Controller
8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
Green mode wakeup function: T0 can be green mode wake-up time as T0ENB = 1. System will be wake-up by
T0 time out.
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T0 Rate
(Fcpu/2~Fcpu/256)
T0ENB
Fcpu
T0 Time Out
CPUM0,1
Bit 7
T0ENB
R/W
0
Bit 6
T0rate2
R/W
0
Bit 5
T0rate1
R/W
0
Bit [6:4]
110 = fcpu/4.
111 = fcpu/2.
Bit 7
Bit 4
T0rate0
R/W
0
Page 74
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Bit 7
T0C7
R/W
0
Bit 6
T0C6
R/W
0
Bit 5
T0C5
R/W
0
Bit 4
T0C4
R/W
0
Bit 3
T0C3
R/W
0
Bit 2
T0C2
R/W
0
Bit 1
T0C1
R/W
0
Bit 0
T0C0
R/W
0
Example: To set 10ms interval time for T0 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select
T0RATE=010 (Fcpu/64).
T0C initial value = 256 - (T0 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10-2 * 4 * 106 / 4 / 64)
= 100
= 64H
Page 75
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Stop T0 timer counting, disable T0 interrupt function and clear T0 interrupt request flag.
B0BCLR
B0BCLR
B0BCLR
FT0ENB
FT0IEN
FT0IRQ
; T0 timer.
; T0 interrupt function is disabled.
; T0 interrupt request flag is cleared.
MOV
A, #0xxx0000b
B0MOV
T0M,A
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FT0IEN
FT0ENB
; Enable T0 timer.
A,#7FH
T0C,A
Enable T0 timer.
B0BSET
Page 76
Version 0.3
SN8P2604A
8-Bit Micro-Controller
TC1OUT
Internal P5.3 I/O Circuit
ALOAD1
Buzzer
Auto. Reload
TC1 / 2
P5.3
TC1R Reload
Data Buffer
R
TC1 Rate
(Fcpu/2~Fcpu/256)
TC1CKS
Compare
TC1ENB
PWM1OUT
PWM
S
Load
Fcpu
TC1C
8-Bit Binary Up
Counting Counter
INT1
(Schmitter Trigger)
CPUM0,1
Page 77
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Bit 7
TC1ENB
R/W
0
Bit 6
TC1rate2
R/W
0
Bit 5
TC1rate1
R/W
0
Bit 4
TC1rate0
R/W
0
Bit 3
TC1CKS
R/W
0
Bit 2
ALOAD1
R/W
0
Bit 1
TC1OUT
R/W
0
Bit 0
Bit 1
TC1OUT: TC1 time out toggle signal output control bit. Only valid when PWM1OUT = 0.
0 = Disable, P5.3 is I/O function.
1 = Enable, P5.3 is output TC1OUT signal.
Bit 2
Bit 0
PWM1OUT
R/W
0
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0 = Disable
Bit 3
Bit [6:4]
110 = fcpu/4.
111 = fcpu/2.
Bit 7
Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1
interrupt request will be raised. (P0.1IRQ will be always 0).
Page 78
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Bit 7
TC1C7
R/W
0
Bit 6
TC1C6
R/W
0
Bit 5
TC1C5
R/W
0
Bit 4
TC1C4
R/W
0
Bit 3
TC1C3
R/W
0
Bit 2
TC1C2
R/W
0
Bit 1
TC1C1
R/W
0
Bit 0
TC1C0
R/W
0
Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0). High clock is
external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).
TC1C initial value = 256 - (TC1 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10-2 * 4 * 106 / 4 / 64)
= 100
= 64H
Page 79
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Bit 7
TC1R7
W
0
Bit 6
TC1R6
W
0
Bit 5
TC1R5
W
0
Bit 4
TC1R4
W
0
Bit 3
TC1R3
W
0
Bit 2
TC1R2
W
0
Bit 1
TC1R1
W
0
Bit 0
TC1R0
W
0
N is TC1 overflow boundary number. TC1 timer overflow time has five types (TC1 timer, TC1 event counter, TC1 Fcpu
clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time and valid value as follow
table.
TC1CKS PWM1 ALOAD1 TC1OUT
0
1
1
1
1
-
x
0
0
1
1
-
x
0
1
0
1
-
N
256
256
64
32
16
256
TC1R valid
value
0x00~0xFF
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
0x00~0xFF
TC1R value
binary type
00000000b~11111111b
00000000b~11111111b
xx000000b~xx111111b
xxx00000b~xxx11111b
xxxx0000b~xxxx1111b
00000000b~11111111b
Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM
output (PWM1=0). High clock is external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).
Page 80
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Example: Setup TC1OUT output from TC1 to TC1OUT (P5.3). The external high-speed clock is 4MHz. The
TC1OUT frequency is 0.5KHz. Because the TC1OUT signal is divided by 2, set the TC1 clock to 1KHz. The
TC1 clock source is from external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110.
TC1C = TC1R = 131.
MOV
B0MOV
A,#01100000B
TC1M,A
MOV
B0MOV
B0MOV
A,#131
TC1C,A
TC1R,A
B0BSET
B0BSET
B0BSET
FTC1OUT
FALOAD1
FTC1ENB
Page 81
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Stop TC1 timer counting, disable TC1 interrupt function and clear TC1 interrupt request flag.
B0BCLR
B0BCLR
B0BCLR
FTC1ENB
FTC1IEN
FTC1IRQ
A, #0xxx0000b
B0MOV
TC1M,A
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) Set TC1 timer
clock source.
FALOAD1
B0BSET
FALOAD1
or
)
Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty cycle.
; Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty.
MOV
A,#7FH
; TC1C and TC1R value is decided by TC1 mode.
B0MOV
TC1C,A
; Set TC1C value.
B0MOV
TC1R,A
; Set TC1R value under auto reload mode or PWM mode.
; In PWM mode, set PWM cycle.
B0BCLR
B0BCLR
or
B0BCLR
B0BSET
or
B0BSET
B0BCLR
or
B0BSET
B0BSET
FALOAD1
FTC1OUT
FALOAD1
FTC1OUT
FALOAD1
FTC1OUT
FALOAD1
FTC1OUT
Page 82
Version 0.3
SN8P2604A
8-Bit Micro-Controller
FTC1IEN
B0BSET
FTC1OUT
B0BSET
FPWM1OUT
FTC1ENB
or
or
)
Example: TC1C = 0xFF and TC1IRQ = 0. TC1IRQ will set as 1 when TC1C is cleared by program (TC1C =
0).
MOV
B0MOV
A, #0
TC1C, A
; Clear TC1C.
; TC1IRQ changed from 0 to 1.
B0BSET
FTC1IEN
If TC1C changing in system operating duration is necessary, to disable TC1 interrupt function (TC1IEN = 0) before
changing TC1C value. The solution can avoid unexpected TC1 interrupt occurring and example is as following.
Example: TC1C = 0xFF and TC1IRQ = 0. Clearing TC1C must be after TC1 interrupt disable.
B0BCLR
FTC1IEN
MOV
B0MOV
A, #0
TC1C, A
; Clear TC1C.
; TC1IRQ changed from 0 to 1.
B0BCLR
FTC1IRQ
B0BSET
FTC1IEN
Note: Disable TC1 interrupt function first, and load new TC1C value into TC1C buffer. This way can avoid
unexpected TC1 interrupt occurring.
Page 83
Version 0.3
SN8P2604A
8-Bit Micro-Controller
8.4.1
OVERVIEW
PWM function is generated by TC1 timer counter and output the PWM signal to PWM1OUT pin (P5.3). The 8-bit
counter counts modulus 256, 64, 32, 16 controlled by ALOAD1, TC1OUT bits. The value of the 8-bit counter (TC1C) is
compared to the contents of the reference register (TC1R). When the reference register value (TC1R) is equal to the
counter value (TC1C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The
low-to-high ratio (duty) of the PWM1 output is TC1R/256, 64, 32, 16.
0
1
0
1
MAX. PWM
Frequency
(Fcpu = 4MHz)
7.8125K
31.25K
62.5K
125K
0/256~255/256
0/64~63/64
0/32~31/32
0/16~15/16
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
Remark
Overflow per 256 count
Overflow per 64 count
Overflow per 32 count
Overflow per 16 count
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The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256.
0
128
254
255
128
254
255
TC1 Clock
TC1R=00H
Low
High
TC1R=01H
TC1R=80H
TC1R=FFH
Low
High
Low
High
Low
Page 84
Version 0.3
SN8P2604A
8-Bit Micro-Controller
8.4.2
In PWM mode, the frequency of TC1IRQ is depended on PWM duty range. From following diagram, the TC1IRQ
frequency is related with PWM duty.
TC1 Overflow,
TC1IRQ = 1
0xFF
TC1C Value
0x00
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PWM1 Output
(Duty Range 0~255)
PWM1 Output
(Duty Range 0~63)
PWM1 Output
(Duty Range 0~31)
PWM1 Output
(Duty Range 0~15)
Page 85
Version 0.3
SN8P2604A
8-Bit Micro-Controller
8.4.3
Example: Setup PWM1 output from TC1 to PWM1OUT (P5.3). The external high-speed oscillator clock is 4MHz.
Fcpu = Fosc/4. The duty of PWM is 30/256. The PWM frequency is about 1KHz. The PWM clock source is
from external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 30.
MOV
B0MOV
A,#01100000B
TC1M,A
MOV
B0MOV
B0MOV
A,#30
TC1C,A
TC1R,A
FTC1OUT
FALOAD1
FPWM1OUT
FTC1ENB
B0BCLR
B0BCLR
B0BSET
B0BSET
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Note: The TC1R is write-only register. Dont process them using INCMS, DECMS instructions.
MOV
B0MOV
A, #30H
TC1R, A
INCMS
NOP
B0MOV
B0MOV
BUF0
; Get the new TC1R value from the BUF0 buffer defined by
; programming.
A, BUF0
TC1R, A
Page 86
Version 0.3
SN8P2604A
8-Bit Micro-Controller
8.4.4
In PWM mode, the system will compare TC1C and TC1R all the time. When TC1C<TC1R, the PWM will output logic
High, when TC1CTC1R, the PWM will output logic Low. If TC1C is changed in certain period, the PWM duty will
change immediately. If TC1R is fixed all the time, the PWM waveform is also the same.
TC1C = TC1R
TC1C overflow
and TC1IRQ set
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0xFF
TC1C Value
0x00
PWM1 Output
Period
Above diagram is shown the waveform with fixed TC1R. In every TC1C overflow PWM output High, when TC1C
TC1R PWM output Low.
Note: Setting PWM duty in program processing must be at the new cycle start.
Page 87
Version 0.3
SN8P2604A
8-Bit Micro-Controller
If TC1R is changing in the program processing, the PWM waveform will became as following diagram.
TC1C < TC1R
PWM Low > High
TC1C > = TC1R
PWM High > Low
TC1C overflow
and TC1IRQ set
Update New TC1R!
Old TC1R < TC1C < New TC1R
Old TC1R
0xFF
New TC1R
New TC1R
Old TC1R
TC1C Value
0x00
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PWM1 Output
Period
1
1st PWM
2
Update PWM Duty
3
2nd PWM
4
Update PWM Duty
5
3th PWM
In period 2 and period 4, new Duty (TC1R) is set, but the PWM output waveform of period 2 and period 4 are wrong. In
period 2, the new TC1R value is greater than old TC1R value. If setting new TC1R is after PWM output low, system is
getting TC1C < TC1R result and making PWM output high. There are two high level periods in the cycle, and the
waveform is unexpected. Until next cycle, PWM outputs correct duty. In period 4, the new TC1R value is smaller than
the old TC1R value. If setting new TC1R is before PWM output low, system is getting TC1CTC1R result and
making PWM output low. In the cycle, the high duty is shorter than last cycle and longer than correct cycle. It is an
unexpected PWM output.
Though the wrong waveforms only exist in one cycle, it is still a problem for precise PWM application and might make
outside loading operations error. The solution is to load new TC1R after TC1 timer overflow. Using TC1IRQ status to
determine TC1 timer is overflow or not. When TC1IRQ becomes 1, to set the new TC1R value into TC1R buffer, and
the unexpected PWM output is resolved.
Example: Using TC1 interrupt function to set new TC1R value for changing PWM duty.
MAIN:
B0MOV
TC1RBUF, A
INT_SER:
B0BTS1
JMP
B0MOV
B0MOV
INT_SER90:
RETI
Page 88
Version 0.3
SN8P2604A
8-Bit Micro-Controller
9
Field
M
O
V
E
INSTRUCTION TABLE
Mnemonic
MOV
A,M
MOV
M,A
B0MOV
A,M
B0MOV
M,A
MOV
A,I
B0MOV
M,I
XCH
A,M
B0XCH
A,M
MOVC
P
R
O
C
E
S
S
B
R
A
N
C
H
C
-
DC
-
Cycle
1
1
1
1
1
1
1+N
1+N
2
1
1+N
1
1+N
1+N
1
1
1+N
1
1+N
1
1
1+N
1
1
1+N
1
1
1+N
1
1
1+N
1
1+N
1
1+N
1
1+N
1+N
1+N
1+N
AND
AND
AND
OR
OR
OR
XOR
XOR
XOR
A,M
M,A
A,I
A,M
M,A
A,I
A,M
M,A
A,I
A A and M
M A and M
A A and I
A A or M
M A or M
A A or I
A A xor M
M A xor M
A A xor I
SWAP
SWAPM
RRC
RRCM
RLC
RLCM
CLR
BCLR
BSET
B0BCLR
B0BSET
M
M
M
M
M
M
M
M.b
M.b
M.b
M.b
CMPRS
CMPRS
INCS
INCMS
DECS
DECMS
BTS0
BTS1
B0BTS0
B0BTS1
JMP
CALL
A,I
A,M
M
M
M
M
M.b
M.b
M.b
M.b
d
d
1+S
1+S
1+ S
1+N+S
1+ S
1+N+S
1+S
1+S
1+S
1+S
2
2
2
2
1
1
1
ADC
A,M
A
ADC
M,A
R
ADD
A,M
I
ADD
M,A
www.DataSheet4U.com
T
B0ADD
M,A
H
ADD
A,I
M
SBC
A,M
E
SBC
M,A
T
SUB
A,M
I
SUB
M,A
C
SUB
A,I
L
O
G
I
C
Description
AM
MA
A M (bank 0)
M (bank 0) A
AI
M I, M only supports 0x80~0x87 registers (e.g. PFLAG,R,Y,Z)
A M
A M (bank 0)
R, A ROM [Y,Z]
RET
PC Stack
RETI
PC Stack, and to enable global interrupt
PUSH
To push ACC and PFLAG (except NT0, NPD bit) into buffers.
POP
To pop ACC and PFLAG (except NT0, NPD bit) from buffers.
NOP
No operation
Note: 1. M is system register or RAM. If M is system registers then N = 0, otherwise N = 1.
2. If branch condition is true then S = 1, otherwise S = 0.
M
I
S
C
Page 89
Version 0.3
SN8P2604A
8-Bit Micro-Controller
10 ELECTRICAL CHARACTERISTIC
10.1 ABSOLUTE MAXIMUM RATING
Supply voltage (Vdd). - 0.3V ~ 6.0V
Input in voltage (Vin). Vss 0.2V ~ Vdd + 0.2V
Operating ambient temperature (Topr)
SN8P2604AK, SN8P2604AS, SN8P2604AX ... 0C ~ + 70C
SN8P26042AP, SN8P26042AS, SN8P26042AX ... 0C ~ + 70C
SN8P2604AKD, SN8P2604ASD, SN8P2604AXD . 40C ~ + 85C
SN8P26042APD, SN8P26042ASD, SN8P26042AXD . 40C ~ + 85C
Storage ambient temperature (Tstor) . 40C ~ + 125C
Operating voltage
Vdd
Vdr
Vpor
ViL1
ViL2
ViH1
2.4
5.0
5.5
2.5
1.5
0.05
Vss
Vss
0.7Vdd
5.0
-
5.5
0.3Vdd
0.2Vdd
Vdd
V
V
V/ms
V
V
V
UNIT
ViH2
Reset pin
0.9Vdd
Vdd
Ilekg
Rup
Ilekg
IoH
IoL
Tint0
100
50
8
8
2/fcpu
-
200
100
12
15
2.5
2
300
180
2
5
uA
Vin = Vdd
Vin = Vss , Vdd = 3V
Vin = Vss , Vdd = 5V
Pull-up resistor disable, Vin = Vdd
Vop = Vdd 0.5V
Vop = Vss + 0.5V
INT0 interrupt request pulse width
Vdd= 5V, 4Mhz
Run Mode
(No loading,
Vdd= 3V, 4Mhz
Fcpu = Fosc/4)
Slow Mode
Vdd= 5V, 32Khz
(Internal low RC, Stop
Vdd= 3V, 16Khz
high clock)
Vdd= 5V, 25C
Vdd= 3V, 25C
Sleep Mode
Vdd= 5V, -40C~85C
Vdd= 3V, -40C~85C
Vdd= 5V, 4Mhz
Green Mode
Vdd= 3V, 4Mhz
(No loading,
Vdd=5V, ILRC 32Khz
Fcpu = Fosc/4)
Vdd=3V, ILRC 16Khz
Low voltage reset level.
Low voltage reset level. Fcpu = 1 MHz.
Low voltage indicator level. Fcpu = 1 MHz.
Low voltage indicator level. Fcpu = 1 MHz
cycle
mA
Idd1
Idd2
Supply Current
Idd3
Idd4
Vdet0
LVD Voltage
Vdet1
Vdet2
K
uA
mA
mA
25
50
uA
10
uA
1
0.70
10
10
0.60
2
1.5
21
21
1.2
uA
uA
uA
uA
mA
0.25
0.5
mA
1.6
15
3
2.0
30
6
2.3
uA
uA
V
2.0
2.3
2.7
3.3
4.5
Page 90
Version 0.3
SN8P2604A
8-Bit Micro-Controller
11 DEVELOPMENT TOOL
SN8P2604A development tools are as following.
z
z
z
www.DataSheet4U.com
1 VDD
3 CLK/PGCLK
5 PGM/OTPCLK
7 D1
9 D3
11 D5
13 D7
15 VDD
17 HLS
19 -
Page 91
Version 0.3
SN8P2604A
8-Bit Micro-Controller
Page 92
Version 0.3
SN8P2604A
8-Bit Micro-Controller
13 PACKAGE INFORMATION
13.1 SK-DIP 28 PIN
www.DataSheet4U.com
SYMBOLS
MIN
NOR
MAX
MIN
(inch)
A
A1
A2
D
E
E1
L
0.015
0.114
1.390
MAX
(mm)
0.210
0.135
1.400
0.381
2.896
35.306
0.283
0.115
0.130
1.390
0.310
0.288
0.130
0.293
0.150
0.330
0.350
NOR
5.334
3.429
35.560
7.188
2.921
3.302
35.306
7.874
7.315
3.302
0.370
8.382
8.890
9.398
15
15
Page 93
7.442
3.810
Version 0.3
SN8P2604A
8-Bit Micro-Controller
www.DataSheet4U.com
SYMBOLS
A
A1
D
E
H
L
MIN
NOR
MAX
MIN
(inch)
0.093
0.004
0.697
0.291
0.394
0.016
0
0.099
0.008
0.705
0.295
0.407
0.033
4
NOR
MAX
(mm)
0.104
0.012
0.713
0.299
0.419
0.050
8
Page 94
2.362
0.102
17.704
7.391
10.008
0.406
0
2.502
0.203
17.907
7.493
10.325
0.838
4
2.642
0.305
18.110
7.595
10.643
1.270
8
Version 0.3
SN8P2604A
8-Bit Micro-Controller
www.DataSheet4U.com
SYMBOLS
A
A1
A2
b
C
D
E
E1
[e]
L
R
MIN
NOR
MAX
MIN
(inch)
MAX
(mm)
0.00
0.06
0.01
0.00
0.39
0.29
0.20
0.07
0.40
0.31
0.21
0.0259BSC
0.08
0.01
0.07
0.01
0.01
0.41
0.32
0.22
0.05
1.63
0.22
0.09
9.90
7.40
5.00
0.02
0.00
0
0.04
4
0.04
8
0.63
0.09
0
NOR
Page 95
1.75
10.20
7.80
5.30
0.65BSC
0.90
4
2.13
0.25
1.88
0.38
0.20
10.50
8.20
5.60
1.03
8
Version 0.3
SN8P2604A
8-Bit Micro-Controller
www.DataSheet4U.com
SYMBOLS
MIN
NOR
MAX
MIN
(inch)
A
A1
A2
D
E
E1
L
0.015
0.125
0.980
MAX
(mm)
0.210
0.135
1.060
0.381
3.175
24.892
0.245
0.115
0.130
1.030
0.300
0.250
0.130
0.255
0.150
0.335
0.355
NOR
5.334
3.429
26.924
6.223
2.921
3.302
26.162
7.620
6.350
3.302
0.375
8.509
9.017
9.525
15
15
Page 96
6.477
3.810
Version 0.3
SN8P2604A
8-Bit Micro-Controller
www.DataSheet4U.com
SYMBOLS
A
A1
D
E
H
L
MIN
NOR
MAX
MIN
(inch)
0.093
0.004
0.496
0.291
0.394
0.016
0
0.099
0.008
0.502
0.295
0.407
0.033
4
NOR
MAX
(mm)
0.104
0.012
0.508
0.299
0.419
0.050
8
Page 97
2.362
0.102
12.598
7.391
10.008
0.406
0
2.502
0.203
12.751
7.493
10.325
0.838
4
2.642
0.305
12.903
7.595
10.643
1.270
8
Version 0.3
SN8P2604A
8-Bit Micro-Controller
www.DataSheet4U.com
SYMBOLS
A
A1
A2
b
c
D
E
E1
[e]
h
L
L1
ZD
Y
MIN
NOR
MAX
MIN
(inch)
0.053
0.004
0.008
0.007
0.337
0.228
0.150
0.010
0.016
0.039
0
0.063
0.006
0.010
0.008
0.341
0.236
0.154
0.025
0.017
0.025
0.041
0.059
-
NOR
MAX
(mm)
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
1.350
0.100
0.200
0.180
8.560
5.800
3.800
0.020
0.050
0.043
0.250
0.400
1.000
0.004
8
Page 98
1.600
0.150
0.254
0.203
8.660
6.000
3.900
0.635
0.420
0.635
1.050
1.500
-
1.750
0.250
1.500
0.300
0.250
8.740
6.200
4.000
0.500
1.270
1.100
0.100
8
Version 0.3
SN8P2604A
8-Bit Micro-Controller
14 Marking Definition
14.1
INTRODUCTION
There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit
MCU for order or obtain information. This definition is only for Blank OTP MCU.
14.2
www.DataSheet4U.com
Material
B = PB-Free Package
G = Green Package
Temperature
Range
- = 0 ~ 70
Shipping
Package
W = Wafer
H = Dice
K = SK-DIP
P = P-DIP
S = SOP
X = SSOP
Device
2604A
26042A
ROM
Type
P=OTP
Title
Page 99
D = -40 ~ 85
Version 0.3
SN8P2604A
8-Bit Micro-Controller
14.3
MARKING EXAMPLE
Name
SN8P2604AKDB
SN8P26042APB
ROM Type
OTP
OTP
Device
2604A
26042A
Package
SK-DIP
P-DIP
Temperature
-40~85
0~70
Material
PB-Free Package
PB-Free Package
X X X X XXXXX
SONiX Internal Use
www.DataSheet4U.com
1=01
2=02
....
9=09
A=10
B=11
....
Day
Month
Year
1=January
2=February
....
9=September
A=October
B=November
C=December
03= 2003
04= 2004
05= 2005
06= 2006
....
Page 100
Version 0.3
SN8P2604A
8-Bit Micro-Controller
www.DataSheet4U.com
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or
design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed,
intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a
situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such
unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries,
affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use
even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
Main Office:
Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C.
Tel: 886-3-551 0520
Fax: 886-3-551 0523
Taipei Office:
Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C.
Tel: 886-2-2759 1980
Fax: 886-2-2759 8180
Page 101
Version 0.3