Board Buses: System Buses (Also Referred To As "Main," "Local," or "Processor-Memory" Buses)

11.
BOARD BUSES
All of the other major components that make up an embedded board the master
processor, I/O components, and memory are interconnected via buses on the
embedded board.
As defined earlier, a bus is simply a collection of wires carrying various data
signals,
addresses,
and
control
signals
(clock
signals,
requests,
acknowledgements, data type, etc.) between all of the other major components on
the embedded board, which include the I/O subsystems, memory subsystem, and
the master processor.
On more complex boards, multiple buses can be integrated on one board. For
embedded boards with several buses connecting components that need to intercommunicate, bridges on the board connect the various buses and carry
information from one bus to another.
Fig 1: MPC620 board with bridge

In above Figure, the PowerManna PCI bridge is one such example.
A bridge can automatically provide a transparent mapping of address information
when data is transferred from one bus to another.
Board buses typically fall under one of three main categories: system buses,
backplane buses or I/O buses.
System buses (also referred to as main, local, or processor-memory buses)
interconnect external main memory and cache to the master CPU and/or any
bridges to the other buses. System buses are typically shorter, higher speed,
custom buses.
Backplane buses are also typically faster buses that interconnect memory, the
master processor, and I/O, all on one bus.
I/O buses, also referred to as expansion, external, or host buses, in effect

act as extensions of the system bus to connect the remaining components to the
master CPU, to each other, to the system bus via a bridge, and/or to the embedded
system itself, via an I/O communication port.
The major difference between system buses and I/O buses is the possible
presence of IRQ (interrupt request) control signals on an I/O bus.
There are a variety of ways I/O and the master processor can communicate, and
interrupts are one of the most common methods.
An IRQ line allows for I/O devices on a bus to indicate to the master processor
that an event has taken place or an operation has been completed by a signal on
that IRQ bus line.
Different I/O buses can have different impacts on interrupt schemes. An ISA bus,
for example, requires that each card that generates interrupts must be assigned its
own unique IRQ value.
The PCI bus, on the other hand, allows two or more I/O cards to share the same
IRQ value.
Within each bus category, buses can be further divided into whether the bus is
expandable or non-expandable.
An expandable bus (PCMCIA, PCI, IDE, SCSI, USB, and so on) is one in which
additional components can be plugged into the board on-the-fly.
Whereas a non-expandable bus (DIB, VME, I2C are examples) is one in which
additional components cannot be simply plugged into the board and then
communicate over that bus to the other components.
While systems implementing expandable buses are more flexible because
components can be added ad-hoc to the bus and work out of the box,
expandable buses tend to be more expensive to implement.
If the board is not initially designed with all of the possible types of components
that could be added in the future in mind, performance can be negatively
impacted by the addition of too many draining or poorly designed components
onto the expandable bus.
Bus Arbitration and Timing:

Associated with every bus is some type of protocol that defines how devices gain
access to the bus (arbitration), the rules attached devices must follow to
communicate over the bus (handshaking), and the signals associated with the
various bus lines.
Board devices obtain access to a bus using a bus arbitration scheme. Bus
arbitration is based upon devices being classified as either master devices or
slave devices.
For buses that allow for multiple masters, some have an arbitrator that
determines under what circumstances a master gets control of the bus.
There are several bus arbitration schemes used for embedded buses, the most
common being dynamic central parallel, centralized serial (daisy-chain), and
distributed self-selection.
Fig 2a: Dynamic central parallel arbitration
Fig 2b: FIFO-based arbitration
Fig 2c: Priority-based arbitration

Dynamic central parallel arbitration (fig 2a) is a scheme in which the arbitrator is
centrally located. All bus masters connect to the central arbitrator. In this scheme,
masters are then granted access to the bus via a FIFO (fig 2b) or priority-based
system (fig 2c).
The priority arbitration scheme differentiates between masters based upon their
relative importance to each other and the system. Basically, every master device
is assigned a priority, which acts as an indicator of order of precedence within the
system.
If the arbitrator implements a preemption priority-based scheme, the master with
the highest priority always can preempt lower priority master devices when they
want access to the bus, meaning a master currently accessing the bus can be
forced to relinquish it by the arbitrator if a higher priority master wants the bus.
Fig 3c shows three master devices (1, 2, 3 where master 1 is the lowest priority
device and master 3 is the highest) master 3 preempts master 2, and master 2
preempts master 1 for the bus.
Central-serialized arbitration, also referred to as daisy-chain arbitration, is a

scheme in which the arbitrator is connected to all masters, and the masters are
connected in serial.
Regardless of which master makes the request for the bus, the first master in the
chain is granted the bus, and passes the bus grant on to the next master in the
chain if/when the bus is no longer needed .
Fig 3: Distributed arbitration via self-selection

There are also distributed arbitration schemes, which means there is no central
arbitrator and no additional circuitry, as shown in fig 3.
In these schemes, masters arbitrate themselves by trading priority information to
determine if a higher priority master is making a request for the bus, or even by
removing all arbitration lines and waiting to see if there is a collision on the bus,
which means that the bus is busy with more than one master trying to use it.
Once a master device is granted the bus, only two devices a master and another
device in slave mode communicate over that bus at any given time. There are
only two types of transactions that a bus device can do READ (receive) and/or
WRITE (transmit).
These transactions can take place either between two processors (a master and
I/O controller, for example) or processor and memory (a master and memory, for
example).
Within each type of transaction, whether READ or WRITE, there can also be
several specific rules that each device needs to follow in order to complete a
transaction.
The basis of any bus handshake is ultimately determined by a buss timing
scheme. Buses are based upon one or some combination of synchronous or
asynchronous bus timing schemes, which allow for components attached to the
bus to synchronize their transmissions.
A synchronous bus includes a clock signal among the other signals it transmits,
such as data, address and other control information.
Components using a synchronous bus all are run at the same clock rate as the bus,
data is transmitted either on the rising edge or falling edge of a clock cycle.
An asynchronous bus, transmits no clock signal, but transmits other (non-clock

based) handshaking signals instead, such as request and acknowledgment
signals.
While the asynchronous scheme is more complex for devices having to

coordinate request commands, reply commands, and so on, an asynchronous bus
has no problem with the length of the bus or a larger number of components
communicating over the bus, because a clock is not the basis for synchronizing
communication.
Non-Expandable Bus: I2C Bus Example:

The I2C (Inter IC) bus interconnects processors that have incorporated an I 2C onchip interface, allowing direct communication between these processors over the
bus.
A master/slave relationship between these processors exists at all times, with the
master acting as a master transmitter or master receiver.
As shown in fig 6, the I 2C bus is a two-wire bus with one serial data line (SDA)
and one serial clock line (SCL). The processors connected via I 2C are each
addressable by a unique address that is part of the data stream transmitted
between devices.
The I2C master initiates data transfer and generates the clock signals to permit the
transfer. Basically, the SCL just cycles between HIGH and LOW (fig 7).
The master then uses the SDA line

(as SCL is cycling) to transmit data
to a slave. A session is started and
terminated as shown in fig 4, where
a START is initiated when the
master pulls the SDA port (pin)
LOW while the SCL signal is HIGH,
whereas a STOP condition is
initiated when the master pulls the
SDA port HIGH when SCL is
HIGH.
With regard to the transmission of
data, the I2C bus is a serial, 8-bit bus.
This means that, while there is no
limit on the number of bytes that can
be transmitted in a session, only one
byte (8 bits) of data will be moved at
any one time, 1 bit at a time
(serially).
Fig 4: I2C bus with SCL clock
How this translates into using the SDA and SCL signals is that a data bit is read
whenever the SCL signal moves from HIGH to LOW, edge to edge.
Fig 5a: SCL cycles
Fig 5b: I2C START and STOP conditions
If the SDA signal is HIGH at the point of an edge, then the data bit is read as a
1. If the SDA signal is LOW, the data bit read is a 0.
An example of byte 00000001 transfer is shown in fig 6a, while fig 6b shows
an example of a complete transfer session.
Fig 6a: I2C data transfer example
Fig 6b: I2C complete transfer diagram

Expandable Bus: PCI (Peripheral Component Interconnect) Bus Example:
Fig 7: PCI bus

The latest PCI specification at the time of writing, PCI Local Bus Specification
Revision 2.1, defines requirements (mechanical, electrical, timing, protocols, etc.)
of a PCI bus implementation.
PCI is a synchronous bus, meaning that it synchronizes communication using a
clock.
As shown in fig 7, the PCI bus has two connection interfaces: an internal PCI
interface that connects it to the main board (to bridges, processors, etc.) via EIDE
channels, and the expansion PCI interface, which consists of the slots into which
PCI adaptor cards (audio, video, etc.) plug.
Because the PCI bus allows for multiple bus masters (initiators of a bus
transaction), it implements a dynamic centralized, parallel arbitration scheme.
PCIs arbitration scheme basically uses the REQ# and GNT# signals to facilitate
communication between initiators and bus arbitrators.
In general, a PCI transaction is made up of five steps:

1. An initiator makes a bus request by asserting a REQ# signal to the central
arbitrator.
2. The central arbitrator does a bus grant to the initiator by asserting GNT# signal.
3. The address phase which begins when the initiator activates the FRAME# signal,
and then sets the C/BE[3:0]# signals to define the type of data transfer (memory
or I/O read or write). The initiator then transmits the address via the AD[31:0]
signals at the next clock edge.
4. After the transmission of the address, the next clock edge starts the one or more
data phases (the transmission of data). Data is also transferred via the AD[31:0]
signals. The C/BE[3:0], along with IRDY# and #TRDY signals, indicate if
transmitted data is valid.
5. Either the initiator or target can terminate a bus transfer through the desertion of
the #FRAME signal at the last data phase transmission. The STOP# signal also
acts to terminate all bus transactions.

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11.

Fig 1: MPC620 board with bridge

I/O buses, also referred to as expansion, external, or host buses, in effect

Bus Arbitration and Timing:

Fig 2a: Dynamic central parallel arbitration

Fig 2b: FIFO-based arbitration

Fig 2c: Priority-based arbitration

Central-serialized arbitration, also referred to as daisy-chain arbitration, is a

Fig 3: Distributed arbitration via self-selection

An asynchronous bus, transmits no clock signal, but transmits other (non-clock

While the asynchronous scheme is more complex for devices having to

Non-Expandable Bus: I2C Bus Example:

The master then uses the SDA line

Fig 5a: SCL cycles

Fig 5b: I2C START and STOP conditions

Fig 6a: I2C data transfer example

Fig 6b: I2C complete transfer diagram

Fig 7: PCI bus

In general, a PCI transaction is made up of five steps:

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