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    Combinational Circuits

    Uploaded by

    Shobith
    The document provides information on combinational logic circuits such as decoders, encoders, multiplexers, demultiplexers, adders and subtractors. It discusses their basic functions, truth tables, logic diagrams and applications. Priority encoders and ripple adders/subtractors are explained as cascading smaller components. Various codes for inputs and outputs like binary, gray and BCD are also covered. Block diagrams, timing diagrams and signal conventions are reviewed for clear documentation of digital designs.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Combinational Circuits

    Uploaded by

    Shobith
    34 views50 pages
    The document provides information on combinational logic circuits such as decoders, encoders, multiplexers, demultiplexers, adders and subtractors. It discusses their basic functions, truth tables, logic diagrams and applications. Priority encoders and ripple adders/subtractors are explained as cascading smaller components. Various codes for inputs and outputs like binary, gray and BCD are also covered. Block diagrams, timing diagrams and signal conventions are reviewed for clear documentation of digital designs.

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    Combinational Circuits

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    The document provides information on combinational logic circuits such as decoders, encoders, multiplexers, demultiplexers, adders and subtractors. It discusses their basic functions, truth tables, logic diagrams and applications. Priority encoders and ripple adders/subtractors are explained as cascading smaller components. Various codes for inputs and outputs like binary, gray and BCD are also covered. Block diagrams, timing diagrams and signal conventions are reviewed for clear documentation of digital designs.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    34 views50 pages

    Combinational Circuits

    Uploaded by

    Shobith
    The document provides information on combinational logic circuits such as decoders, encoders, multiplexers, demultiplexers, adders and subtractors. It discusses their basic functions, truth tables, logic diagrams and applications. Priority encoders and ripple adders/subtractors are explained as cascading smaller components. Various codes for inputs and outputs like binary, gray and BCD are also covered. Block diagrams, timing diagrams and signal conventions are reviewed for clear documentation of digital designs.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 50

    Combinational Circuits

    VLSI training

    ttm inc.,

    VLSI training

    ttm inc.,

    Block Diagram
    A block diagram should show all inputs and outputs , the building
    blocks and their function names , and the data flow paths ( the logic
    signals).
    - The internal details of each block need not be shown.
    - Related logic signals are combined together and drawn with a double
    or heavy line, known as a bus
    MIN/MAX

    Example: Min/Max Circuit

    X
    Y

    Comparator
    X>Y
    max(X,Y)

    Mux
    Mux
    Mux

    VLSI training

    min(X,Y)

    ttm inc.,

    Signal Names and Active Levels


    Input and output signals should be labeled either by variable names
    (X,Y, A,...) ,or by names that reflect actions or conditions (ENABLE,
    REQUEST, /READY, ERROR, PAUSE).
    Active level : active high. or active low.
    The signal is asserted when it is in its active level and negated ( or
    deasserted ) when its not in its active level.
    Active low signal has a prefix of / as part of the variable name.
    Example :
    - ERROR is active high means there is an error when the signal is
    HIGH ( logic 1).
    - /READY is active low means the data is ready when the signal is
    LOW ( logic 0).

    VLSI training

    ttm inc.,

    Active Levels for Pins


    In logic gates and logic structures the inversion bubble
    indicates the active level of the signal
    Examples:
    - 2-to- 4 Decoder
    - /EN is active low
    - A and B are active high

    / EN

    EN

    Y0

    / Y0

    Y1

    / Y1

    Y2

    / Y2

    Y3

    / Y3

    - /Y0, /Y1, /Y2,/Y3 are active low

    VLSI training

    ttm inc.,

    Timing Diagrams

    IN
    /ENABLE

    Logic
    Circuit

    OUT

    Delay depends on
    - Internal circuit structure
    - Logic Family type
    - Source Voltage
    - Temperature

    /ENABLE
    IN
    OUT

    tOUT

    /ENABLE
    IN
    OUT

    tOUTmin
    tOUTmax

    VLSI training

    ttm inc.,

    Propagation Delay
    The delay time between input transitions and the output
    transitions due to the propagation delay of the the logic
    gates.
    tp of a signal depends on the signal path inside the logic
    circuit
    For a logic gate tpLH may not equal tpHL
    tp is specified in the manufacturer data sheets of the ICs
    To find tp for a signal, add the propagation delays of all
    gates along the path of the signal

    VLSI training

    ttm inc.,

    Decoder

    Multiple-input / multiple-output device.


    Inputs ( n ) are less than outputs ( m ).
    Converts input code words into output
    code words.
    One-to-One mapping :
    - Each input code produces only one
    output code.
    Input codes :
    - Binary Code
    - Gray Code
    - BCD Code
    - Your Code !

    VLSI training

    input
    code
    DECODER

    output
    code

    enable
    inputs

    ttm inc.,

    Binary Decoder

    n-to-2^n decoder : n inputs and 2^n outputs.


    Input code : Binary Code.
    Output code : 1-out-of-2^n , One output is asserted for each input
    code.
    Example : n=2, 2-to-4 decoder
    Inputs
    Outputs
    EN I1 I0
    Y3 Y2 Y1 Y0
    0 x x
    0 0 0 0
    1 0 0
    0 0 0 1
    Y0
    I0
    1 0 1
    0 0 1 0
    Y1
    I1
    1 1 0
    0 1 0 0
    Y2
    1 1 1
    1 0 0 0
    EN
    Y3

    Logic Diagram???

    VLSI training

    ttm inc.,

    VLSI training

    ttm inc.,

    10

    A 3-to-8 decoder Truth table


    Inputs
    G1 /G2A /G2B
    0
    x
    x
    x
    1
    x
    x
    x
    1
    1
    0
    0
    1
    0
    0
    1
    0
    0
    1
    0
    0
    1
    0
    0
    1
    0
    0
    1
    0
    0
    1
    0
    0

    VLSI training

    C
    x
    x
    x
    0
    0
    0
    0
    1
    1
    1
    1

    B
    x
    x
    x
    0
    0
    1
    1
    0
    0
    1
    1

    A
    x
    x
    x
    0
    1
    0
    1
    0
    1
    0
    1

    Outputs
    /Y7 /Y6 /Y5 /Y4
    1
    1
    1 1
    1
    1
    1 1
    1
    1
    1 1
    1
    1
    1 1
    1
    1
    1 1
    1
    1
    1 1
    1
    1
    1 1
    1
    1
    1 0
    1
    1
    0 1
    1
    0
    1 1
    0
    1
    1 1

    /Y3 /Y2 /Y1 /Y0


    1
    1 1 1
    1
    1 1 1
    1
    1 1 1
    1
    1 1 0
    1
    1 0 1
    1
    0 1 1
    0
    1 1 1
    1
    1 1 1
    1
    1 1 1
    1
    1 1 1
    1
    1 1 1

    ttm inc.,

    11

    Logic design using Decoders


    Advantages :
    - Flexibility
    - Multiple-output Logic functions

    Disadvantages :
    - Complexity : for large number of inputs
    ( 5-variable Function with 3 minterms !
    F= ABCDE + ABCDE+ABCDE )

    VLSI training

    ttm inc.,

    12

    Seven-Segment Displays
    Displays decimal numbers and some characters
    LED (Light Emitting Diode ) or
    LCD (Liquid Crystal Display)
    LED type
    - Common Anode (CA) /Common Cathode (CC) type
    a
    b
    c
    d
    e
    f
    g

    a
    b
    c
    d
    e
    f
    g

    g
    e

    - CA : requires Active Low inputs (a driver with Active Low outputs )


    - CC : requires Active High inputs (a driver with Active High outputs )
    VLSI training

    ttm inc.,

    13

    Seven-Segment Decoders/Drivers
    Input Code : BCD Code
    Output Code : Seven-Segment Code
    Truth Table for Active High Seven-Segment Decoder/Driver
    Input
    Output
    D
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1

    C
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0

    B
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0

    VLSI training

    A
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1

    a
    1
    0
    1
    1
    0
    1
    0
    1
    1
    1

    b
    1
    1
    1
    1
    1
    0
    0
    1
    1
    1

    c
    1
    1
    0
    1
    1
    1
    1
    1
    1
    1

    d
    1
    0
    1
    1
    0
    1
    1
    0
    1
    0

    e
    1
    0
    1
    0
    0
    0
    1
    0
    1
    0

    f
    1
    0
    0
    0
    1
    1
    1
    0
    1
    1

    g
    0
    0
    1
    1
    1
    1
    1
    0
    1
    1

    b
    g

    ttm inc.,

    14

    Encoders
    Multiple-input/multiple-output device.
    output
    code

    Performs the inverse function of a Decoder. input


    code

    ENCODER

    Outputs ( m ) are less than inputs ( n ).


    Converts input code words into output
    code words.

    VLSI training

    ttm inc.,

    15

    Binary Encoder

    2^n-to-n encoder : 2^n inputs and n outputs.


    Input code : 1-out-of-2^n.
    Output code : Binary Code
    Example : n=3, 8-to-3 encoder
    I0
    1
    0
    0
    0
    0
    0
    0
    0

    I1
    0
    1
    0
    0
    0
    0
    0
    0

    Inputs
    I2 I3
    0
    0
    0
    0
    1
    0
    0
    1
    0
    0
    0
    0
    0
    0
    0
    0

    VLSI training

    I4
    0
    0
    0
    0
    1
    0
    0
    0

    I5
    0
    0
    0
    0
    0
    1
    0
    0

    I6
    0
    0
    0
    0
    0
    0
    1
    0

    I7
    0
    0
    0
    0
    0
    0
    0
    1

    Outputs
    Y0 Y1
    0
    0
    0
    0
    0
    1
    0
    1
    1
    0
    1
    0
    1
    1
    1
    1

    Binary encoder
    I0
    I1

    Y2
    0
    1
    0
    1
    0
    1
    0
    1

    I2

    Y0

    I3

    Y1

    I4

    Y2

    I5
    I6
    I7

    ttm inc.,

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    VLSI training

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    17

    Priority Encoder
    Assign priorities to the inputs
    When more than one input are asserted, the output generates the code
    of the input with the highest priority
    Priority encoder
    Priority Encoder :
    H7=I7
    (Highest Priority)
    H6=I6.I7
    H5=I5.I6.I7
    H4=I4.I5.I6.I7
    H3=I3.I4.I5.I6.I7
    H2=I2.I3.I4.I5.I6.I7
    H1=I1. I2.I3.I4.I5.I6.I7
    H0=I0.I1. I2.I3.I4.I5.I6.I7
    IDLE= I0.I1. I2.I3.I4.I5.I6.I7

    - Encoder
    Y0 = I1 + I3 + I5 + I7
    Y1 = I2 + I3 + I6 + I7
    Y2 = I4 + I5 + I6 + I7

    VLSI training

    Priority Circuit

    Binary encoder

    I0

    I0

    H0

    I0

    I1

    I1

    H1

    I1

    I2

    I2

    H2

    I2

    Y0

    Y0

    I3

    I3

    H3

    I3

    Y1

    Y1

    I4

    I4

    H4

    I4

    Y2

    Y2

    I5

    I5

    H5

    I5

    I6

    I6

    H6

    I6

    I7

    I7

    H7

    I7

    IDLE

    ttm inc.,

    IDLE

    18

    Encoder Application (Monitoring Unit)


    Alarm
    Signal

    Contoller
    Response

    Machine 1
    Machine 2

    Machine
    Code
    Encoder

    Action
    Controller

    Machine n

    VLSI training

    ttm inc.,

    19

    BCD Encoder (Application)


    +5V
    BCD encoder

    Switch 0

    I0

    7-segment
    decoder

    I1
    I2
    I3
    I4
    I5
    I6

    I7

    a
    Idle

    BI

    Y0

    Y1

    Y2

    Y3

    b
    c
    d
    e
    f

    I8

    Switch 9

    I9

    VLSI training

    ttm inc.,

    20

    Three State Buffers/Drivers


    A buffer/inverter with enable input

    Buffer
    Active High Enable

    Buffer
    Active Low Enable

    Inverter
    Active High Enable

    Inverter
    Active Low Enable

    The output is floating ( High Impedance, Hi-Z ) when the enable input is
    deasserted ( The input is isolated from the output )
    Application:
    Controlling the access of a single line/bus by multiple devices

    VLSI training

    ttm inc.,

    21

    8 data sources sharing one line


    P
    74x138
    EN1

    G1

    /EN2

    G2A

    /EN3

    G2B

    Y0
    Y1
    Y2
    Y3

    Y4

    S1

    Y5

    S2

    Y6

    S0

    Y7

    /SEL P

    /SEL Q
    /SEL R

    /SEL S
    /SEL T
    /SEL U
    /SEL V
    /SEL W

    T
    U
    V
    W

    VLSI training

    ttm inc.,

    22

    Multiplexers
    Multiplexing : Transmitting large number of signals over a small
    number of channels or lines
    Digital multiplexer (MUX ) : Selects one of many input lines and
    directs it to a single output.
    Selection lines control the selection of a particular input
    n selection lines, 2^n inputs , single output.
    Example : 4-to-1 line multiplexer :
    Function Table :
    I0
    S1 S0 Y
    I1 4 1
    0 0 I0
    Inputs
    Output
    Y
    0 1 I1
    I2 MUX
    1 0 I2
    I3 S1 S0
    1 1 I3
    Select
    VLSI training

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    VLSI training

    ttm inc.,

    24

    Realization of 4:1 MUX using 2:1 MUXes :

    I0
    I1

    0
    0

    1
    S0
    I2

    I3

    S1

    S0
    VLSI training

    ttm inc.,

    25

    Demultiplexers
    Demultiplexer (DMUX) performs the opposite function of a MUX.
    A digital Demultiplexer receives input data on a single input and
    transmits it on one of 2^n possible outputs according to the value of
    the n select inputs
    MUX/DMUX are used in data transmission
    Source
    Destination
    A

    B
    MUX

    BUS

    B
    DMUX

    Select
    VLSI training

    Select

    ttm inc.,

    26

    VLSI training

    ttm inc.,

    27

    Using Decoders as DMUX


    A DMUX has the same structure of a Decoder with enable input.
    Decoder can be used as a DMUX by connecting the input data to the
    enable input.
    Example :
    2-to-4 Decoder can be used as 1-to-4 DMUX

    S0

    I0

    Y0

    D0

    S1

    I1

    Y1

    D1

    Y2

    D2

    Y3

    D3

    INPUT

    VLSI training

    EN

    ttm inc.,

    28

    VLSI training

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    VLSI training

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    Adders/Subtractors

    Half Adder
    Full Adder
    Ripple Adder
    Carry look-ahead adder

    Full Subtractor
    Ripple Subtractor
    Adder/Subtractor Circuit

    VLSI training

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    VLSI training

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    VLSI training

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    Ripple Adder
    Cascade n Full Adders to get n-bit binary Adder

    X(n-1) Y(n-1)

    COUT

    COUT

    CIN

    S(n-1)

    VLSI training

    X1

    Y1

    X0

    Y0

    COUT

    S1

    CIN

    COUT

    CIN

    CIN

    S0

    ttm inc.,

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    VLSI training

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    35

    Ripple Subtractor
    Cascade n Subtractors to get n-bit binary Subtractor
    D= X-Y
    X(n-1) Y(n-1)

    BOUT

    BOUT

    BIN

    D(n-1)

    VLSI training

    X1

    Y1

    X0

    Y0

    BOUT

    D1

    BIN

    BOUT

    BIN

    BIN

    D0

    ttm inc.,

    36

    Using Adder as a Subtractor


    X,Y are n-bit unsigned binary numbers
    Addition : S = X + Y
    Subtraction : D = X - Y = X + (-Y) =
    = X+ (Twos Complement of Y)
    = X+ (Ones Complement of Y) + 1
    = X+ Y+ 1
    Ripple Adder can be used as a subtractor by inverting Y and setting the
    initial carry ( CIN ) to 1

    VLSI training

    ttm inc.,

    37

    VLSI training

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    38

    Carry Look-ahead Adder

    COUT

    X(n-1) Y(n-1)

    Y
    CLL

    I (n-1)

    X1

    Y1

    Y
    CLL

    I1

    X0

    Y0

    Y
    CLL

    S(n-1)

    S1

    S0

    CLL: Carry Look-ahead Logic


    I0=C0
    I i ????????

    VLSI training

    I0

    Carry Look-ahead Adder Units

    ttm inc.,

    39

    VLSI training

    ttm inc.,

    40

    Carry Look-ahead Logic


    We need to provide an expression for the ci in the Carry Lookahead Logic
    Unit
    Question : when does the Full adder produce carry ??
    Answer :
    If both Xi and Yi equal 1 ( carry is generated)
    OR....
    If Ci=1 and either Xi or Yi equal 1 ( carry is propagated )
    In Boolean algebra the above statement is expressed as :
    Ci+1= (Xi.Yi)+ (Xi+Yi).Ci { Compare to : COUT=XY+X CIN+Y CIN}
    Let gi= Xi.Yi
    pi= Xi+Yi
    Ci+1= gi+pi.Ci

    VLSI training

    ttm inc.,

    41

    Carry Look-ahead Logic


    Ci+1= gi+pi.Ci

    gi=Xi.Yi

    pi=xi+yi

    - C1=g0+p0.C0
    - C2=g1+p1.C1 = g1+p1.(g0+p0.C0)
    = g1+p1g0+p1.p0.C0
    - C3= g2+p2.C2 = g2+p2.(g1+p1g0+p1.p0.C0)
    = g2+p2.g1+p2.p1.g0+p2.p1.p0.C0
    - C4= .................

    C1, C2, C3, ..... are generated with almost the same amount of delay

    VLSI training

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    VLSI training

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    VLSI training

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    VLSI training

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    VLSI training

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    VLSI training

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    VLSI training

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