Combinational Circuits
Combinational Circuits
Combinational Circuits
VLSI training
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VLSI training
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Block Diagram
A block diagram should show all inputs and outputs , the building
blocks and their function names , and the data flow paths ( the logic
signals).
- The internal details of each block need not be shown.
- Related logic signals are combined together and drawn with a double
or heavy line, known as a bus
MIN/MAX
X
Y
Comparator
X>Y
max(X,Y)
Mux
Mux
Mux
VLSI training
min(X,Y)
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VLSI training
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/ EN
EN
Y0
/ Y0
Y1
/ Y1
Y2
/ Y2
Y3
/ Y3
VLSI training
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Timing Diagrams
IN
/ENABLE
Logic
Circuit
OUT
Delay depends on
- Internal circuit structure
- Logic Family type
- Source Voltage
- Temperature
/ENABLE
IN
OUT
tOUT
/ENABLE
IN
OUT
tOUTmin
tOUTmax
VLSI training
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Propagation Delay
The delay time between input transitions and the output
transitions due to the propagation delay of the the logic
gates.
tp of a signal depends on the signal path inside the logic
circuit
For a logic gate tpLH may not equal tpHL
tp is specified in the manufacturer data sheets of the ICs
To find tp for a signal, add the propagation delays of all
gates along the path of the signal
VLSI training
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Decoder
VLSI training
input
code
DECODER
output
code
enable
inputs
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Binary Decoder
Logic Diagram???
VLSI training
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VLSI training
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VLSI training
C
x
x
x
0
0
0
0
1
1
1
1
B
x
x
x
0
0
1
1
0
0
1
1
A
x
x
x
0
1
0
1
0
1
0
1
Outputs
/Y7 /Y6 /Y5 /Y4
1
1
1 1
1
1
1 1
1
1
1 1
1
1
1 1
1
1
1 1
1
1
1 1
1
1
1 1
1
1
1 0
1
1
0 1
1
0
1 1
0
1
1 1
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Disadvantages :
- Complexity : for large number of inputs
( 5-variable Function with 3 minterms !
F= ABCDE + ABCDE+ABCDE )
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Seven-Segment Displays
Displays decimal numbers and some characters
LED (Light Emitting Diode ) or
LCD (Liquid Crystal Display)
LED type
- Common Anode (CA) /Common Cathode (CC) type
a
b
c
d
e
f
g
a
b
c
d
e
f
g
g
e
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Seven-Segment Decoders/Drivers
Input Code : BCD Code
Output Code : Seven-Segment Code
Truth Table for Active High Seven-Segment Decoder/Driver
Input
Output
D
0
0
0
0
0
0
0
0
1
1
C
0
0
0
0
1
1
1
1
0
0
B
0
0
1
1
0
0
1
1
0
0
VLSI training
A
0
1
0
1
0
1
0
1
0
1
a
1
0
1
1
0
1
0
1
1
1
b
1
1
1
1
1
0
0
1
1
1
c
1
1
0
1
1
1
1
1
1
1
d
1
0
1
1
0
1
1
0
1
0
e
1
0
1
0
0
0
1
0
1
0
f
1
0
0
0
1
1
1
0
1
1
g
0
0
1
1
1
1
1
0
1
1
b
g
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Encoders
Multiple-input/multiple-output device.
output
code
ENCODER
VLSI training
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Binary Encoder
I1
0
1
0
0
0
0
0
0
Inputs
I2 I3
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
VLSI training
I4
0
0
0
0
1
0
0
0
I5
0
0
0
0
0
1
0
0
I6
0
0
0
0
0
0
1
0
I7
0
0
0
0
0
0
0
1
Outputs
Y0 Y1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Binary encoder
I0
I1
Y2
0
1
0
1
0
1
0
1
I2
Y0
I3
Y1
I4
Y2
I5
I6
I7
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Priority Encoder
Assign priorities to the inputs
When more than one input are asserted, the output generates the code
of the input with the highest priority
Priority encoder
Priority Encoder :
H7=I7
(Highest Priority)
H6=I6.I7
H5=I5.I6.I7
H4=I4.I5.I6.I7
H3=I3.I4.I5.I6.I7
H2=I2.I3.I4.I5.I6.I7
H1=I1. I2.I3.I4.I5.I6.I7
H0=I0.I1. I2.I3.I4.I5.I6.I7
IDLE= I0.I1. I2.I3.I4.I5.I6.I7
- Encoder
Y0 = I1 + I3 + I5 + I7
Y1 = I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 + I7
VLSI training
Priority Circuit
Binary encoder
I0
I0
H0
I0
I1
I1
H1
I1
I2
I2
H2
I2
Y0
Y0
I3
I3
H3
I3
Y1
Y1
I4
I4
H4
I4
Y2
Y2
I5
I5
H5
I5
I6
I6
H6
I6
I7
I7
H7
I7
IDLE
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IDLE
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Contoller
Response
Machine 1
Machine 2
Machine
Code
Encoder
Action
Controller
Machine n
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Switch 0
I0
7-segment
decoder
I1
I2
I3
I4
I5
I6
I7
a
Idle
BI
Y0
Y1
Y2
Y3
b
c
d
e
f
I8
Switch 9
I9
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Buffer
Active High Enable
Buffer
Active Low Enable
Inverter
Active High Enable
Inverter
Active Low Enable
The output is floating ( High Impedance, Hi-Z ) when the enable input is
deasserted ( The input is isolated from the output )
Application:
Controlling the access of a single line/bus by multiple devices
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G1
/EN2
G2A
/EN3
G2B
Y0
Y1
Y2
Y3
Y4
S1
Y5
S2
Y6
S0
Y7
/SEL P
/SEL Q
/SEL R
/SEL S
/SEL T
/SEL U
/SEL V
/SEL W
T
U
V
W
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Multiplexers
Multiplexing : Transmitting large number of signals over a small
number of channels or lines
Digital multiplexer (MUX ) : Selects one of many input lines and
directs it to a single output.
Selection lines control the selection of a particular input
n selection lines, 2^n inputs , single output.
Example : 4-to-1 line multiplexer :
Function Table :
I0
S1 S0 Y
I1 4 1
0 0 I0
Inputs
Output
Y
0 1 I1
I2 MUX
1 0 I2
I3 S1 S0
1 1 I3
Select
VLSI training
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I0
I1
0
0
1
S0
I2
I3
S1
S0
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Demultiplexers
Demultiplexer (DMUX) performs the opposite function of a MUX.
A digital Demultiplexer receives input data on a single input and
transmits it on one of 2^n possible outputs according to the value of
the n select inputs
MUX/DMUX are used in data transmission
Source
Destination
A
B
MUX
BUS
B
DMUX
Select
VLSI training
Select
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VLSI training
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S0
I0
Y0
D0
S1
I1
Y1
D1
Y2
D2
Y3
D3
INPUT
VLSI training
EN
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Adders/Subtractors
Half Adder
Full Adder
Ripple Adder
Carry look-ahead adder
Full Subtractor
Ripple Subtractor
Adder/Subtractor Circuit
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Ripple Adder
Cascade n Full Adders to get n-bit binary Adder
X(n-1) Y(n-1)
COUT
COUT
CIN
S(n-1)
VLSI training
X1
Y1
X0
Y0
COUT
S1
CIN
COUT
CIN
CIN
S0
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Ripple Subtractor
Cascade n Subtractors to get n-bit binary Subtractor
D= X-Y
X(n-1) Y(n-1)
BOUT
BOUT
BIN
D(n-1)
VLSI training
X1
Y1
X0
Y0
BOUT
D1
BIN
BOUT
BIN
BIN
D0
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COUT
X(n-1) Y(n-1)
Y
CLL
I (n-1)
X1
Y1
Y
CLL
I1
X0
Y0
Y
CLL
S(n-1)
S1
S0
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I0
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gi=Xi.Yi
pi=xi+yi
- C1=g0+p0.C0
- C2=g1+p1.C1 = g1+p1.(g0+p0.C0)
= g1+p1g0+p1.p0.C0
- C3= g2+p2.C2 = g2+p2.(g1+p1g0+p1.p0.C0)
= g2+p2.g1+p2.p1.g0+p2.p1.p0.C0
- C4= .................
C1, C2, C3, ..... are generated with almost the same amount of delay
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