EC 6302 2-Marks and 16 Marks Questions
EC 6302 2-Marks and 16 Marks Questions
EC 6302 2-Marks and 16 Marks Questions
Part B
1. a). i). Simplify the following function using K map, f=ABCD+ABCD+ABC+AB &
realize the SOP using only NAND gates and POS using only NOR gates
(12)
ii). Simplify the logic circuit shown in figure
(4)
2. a). i). Minimize the term using Quine McCluskey method & verify the result using Kmap method M(0,1,4,11,13,15)+ d(5,7,8).
(10)
ii). Explain the operation of 3 input TTL NAND gate with required diagram & truth
table.
(6)
3. a). i). Using K-map method, Simplify the following Boolean function and obtain
(a) minimal SOP and
(b) minimal POS expression & realize using only NAND and NOR gates
F=m(0,2,3,6,7) + d(8,10,11,15)
ii). Draw the circuits of 2 input NAND & 2 input NOR gate using CMOS
(10)
(6)
4. a). i). Using Quine McCluskey method Simplify the Boolean expression
F(v,w,x,y,z) = (4,5,9,11,12,14,15,27,30) +(1,17,25,26,31)
ii). Explain the working of a basic totem-pole TTL 2 input NAND gate.
(10)
(6)
(8)
(i). A+AB = A
(ii) A(A+B) = A
(iii) A+AB = A+B and
(iv) A(A+B) =AB
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9. (i). Compare & contrast the features of TTL & CMOS logic families.
(8)
(ii). List out the basic rules (laws) that are used in Boolean algebra expressions with
example.
(8)
10. Simplify using K-map to obtain minimum POS expression (A+B+C+D) (A+B+C+D)
(A+B+C+D) (A+B+C+D) (A+B+C+D) (A+B+C+D).
(16)
11. (i). Implement the expression Y (A, B, C) = M (0, 2, 4, 5, 6,) using only NOR-NOR
logic.
(8)
(ii). Draw the schematic and explain the operation of a CMOS inverter. Also explain its
characteristics.
(8)
12. (i). Express the Boolean function F=XY+XZ in product of maxterm.
(4)
(ii). Simplify the 5 variable switching function using Karnaugh map
(12)
f(EDCBA)=m(3,5,6,8,9,12,13,14,19,22,24,25,30).
UNIT II
COMBINATIONAL CIRCUITS
Part A
1. What is combinational circuit? Give examples.
2. Draw the block diagram of n-bit parallel adder
3. Write an expression for borrow and difference in a full Subtractor circuit.
4. Differentiate a decoder from a Demultiplexer.
5. Design Half adder using only NAND gates.
6. What is code converter? List their types.
7. Draw a logic diagram of 1 to 4 data distributor
8. Express Gray code 10111into binary numbers.
9. Implement full adder using multiplexer.
10. Draw the block diagram of a 2s complement 4 bit adder/ Subtractor.
11. Write the function table and logic diagram of a 4:1 data selector.
12. Implement the following function using suitable multiplexer F= m(0,2,5,7)
13. Relate carry generate, carry propagate, sum and carry-out of a carry look ahead adder.
14. Design a single bit magnitude comparator to compare two words A and B.
15. What is priority encoder?
16. Design a three bit even parity generator.
17. Draw the logic diagram of a serial adder.
18. Design a half subtractor combinational circuit to produce the outputs Difference and
Borrow.
19. Draw the logic diagram of a 2 bit multiplier.
20. Suggest a solution to overcome the limitation on the speed of an adder.
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Part B
1. (i). Implement the following function using suitable multiplexer F (A, B, C, D) = (1, 3,
4, 11, 12, 13, 14 , 15 )
(8)
(ii). Draw the logic diagram of a 2-bit by 2-bit binary multiplier and explain its operation.
(8)
2. Draw the block schematic of Magnitude comparator and explain its operation
(16)
3. Draw & explain the block diagram of a 4-bit parallel adder / Subtractor
(16)
4. Design & implement the conversion circuits for BCD to Excess 3 code.
(16)
(10)
(6)
(16)
(6)
(10)
8. Explain the operation of carry look ahead adder with neat diagram
(16)
(10)
(ii). Design a seven segment decoder circuit to display the numbers from 0 to 3.
(6)
10. (i).Design & explain the working of Gray to BCD converter.
(ii).Explain even parity checker and generator.
(10)
(6)
11. (i).Draw the logic diagram of BCD to Decimal decoder and explain its operations.
(10)
(ii).Design & explain the following circuits, (i) Comparator (ii) 4 to 1 Mux.
(6)
12. Draw & explain the block diagram of a 4-bit serial adder to add contents of two registers.
(16)
UNIT III
SEQUENTIAL CIRCUITS
Part A
1. Compare Asynchronous and Synchronous sequential logic.
2. Draw the state diagram and characteristics equation of a D FF.
3. What is latch? What is the difference between latch and flip flop?
4. Realize T Flip Flop using SR Flip Flop
5. How does the JK FF differ from an SR FF in its basic equation?
6. Define Synchronous counter.
7. Define Setup and Hold time.
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(8)
(8)
2. i).Design a 3 bit synchronous counter which counts in the sequence 000, 001, 011,
010,100, 110, (repeat) 000, using D flip flop.
ii).Analyze the logic diagram and draw the state diagram for the given logic.
(10)
(6)
(8)
(8)
(8)
(8)
(8)
(8)
(10)
(6)
7. Design a sequence detector which detects the sequence 01110 using D flip flop
(16)
8. (i).Explain the operation of universal shift register with neat block diagram.
(8)
(8)
9. i). Draw the logic diagram for a 5- bit serial load shift register using D FF & explain. (10)
ii). Write notes on state minimization.
(6)
10. Draw a 4-bit SISO SIPO, PIPO and PISO shift register and draw its waveforms
(16)
11. i). Draw an asynchronous decade counter & explain its operation with neat waveforms.(8)
ii). Design a 3-bit binary counter using T FF that has a repeated sequence of 6 states.
000-001-010-011-100-101-110. Give the state table, state diagram & logic diagram. (8)
12. i). Design and explain the working of a MOD-11 counter.
ii). Design a counter to count the sequence 0, 1, 2, 4, 5, 6,...using SR FFs
UNIT IV
MEMORY DEVICES
Part A
1. How the memories are classified.
2. What is an EPROM?
3. Compare and contrast static RAM and dynamic RAM
4. What is PLD? List their types.
5. Explain write operation with an example.
6. Distinguish between PAL and PLA.
7. Which memory is called volatile? Why?
8. Write the advantages of EPROM over a PROM.
9. Compare the features of PROM, PAL and PLA
10. What is access time and cycle time of a memory?
11. What is PLA? How does it differ from PAL and GAL?
12. What is memory decoding?
13. Implement the Exclusive-OR function using PROM
14. Write the advantages of E2PROM over an EPROM.
15. Implement the function F1= (0, 1, 2, 5, 7) and F2 = (1, 2, 4, 6) using PROM.
16. Draw the static and dynamic RAM cells.
17. Implement a 2-bit multiplier using ROM.
18. What is meant by memory expansion? Mention its limit.
19. Compare PLDs with FPGA.
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(8)
(8)
20. Draw the equivalent logic circuit of a binary memory cell that stores one bit of
information.
Part B
1. i). Give the classification of semiconductor memories
(8)
ii). Implement the following function using PLA F1= (2, 4, 5, 10, 12, 13, 14) and
F2 = (2, 9, 10, 11, 13, 14, 15).
(8)
(8)
(8)
(10)
ii). Implement the following function using PLA F1= (0, 1, 2, 4) and
F2 = (0, 5, 6, 7).
(6)
(8)
(8)
5. i). Explain read cycle and write cycle timing parameter with the help of timing
diagram.
(10)
F1 = ABC+ABC+ABC and
(6)
(8)
ii). Implement the following Boolean function using 342 PLA, F1(x, y, z) = (0, 1,
3, 5) and F2(x, y, z) = (3, 5, 7)
7. Design using PAL the following Boolean functions
(8)
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(8)
(8)
(8)
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(8)
10. i). Realize the following function using PLA F (w, x, y, z) = (0, 3, 5, 7, 12, 15)
+ d (2, 9).
(8)
ii.
iii.
iv.
(8)
(16)
(8)
ii). How can one make 64X8 ROM using 32X4 ROMs? Draw such a circuit & explain.
(8)
UNIT V
SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS
Part A
(16)
2. What is a Hazard? What are the types of hazards? Check whether the following
circuit contains a hazard or not Y = x1x2 + x2x3 2If the hazard is present,
demonstrate its removal
3.
(16)
Design a clocked sequential machine using JK flip flops for the state diagram shown
in figure. Use state reduction if possible and make proper state assignment.
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(16)
4. Derive the transition table, state table and state diagram for moor sequential circuit
shown in below figure.
(16)
5. Sequential circuit has three flip flops A, B, and C; one input x_in ; and one output
y_out. The state diagram is shown in below figure. The circuit is to be designed by
treating the unused states as dont care conditions. Analyze the circuit obtain from
the design to determine the effect of the unused states. Use T flip flops in the design.
(16)
6. i). Reduce the number of states in the following state table, and tabulate the reduced
state table.
(8)
Present State
Next State
Output
X=0
X =1
X =0
X=1
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ii). Analyze the synchronous sequential logic circuit and derive the transition table
and state diagram.
(8)
7. Design a clocked synchronous sequential machine using T flip flops for the following
state diagram. Use state reduction if possible .also use straight binary state assignment.
(16)
8. i).What is hazards? Give hazard free realization for the following Boolean function.
F(A, B, C, D) = m(0, 2, 6, 7, 8, 10, 12)
ii).Differentiate Moore and Mealy machines with block diagram
(10)
(6)
9. Derive the state table and state diagram of the sequential circuit shown in below
figure. Explain the function that the circuit performs.
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(16)
10. Design a clocked synchronous sequential logic circuit for the following state diagram.
Use state reduction if possible. (1) Using D flip flops (2) Using T flip flops
(16)
11. i). For the state diagram shown in below figure, design a synchronous sequential
circuit using JK flip flops.
(12)
(4)
12. i). What are static and dynamic hazards? Give static 0 hazard free realizations for
the following Boolean function. F(A, B, C, D) = M(3, 4, 5, 7, 9, 13, 14, 15).
ii). Write the design procedure for Asynchronous sequential logic circuits.
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