Verilog Examples

Encoders
Encoder - Using if-else Statement
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//----------------------------------------------------// Design Name : encoder_using_if

// File Name : encoder_using_if.v
// Function : Encoder using If
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module encoder_using_if(
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable
// Enable for the encoder
);
//-----------Output Ports--------------output [3:0] binary_out ;
//-----------Input Ports--------------input enable ;
input [15:0] encoder_in ;
//------------Internal Variables-------reg [3:0] binary_out ;
//-------------Code Start----------------always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
if (encoder_in == 16'h0002) begin
binary_out = 1;
end if (encoder_in == 16'h0004)
binary_out = 2;
binary_out = 3;
binary_out = 4;
binary_out = 5;
begin
begin
begin
begin
begin
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binary_out = 6;
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end if (encoder_in == 16'h0080) begin
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binary_out = 7;
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binary_out = 8;
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binary_out = 9;
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binary_out = 10;
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binary_out = 11;
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binary_out = 12;
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binary_out = 13;
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binary_out = 14;
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binary_out = 15;
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end
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end
56 end
57
58 endmodule
You could download file encoder_using_if.v here
Encoder - Using case Statement
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//----------------------------------------------------// Design Name : encoder_using_case

// File Name : encoder_using_case.v
// Function : Encoder using Case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module encoder_using_case(
binary_out , // 4 bit binary Output
encoder_in , // 16-bit Input
enable
);
output [3:0] binary_out ;
input enable ;
reg [3:0] binary_out ;
always @ (enable or encoder_in)
19 begin
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binary_out = 0;
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if (enable) begin
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case (encoder_in)
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16'h0002 : binary_out = 1;
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16'h0004 : binary_out = 2;
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16'h0008 : binary_out = 3;
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16'h0010 : binary_out = 4;
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16'h0020 : binary_out = 5;
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16'h0040 : binary_out = 6;
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16'h0080 : binary_out = 7;
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16'h0100 : binary_out = 8;
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16'h0200 : binary_out = 9;
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16'h0400 : binary_out = 10;
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16'h0800 : binary_out = 11;
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16'h1000 : binary_out = 12;
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16'h2000 : binary_out = 13;
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16'h4000 : binary_out = 14;
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16'h8000 : binary_out = 15;
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endcase
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end
40 end
41
42 endmodule
Priority Encoders
Pri-Encoder - Using if-else Statement
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//----------------------------------------------------// Design Name : pri_encoder_using_if

// File Name : pri_encoder_using_if.v
// Function : Pri Encoder using If
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module pri_encoder_using_if (
enable
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);
input enable ;
reg [3:0] binary_out ;
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
if (encoder_in[0] == 1) begin
binary_out = 1;
end else if (encoder_in[1] == 1) begin
binary_out = 2;
binary_out = 3;
binary_out = 4;
binary_out = 5;
binary_out = 6;
binary_out = 7;
binary_out = 8;
binary_out = 9;
binary_out = 10;
binary_out = 11;
binary_out = 12;
binary_out = 13;
binary_out = 14;
binary_out = 15;
end
end
end
endmodule
You could download file pri_encoder_using_if.v here
Encoder - Using assign Statement
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//----------------------------------------------------// Design Name : pri_encoder_using_assign

// File Name : pri_encoder_using_assign.v
// Function : Pri Encoder using assign
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module pri_encoder_using_assign (
enable
);
input enable ;
wire [3:0] binary_out ;
assign binary_out = ( ! enable) ? 0 : (
(encoder_in[0]) ? 0 :
(encoder_in[10]) ? 10 :
(encoder_in[11]) ? 11 :
(encoder_in[12]) ? 12 :
(encoder_in[13]) ? 13 :
(encoder_in[14]) ? 14 : 15);
endmodule
Decoders
Decoder - Using case Statement
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//----------------------------------------------------// Design Name : decoder_using_case

// File Name : decoder_using_case.v
// Function : decoder using case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module decoder_using_case (
binary_in
, // 4 bit binary input
decoder_out , // 16-bit out
enable
// Enable for the decoder
);
input [3:0] binary_in ;
input enable ;
output [15:0] decoder_out ;
reg [15:0] decoder_out ;
always @ (enable or binary_in)
begin
decoder_out = 0;
if (enable) begin
case (binary_in)
4'h0 : decoder_out = 16'h0001;
4'hA : decoder_out = 16'h0400;
4'hB : decoder_out = 16'h0800;
4'hC : decoder_out = 16'h1000;
4'hD : decoder_out = 16'h2000;
4'hE : decoder_out = 16'h4000;
4'hF : decoder_out = 16'h8000;
endcase
end
end
endmodule
You could download file decoder_using_case.v here
Decoder - Using assign Statement
1 //----------------------------------------------------2 // Design Name : decoder_using_assign

3 // File Name : decoder_using_assign.v
4 // Function : decoder using assign
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module decoder_using_assign (
8 binary_in
, // 4 bit binary input
9 decoder_out , // 16-bit out
10 enable
// Enable for the decoder
11 );
12 input [3:0] binary_in ;
13 input enable ;
14 output [15:0] decoder_out ;
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16 wire [15:0] decoder_out ;
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18 assign decoder_out = (enable) ? (1 <<
binary_in) : 16'b0 ;
19
20 endmodule
Mux : Using assign Statement
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//----------------------------------------------------// Design Name : mux_using_assign

// File Name : mux_using_assign.v
// Function : 2:1 Mux using Assign
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_assign(
din_0
, // Mux first input
din_1
, // Mux Second input
sel
, // Select input
mux_out
// Mux output
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);
//-----------Input Ports--------------input din_0, din_1, sel ;
//-----------Output Ports--------------output mux_out;
//------------Internal Variables-------wire mux_out;
//-------------Code Start----------------assign mux_out = (sel) ? din_1 : din_0;
endmodule //End Of Module mux
You could download file mux_using_assign.v here
Mux : Using if Statement
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//----------------------------------------------------// Design Name : mux_using_if

// File Name : mux_using_if.v
// Function : 2:1 Mux using If
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_if(
din_0
din_1
sel
, // Select input
mux_out
// Mux output
);
//------------Internal Variables-------reg mux_out;
//-------------Code Starts Here--------always @ (sel or din_0 or din_1)
begin : MUX
if (sel == 1'b0) begin
mux_out = din_0;
end else begin
mux_out = din_1 ;
end
end
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29 endmodule //End Of Module mux
You could download file mux_using_if.v here
Mux : Using case Statement
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//----------------------------------------------------// Design Name : mux_using_case

// File Name : mux_using_case.v
// Function : 2:1 Mux using Case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_case(
din_0
din_1
sel
, // Select input
mux_out
// Mux output
);
//------------Internal Variables-------reg mux_out;
//-------------Code Starts Here--------always @ (sel or din_0 or din_1)
begin : MUX
case(sel )
1'b0 : mux_out = din_0;
1'b1 : mux_out = din_1;
endcase
end
endmodule //End Of Module mux
D Flip-Flop
Asynchronous reset D- FF
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//----------------------------------------------------// Design Name : dff_async_reset

// File Name : dff_async_reset.v
// Function : D flip-flop async reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module dff_async_reset (
data , // Data Input
clk
, // Clock Input
reset , // Reset input
q
// Q output
);
//-----------Input Ports--------------input data, clk, reset ;
//-----------Output Ports--------------output q;
//------------Internal Variables-------reg q;
//-------------Code Starts Here--------always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_async_reset
You could download file dff_async_reset.v here
Synchronous reset D- FF
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//----------------------------------------------------// Design Name : dff_sync_reset

// File Name : dff_sync_reset.v
// Function : D flip-flop sync reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module dff_sync_reset (
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data
, // Data Input
clk
, // Clock Input
q
// Q output
);
//-------------Code Starts Here--------always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_sync_reset
T Flip-Flop
Asynchronous reset T - FF
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//----------------------------------------------------// Design Name : tff_async_reset

// File Name : tff_async_reset.v
// Function : T flip-flop async reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module tff_async_reset (
clk
, // Clock Input
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q
// Q output
);
//-------------Code Starts Here--------always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= ! q;
end
endmodule //End Of Module tff_async_reset
You could download file tff_async_reset.v here
Synchronous reset T - FF
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//----------------------------------------------------// Design Name : tff_sync_reset

// File Name : tff_sync_reset.v
// Function : T flip-flop sync reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module tff_sync_reset (
clk
, // Clock Input
q
// Q output
);
//-------------Code Starts Here--------always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= ! q;
end
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27 endmodule //End Of Module tff_async_reset
D latch
Regular D Latch
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//----------------------------------------------------// Design Name : dlatch_reset

// File Name : dlatch_reset.v
// Function : DLATCH async reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module dlatch_reset (
data
, // Data Input
en
, // LatchInput
q
// Q output
);
//-----------Input Ports--------------input data, en, reset ;
//-------------Code Starts Here--------always @ ( en or reset or data)
if (~reset) begin
q <= 1'b0;
end else if (en) begin
q <= data;
end
endmodule //End Of Module dlatch_reset
8-Bit Simple Up Counter
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//----------------------------------------------------// Design Name : up_counter

// File Name : up_counter.v
// Function : Up counter
// Coder : Deepak
//----------------------------------------------------module up_counter
(
out
, // Output of the counter
enable , // enable for counter
clk
, // clock Input
reset
// reset Input
);
//----------Output Ports-------------output [7:0] out;
//------------Input Ports-------------input enable, clk, reset;
//------------Internal Variables-------reg [7:0] out;
//-------------Code Starts Here------always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule
8-Bit Up Counter With Load
1 //-----------------------------------------------------
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// Design Name : up_counter_load

// File Name : up_counter_load.v
// Function : Up counter with load
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module up_counter_load
(
out
data
, // Parallel load for the counter
load
, // Parallel load enable
enable
, // Enable counting
clk
, // clock input
reset
// reset input
);
//------------Input Ports-------------input [7:0] data;
input load, enable, clk, reset;
if (reset) begin
out <= 8'b0 ;
end else if (load) begin
out <= data;
out <= out + 1;
end
endmodule
8-Bit Up-Down Counter
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//----------------------------------------------------// Design Name : up_down_counter

// File Name : up_down_counter.v
// Function : Up down counter
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module up_down_counter
(
out
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up_down , // up_down control for counter

clk
, // clock input
data
, // Data to load
reset
// reset input
);
input up_down, clk, reset;
if (reset) begin // active high reset
out <= 8'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= out - 1;
end
endmodule
Random Counter (LFSR)
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//----------------------------------------------------// Design Name : lfsr

// File Name : lfsr.v
// Function : Linear feedback shift register
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module lfsr
(
out
enable
, // Enable for counter
clk
, // clock input
reset
// reset input
);
input enable, clk, reset;
wire
linear_feedback;
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//-------------Code Starts Here------assign linear_feedback = ! (out[7] ^ out[3]);

always @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
out <= {out[6],out[5],
out[4],out[3],
out[2],out[1],
out[0], linear_feedback};
end
endmodule // End Of Module counter
You could download file lfsr.v here
LFSR Up/Down
1 `define WIDTH 8
2 module lfsr_updown (
3 clk
,
// Clock input
4 reset
,
// Reset input
5 enable
,
// Enable input
6 up_down
,
// Up Down input
7 count
,
// Count output
8 overflow
// Overflow output
9 );
10
11 input clk;
12 input reset;
13 input enable;
14 input up_down;
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16 output [`WIDTH-1 : 0] count;
17 output overflow;
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19 reg [`WIDTH-1 : 0] count;
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21 assign overflow = (up_down) ? (count ==
{{`WIDTH-1{1'b0}}, 1'b1}) :
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(count ==
{1'b1, {`WIDTH-1{1'b0}}}) ;
23
24 always @(posedge clk)
25 if (reset)
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count <= {`WIDTH{1'b0}};
27 else if (enable) begin

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if (up_down) begin
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count <= {~(^(count &
`WIDTH'b01100011)),count[`WIDTH-1:1]};
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end else begin
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count <= {count[`WIDTH-2:0],~(^(count &
`WIDTH'b10110001))};
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end
33 end
34
35 endmodule
You could download file lfsr_updown.v here
1 module tb();
2 reg clk;
3 reg reset;
4 reg enable;
5 reg up_down;
6
7 wire [`WIDTH-1 : 0] count;
8 wire overflow;
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10 initial begin
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$monitor("rst %b en %b updown %b cnt %b overflow
%b",
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reset,enable,up_down,count, overflow);
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clk = 0;
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reset = 1;
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enable = 0;
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up_down = 0;
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#10 reset = 0;
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#1 enable = 1;
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#20 up_down = 1;
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#30 $finish;
21 end
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23 always #1 clk = ~clk;
24
25 lfsr_updown U(
26 .clk
( clk
),
27 .reset
( reset
),
28 .enable
( enable
),
29 .up_down ( up_down ),
30 .count
( count
),
31 .overflow ( overflow )
32 );
33
34 endmodule
Gray Counter
1 //----------------------------------------------------2 // Design Name : gray_counter

3 // File Name : gray_counter.v
4 // Function : 8 bit gray counterS
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module gray_counter (
8
out
, // counter out
9
enable , // enable for counter
10
clk
, // clock
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rst
// active hight reset
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);
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//------------Input Ports-------------15
input clk, rst, enable;
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//----------Output Ports---------------17
output [ 7:0] out;
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//------------Internal Variables-------19
wire [7:0] out;
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reg [7:0] count;
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//-------------Code Starts Here--------22
always @ (posedge clk)
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if (rst)
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count <= 0;
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else if (enable)
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count <= count + 1;
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assign out = { count[7], (count[7] ^ count[6]),
(count[6] ^
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count[5]),(count[5] ^ count[4]),
(count[4] ^
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count[3]),(count[3] ^ count[2]),
(count[2] ^
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count[1]),(count[1] ^
count[0]) };
32
33 endmodule
One Hot Counter
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//----------------------------------------------------// Design Name : one_hot_cnt

// File Name : one_hot_cnt.v
// Function : 8 bit one hot counter
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module one_hot_cnt (
out
enable
, // enable for counter
clk
, // clock input
reset
// reset input
);
//------------Input Ports-------------input enable, clk, reset;
//-------------Code Starts Here------always @ (posedge clk)
if (reset) begin
out <= 8'b0000_0001 ;
out <= {out[6],out[5],out[4],out[3],
out[2],out[1],out[0],out[7]};
end
endmodule
Divide by 2 Counter
1 //----------------------------------------------------2 // Design Name : clk_div

3 // File Name : clk_div.v
4 // Function : Divide by two counter
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7
8 module clk_div (clk_in, enable,reset,
clk_out);
9 // --------------Port Declaration----------------------10 input

clk_in
11 input
reset
12 input
enable
13 output
clk_out
14 //--------------Port data type declaration------------15 wire
clk_in
16 wire
enable
17 //--------------Internal Registers---------------------18 reg
clk_out
;
19 //--------------Code Starts Here----------------------20 always @ (posedge clk_in)
21 if (reset) begin
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clk_out <= 1'b0;
23 end else if (enable) begin
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clk_out <= ! clk_out ;
25 end
26
27 endmodule
Divide By 3 Counter
This module divides the input clock frequency by 3
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//----------------------------------------------------// Design Name : divide_by_3

// File Name : divide_by_3.v
// Function : Divide By 3
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module divide_by_3 (
clk_in
, //Input Clock
reset
, // Reset Input
clk_out
// Output Clock
);
//-----------Input Ports--------------input clk_in;
input reset;
//-----------Output Ports--------------output clk_out;
//------------Internal Variables-------reg [1:0] pos_cnt;
reg [1:0] neg_cnt;
//-------------Code Start-----------------
;
;
;
;
;
;
21 // Posedge counter
22 always @ (posedge clk_in)
23 if (reset) begin
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pos_cnt <= 0;
25 end else begin
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pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;
27 end
28 // Neg edge counter
29 always @ (negedge clk_in)
30 if (reset) begin
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neg_cnt <= 0;
32 end else begin
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neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;
34 end
35
36 assign clk_out = ((pos_cnt ! = 2) && (neg_cnt ! =
2));
37
38 endmodule
39
40 // Testbench to check the divide_by_3 logic
41 module test();
42 reg reset, clk_in;
43 wire clk_out;
44 divide_by_3 U (
45
.clk_in (clk_in),
46
.reset (reset),
47
.clk_out (clk_out)
48 );
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50 initial begin
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clk_in = 0;
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reset = 0;
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#2 reset = 1;
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#2 reset = 0;
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#100 $finish;
56 end
57
58 always #1 clk_in = ~clk_in;
59
60 endmodule
Divide By 4.5 Counter
1 //----------------------------------------------------2 // Design Name : clk_div_45

3 // File Name : clk_div_45.v
4 // Function : Divide by 4.5
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module clk_div_45 (
8 clk_in, // Input Clock
9 enable, // Enable is sync with falling edge of clk_in
10 clk_out // Output Clock
11 );
12
13 // --------------Port Declaration----------------------14 input
clk_in
;
15 input
enable
;
16 output
clk_out
;
17
18 //--------------Port data type declaration------------19 wire
clk_in
;
20 wire
enable
;
21 wire
clk_out
;
22
23 //--------------Internal Registers---------------------24 reg
[3:0] counter1
;
25 reg
[3:0] counter2
;
26 reg
toggle1
;
27 reg
toggle2
;
28
29 //--------------Code Starts Here----------------------30 always @ (posedge clk_in)
31 if (enable == 1'b0) begin
32
counter1 <= 4'b0;
33
toggle1 <= 0;
34 end else if ((counter1 == 3 && toggle2) ||
(~toggle1 && counter1 == 4)) begin
35
counter1 <= 4'b0;
36
toggle1 <= ~toggle1;
37 end else
begin
38
counter1 <= counter1 + 1;
39 end
40
41 always @ (negedge clk_in)
42 if (enable == 1'b0) begin
43
counter2 <= 4'b0;
44
toggle2 <= 0;
45 end else if ((counter2 == 3 && ~toggle2) ||
(toggle2 && counter2 == 4)) begin
46
counter2 <= 4'b0;
47
toggle2 <= ~toggle2;
48 end else
begin
49
counter2 <= counter2 + 1;
50 end
51
52 assign clk_out = (counter1 <3 && counter2 < 3)
& enable;
53
54 endmodule
Single Port RAM Synchronous Read/Write
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//----------------------------------------------------// Design Name : ram_sp_sr_sw

// File Name : ram_sp_sr_sw.v
// Function : Synchronous read write RAM
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module ram_sp_sr_sw (
clk
, // Clock Input
address
, // Address Input
data
, // Data bi-directional
cs
, // Chip Select
we
, // Write Enable/Read Enable
oe
// Output Enable
);
parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports----------------------input
clk
input [ADDR_WIDTH-1:0] address
input
cs
input
we
input
oe
;
;
;
;
;
//--------------Inout Ports----------------------inout [DATA_WIDTH-1:0] data
//--------------Internal variables----------------
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reg [DATA_WIDTH-1:0] data_out ;

reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg
oe_r;
//--------------Code Starts Here-----------------// Tri-State Buffer control
// output : When we = 0, oe = 1, cs = 1
assign data = (cs && oe && ! we) ? data_out : 8'bz;
// Memory Write Block
// Write Operation : When we = 1, cs = 1
begin : MEM_WRITE
if ( cs && we ) begin
mem[address] = data;
end
end
// Memory Read Block
// Read Operation : When we = 0, oe = 1, cs = 1
begin : MEM_READ
if (cs && ! we && oe) begin
data_out = mem[address];
oe_r = 1;
end else begin
oe_r = 0;
end
end
endmodule // End of Module ram_sp_sr_sw
Single Port RAM Asynch Read, Synch Write
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//----------------------------------------------------// Design Name : ram_sp_ar_sw

// File Name : ram_sp_ar_sw.v
// Function : Asynchronous read write RAM
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module ram_sp_ar_sw (
clk
, // Clock Input
address
, // Address Input
data
cs
, // Chip Select
we
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oe
);
// Output Enable
//--------------Input Ports----------------------input
clk
22 input [ADDR_WIDTH-1:0] address ;

23 input
cs
;
24 input
we
;
25 input
oe
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//--------------Internal variables---------------reg [DATA_WIDTH-1:0]

data_out ;
begin : MEM_WRITE
end
end
always @ (address or cs or we or oe)
begin : MEM_READ
end
end
endmodule // End of Module ram_sp_ar_sw
Single Port RAM Asynchronous Read/Write
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//----------------------------------------------------// Design Name : ram_sp_ar_aw

// File Name : ram_sp_ar_aw.v
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module ram_sp_ar_aw (
address
, // Address Input
data
cs
, // Chip Select
we
oe
// Output Enable
);
//--------------Input Ports----------------------input [ADDR_WIDTH-1:0] address ;
input
cs
21 input
we
22 input
oe
;
;
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//--------------Internal variables---------------reg [DATA_WIDTH-1:0]

data_out ;
always @ (address or data or cs or we)
begin : MEM_WRITE
end
end
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always @ (address or cs or we or oe)
begin : MEM_READ
end
end
endmodule // End of Module ram_sp_ar_aw
Dual Port RAM Synchronous Read/Write
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//----------------------------------------------------// Design Name : ram_dp_sr_sw

// File Name : ram_dp_sr_sw.v
// Function : Synchronous read write RAM
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module ram_dp_sr_sw (
clk
, // Clock Input
address_0 , // address_0 Input
data_0
, // data_0 bi-directional
cs_0
, // Chip Select
we_0
oe_0
, // Output Enable
data_1
cs_1
, // Chip Select
we_1
oe_1
// Output Enable
);
parameter data_0_WIDTH = 8 ;
//--------------Input Ports----------------------input [ADDR_WIDTH-1:0] address_0 ;
input cs_0 ;
input we_0 ;
input oe_0 ;
input [ADDR_WIDTH-1:0] address_1 ;
input cs_1 ;
input we_1 ;
33 input oe_1 ;
34
35 //--------------Inout Ports----------------------36 inout [data_0_WIDTH-1:0] data_0 ;
37 inout [data_0_WIDTH-1:0] data_1 ;
38
39 //--------------Internal variables---------------40 reg [data_0_WIDTH-1:0] data_0_out ;
41 reg [data_0_WIDTH-1:0] data_1_out ;
42 reg [data_0_WIDTH-1:0] mem [0:RAM_DEPTH-1];
43
44 //--------------Code Starts Here-----------------45 // Memory Write Block
46 // Write Operation : When we_0 = 1, cs_0 = 1
47 always @ (posedge clk)
48 begin : MEM_WRITE
49
if ( cs_0 && we_0 ) begin
50
mem[address_0] <= data_0;
51
end else if (cs_1 && we_1) begin
52
53
end
54 end
55
56
57
58 // Tri-State Buffer control
59 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
60 assign data_0 = (cs_0 && oe_0 && ! we_0) ?
data_0_out : 8'bz;
61
62 // Memory Read Block
63 // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1
65 begin : MEM_READ_0
66
if (cs_0 && ! we_0 && oe_0) begin
67
data_0_out <= mem[address_0];
68
end else begin
69
data_0_out <= 0;
70
end
71 end
72
73 //Second Port of RAM
data_1_out : 8'bz;
77 // Memory Read Block 1
81
if (cs_1 && ! we_1 && oe_1) begin
82
83
end else begin
84
data_1_out <= 0;
85
end
86 end
87
88 endmodule // End of Module ram_dp_sr_sw
Dual Port RAM Asynchronous Read/Write
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//----------------------------------------------------// Design Name : ram_dp_ar_aw

// File Name : ram_dp_ar_aw.v
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module ram_dp_ar_aw (
data_0
cs_0
, // Chip Select
we_0
oe_0
, // Output Enable
data_1
cs_1
, // Chip Select
we_1
oe_1
// Output Enable
);
//--------------Input Ports----------------------input [ADDR_WIDTH-1:0] address_0 ;
input cs_0 ;
input we_0 ;
input oe_0 ;
input [ADDR_WIDTH-1:0] address_1 ;
input cs_1 ;
input we_1 ;
input oe_1 ;
//--------------Inout Ports----------------------inout [DATA_WIDTH-1:0] data_0 ;
inout [DATA_WIDTH-1:0] data_1 ;
//--------------Internal variables----------------
39 reg [DATA_WIDTH-1:0] data_0_out ;

40 reg [DATA_WIDTH-1:0] data_1_out ;
41 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
42
43 //--------------Code Starts Here-----------------44 // Memory Write Block
45 // Write Operation : When we_0 = 1, cs_0 = 1
46 always @ (address_0 or cs_0 or we_0 or data_0
47 or address_1 or cs_1 or we_1 or data_1)
48 begin : MEM_WRITE
49
if ( cs_0 && we_0 ) begin
50
51
end else if (cs_1 && we_1) begin
52
53
end
54 end
55
data_0_out : 8'bz;
59
60 // Memory Read Block
62 always @ (address_0 or cs_0 or we_1 or oe_0)
64
if (cs_0 && ! we_0 && oe_0) begin
65
66
end else begin
67
data_0_out <= 0;
68
end
69 end
70
71 //Second Port of RAM
data_1_out : 8'bz;
75 // Memory Read Block 1
77 always @ (address_1 or cs_1 or we_1 or oe_1)
79
if (cs_1 && ! we_1 && oe_1) begin
80
81
end else begin
82
data_1_out <= 0;
83
end
84 end
85
86 endmodule // End of Module ram_dp_ar_aw
ROM, EPROM, EEPROM
ROM/EPROM - Loading from File
1 //----------------------------------------------------2 // Design Name : rom_using_file

3 // File Name : rom_using_file.v
4 // Function : ROM using readmemh
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module rom_using_file (
8 address , // Address input
9 data
, // Data output
10 read_en , // Read Enable
11 ce
// Chip Enable
12 );
13 input [7:0] address;
14 output [7:0] data;
15 input read_en;
16 input ce;
17
18 reg [7:0] mem [0:255] ;
19
20 assign data = (ce && read_en) ? mem[address] :
8'b0;
21
22 initial begin
23
$readmemb("memory.list", mem); // memory_list
is memory file
24 end
25
26 endmodule
You could download file rom_using_file.v here
You can find the rom model and testbench here and
memory_list filehere.
rom_using_case
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//----------------------------------------------------// Design Name : rom_using_case

// File Name : rom_using_case.v
// Function : ROM using case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module rom_using_case (
address , // Address input
data
, // Data output
read_en , // Read Enable
ce
// Chip Enable
);
input [3:0] address;
output [7:0] data;
input read_en;
input ce;
reg [7:0] data ;
always @ (ce or read_en or address)
begin
case (address)
0 : data = 10;
1 : data = 55;
2 : data = 244;
3 : data = 0;
4 : data = 1;
5 : data = 8'hff;
6 : data = 8'h11;
7 : data = 8'h1;
8 : data = 8'h10;
9 : data = 8'h0;
10 : data = 8'h10;
11 : data = 8'h15;
12 : data = 8'h60;
13 : data = 8'h90;
14 : data = 8'h70;
15 : data = 8'h90;
endcase
end
41
42 endmodule
Synchronous FIFO
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//----------------------------------------------------// Design Name : syn_fifo

// File Name : syn_fifo.v
// Function : Synchronous (single clock) FIFO
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module syn_fifo (
clk
, // Clock input
rst
, // Active high reset
wr_cs
, // Write chip select
rd_cs
, // Read chipe select
data_in , // Data input
rd_en
, // Read enable
wr_en
, // Write Enable
data_out , // Data Output
empty
, // FIFO empty
full
// FIFO full
);
// FIFO constants
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
// Port Declarations
input clk ;
input rst ;
input wr_cs ;
input rd_cs ;
input rd_en ;
input wr_en ;
input [DATA_WIDTH-1:0] data_in ;
output full ;
output empty ;
output [DATA_WIDTH-1:0] data_out ;
//-----------Internal variables------------------reg [ADDR_WIDTH-1:0] wr_pointer;
reg [ADDR_WIDTH-1:0] rd_pointer;
reg [ADDR_WIDTH :0] status_cnt;
reg [DATA_WIDTH-1:0] data_out ;
41 wire [DATA_WIDTH-1:0] data_ram ;

42
43 //-----------Variable assignments--------------44 assign full = (status_cnt == (RAM_DEPTH-1));
45 assign empty = (status_cnt == 0);
46
47 //-----------Code Start--------------------------48 always @ (posedge clk or posedge rst)
49 begin : WRITE_POINTER
50
if (rst) begin
51
wr_pointer <= 0;
52
end else if (wr_cs && wr_en ) begin
53
wr_pointer <= wr_pointer + 1;
54
end
55 end
56
57 always @ (posedge clk or posedge rst)
58 begin : READ_POINTER
59
if (rst) begin
60
rd_pointer <= 0;
61
end else if (rd_cs && rd_en ) begin
62
rd_pointer <= rd_pointer + 1;
63
end
64 end
65
67 begin : READ_DATA
68
if (rst) begin
69
data_out <= 0;
70
end else if (rd_cs && rd_en ) begin
71
data_out <= data_ram;
72
end
73 end
74
76 begin : STATUS_COUNTER
77
if (rst) begin
78
status_cnt <= 0;
79
// Read but no write.
80
end else if ((rd_cs && rd_en) && ! (wr_cs &&
wr_en)
81
&& (status_cnt ! = 0)) begin
82
status_cnt <= status_cnt - 1;
83
// Write but no read.
84
end else if ((wr_cs && wr_en) && ! (rd_cs &&
rd_en)
85
&& (status_cnt ! = RAM_DEPTH))
begin
86
status_cnt <= status_cnt + 1;
87
end
88 end
89
90 ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM
(
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.address_0
.data_0
.cs_0
.we_0
.oe_0
.address_1
.data_1
.cs_1
.we_1
.oe_1
);
(wr_pointer)
(data_in)
(wr_cs)
(wr_en)
(1'b0)
(rd_pointer)
(data_ram)
(rd_cs)
(1'b0)
(rd_en)
,
,
,
,
,
,
,
,
,
// address_0 input
// data_0 bi-directional
// chip select
// write enable
// output enable
// address_q input
// data_1 bi-directional
// chip select
// Read enable
// output enable
endmodule
Asynchronous FIFO
Note: This code is written in Verilog 2001.
1 //==========================================
2 // Function : Asynchronous FIFO (w/ 2 asynchronous
clocks).
3 // Coder : Alex Claros F.
4 // Date : 15/May/2005.
5 // Notes : This implementation is based on the article
6 //
'Asynchronous FIFO in Virtex-II FPGAs'
7 //
writen by Peter Alfke. This TechXclusive
8 //
article can be downloaded from the
9 //
Xilinx website. It has some minor
modifications.
10 //=========================================
11
12 `timescale 1ns/1ps
13
14 module aFifo
15
#(parameter
DATA_WIDTH
= 8,
16
ADDRESS_WIDTH = 4,
17
FIFO_DEPTH
= (1 <<
ADDRESS_WIDTH))
18
//Reading port
19
(output reg [DATA_WIDTH-1:0]
Data_out,
20
output reg
Empty_out,
21
input wire
ReadEn_in,
22
input wire
RClk,
23
//Writing port.
24
input wire [DATA_WIDTH-1:0]
Data_in,
25
output reg
Full_out,
26
input wire
WriteEn_in,
27
input wire
WClk,
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input wire
Clear_in);
30
31
// 32
reg
[DATA_WIDTH-1:0]
Mem [FIFO_DEPTH-1:0];
33
wire [ADDRESS_WIDTH-1:0]
pNextWordToWrite, pNextWordToRead;
34
wire
EqualAddresses;
35
wire
NextWriteAddressEn, NextReadAddressEn;
36
wire
Set_Status, Rst_Status;
37
reg
Status;
38
wire
PresetFull, PresetEmpty;
39
40
// 41
//Data ports logic:
42
//(Uses a dual-port RAM).
43
//'Data_out' logic:
44
always @ (posedge RClk)
45
if (ReadEn_in & ! Empty_out)
46
Data_out <=
Mem[pNextWordToRead];
47
48
//'Data_in' logic:
49
always @ (posedge WClk)
50
if (WriteEn_in & ! Full_out)
51
Mem[pNextWordToWrite] <=
Data_in;
52
53
//Fifo addresses support logic:
54
//'Next Addresses' enable logic:
55
assign NextWriteAddressEn = WriteEn_in &
~Full_out;
56
assign NextReadAddressEn = ReadEn_in &
~Empty_out;
57
58
//Addreses (Gray counters) logic:
59
GrayCounter GrayCounter_pWr
60
(.GrayCount_out(pNextWordToWrite),
61
62
.Enable_in(NextWriteAddressEn),
63
.Clear_in(Clear_in),
64
65
.Clk(WClk)
66
);
67
68
GrayCounter GrayCounter_pRd
69
(.GrayCount_out(pNextWordToRead),
70
.Enable_in(NextReadAddressEn),
71
.Clear_in(Clear_in),
72
.Clk(RClk)
73
);
74
75
76
//'EqualAddresses' logic:
77
assign EqualAddresses = (pNextWordToWrite
== pNextWordToRead);
78
79
//'Quadrant selectors' logic:
80
assign Set_Status =
(pNextWordToWrite[ADDRESS_WIDTH-2] ~^
pNextWordToRead[ADDRESS_WIDTH-1]) & 81
(pNextWordToWrite[ADDRESS_WIDTH-1] ^
pNextWordToRead[ADDRESS_WIDTH-2]);
82
83
assign Rst_Status =
(pNextWordToWrite[ADDRESS_WIDTH-2] ^
pNextWordToRead[ADDRESS_WIDTH-1]) & 84
(pNextWordToWrite[ADDRESS_WIDTH-1] ~^
pNextWordToRead[ADDRESS_WIDTH-2]);
85
86
//'Status' latch logic:
87
always @ (Set_Status, Rst_Status,
Clear_in) //D Latch w/ Asynchronous Clear & Preset.
88
if (Rst_Status | Clear_in)
89
Status = 0; //Going 'Empty'.
90
else if (Set_Status)
91
Status = 1; //Going 'Full'.
92
93
//'Full_out' logic for the writing port:
94
assign PresetFull = Status &
EqualAddresses; //'Full' Fifo.
95
96
always @ (posedge WClk, posedge
PresetFull) //D Flip-Flop w/ Asynchronous Preset.
97
if (PresetFull)
98
Full_out <= 1;
99
else
100
Full_out <= 0;
101
102
//'Empty_out' logic for the reading port:
103
assign PresetEmpty = ~Status &
EqualAddresses; //'Empty' Fifo.
104
105
always @ (posedge RClk, posedge
PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
106
if (PresetEmpty)
107
Empty_out <= 1;
108
else
109
Empty_out <= 0;
110
111 endmodule
You could download file aFifo.v here
1 //==========================================
2 // Function : Code Gray counter.
3 // Coder : Alex Claros F.
4 // Date : 15/May/2005.
5 //=======================================
6
7 `timescale 1ns/1ps
8
9 module GrayCounter
10
#(parameter
COUNTER_WIDTH = 4)
11
12
(output reg [COUNTER_WIDTH-1:0]
GrayCount_out, //'Gray' code count output.
13
14
input wire
Enable_in, //Count enable.
15
input wire
Clear_in,
//Count reset.
16
17
input wire
Clk);
18
19
// 20
reg
[COUNTER_WIDTH-1:0]
BinaryCount;
21
22
// 23
24
always @ (posedge Clk)
25
if (Clear_in) begin
26
BinaryCount
<=
{COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1'
with
27
GrayCount_out <=
{COUNTER_WIDTH{1'b 0}};
// first 'Enable_in'.
28
end
29
else if (Enable_in) begin
30
BinaryCount
<= BinaryCount + 1;
31
GrayCount_out <=
{BinaryCount[COUNTER_WIDTH-1],
32
BinaryCount[COUNTER_WIDTH-2:0] ^
BinaryCount[COUNTER_WIDTH-1:1]};
33
end
34
35 endmodule
Content Addressable Memory (CAM)
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//----------------------------------------------------// Design Name : cam

// File Name : cam.v
// Function : CAM
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module cam (
clk
, // Cam clock
cam_enable , // Cam enable
cam_data_in , // Cam data to match
cam_hit_out , // Cam match has happened
cam_addr_out // Cam output address
);
parameter ADDR_WIDTH = 8;
parameter DEPTH
= 1 << ADDR_WIDTH;
//------------Input Ports-------------input
clk;
input
cam_enable;
input [DEPTH-1:0]
cam_data_in;
//----------Output Ports-------------output
cam_hit_out;
output [ADDR_WIDTH-1:0] cam_addr_out;
//------------Internal Variables-------reg [ADDR_WIDTH-1:0] cam_addr_out;
reg
cam_hit_out;
reg [ADDR_WIDTH-1:0] cam_addr_combo;
reg
cam_hit_combo;
reg
found_match;
integer
i;
//-------------Code Starts Here-------
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always @(cam_data_in) begin

cam_addr_combo = {ADDR_WIDTH{1'b0}};
found_match
= 1'b0;
cam_hit_combo
= 1'b0;
for (i=0; i<DEPTH; i=i+1) begin
if (cam_data_in[i] && ! found_match) begin
found_match
= 1'b1;
cam_hit_combo = 1'b1;
cam_addr_combo = i;
end else begin
found_match
= found_match;
cam_hit_combo = cam_hit_combo;
cam_addr_combo = cam_addr_combo;
end
end
end
// Register the outputs
always @(posedge clk) begin
if (cam_enable) begin
cam_hit_out <= cam_hit_combo;
cam_addr_out <= cam_addr_combo;
end else begin
cam_hit_out <= 1'b0;
cam_addr_out <= {ADDR_WIDTH{1'b0}};
end
end
endmodule
Parity
Using Assign
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//----------------------------------------------------// Design Name : parity_using_assign

// File Name : parity_using_assign.v
// Function : Parity using assign
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module parity_using_assign (
data_in
, // 8 bit data in
parity_out
// 1 bit parity out
);
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output parity_out ;
input [7:0] data_in ;
wire parity_out ;
assign parity_out = (data_in[0] ^ data_in[1]) ^
(data_in[2] ^ data_in[3]) ^
(data_in[6] ^ data_in[7]);
endmodule
You could download file parity_using_assign.v here
Using function- I
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//----------------------------------------------------// Design Name : parity_using_function

// File Name : parity_using_function.v
// Function : Parity using function
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module parity_using_function (
data_in
, // 8 bit data in
parity_out
// 1 bit parity out
);
output parity_out ;
wire parity_out ;
function parity;
input [31:0] data;
begin
parity = (data_in[0] ^ data_in[1]) ^
(data_in[6] ^ data_in[7]);
end
endfunction
assign parity_out = parity(data_in);
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29 endmodule
You could download file parity_using_function.v here
Using function- II
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//----------------------------------------------------// Design Name : parity_using_function2

// File Name : parity_using_function2.v
// Function : Parity using function
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module parity_using_function2 (
data_in
, // 8 bit data in
parity_out
// 1 bit parity out
);
output parity_out ;
wire parity_out ;
function parity;
input [31:0] data;
integer i;
begin
parity = 0;
for (i = 0; i < 32; i = i + 1) begin
parity = parity ^ data[i];
end
end
endfunction
always @ (data_in)
begin
parity_out = parity(data_in);
end
endmodule
You could download file parity_using_function2.v here
And the Practical One
//----------------------------------------------------// Design Name : parity_using_bitwise

// File Name : parity_using_bitwise.v
// Function : Parity using bitwise xor
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module parity_using_bitwise (
data_in
, // 8 bit data in
parity_out
// 1 bit parity out
);
output parity_out ;
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assign parity_out = ^data_in;

endmodule
Serial CRC
Below code is 16-bit CRC-CCITT implementation, with
following features
Width = 16 bits
Truncated polynomial = 0x1021
Initial value = 0xFFFF
Input data is NOT reflected
Output CRC is NOT reflected
No XOR is performed on the output CRC
1 //----------------------------------------------------2 // Design Name : serial_crc_ccitt

3 // File Name : serial_crc.v
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// Function : CCITT Serial CRC

// Coder
: Deepak Kumar Tala
//----------------------------------------------------module serial_crc_ccitt (
clk
,
reset
,
enable ,
init
,
data_in ,
crc_out
);
//-----------Input Ports--------------input clk
;
input reset
;
input enable ;
input init
;
input data_in ;
//-----------Output Ports--------------output [15:0] crc_out;
//------------Internal Variables-------reg
[15:0] lfsr;
//-------------Code Start----------------assign crc_out = lfsr;
// Logic to CRC Calculation
if (reset) begin
lfsr <= 16'hFFFF;
if (init) begin
lfsr <= 16'hFFFF;
end else begin
lfsr[0] <= data_in ^ lfsr[15];
lfsr[1] <= lfsr[0];
lfsr[2] <= lfsr[1];
lfsr[3] <= lfsr[2];
lfsr[4] <= lfsr[3];
lfsr[5] <= lfsr[4] ^ data_in ^ lfsr[15];
lfsr[6] <= lfsr[5];
lfsr[7] <= lfsr[6];
lfsr[8] <= lfsr[7];
lfsr[9] <= lfsr[8];
lfsr[10] <= lfsr[9];
lfsr[11] <= lfsr[10];
lfsr[12] <= lfsr[11] ^ data_in ^ lfsr[15];
lfsr[13] <= lfsr[12];
lfsr[14] <= lfsr[13];
lfsr[15] <= lfsr[14];
end
end
endmodule
Parallel CRC
Below code is 16-bit CRC-CCITT implementation, with
following features
Width = 16 bits
Truncated polynomial = 0x1021
Initial value = 0xFFFF
Input data is NOT reflected
Output CRC is NOT reflected
No XOR is performed on the output CRC
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//----------------------------------------------------// Design Name : parallel_crc_ccitt

// File Name : parallel_crc.v
// Function : CCITT Parallel CRC
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module parallel_crc_ccitt (
clk
,
reset
,
enable ,
init
,
data_in ,
crc_out
);
//-----------Input Ports--------------input clk
;
input reset
;
input enable ;
input init
;
20 input [7:0] data_in ;

21 //-----------Output Ports--------------22 output [15:0] crc_out;
23 //------------Internal Variables-------24 reg [15:0]
crc_reg;
25 wire [15:0] next_crc;
26 //-------------Code Start----------------27 assign crc_out = crc_reg;
28 // CRC Control logic
30 if (reset) begin
31
crc_reg <= 16'hFFFF;
32 end else if (enable) begin
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if (init) begin
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crc_reg <= 16'hFFFF;
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end else begin
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crc_reg <= next_crc;
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end
38 end
39 // Parallel CRC calculation
40 assign next_crc[0] = data_in[7] ^ data_in[0] ^
crc_reg[4] ^ crc_reg[11];
41 assign next_crc[1] = data_in[1] ^ crc_reg[5];
data_in[0] ^ crc_reg[4] ^ crc_reg[9] ^ crc_reg[11];
48 assign next_crc[8] = data_in[3] ^ crc_reg[0] ^
crc_reg[7];
crc_reg[8];
crc_reg[9];
crc_reg[10];
52
53 endmodule
Gates Using Switch
Not Gate
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//----------------------------------------------------// Design Name : not_switch

// File Name : not_switch.v
// Function : NOT Gate Using Switch Primitives
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module not_switch (out, in);
output out;
input
in;
supply1 power;
supply0 ground;
pmos (out, power, in);
nmos (out, ground, in);
endmodule
You could download file not_switch.v here
Two Input XOR
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module nor2_switch (a,b,y);

input a, b;
output y;
supply1 power;
supply0 ground;
wire
connect;
nmos
nmos
pmos
pmos
(y,ground,a);
(y,ground,b);
(y,connect,b);
(power,connect,a);
endmodule
You could download file xor_switch.v here
Two Input NAND
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module nand_switch(a,b,out);
input a,b;
output out;
supply0 vss;
supply1 vdd;
wire net1;
pmos
pmos
nmos
nmos
p1
p2
n1
n2
(vdd,out,a);
(vdd,out,b);
(vss,net1,a);
(net1,out,b);
endmodule
Combinational Logic Using Switch
2:1 Mux
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//----------------------------------------------------// Design Name : mux21_switch

// File Name : mux21_switch.v
// Function : 2:1 Mux using Switch Primitives
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux21_switch (out, ctrl, in1, in2);
output out;
input ctrl, in1, in2;
wire
w;
supply1 power;
supply0 ground;
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pmos N1
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nmos N2
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cmos C1
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cmos C2
21
22 endmodule
(w, power, ctrl);

(w, ground, ctrl);
(out, in1, w, ctrl);
(out, in2, ctrl, w);
Sequential Logic Using Switch
D Latch
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module not_switch (out, in);

output out;
input
in;
supply1 power;
supply0 ground;
pmos (out, power, in);
nmos (out, ground, in);
endmodule
module d_latch_switch(clk,d,q);
input clk,d;
output q;
wire clkn, net1, qn;
not_switch i1 (clkn,clk);
pmos p1 (d,q,clkn);
nmos n1 (d,q,clk);
pmos p2 (q,net1,clk);
nmos n2 (q,net1,clkn);
not_switch i2 (qn,q);
not_switch i3 (net1,qn);
endmodule
Misc Functions Using Switch
Transimission Gate
1 module t_gate_switch (L,R,nC,C);

2 inout L;
3 inout R;
4 input nC;
5 input C;
6
7 //Syntax: keyword unique_name (drain. source, gate);
8 pmos p1 (L,R,nC);
9 nmos p2 (L,R,C);
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11 endmodule
You could download file t_gate_switch.v here
!((a+b+c).d)
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module misc1 (a,b,c,d,y);

input a, b,c,d;
output y;
wire net1,net2,net3;
supply1 vdd;
supply0 vss;
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// y = !((a+b+c).d)
pmos
pmos
pmos
pmos
p1
p2
p3
p4
(vdd,net1,a);
(net1,net2,b);
(net2,y,c);
(vdd,y,d);
nmos
nmos
nmos
nmos
n1
n2
n3
n4
(vss,net3,a);
(vss,net3,b);
(vss,net3,c);
(net3,y,d);
endmodule
Adder Using Gates
Half Adder
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//----------------------------------------------------// Design Name : half_adder_gates

// File Name : half_adder_gates.v
// Function : CCITT Serial CRC
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module half_adder_gates(x,y,sum,carry);
input x,y;
output sum,carry;
and U_carry (carry,x,y);
xor U_sum (sum,x,y);
endmodule
You could download file half_adder_gates.v here
Full Adder
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//----------------------------------------------------// Design Name : full_adder_gates

// File Name : full_adder_gates.v
// Function : Full Adder Using Gates
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module full_adder_gates(x,y,z,sum,carry);
input x,y,z;
output sum,carry;
wire and1,and2,and3,sum1;
and U_and1 (and1,x,y),
U_and2 (and2,x,z),
U_and3 (and3,y,z);
or U_or
(carry,and1,and2,and3);
xor U_sum (sum,x,y,z);
endmodule
Subtracter Using Gates
Half Subtracter
You could download file half_subtrater_gates.v here
Full Subtracter
1 //----------------------------------------------------2 // Design Name : full_subtracter_gates
3 // File Name : full_subtracter_gates.v

4 // Function : Full Subtracter Using Gates
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module
full_subtracter_gates(x,y,z,difference,borrow);
8 input x,y,z;
9 output difference,borrow;
10
11 wire inv_x,borrow1,borrow2,borrow3;
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13 not (inv_x,x);
14 and U_borrow1 (borrow1,inv_x,y),
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U_borrow2 (borrow2,inv_x,z),
16
U_borrow3 (borrow3,y,z);
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18 xor U_diff
(difference,borrow1,borrow2,borrows);
19
20 endmodule
Mux Using Gates
2:1 Mux
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//----------------------------------------------------// Design Name : mux_2to1_gates

// File Name : mux_2to1_gates.v
// Function : 2:1 Mux using Gate Primitives
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_2to1_gates(a,b,sel,y);
input a,b,sel;
output y;
wire sel,a_sel,b_sel;
not U_inv (inv_sel,sel);
and U_anda (asel,a,inv_sel),
U_andb (bsel,b,sel);
16 or U_or (y,asel,bsel);
17
18 endmodule
You could download file mux_2to1_gates.v here
4:1 Mux
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//----------------------------------------------------// Design Name : mux_4to1_gates

// File Name : mux_4to1_gates.v
// Function : 4:1 Mux Using Gates
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_4to1_gates(a,b,c,d,sel,y);
input a,b,c,d;
input [1:0] sel;
output y;
wire mux_1,mux_2;
mux_2to1_gates U_mux1 (a,b,sel[0],mux_1),
U_mux2 (c,d,sel[0],mux_2),
U_mux3 (mux_1,mux_2,sel[1],y);
endmodule
Decoder Using Gates
2 To 4 Decoder
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module decoder_2to4_gates (x,y,f0,f1,f2,f3);

input x,y;
output f0,f1,f2,f3;
wire n1,n2;
not i1 (n1,x);
not i2 (n2,y);
and
and
and
and
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a1
a2
a3
a4
(f0,n1,n2);
(f1,n1,y);
(f2,x,n2);
(f3,x,y);
endmodule
Encoder Using Gates
4 To 2 Encoder
module encoder_4to2_gates (i0,i1,i2,i3,y);

input i0,i1,i2,i3;
output [1:0] y;
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or o1 (y[0],i1,i3);
or o2 (y[1],i2,i3);
endmodule
Latch Using Gates
D Latch
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module d_latch_gates(d,clk,q,q_bar);
input d,clk;
output q, q_bar;
wire n1,n2,n3;
not (n1,d);
nand (n2,d,clk);
nand (n3,n1,clk);
nand (q,q_bar,n2);
13 nand (q_bar,q,n3);
14
15 endmodule
Flip-Flop Using Gates
D Flip Flop
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module d_ff_gates(d,clk,q,q_bar);
input d,clk;
output q, q_bar;
wire n1,n2,n3,q_bar_n;
wire cn,dn,n4,n5,n6;
// First Latch
not (n1,d);
nand (n2,d,clk);
nand (n3,n1,clk);
nand (dn,q_bar_n,n2);
nand (q_bar_n,dn,n3);
// Second Latch
not (cn,clk);
not (n4,dn);
nand (n5,dn,cn);
nand (n6,n4,cn);
nand (q,q_bar,n5);
nand (q_bar,q,n6);
endmodule

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Encoders

Encoder - Using if-else Statement

//----------------------------------------------------// Design Name : encoder_using_if

You could download file encoder_using_if.v here

Encoder - Using case Statement

//----------------------------------------------------// Design Name : encoder_using_case

Pri-Encoder - Using if-else Statement

//----------------------------------------------------// Design Name : pri_encoder_using_if

You could download file pri_encoder_using_if.v here

Encoder - Using assign Statement

//----------------------------------------------------// Design Name : pri_encoder_using_assign

Decoder - Using case Statement

//----------------------------------------------------// Design Name : decoder_using_case

You could download file decoder_using_case.v here

Decoder - Using assign Statement

1 //----------------------------------------------------2 // Design Name : decoder_using_assign

Mux : Using assign Statement

//----------------------------------------------------// Design Name : mux_using_assign

You could download file mux_using_assign.v here

Mux : Using if Statement

//----------------------------------------------------// Design Name : mux_using_if

You could download file mux_using_if.v here

Mux : Using case Statement

//----------------------------------------------------// Design Name : mux_using_case

//----------------------------------------------------// Design Name : dff_async_reset

You could download file dff_async_reset.v here

//----------------------------------------------------// Design Name : dff_sync_reset

//----------------------------------------------------// Design Name : tff_async_reset

You could download file tff_async_reset.v here

//----------------------------------------------------// Design Name : tff_sync_reset

//----------------------------------------------------// Design Name : dlatch_reset

8-Bit Simple Up Counter

//----------------------------------------------------// Design Name : up_counter

8-Bit Up Counter With Load

// Design Name : up_counter_load

8-Bit Up-Down Counter

//----------------------------------------------------// Design Name : up_down_counter

up_down , // up_down control for counter

Random Counter (LFSR)

//----------------------------------------------------// Design Name : lfsr

//-------------Code Starts Here------assign linear_feedback = ! (out[7] ^ out[3]);

You could download file lfsr.v here

27 else if (enable) begin

You could download file lfsr_updown.v here

1 //----------------------------------------------------2 // Design Name : gray_counter

One Hot Counter

//----------------------------------------------------// Design Name : one_hot_cnt

1 //----------------------------------------------------2 // Design Name : clk_div

9 // --------------Port Declaration----------------------10 input

//----------------------------------------------------// Design Name : divide_by_3

Divide By 4.5 Counter

1 //----------------------------------------------------2 // Design Name : clk_div_45

Single Port RAM Synchronous Read/Write

//----------------------------------------------------// Design Name : ram_sp_sr_sw

//--------------Inout Ports----------------------inout [DATA_WIDTH-1:0] data

reg [DATA_WIDTH-1:0] data_out ;

Single Port RAM Asynch Read, Synch Write

//----------------------------------------------------// Design Name : ram_sp_ar_sw

22 input [ADDR_WIDTH-1:0] address ;