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EE-421 Digital System Design Lab (Fall 2016) : Or, Not

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69 views

EE-421 Digital System Design Lab (Fall 2016) : Or, Not

Uploaded by

Bilal Siddique
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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EE-421 Digital System Design Lab (Fall 2016)

Lab01
Instructor: Muhammad Awais Bin Altaf
TA: Mirza Athar Baig
Objective:

Understanding HDL based design flow


Identifying the components of a Verilog module definition
Understanding how to define the port list for a module and declare it in Verilog
Familiarization with the logic gate primitives provided in Verilog
Understanding instantiation of gates and construction of a Verilog
description from the logic diagram of the circuit
Simulation of basic building blocks of digital circuits in Verilog
ModelSim simulator

using

Introduction to Verilog HDL: Verilog standardized as IEEE 1364 is a Hardware Description


Language (HDL), used to design digital circuits using FPGA.
Synthesis or Synthesizable code: The code or design that can be transferred to the hardware or
can be easily implemented. For FPGAs the synthesis creates gate patterns and maps the logic
described by the program.
Verilog Basics:
Verilog has three main levels of abstraction:
1. Gate level modeling: Logic gates are used to design the program logic. For example AND,
OR, NOT.
2. Dataflow modeling: Here the data flows through the registers. The designer is aware of
the process of data flow in the registers. Assign keyword and operators (logic and
arithmetic) are used.
3. Behavioral modeling: It is the highest level of abstraction. Implementation can be done
according to the desired algorithm design. Programming at this level is similar to C. Loops
can be used to design the module.
Module: The basic building block of Verilog. It can be a combination of lower level design
blocks. It has a name, port list and internals (functionality). The keyword endmodule must
appear at the end of the module definition. Modules cannot be nested.

Ports: Ports provide the module with a means to communicate with other modules or its
environment. A module can have a port list. Ports in the port list must be declared as input,
output, or inout.When instantiating a module, port connection rules are enforced by the Verilog
simulator.
Test bench/Stimulus: The module functionality is tested by creating a stimulus in which the
inputs are defined to drive the outputs. Stimulus is not synthesized.

end
endmodule

Identifiers and Keywords: Identifiers are the names given to the objects so that they can be
referred anywhere in the design while keywords are special identifiers used to describe the
language constructs.

Registers and Nets: Registers (reg) are used to store values. Usually inputs are given the name
reg. Nets or wires do not store values they just pass on them to the other part of the design.
Outputs are named wires in a design.
Gate level modeling Using predefined primitives (AND, OR, NOT etc) to design a logic.
Simulation:
Simulators are available from many vendors, at all price points. For desktop/personal use, Aldec,
Mentor, LogicSim, SynaptiCAD,TarangEDA Altera Quartus and others offer <$5000 USD toolsuites.
In this lab, we will be using ModelSim by Mentor Graphics. ModelSim is an easy-to-use yet
versatile VHDL/(System)Verilog/SystemC simulator by Mentor Graphics. It supports behavioral,
register transfer level, and gate-level modeling. ModelSim supports all platforms used here at the
Department of Pervasive Computing (i.e. Linux, Solaris and Windows) and many others too.
ModelSim can be found preinstalled on Department's computers.

Getting Started Using Mentor Graphics ModelSim


1.

Open ModelSim

2.

Goto File->New->Project and click Project.

3.

This window will pop up. Name your project something useful, in this case

Project1 was the name chosen. Add the name of the project onto the project location. This
keeps the project in an easy to find place.

4.

If this is the first project most likely you will want to create a new file. Click the

Create New File button and a window pops up. A project can have more than one files so
name this file according to its functionality.

5.
Right click the file name and select edit. Now you are going to write Verilog
code in this file, Use the following code, This is 2 input and gate.
//This module designs the 2 input and one output and gate.
module andgate (a, b, y);
input a, b;
output y;
and a2(y,a,b);
endmodule

6.
After you complete the code, Right click on file name and select compile. This step
will compile the Verilog file.

7.
Now create another Verilog file to write the testbench for you code. Use the
following code for the test bench of AND gate Verilog file.

/// add the code for testfile here


`timescale 1ns/1ns
module andgate_tb;
wire t_y;
reg t_a, t_b;
andgate my_gate( .a(t_a), .b(t_b), .y(t_y) );
initial
begin
t_a = 1'b0;
t_b = 1'b0;
#5
t_a = 1'b0;
t_b = 1'b1;

#5
t_a = 1'b1;
t_b = 1'b0;
#5
t_a = 1'b1;
t_b = 1'b1;
end
endmodule
8.
9.

Compile the testbench file using step 6 again. Make sure you get no error.
Go to simulate option and select start simulation.

10.

Select test bench file to start simulation.

11.
Following window will pop up. Right click on test bench file and select Add
wave.

12.
Select Run. Make sure you get green colored wave forms and check your logic
as well.

Lab Tasks:
1. Simulate four input OR, XOR and XNOR gates using 2 input primitive gates
2. Simulate the given design using gate level modeling.

3. Simulate the gate level model of 4 to 1 Mux using


Verilog (HDL).

Figure 1 4 to 1 multiplexer

Appendix

Gate Primitives in Verilog


The gates have one scalar output and multiple scalar inputs. The 1st terminal in the
list of gate terminals is an output and the other terminals are inputs.
Gate
and
nand
or
nor
xor
xnor
Not

Description
N-input AND gate
N-input NAND gate
N-input OR gate
N-input NOR gate
N-input XOR gate
N-input XNOR gate
One input NOT gate

The name of these gates are keywords and cannot be used as identifiers (like variable name in c).

How to use these Primitive gates


<<name of primitive gate> <<instance name>>(<<output identifier>> <<inputidentifier>>)

Example:
Write Verilog description for 3 input one output and gate using gate primitive
and a2(y,a,b,c)

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