Speed Control of BLDC Motor Using IPM and Micro 2812 Ver.2.0

SPEED CONTROL OF BLDC MOTOR
USING IPM AND MICRO - 2812
User Manual
Version 2.0
Technical Clarification /Suggestion :

N/F
Technical Support Division,
Vi Microsystems Pvt. Ltd.,

Plot No :75,Electronics Estate,
Perungudi,Chennai - 600 096,INDIA.
Ph: 91- 44-2496 1842, 91-44-2496 1852,
Mail : [email protected],
Web : www.vimicrosystems.com
02-11-06-02
CONTENTS
1.
INTRODUCTION
2.
BLDC MOTOR
3.
BLDC HALL SENSOR
4.
MOTOR SPECIFICATIONS
5.
CONNECTOR DETAILS
6.
MICRO 2812
11
7.
DEVICE OVERVIEW
13
8.
WIRING DIAGRAM
24
9.
FLOWCHART
25
10.
EXPERIMENTAL SECTION
28
Speed control of BLDC Motor using IPM and Micro 2812
1. INTRODUCTION
In every industry there are processes some form that require adjustment for normal
operation. Such adjustments are usually accomplished with variable speed drive and it consists
of
* Controller
* Power Converter
* Electric Motor
Controller
Power Converter
Electric Motor
The controller generates PWM signal to the converter &

hence forms the heart of the Variable speed system.(VSDs)
It controls the power flow from an AC supply to the motor
by appropriate control of power semiconductor switches
(part of power Converter).
It is connected directly/indirectly to the load.
2. BLDC MOTOR
Brushless Permanent Magnet Motors, Permanent Magnet AC motors, Permanent Magnet
Synchronous Motors etc. The confusion arises because a brushless dc motor does not directly
operate of a dc voltage source. However, as we shall see, the basic principle of operation is similar
to a dc motor.
A Brushless DC motor has a rotor with permanent magnets and a stator with windings. It
is essentially a dc motor turned inside out. The brushes and commutator have been eliminated and
the windings are connected to the control electronics. The control electronics replace the function
of the commutator and energize the proper winding.
The energized stator winding leads the rotor magnet, and switches just as the rotor aligns
with the stator. There are no sparks, which is one advantage of the BLDC motor. The brushes of
a dc motor have several limitations; brush life, brush residue, maximum speed, and electrical
noise.
BLDC Motors are potentially cleaner, faster, more efficient, less noisy and more reliable.
However, BLDC motors require electronic control.
2.1. BLDC OPERATION
A permanent Magnet AC motor, which has a trapezoidal back emf, is referred to as
brushless DC motor (BLDC). The BLDC drive system is based on the feedback of rotor system
at fixed points for commutation of the phase currents. The BLDC motor requires quasi-rectangle
shaped currents fed into the machine. Alternatively, the voltage may be applied to the motor every
120, with current limit to hold the current within motor capabilities.
[1]

Because the phase currents are excited in synchronism with the constant part of the back
emf, constant torque is generated.
The electromagnetic torque of the BLDC motor is related to the product of phase, back emf
and current. The back emf in each phase are trapezoidal in shape and are displaced by 120
electrical degree with respect to each other in 3 phase machine. A rectangle current pulse is
injected into each phase so that current coincides with the back emf waveform; hence the motor
develops an almost constant toque.
Figure- 1 IGBT Inverter Driver
[2]

GATING SIGNAL
Figure- 2 Timing Diagram
[3]
Figure-3 Motor Output Current Waveforms
Figure-4 Motor Terminal Voltage Waveforms
[4]
"x" denotes either 0 or 1.

1, 2 ..........6 denotes the switches.
Figure-5. Switching sequence
[5]

3 BLDC HALL SENSOR
Hall effect sensor provides the portion of information needed to synchronize the motor excitation
with rotor position in order to produce constant torque. It detects the change in magnetic field. The
rotor magnets are used as triggers to the Hall Sensor. A signal conditioning circuit integrated
within the Hall switch provides a TTL-compatible pulse with sharp edges. Three Hall Sensors
placed 120 apart, are mounted on the stator frame. The Hall Sensor digital signals are used to
sense the rotor position.
Figure-6 Hall sensor
Figure-7: Hall Sensor Connector Details
[6]
Figure-8 Hall Sensor Signal Conditioner Output Buffer
Figure-9 Motor output waveforms for Clockwise Rotation
[7]

4. MOTOR SPECIFICATIONS
4.1. FEATURES
1. Trapezoidal three phase back emf waveform
2. Hall effect sensors, Encoder and index feed back.
3. Temperature sensor mounted in motor winding
4. Additional Encoder interfacing facility
5. Motor and feed back connector, counter part plugs optional.
6. Malt Block paint finish
[8]

5. CONNECTOR DETAILS
The BLDC Motor is provided with two connectors
i. Supply connector
ii. Speed Feedback connector.
i. Supply Connector
The supply connector is provided with 7 pins. It is provided for the supply input to the motor.
The below figure-10 shows the schematic and pin details of supply connector
Supply Connector (Option)
ii. Speed Feedback Connector

The Speed Feedback connector is provided with 17 pins. The Schematic Diagram for speed
feedback connector and pin details are as shown below.
Figure-10 Speed Feed back connector Details
[9]
[ 10 ]

6.
MICRO 2812
6.1.
BENEFITS OF THE DSP CONTROLLERS
The performances of a motor are strongly dependent on its control. DSP controllers enable
enhanced real time algorithms as well as sensor less control. The combination of both allows
reducing the number of components and to optimize the design of silicon, to achieve a system cost
reduction. A powerful processor such as a DSP controller does the following:
Favours system cost reduction by an efficient control in all speed range implying
right dimensioning of power device circuits
Performs high level algorithms due to reduced torque ripple, resulting in lower
vibration and longer life time
Enables a reduction of harmonics using enhanced algorithms, to meet easier
requirements and to reduce filters cost
Removes speed or position sensors by the implementation of sensorless algorithms
Decreases the number of look-up tables which reduces the amount of memory
required
Real-time generation of smooth near-optimal reference profiles and move
trajectories, resulting in better-performing
Controls power switching inverters and generates high-resolution PWM outputs
provides single chip control system
For advanced controls, DSPs controllers may also performs the following:
Enables control of multi-variable and complex systems using modern intelligent

methods such as neural networks and fuzzy logic.
Perform adaptive control. DSPs have the speed capabilities to concurrently monitor
the system and control it. A dynamic control algorithm adapts itself in real time to
variations in system behavior.
Provides diagnostic monitoring with FFT of spectrum analysis by observing the
frequency spectrum of mechanical vibrations, failure modes can be predicted in
early stages.
Produces sharp-cut-off notch filters that eliminate narrow-band mechanical
resonance. Notch filters remove energy that would otherwise excite resonant modes
and possibly make the system unstable.
The TMS320F28x DSP includes the same advantages as the microcontroller but also offers
higher speed, higher resolution, and capabilities to implement the math intensive algorithms to
lower the system cost. The high speed is attributable mainly to the dual bus of the Harvard
architecture as well as single-cycle multiplication and addition instructions. One bus is used for
data and the other is used for program instructions. This saves time because each is utilized
simultaneously. Traditionally, cost has been a potential disadvantage of the DSP solution, but this
aspect has diminished with the continuing decline of DSP costs. DSP controllers enable enhanced,
real-time algorithms as well as sensor less control. The combination reduces the number of
components and optimizes the design of silicon to achieve a system cost reduction.
[ 11 ]

DSPs are capable of processing data at much faster rates than microcontrollers. For
example, the speed of the DSP allows it to estimate motor velocity, a task accomplished by a
tachometer in analog and microcontroller systems.
6.2. APPLICATIONS
The target applications for a fixed point DSP controller having the necessary features are
where the above-mentioned advantages meet the customers needs. Typical end equipment
applications with an advanced control are:
Appliances (washers, blowers, compressors)
HVAC (heating, ventilation and air conditioning)
Industrial servo drives (Motion control, Power supply inverters, Robotics)
Automotive control (electric vehicles).
6.3. DIGITAL CONTROLLER REQUIREMENTS

The following list highlights the digital controller requirements. Calculations powerful
enough to implement advanced and math-intensive control algorithms, such as
Fast response to events to obtain input signals and to unexpected events to secure
the system and Accurate resolution to minimize quantization errors; therefore, a
precise digital control system is offered
High sampling rate to avoid aliasing introduced by sampling effects
Required peripherals to reduce CPU overhead and system cost
6.4. PROCESSOR REQUIREMENTS

The following list highlights the processor requirements.
Strong calculating power for advanced and math-intensive control algorithms
Capability to support large word lengths for required resolution and dynamic range
Small interrupt latency and fast branch operations capabilities to facilitate quick
response to events, including unexpected events
High-MIPS CPU to increase the range of the sampling frequency
Integrate the application-specific peripherals with the processor such as timers, A/D
converters, PWM generators, and communication interfaces.
Hence, CPU overhead and total system costs are reduced.
[ 12 ]

6.5. TI TMS320F28X DSP FAMILY the Optimal Digital Control System Solution
A new class of DSP controllers is becoming a viable option for even the most cost sensitive
applications like appliances, HVAC systems etc. In addition to traditional mathematical functions
like digital filter, FFT implementations, this new class of DSPs integrates all the important power
electronics peripherals to simplify the overall system implementation. This integration lowers over
all part count of the system and reduces the board size.
The TMS320F28x, the first single-chip DSP solution for the digital control system market,
integrates the TI 32 bit, fixed-point TMS320F28x DSP core with several microcontroller
peripherals. The DSP core itself has up to 150 MIPS (6.67 ns cycle time) speed and can perform
the useful multiply/accumulate instruction in a single cycle. The DSP controller TMS320F2812
from Texas Instruments is utilized to implement a three-phase AC induction motor drive with
multiple functions. These functions include basic motor control with closed loop speed control,
input power factor correction using boost topology and serial communication.
TMS320F2812 has a 150 MIPS 16 bit fixed point DSP core. It also integrates the following
power electronics peripherals 16 PWM channels three 16 bit multi-mode general purpose timers,
16 channel 12 bit ADC with simultaneous conversion capability, six capture pins, encoder interface
capability, SCI, SPI, Watch Dog etc. 16 PWM channels (PWM1 through PWM6) control the threephase voltage source inverter. These six PWM channels are grouped in three pairs (PWM 1&2,
PWM 3&4, PWM 5&6). Three compare registers, called Full Compare, are associated with each
PWM channel pair. The compare register values are updated to obtain the proper PWM output. The
onchip software programmable, dead band module provides sufficient dead time to avoid shoot
through fault. There are three more PWM channels left to implement other functions like power
factor correction.
7. DEVICE OVERVIEW
The hardware description of Micro-2812 is provided in this chapter. It describes the
technical capabilities of TMS320F2812 trainer board and the peripherals & memory as related to
TMS320F2812 CPU.
The Block Diagram of Micro-2812 Trainer consists of Processor section, Memory section,
DAC section, ADC section, Display section etc., The following are the buses connecting various
sections to processor in Micro
[ 13 ]

7.1. Architecture of TMS320F2812 CPU
Figure 11: Architecture of TMS320F2812 CPU

The TMS320F2812 DSP controller is a programmable digital controller. The controller
combines the power CPU with the on-chip memory and the peripherals. The Controller offers 60
MIPS (million instructions per second) performance. This fast performance is well suited for
processing control parameter in application where large amount of calculation are to be computed
quickly.
The figure illustrates the Architecture of TMS320F2812 CPU and the explanation for the
peripherals in CPU is given below.
[ 14 ]

7.1.1 Introduction to the CPU
The CPU is a low-cost 32-bit fixed-point digital signal processor (DSP). This device draws
from the best features of digital signal processing; reduced instruction set computing (RISC); and
microcontroller architectures, firmware, and tool sets. The DSP features include a modified
Harvard architecture and circular addressing. The RISC features are single-cycle instruction
execution, register-to-register operations, and modified Harvard architecture (usable in Von
Neumann mode). The microcontroller features include ease of use through an intuitive instruction
set, byte packing and unpacking, and bit manipulation. The modified Harvard architecture of the
CPU enables instruction and data fetches to be performed in parallel. The CPU can read
instructions and data while it writes data simultaneously to maintain the single-cycle instruction
operation across the pipeline. The CPU does this over six separate address/data buses.
7.1.2 Components of the CPU
As shown in Figure, the CPU contains
1.
A CPU for generating data- and program-memory addresses; decoding and executing
instructions; performing arithmetic, logical, and shift operations; and controlling data
transfers among CPU registers, data memory, and program memory
2.
Emulation logic for monitoring and controlling various parts and functionalities of the DSP
and for testing device operation
3.
Signals for interfacing with memory and peripherals, clocking and controlling the CPU and
the emulation logic, showing the status of the CPU and the emulation logic, and using
interrupts The CPU does not contain memory, a clock generator, or peripheral devices. For
information about interfacing to these items, see the C28x Peripheral Users Guide
(literature number SPRU566) and the data sheet that corresponds to your DSP.
Figure 12: High-Level Conceptual Diagram of the CPU
[ 15 ]

7.1.3 Central Processing Unit (CPU)
1.
2.
3.
4.
5.
6.
Protected pipeline. The CPU implements an 8-phase pipeline that prevents a write to and
a read from the same location from occurring out of order.
Independent register space. The CPU contains registers that are not mapped to data
space. These registers function as system-control Components of the CPU 1-5 Architectural
Overview registers, math registers, and data pointers. The system-control registers are
accessed by special instructions. The other registers are accessed by special instructions or
by a special addressing mode (register addressing mode).
Arithmetic logic unit (ALU). The 32-bit ALU performs 2s-complement arithmetic and
Boolean logic operations.
Address register arithmetic unit (ARAU). The ARAU generates data memory addresses
and increments or decrements pointers in parallel with ALU operations.
Barrel shifter. This shifter performs all left and right shifts of data. It can shift data to the
left by up to 16 bits and to the right by up to 16 bits.
Multiplier. The multiplier performs 32-bit 32-bit 2s-complement multiplication with a
64-bit result. The multiplication can be performed with two signed numbers, two unsigned
numbers, or one signed number and one unsigned number.
7.2 C28xx DSP CORE

7.2.1 C28x CPU
The C28x. DSP generation is the newest member of the TMS320C2000 DSP platform. The
C28x is source code compatible to the 24x/240x DSP devices, hence existing 240x users can
leverage their significant software investment. Additionally, the C28x is a very efficient C/C++
engine, hence enabling users to develop not only their system control software in a high-level
language, but also enables math algorithms to be developed using C/C++. The C28x is as efficient
in DSP math tasks as it is in system control tasks that typically are handled by microcontroller
devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit
MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently
handle higher numerical resolution problems that would otherwise demand a more expensive
floating point processor solution. Add to this the fast interrupt response with automatic context
save of critical registers, resulting in a device that is capable of servicing many asynchronous
events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined
memory accesses. This pipelining enables the C28x to execute at high speeds without resorting to
expensive high-speed memories.
7.2.2 Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the
memories and peripherals and the CPU. The C28x memory bus architecture contains a program
read bus, data read bus and data write bus. The program read bus consists of 22 address lines and
32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The
32- bit-wide data busses enable single cycle 32-bit operations.
[ 16 ]

The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch
an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of
Memory Bus accesses can be summarized as follows:
Highest: Data Writes
Program Writes
Data Reads
Program Reads
Lowest: Fetches
7.2.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of
devices, the F281x and C281x adopt a peripheral bus standard for peripheral interconnect. The
peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus
into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control
signals. Two versions of the peripheral bus are supported on the F281x and C281x. One version
only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with C240xcompatible peripherals. The other version supports both 16- and 32-bit accesses called peripheral
frame 1).
7.2.4 Flash (F281x Only)
The F2812 and F2811 contain 128K x 16 of embedded flash memory, segregated into four
8K X 16 sectors, and six 16K X 16 sectors. The F2810 has 64K X 16 of embedded flash,
segregated into two 8K X 16 sectors, and three 16K X 16 sectors. All three devices also contain
a single 1K x 16 of OTP memory at address range 0x3D 7800 - 0x3D 7BFF. The user can
individually erase, program, and validate a flash sector while leaving other sectors untouched.
However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that
erase/program other sectors. Special memory pipelining is provided to enable the flash module to
achieve higher performance. The flash/OTP is mapped to both program and data space; therefore,
it can be used to execute code or store data information.
NOTE: The F280/F2811/F2812 Flash and OTP wait states can be configured by the
application. This allows applications running at slower frequencies to configure the flash to use
fewer wait states. Flash effective performance can be improved by enabling the flash pipeline mode
in the Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait state configuration
alone. The exact performance gain when using the Flash pipeline mode is application-dependent.
The pipeline mode is not available for the OTP block. For more information on the Flash options,
Flash wait-state, and OTP wait-state registers, sees the TMS320F28x System Control and
Interrupts Reference Guide (literature number SPRU078).
[ 17 ]

7.2.5 ROM (C281x Only)
The C2812 and C2811 contain 128K x 16 of ROM. The C2810 has 64K x 16 of ROM. In
addition to this, there is a 1K X 16 ROM block that replaces the OTP memory available in flash
devices. For information on how to submit ROM codes to TI, see the TMS320C28x CPU and
Instruction Set Reference Guide (literature number SPRU430).
7.2.6 M0, M1 SARAMs
All C28x devices contain these two blocks of single access memory, each 1K x 16 in size.
The stack pointer points to the beginning of block M1 on reset. The M0 block overlaps the 240x
device B0, B1, B2 RAM blocks and hence the mapping of data variables on the 240x devices can
remain at the same physical address on C28x devices. The M0 and M1 blocks, like all other
memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can
use M0 and M1 to execute code or for data variables. The partitioning is performed within the
linker. The C28x device presents a unified memory map to the programmer. This makes for easier
programming in high-level languages.
7.2.7 L0, L1, H0 SARAMs
The F281x and C281x contain an additional 16K x 16 of single-access RAM, divided into
3 blocks (4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline
stalls. Each block is mapped to both program and data space.
7.2.8 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are
provided to tell the boot loader software what boot mode to use on power up. The user can select
to boot normally or to download new software from an external connection or to select boot
software that is programmed in the internal Flash. The Boot ROM will also contain standard tables,
such as SIN/COS waveforms, for use in math related algorithms.
7.3.9 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presentable periods and with 16-bit
clock prescaling. The timers have a 32-bit countdown register, which generates an interrupt when
the counter reaches zero. The counter is decremented at the CPU clock speed divided by the
presales value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit
period value. CPU-Timer 2 is reserved for Real-Time OS (RTOS)/BIOS applications. CPU-Timer
1 is also reserved for TI system functions. CPU-Timer 2 is connected to INT14 of the CPU.
CPUTimer1 can be connected to INT13 of the CPU. CPU-Timer 0 is for general use and is
connected to the PIE block.
7.2.10 Control Peripherals
The F281x and C281x support the following peripherals which are used for embedded
control and communication:
EV: The event manager module includes general-purpose timers, full-compare/PWM units, capture
inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event managers are provided
which enable two three-phase motors to be driven or four two-phase motors.
[ 18 ]

The event managers on the F281x and C281x are compatible to the event managers on the 240x
devices (with some minor enhancements).
ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sample andhold units for simultaneous sampling.
7.2.11 Serial Port Peripherals
The F281x and C281x support the following serial communication peripherals:
eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
McBSP: This is the multichannel buffered serial port that is used to connect to E1/T1 lines, phonequality codecs for modem applications or high-quality stereo-quality Audio DAC devices. The
McBSP receive and transmit registers are supported by a 16-level FIFO. This significantly reduces
the overhead for servicing his peripheral.
SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable
bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and
external peripherals or another processor. Typical applications include external I/O or peripheral
expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
communications are supported by the master/slave operation of the SPI. On the F281x and C281x,
the port supports a 16-level, receive and transmit FIFO for reducing servicing overhead.
SCI: The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F281x and C281x, the port supports a 16-level, receive and transmit FIFO
for reducing servicing overhead.
7.3 EVENT MANAGER (EV)
There are two identical Event Managers (EVA and EVB) on TMS320F2812. The event
manager is a most important peripheral in digital motor control. It supports the functions needed
for controlling the electromechanical device.
Each EV Module in the TMS320F2812 contains following sub components:
i. Interrupt logic
ii. General-Purpose (GP) Timers
iii. Full- Compare Units
iv. Programmable Deadband Generator
v. PWM Waveform Generation
vi. Double Update PWM Mode
vii. Capture Unit
viii.Quadrature - Encoder Pulse (QEP) Circuit
ix. GP Timer
x. Compare Unit
xi. Capture Unit
xii. Quadrature Encoder Pulse
[ 19 ]

i. Interrupt Logic
EV interrupt sub-system is slightly different from the main interrupt and are arranged into
three groups (A, B, C ) and each group has its own mask and flag register and is assigned to
particular CPU Interrupt priority level at the PIE. There are several event manager peripheral
interrupt requests in each event manager interrupt group.
ii. General-Purpose (GP) Timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB)
The GP timers can be operated independently or synchronized with each other. The compare
register associated with each GP timer can be used for compare function and PWM-waveform
generation. There are three continuous modes of operations for each GP timer in up- or up/down
counting operations. Internal or external input clocks with programmable prescaler are used for
each GP timer. GP timers also provide the time base for the other event-manager submodules: GP
timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the
quadrature-pulse counting operations. Double-buffering of the period and compare registers allows
programmable change of the timer (PWM) period and the compare/PWM pulse width as needed.
iii. Full-Compare Units
There are three full-compare units on each event manager. These compare units use GP
timer1 as the time base and generate six outputs for compare and PWM-waveform generation using
programmable deadband circuit. The state of each of the six outputs is configured independently.
The compare registers of the compare units are double- buffered, allowing programmable
change of the compare/PWM pulse widths as needed.
iv. Programmable Deadband Generator
Deadband generation can be enabled/disabled for each compare unit output individually.
The deadband-generator circuit produces two outputs (with or without deadband zone) for each
compare unit output signal. The output states of the deadband generator are configurable and
changeable as needed by way of the double-buffered ACTRx register.
v. PWM Waveform Generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event
manager: three independent pairs (six outputs) by the three full-compare units with programmable
deadbands, and two independent PWMs by the GP-timer compares.
vi. Double Update PWM Mode
The F281x and C281x Event Manager support Double Update PWM Mode. This mode
refers to a PWM operation mode in which the position of the leading edge and the position of the
trailing edge of a PWM pulse are independently modifiable in each PWM period. To support this
mode, the compare register that determines the position of the edges of a PWM pulse must allow
(buffered) compare value update once at the beginning of a PWM period and another time in the
middle of a PWM period. The compare registers in F281x and C281x Event Managers are all
buffered and support three compare value reload/update (value in buffer becoming active) modes.
These modes have earlier been documented as compare value reload conditions. The reload
condition that supports double update PWM mode is reloaded on Underflow (beginning of PWM
period) OR period (middle of PWM period). Double update PWM mode can be achieved by using
this condition for compare value reload.
[ 20 ]

vii. Capture Unit
The capture unit provides a logging function for different events or transitions. The values of the
selected GP timer counter is captured and stored in the two-level-deep FIFO stacks when selected
transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for
EVB). The capture unit consists of three capture circuits.
viii. Quadrature-Encoder Pulse (QEP) Circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to
interface the on-chip QEP circuit with a quadrature encoder pulse. Full synchronization of these
inputs is performed on-chip. Direction or leading-quadrature pulse sequence is detected, and GP
timer 2/4 is incremented or decremented by the rising and falling edges of the two input signals
(four times the frequency of either input pulse). With EXTCONA register bits, the EVA QEP
circuit can use CAP3 as a capture index pin as well. Similarly, with EXTCONB register bits, the
EVB QEP circuit can use CAP6 as a capture index pin.
ix. GP Timer
A General purpose timer is configured to count up, down or continuously up and down.
Each EV has two GP timers; Timer 1 & 2 for EVA and Timer 3 & 4 for EVB. Timers are
configured to generate interrupt or trigger another peripheral on certain cases such as timer
overflow, underflow or compare.
x. Compare Unit
A PWM signal can also be generated using compare unit .Their functions are identical to
GP Timer compare units. The PWM outputs associated with the compare unit allows for generation
of six PWM ouputs per EV whereas GP timer associated for two PWM outputs.
xi. Capture Unit
The capture unit on TMS320F2812 allows an event on the capture pin to be time stamped
by selected GP Timer. Capture units 1, 2 and 3 are associated with EVA while capture units 4, 5,
6 are associated with EVB.
xii. Quadrature Encoder Pulse
QEP's are two sequences of pulses which have a variable frequency and are 90o out of phase
with each other. QEP's are usually generated by position speed sensing device such as a rotary
optical encoder. Each EV module has a QEP circuit associated with capture unit.
Figure 13: Quadrature Encoder Pulses
[ 21 ]

7.4 PERIPHERALS UNITS
1. Controller Area Network
CAN module is a useful peripheral for specific application of TMS320F2812. The CAN
module is used for multi-master serial communication between external hardware. The CAN bus
has a high level of data integrity and is ideal for operation in noisy environment such as in an
automobile, or industrial environments that requires reliable communication and data integrity.
2. Serial Peripheral Interface
The SPI is a high speed synchronous serial input / output port that allow a serial bit stream
of program length to be shifted in and out of device at a programmed bit transfer rate. SPI is mainly
used for communication between DSP and external peripherals or another DSP device. Typical
uses of SPI include communication with external shift register, display drivers or ADC's.
3. Serial Communication Interface
The programmable SCI module that supports asynchronous serial digital communication
between CPU and other asynchronous peripherals that use standard NRZ format (Non-return tozero). It is used for communication between external device and CPU. The SCI transmits and
receives serial data one bit at a time at programmable bit rate. The SCI's receivers and transmitter
are double buffered and each has its own separate enable and interrupt bits. Both may be operated
independently or simultaneously in full-duplex mode.
4. Watch Dog Timer (Wd)
The F281x and C281x support a watchdog timer. The user software must regularly reset
the watchdog counter within a certain time frame; otherwise, the watchdog will generate a reset
to the processor. The watchdog can be disabled if necessary.
5. Oscillator and PLL
The F281x and C281x can be clocked by an external oscillator or by a crystal attached to
the onchip oscillator circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The
PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating
frequency if lower power operation is desired. Refer to the Electrical Specification section for
timing details. The PLL block can be getting in bypass mode.
6. Enhanced Analog-to-Digital Converter (ADC) Module
The ADC module in the F281x and C281x has been enhanced to provide flexible interface
to event managers A and B. The ADC interface is built around a fast, 12-bit ADC module with a
fast conversion rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels,
configurable as two independent 8-channel modules to service event managers A and B. The two
independent 8-channel modules can be cascaded to form a 16-channel module. Although there are
multiple input channels and two sequencers, there is only one converter in the ADC module.
[ 22 ]

7. Real-Time JTAG and Analysis
The F281x and C281x implement the standard IEEE 1149.1 JTAG interface. Additionally,
the F281x and C281x support real-time mode of operation whereby the contents of memory,
peripheral and register locations can be modified while the processor is running and executing code
and servicing interrupts. The user can also single step through non-time critical code while
enabling time-critical interrupts to be serviced without interference. The F281x and C281x
implement the real-time mode in hardware within the CPU. This is a unique feature to the F281x
and C281x, no software monitor is required. Additionally, special analysis hardware is provided
which allows the user to set hardware breakpoint or data/address watch-points and generate various
user selectable break events when a match occurs.
Figure 14: Interfacing of PC to Micro-2812

7.5. PRECAUTIONS
To avail the features provided with the trainer, you are advised to confirm certain basic
norms and are requested to abstain from the following,
1.
Dont connect the CRO probe at the output terminal of the IPM without isolation
2.
If user wants to see the high voltage waveform using CRO, please connect one
isolation transformer between auto transformer and IPM otherwise remove the earth
terminal of the CRO power card.
3.
If the protection circuit LED in the IPM is glow during the operation, user must
reset the trainer kit first and then reset the power module.
4.
Please do not insert any add-on card while the trainer is powered ON.
5.
Please do not tamper with any of the components in the trainer.
6.
Please do not solder any wire from connectors when the power is ON.
7.
Wires are to be soldered only from the solder side of the board in unavoidable
conditions.
8.
The headers should be used only with cables and not with wires soldered from the
pins.
9.
Don't attempt to service the trainer yourself in case of problems.
10
Don't insert or remove any ICs while power is ON.
[ 23 ]

8.
WIRING DIAGRAM
Figure -15. Speed control of BLDC Motor using IPM and Micro 2812
[ 24 ]

9. FLOWCHART
[ 25 ]
[ 26 ]
[ 27 ]

10. EXPERIMENTAL SECTION
AIM
To study the open loop and closed loop speed control of BLDC Motor by using MICRO 2812 and
PEC16DSMO1( IPM)module.
EQUIPMENTS REQUIRED
1.
PEC16DSMO1 Power Module
2.
MICRO - 2812 (DSP trainer)
3.
BLDC Motor
4.
Hall signal conditioning card
5.
Cables
i.
34 pin FRC 1 to 1 to 1.
ii.
26 pin FRC 1 to 1.
iii.
Feedback connector cable (9 pin D cable).
iv.
PC to PC cable (Serial port cable).
[ 28 ]

CONNECTION PROCEDURE
1.
Connect the 34 pin cable from the MICRO - 2812 to power module(IPM) along with the
Hall signal conditional card.
2.
Connect the 26 pin cable from the MICRO - 2812 to power module(IPM).
3.
Connect the feed back cable between motor and Hall signal conditioning card.
4.
Connect the serial port from the PC to 9 - pin termination of the DSP trainer.
5.
Connect the motor terminals R, Y, B to the U, V, W terminals in IPM Power Module
[ 29 ]

EXPERIMENTAL PROCEDURE
1.
Verify the connections as per the connection procedure and Wiring Diagram.
2.
Switch ON the MICRO - 2812 DSP trainer kit.
3.
Power ON the IPM Power Module (PEC16DSM01).
4.
Check whether shut down LED "SD" glows or not. If 'SD' LED glows, press the Reset
switch, the LED gets OFF.
6.
Download the program to the MICRO - 2812 Kit by following the downloading
procedure.
[ 30 ]

DOWNLOADING PROCEDURE
Double click the VI_BLDC_2812 icon in the desktop
[ 31 ]
Following window will appear
[ 32 ]
Set the com port and Baud Rate value
[ 33 ]
Then connect and reset the 2812 trainer kit
[ 34 ]
Then select open loop for running the openloop program and close loop for running the
closeloop program. Then click download to download the program
[ 35 ]
The program get downloaded.
[ 36 ]
Then click ok on the file successfully downloaded block
[ 37 ]
Now the actual speed and the set speed are displayed in the window
[ 38 ]

OPEN LOOP CONTROL
1.
Verify the PWM waveform and Hall sensor output which are terminated in the power
module.
2.
After ensuring all the connection, apply the input voltage to the IPM power module
(DC rail voltage (350V), which is shown in the power module voltmeter).
3.
Now the motor starts to rotate in the set speed.
4.
By using the switches increment(S2) and decrement(S3) set the speed of the motor.
5.
The actual speed of the motor will be displayed in the LCD and PC.
6.
To measure the load current of the motor, externally connect one AC ammeter in series
with any one phase.
CLOSED LOOP CONTROL

1.
Verify the PWM waveform and Hall sensor output which are terminated in the power
module.
2.
After ensuring all the connection, apply the input voltage to the IPM power module (DC
rail voltage (350V), which is shown in the power module voltmeter).
3.
Now the motor starts to rotate in the set speed.
4.
By using the switches increment(S2) and decrement(S3) set the speed of the motor.
5.
The actual speed of the motor will be displayed in the LCD and PC.
6.
Now apply the load to the motor at rated current rating and analyze the performance of
7
8.
the closed loop control .

The actual speed of the motor remains same as set speed after applying the load in close
loop condition
To measure the load current of the motor, externally connect one AC ammeter in series
with any one phase.
[ 39 ]

Speed Control of BLDC Motor Using IPM and Micro 2812 Ver.2.0

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SPEED CONTROL OF BLDC MOTOR

USING IPM AND MICRO - 2812

Technical Clarification /Suggestion :

Vi Microsystems Pvt. Ltd.,

BLDC HALL SENSOR