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    This document provides problem set #3 for the course EE 143 Microfabrication Technology taught in Fall 2014. It includes two problems - the first asks students to analyze a process flow and layout for an integrated circuit and determine mask polarities and plot cross-sections; the second problem involves analyzing a process flow and designing a layout for a MEMS cantilever device. Students are asked to determine dimensions, plot cross-sections, and design the cantilever layout on graph paper. The problem set is due on September 24, 2014.

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    hw3 Ee143 f14 Web

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    stansilaw
    90 views4 pages
    This document provides problem set #3 for the course EE 143 Microfabrication Technology taught in Fall 2014. It includes two problems - the first asks students to analyze a process flow and layout for an integrated circuit and determine mask polarities and plot cross-sections; the second problem involves analyzing a process flow and designing a layout for a MEMS cantilever device. Students are asked to determine dimensions, plot cross-sections, and design the cantilever layout on graph paper. The problem set is due on September 24, 2014.

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    hw3.ee143.f14.web

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    This document provides problem set #3 for the course EE 143 Microfabrication Technology taught in Fall 2014. It includes two problems - the first asks students to analyze a process flow and layout for an integrated circuit and determine mask polarities and plot cross-sections; the second problem involves analyzing a process flow and designing a layout for a MEMS cantilever device. Students are asked to determine dimensions, plot cross-sections, and design the cantilever layout on graph paper. The problem set is due on September 24, 2014.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    90 views4 pages

    hw3 Ee143 f14 Web

    Uploaded by

    stansilaw
    This document provides problem set #3 for the course EE 143 Microfabrication Technology taught in Fall 2014. It includes two problems - the first asks students to analyze a process flow and layout for an integrated circuit and determine mask polarities and plot cross-sections; the second problem involves analyzing a process flow and designing a layout for a MEMS cantilever device. Students are asked to determine dimensions, plot cross-sections, and design the cantilever layout on graph paper. The problem set is due on September 24, 2014.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    EE 143

    MICROFABRICATION TECHNOLOGY

    FALL 2014
    C. Nguyen

    PROBLEM SET #3
    Issued: Tuesday, Sep. 17, 2014
    Due: Wednesday, Sep. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory

    Layout to Cross-Section
    1. Consider the following layout of an integrated circuit and the corresponding process
    flow:

    N-well

    Active

    Buried
    Contact

    Poly-Si

    P+/N+

    Contact

    Metal

    The Process Flow


    1)
    2)
    3)
    4)
    5)
    6)
    7)
    8)

    Silicon oxidation: target = 300nm


    Lithography: Mask I (N-well)
    Etch SiO2
    Remove PR
    N-well diffusion: P (n-type)
    Etch SiO2
    Silicon oxidation: target = 100nm
    LPCVD Si3N4: target = 500nm

    9)
    10)
    11)
    12)
    13)
    14)

    Lithography: Mask II (Active)


    Etch Si3N4
    Etch SiO2
    Field isolation implant: B+ (p-type)
    Remove PR
    Grow 1m of SiO2 thermally
    (LOCOS oxidation)
    15) Etch Si3N4

    EE 143

    MICROFABRICATION TECHNOLOGY

    16) Etch SiO2


    17) Dry oxidation for gate oxide:
    target = 100nm
    18) Lithography: Mask III (Buried
    Contact)(dark field)
    19) Etch SiO2
    20) Remove PR
    21) LPCVD in situ phosphorous-doped
    gate polysilicon: target = 350nm
    22) Lithography: Mask IV (Poly)
    23) Dry etch polysilicon
    24) Remove PR
    25) Lithography: Mask V (n+
    implant)(dark field)
    26) D/S ion implantation: P (n-type)
    27) Remove PR

    FALL 2014
    C. Nguyen

    28) Lithography: Mask VI (p+


    implant)(clear field)
    29) D/S ion implantation: B (p-type)
    30) Remove PR
    31) Anneal at 1050C to activate
    dopants and drive-in diffusion
    32) LPCVD PSG: target = 1 m and
    reflow at 950C
    33) Lithography: Mask VII (Contact)
    34) Etch SiO2 down to S/D regions
    and polysilicon
    35) Remove PR
    36) Deposit Al: sputtering target =
    1m
    37) Lithography: Mask VIII (Metal)
    38) Dry etch Al
    39) Remove PR

    (a) Suppose positive photoresist is used in all lithography steps. What is the polarity
    (i.e., dark or clear field) for Mask I and II, Mask IV, and Mask VII and VIII?
    (b) Plot the cross-sections along AA and BB planes, through step 14), 20), and 39).
    2. Suppose that the following process flow is used to achieve a MEMS cantilever as
    shown below together with its cross-section along AA plane. Note that the cantilever
    is similar to that in HW#2 Problem 2 but now with an additional bottom electrode layer
    for electrical access.
    MEMS Cantilever Process Flow
    1) Start with a Si wafer
    2) LPCVD Si3N4: target = 500nm
    3) LPCVD in situ phosphorous-doped
    polysilicon: target = 300nm
    4) Lithography: Mask I (Bottom
    Electrode)
    5) Dry etch polysilicon
    6) Remove PR
    7) LPCVD SiO2: target = 300nm

    8)
    9)
    10)
    11)
    12)
    13)
    14)
    15)

    Lithography: Mask II (Anchor)


    Etch SiO2
    Remove PR
    LPCVD in situ phosphorous-doped
    polysilicon: target =
    Lithography: Mask III (Beam)
    Dry etch polysilicon
    Remove PR
    Release in liquid HF

    EE 143

    MICROFABRICATION TECHNOLOGY

    FALL 2014
    C. Nguyen

    PolySi Cantilever

    A
    6
    Silicon Nitride
    Si-Substrate

    (a) How high does the cantilever suspend from the bottom electrode (i.e., dimension
    of d)?
    (b) Assume = 5 m. Draw a layout for the cantilever on graph paper (which is
    provided) with each box corresponding to one i.e., 5 m Label dimensions
    whenever they are applicable and indicate each of the mask layers (i.e., Mask I
    (Bottom electrode), Mask II (Anchor) etc.).

    EE 143

    MICROFABRICATION TECHNOLOGY

    FALL 2014
    C. Nguyen

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